adwlib.h revision 1.8
1 /* $NetBSD: adwlib.h,v 1.8 2000/04/30 18:52:15 dante Exp $ */ 2 3 /* 4 * Definitions for low level routines and data structures 5 * for the Advanced Systems Inc. SCSI controllers chips. 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 /* 41 * Ported from: 42 */ 43 /* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-2000 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 */ 54 55 #ifndef _ADVANSYS_WIDE_LIBRARY_H_ 56 #define _ADVANSYS_WIDE_LIBRARY_H_ 57 58 59 /* 60 * --- Adv Library Constants and Macros 61 */ 62 63 #define ADW_LIB_VERSION_MAJOR 5 64 #define ADW_LIB_VERSION_MINOR 8 65 66 /* 67 * Define Adv Reset Hold Time grater than 25 uSec. 68 * See AdvResetSCSIBus() for more info. 69 */ 70 #define ASC_SCSI_RESET_HOLD_TIME_US 60 71 72 /* 73 * Define Adv EEPROM constants. 74 */ 75 76 #define ASC_EEP_DVC_CFG_BEGIN (0x00) 77 #define ASC_EEP_DVC_CFG_END (0x15) 78 #define ASC_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 79 #define ASC_EEP_MAX_WORD_ADDR (0x1E) 80 81 #define ASC_EEP_DELAY_MS 100 82 83 /* 84 * EEPROM bits reference by the RISC after initialization. 85 */ 86 #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 87 #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 88 #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 89 90 /* 91 * EEPROM configuration format 92 * 93 * Field naming convention: 94 * 95 * *_enable indicates the field enables or disables the feature. The 96 * value is never reset. 97 * 98 * *_able indicates both whether a feature should be enabled or disabled 99 * and whether a device isi capable of the feature. At initialization 100 * this field may be set, but later if a device is found to be incapable 101 * of the feature, the field is cleared. 102 * 103 * Default values are maintained in the structure Default_EEPROM_Config. 104 */ 105 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 106 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 107 /* 108 * For the ASC3550 Bit 13 is Termination Polarity control bit. 109 * For later ICs Bit 13 controls whether the CIS (Card Information 110 * Service Section) is loaded from EEPROM. 111 */ 112 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 113 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 114 115 /* 116 * ASC38C1600 Bit 11 117 * 118 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 119 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 120 * Function 0 will specify INT B. 121 * 122 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 123 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 124 * Function 1 will specify INT A. 125 */ 126 #define ADW_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 127 128 typedef struct adw_eep_3550_config 129 { 130 /* Word Offset, Description */ 131 132 u_int16_t cfg_lsw; /* 00 power up initialization */ 133 /* bit 13 set - Term Polarity Control */ 134 /* bit 14 set - BIOS Enable */ 135 /* bit 15 set - Big Endian Mode */ 136 u_int16_t cfg_msw; /* 01 unused */ 137 u_int16_t disc_enable; /* 02 disconnect enable */ 138 u_int16_t wdtr_able; /* 03 Wide DTR able */ 139 u_int16_t sdtr_able; /* 04 Synchronous DTR able */ 140 u_int16_t start_motor; /* 05 send start up motor */ 141 u_int16_t tagqng_able; /* 06 tag queuing able */ 142 u_int16_t bios_scan; /* 07 BIOS device control */ 143 u_int16_t scam_tolerant; /* 08 no scam */ 144 145 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 146 u_int8_t bios_boot_delay; /* power up wait */ 147 148 u_int8_t scsi_reset_delay; /* 10 reset delay */ 149 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 150 /* high nibble is lun */ 151 /* low nibble is scsi id */ 152 153 u_int8_t termination; /* 11 0 - automatic */ 154 /* 1 - low off / high off */ 155 /* 2 - low off / high on */ 156 /* 3 - low on / high on */ 157 /* There is no low on / high off */ 158 159 u_int8_t reserved1; /* reserved byte (not used) */ 160 161 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 162 /* bit 0 BIOS don't act as initiator. */ 163 /* bit 1 BIOS > 1 GB support */ 164 /* bit 2 BIOS > 2 Disk Support */ 165 /* bit 3 BIOS don't support removables */ 166 /* bit 4 BIOS support bootable CD */ 167 /* bit 5 BIOS scan enabled */ 168 /* bit 6 BIOS support multiple LUNs */ 169 /* bit 7 BIOS display of message */ 170 /* bit 8 SCAM disabled */ 171 /* bit 9 Reset SCSI bus during init. */ 172 /* bit 10 */ 173 /* bit 11 No verbose initialization. */ 174 /* bit 12 SCSI parity enabled */ 175 /* bit 13 */ 176 /* bit 14 */ 177 /* bit 15 */ 178 u_int16_t ultra_able; /* 13 ULTRA speed able */ 179 u_int16_t reserved2; /* 14 reserved */ 180 u_int8_t max_host_qng; /* 15 maximum host queuing */ 181 u_int8_t max_dvc_qng; /* maximum per device queuing */ 182 u_int16_t dvc_cntl; /* 16 control bit for driver */ 183 u_int16_t bug_fix; /* 17 control bit for bug fix */ 184 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 185 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 186 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 187 u_int16_t check_sum; /* 21 EEP check sum */ 188 u_int8_t oem_name[16]; /* 22 OEM name */ 189 u_int16_t dvc_err_code; /* 30 last device driver error code */ 190 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 191 u_int16_t adv_err_addr; /* 32 last uc error address */ 192 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 193 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 194 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 195 u_int16_t num_of_err; /* 36 number of error */ 196 } ADW_EEP_3550_CONFIG; 197 198 typedef struct adw_eep_38C0800_config 199 { 200 /* Word Offset, Description */ 201 202 u_int16_t cfg_lsw; /* 00 power up initialization */ 203 /* bit 13 set - Load CIS */ 204 /* bit 14 set - BIOS Enable */ 205 /* bit 15 set - Big Endian Mode */ 206 u_int16_t cfg_msw; /* 01 unused */ 207 u_int16_t disc_enable; /* 02 disconnect enable */ 208 u_int16_t wdtr_able; /* 03 Wide DTR able */ 209 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 210 u_int16_t start_motor; /* 05 send start up motor */ 211 u_int16_t tagqng_able; /* 06 tag queuing able */ 212 u_int16_t bios_scan; /* 07 BIOS device control */ 213 u_int16_t scam_tolerant; /* 08 no scam */ 214 215 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 216 u_int8_t bios_boot_delay; /* power up wait */ 217 218 u_int8_t scsi_reset_delay; /* 10 reset delay */ 219 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 220 /* high nibble is lun */ 221 /* low nibble is scsi id */ 222 223 u_int8_t termination_se; /* 11 0 - automatic */ 224 /* 1 - low off / high off */ 225 /* 2 - low off / high on */ 226 /* 3 - low on / high on */ 227 /* There is no low on / high off */ 228 229 u_int8_t termination_lvd; /* 11 0 - automatic */ 230 /* 1 - low off / high off */ 231 /* 2 - low off / high on */ 232 /* 3 - low on / high on */ 233 /* There is no low on / high off */ 234 235 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 236 /* bit 0 BIOS don't act as initiator. */ 237 /* bit 1 BIOS > 1 GB support */ 238 /* bit 2 BIOS > 2 Disk Support */ 239 /* bit 3 BIOS don't support removables */ 240 /* bit 4 BIOS support bootable CD */ 241 /* bit 5 BIOS scan enabled */ 242 /* bit 6 BIOS support multiple LUNs */ 243 /* bit 7 BIOS display of message */ 244 /* bit 8 SCAM disabled */ 245 /* bit 9 Reset SCSI bus during init. */ 246 /* bit 10 */ 247 /* bit 11 No verbose initialization. */ 248 /* bit 12 SCSI parity enabled */ 249 /* bit 13 */ 250 /* bit 14 */ 251 /* bit 15 */ 252 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 253 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 254 u_int8_t max_host_qng; /* 15 maximum host queueing */ 255 u_int8_t max_dvc_qng; /* maximum per device queuing */ 256 u_int16_t dvc_cntl; /* 16 control bit for driver */ 257 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 258 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 259 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 260 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 261 u_int16_t check_sum; /* 21 EEP check sum */ 262 u_int8_t oem_name[16]; /* 22 OEM name */ 263 u_int16_t dvc_err_code; /* 30 last device driver error code */ 264 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 265 u_int16_t adv_err_addr; /* 32 last uc error address */ 266 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 267 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 268 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 269 u_int16_t reserved36; /* 36 reserved */ 270 u_int16_t reserved37; /* 37 reserved */ 271 u_int16_t reserved38; /* 38 reserved */ 272 u_int16_t reserved39; /* 39 reserved */ 273 u_int16_t reserved40; /* 40 reserved */ 274 u_int16_t reserved41; /* 41 reserved */ 275 u_int16_t reserved42; /* 42 reserved */ 276 u_int16_t reserved43; /* 43 reserved */ 277 u_int16_t reserved44; /* 44 reserved */ 278 u_int16_t reserved45; /* 45 reserved */ 279 u_int16_t reserved46; /* 46 reserved */ 280 u_int16_t reserved47; /* 47 reserved */ 281 u_int16_t reserved48; /* 48 reserved */ 282 u_int16_t reserved49; /* 49 reserved */ 283 u_int16_t reserved50; /* 50 reserved */ 284 u_int16_t reserved51; /* 51 reserved */ 285 u_int16_t reserved52; /* 52 reserved */ 286 u_int16_t reserved53; /* 53 reserved */ 287 u_int16_t reserved54; /* 54 reserved */ 288 u_int16_t reserved55; /* 55 reserved */ 289 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ 290 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ 291 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ 292 u_int16_t subsysid; /* 59 SubSystem ID */ 293 u_int16_t reserved60; /* 60 reserved */ 294 u_int16_t reserved61; /* 61 reserved */ 295 u_int16_t reserved62; /* 62 reserved */ 296 u_int16_t reserved63; /* 63 reserved */ 297 } ADW_EEP_38C0800_CONFIG; 298 299 typedef struct adw_eep_38C1600_config 300 { 301 /* Word Offset, Description */ 302 303 u_int16_t cfg_lsw; /* 00 power up initialization */ 304 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */ 305 /* clear - Func. 0 INTA, Func. 1 INTB */ 306 /* bit 13 set - Load CIS */ 307 /* bit 14 set - BIOS Enable */ 308 /* bit 15 set - Big Endian Mode */ 309 u_int16_t cfg_msw; /* 01 unused */ 310 u_int16_t disc_enable; /* 02 disconnect enable */ 311 u_int16_t wdtr_able; /* 03 Wide DTR able */ 312 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 313 u_int16_t start_motor; /* 05 send start up motor */ 314 u_int16_t tagqng_able; /* 06 tag queuing able */ 315 u_int16_t bios_scan; /* 07 BIOS device control */ 316 u_int16_t scam_tolerant; /* 08 no scam */ 317 318 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 319 u_int8_t bios_boot_delay; /* power up wait */ 320 321 u_int8_t scsi_reset_delay; /* 10 reset delay */ 322 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 323 /* high nibble is lun */ 324 /* low nibble is scsi id */ 325 326 u_int8_t termination_se; /* 11 0 - automatic */ 327 /* 1 - low off / high off */ 328 /* 2 - low off / high on */ 329 /* 3 - low on / high on */ 330 /* There is no low on / high off */ 331 332 u_int8_t termination_lvd; /* 11 0 - automatic */ 333 /* 1 - low off / high off */ 334 /* 2 - low off / high on */ 335 /* 3 - low on / high on */ 336 /* There is no low on / high off */ 337 338 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 339 /* bit 0 BIOS don't act as initiator. */ 340 /* bit 1 BIOS > 1 GB support */ 341 /* bit 2 BIOS > 2 Disk Support */ 342 /* bit 3 BIOS don't support removables */ 343 /* bit 4 BIOS support bootable CD */ 344 /* bit 5 BIOS scan enabled */ 345 /* bit 6 BIOS support multiple LUNs */ 346 /* bit 7 BIOS display of message */ 347 /* bit 8 SCAM disabled */ 348 /* bit 9 Reset SCSI bus during init. */ 349 /* bit 10 Basic Integrity Checking disabled */ 350 /* bit 11 No verbose initialization. */ 351 /* bit 12 SCSI parity enabled */ 352 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */ 353 /* bit 14 */ 354 /* bit 15 */ 355 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 356 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 357 u_int8_t max_host_qng; /* 15 maximum host queueing */ 358 u_int8_t max_dvc_qng; /* maximum per device queuing */ 359 u_int16_t dvc_cntl; /* 16 control bit for driver */ 360 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 361 u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ 362 u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ 363 u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ 364 u_int16_t check_sum; /* 21 EEP check sum */ 365 u_int8_t oem_name[16]; /* 22 OEM name */ 366 u_int16_t dvc_err_code; /* 30 last device driver error code */ 367 u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ 368 u_int16_t adv_err_addr; /* 32 last uc error address */ 369 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 370 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 371 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 372 u_int16_t reserved36; /* 36 reserved */ 373 u_int16_t reserved37; /* 37 reserved */ 374 u_int16_t reserved38; /* 38 reserved */ 375 u_int16_t reserved39; /* 39 reserved */ 376 u_int16_t reserved40; /* 40 reserved */ 377 u_int16_t reserved41; /* 41 reserved */ 378 u_int16_t reserved42; /* 42 reserved */ 379 u_int16_t reserved43; /* 43 reserved */ 380 u_int16_t reserved44; /* 44 reserved */ 381 u_int16_t reserved45; /* 45 reserved */ 382 u_int16_t reserved46; /* 46 reserved */ 383 u_int16_t reserved47; /* 47 reserved */ 384 u_int16_t reserved48; /* 48 reserved */ 385 u_int16_t reserved49; /* 49 reserved */ 386 u_int16_t reserved50; /* 50 reserved */ 387 u_int16_t reserved51; /* 51 reserved */ 388 u_int16_t reserved52; /* 52 reserved */ 389 u_int16_t reserved53; /* 53 reserved */ 390 u_int16_t reserved54; /* 54 reserved */ 391 u_int16_t reserved55; /* 55 reserved */ 392 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ 393 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ 394 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ 395 u_int16_t subsysid; /* 59 SubSystem ID */ 396 u_int16_t reserved60; /* 60 reserved */ 397 u_int16_t reserved61; /* 61 reserved */ 398 u_int16_t reserved62; /* 62 reserved */ 399 u_int16_t reserved63; /* 63 reserved */ 400 } ADW_EEP_38C1600_CONFIG; 401 402 403 /* 404 * EEPROM Commands 405 */ 406 #define ASC_EEP_CMD_READ 0x80 407 #define ASC_EEP_CMD_WRITE 0x40 408 #define ASC_EEP_CMD_WRITE_ABLE 0x30 409 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 410 411 #define ASC_EEP_CMD_DONE 0x0200 412 #define ASC_EEP_CMD_DONE_ERR 0x0001 413 414 /* cfg_word */ 415 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000 416 417 /* bios_ctrl */ 418 #define BIOS_CTRL_BIOS 0x0001 419 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 420 #define BIOS_CTRL_GT_2_DISK 0x0004 421 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 422 #define BIOS_CTRL_BOOTABLE_CD 0x0010 423 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 424 #define BIOS_CTRL_DISPLAY_MSG 0x0080 425 #define BIOS_CTRL_NO_SCAM 0x0100 426 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 427 #define BIOS_CTRL_INIT_VERBOSE 0x0800 428 #define BIOS_CTRL_SCSI_PARITY 0x1000 429 #define BIOS_CTRL_AIPP_DIS 0x2000 430 431 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 432 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */ 433 434 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 435 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ 436 437 #define ADV_38C1600_MEMSIZE 0x8000 /* 32 KB Internal Memory */ 438 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */ 439 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */ 440 441 /* 442 * Byte I/O register address from base of 'iop_base'. 443 */ 444 #define IOPB_INTR_STATUS_REG 0x00 445 #define IOPB_CHIP_ID_1 0x01 446 #define IOPB_INTR_ENABLES 0x02 447 #define IOPB_CHIP_TYPE_REV 0x03 448 #define IOPB_RES_ADDR_4 0x04 449 #define IOPB_RES_ADDR_5 0x05 450 #define IOPB_RAM_DATA 0x06 451 #define IOPB_RES_ADDR_7 0x07 452 #define IOPB_FLAG_REG 0x08 453 #define IOPB_RES_ADDR_9 0x09 454 #define IOPB_RISC_CSR 0x0A 455 #define IOPB_RES_ADDR_B 0x0B 456 #define IOPB_RES_ADDR_C 0x0C 457 #define IOPB_RES_ADDR_D 0x0D 458 #define IOPB_SOFT_OVER_WR 0x0E 459 #define IOPB_RES_ADDR_F 0x0F 460 #define IOPB_MEM_CFG 0x10 461 #define IOPB_RES_ADDR_11 0x11 462 #define IOPB_GPIO_DATA 0x12 463 #define IOPB_RES_ADDR_13 0x13 464 #define IOPB_FLASH_PAGE 0x14 465 #define IOPB_RES_ADDR_15 0x15 466 #define IOPB_GPIO_CNTL 0x16 467 #define IOPB_RES_ADDR_17 0x17 468 #define IOPB_FLASH_DATA 0x18 469 #define IOPB_RES_ADDR_19 0x19 470 #define IOPB_RES_ADDR_1A 0x1A 471 #define IOPB_RES_ADDR_1B 0x1B 472 #define IOPB_RES_ADDR_1C 0x1C 473 #define IOPB_RES_ADDR_1D 0x1D 474 #define IOPB_RES_ADDR_1E 0x1E 475 #define IOPB_RES_ADDR_1F 0x1F 476 #define IOPB_DMA_CFG0 0x20 477 #define IOPB_DMA_CFG1 0x21 478 #define IOPB_TICKLE 0x22 479 #define IOPB_DMA_REG_WR 0x23 480 #define IOPB_SDMA_STATUS 0x24 481 #define IOPB_SCSI_BYTE_CNT 0x25 482 #define IOPB_HOST_BYTE_CNT 0x26 483 #define IOPB_BYTE_LEFT_TO_XFER 0x27 484 #define IOPB_BYTE_TO_XFER_0 0x28 485 #define IOPB_BYTE_TO_XFER_1 0x29 486 #define IOPB_BYTE_TO_XFER_2 0x2A 487 #define IOPB_BYTE_TO_XFER_3 0x2B 488 #define IOPB_ACC_GRP 0x2C 489 #define IOPB_RES_ADDR_2D 0x2D 490 #define IOPB_DEV_ID 0x2E 491 #define IOPB_RES_ADDR_2F 0x2F 492 #define IOPB_SCSI_DATA 0x30 493 #define IOPB_RES_ADDR_31 0x31 494 #define IOPB_RES_ADDR_32 0x32 495 #define IOPB_SCSI_DATA_HSHK 0x33 496 #define IOPB_SCSI_CTRL 0x34 497 #define IOPB_RES_ADDR_35 0x35 498 #define IOPB_RES_ADDR_36 0x36 499 #define IOPB_RES_ADDR_37 0x37 500 #define IOPB_RAM_BIST 0x38 501 #define IOPB_PLL_TEST 0x39 502 #define IOPB_PCI_INT_CFG 0x3A 503 #define IOPB_RES_ADDR_3B 0x3B 504 #define IOPB_RFIFO_CNT 0x3C 505 #define IOPB_RES_ADDR_3D 0x3D 506 #define IOPB_RES_ADDR_3E 0x3E 507 #define IOPB_RES_ADDR_3F 0x3F 508 509 /* 510 * Word I/O register address from base of 'iop_base'. 511 */ 512 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 513 #define IOPW_CTRL_REG 0x02 /* CC */ 514 #define IOPW_RAM_ADDR 0x04 /* LA */ 515 #define IOPW_RAM_DATA 0x06 /* LD */ 516 #define IOPW_RES_ADDR_08 0x08 517 #define IOPW_RISC_CSR 0x0A /* CSR */ 518 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 519 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 520 #define IOPW_RES_ADDR_10 0x10 521 #define IOPW_SEL_MASK 0x12 /* SM */ 522 #define IOPW_RES_ADDR_14 0x14 523 #define IOPW_FLASH_ADDR 0x16 /* FA */ 524 #define IOPW_RES_ADDR_18 0x18 525 #define IOPW_EE_CMD 0x1A /* EC */ 526 #define IOPW_EE_DATA 0x1C /* ED */ 527 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 528 #define IOPW_RES_ADDR_20 0x20 529 #define IOPW_Q_BASE 0x22 /* QB */ 530 #define IOPW_QP 0x24 /* QP */ 531 #define IOPW_IX 0x26 /* IX */ 532 #define IOPW_SP 0x28 /* SP */ 533 #define IOPW_PC 0x2A /* PC */ 534 #define IOPW_RES_ADDR_2C 0x2C 535 #define IOPW_RES_ADDR_2E 0x2E 536 #define IOPW_SCSI_DATA 0x30 /* SD */ 537 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 538 #define IOPW_SCSI_CTRL 0x34 /* SC */ 539 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 540 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 541 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 542 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 543 #define IOPW_RES_ADDR_3C 0x3C 544 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 545 546 /* 547 * Doubleword I/O register address from base of 'iop_base'. 548 */ 549 #define IOPDW_RES_ADDR_0 0x00 550 #define IOPDW_RAM_DATA 0x04 551 #define IOPDW_RES_ADDR_8 0x08 552 #define IOPDW_RES_ADDR_C 0x0C 553 #define IOPDW_RES_ADDR_10 0x10 554 #define IOPDW_COMMA 0x14 555 #define IOPDW_COMMB 0x18 556 #define IOPDW_RES_ADDR_1C 0x1C 557 #define IOPDW_SDMA_ADDR0 0x20 558 #define IOPDW_SDMA_ADDR1 0x24 559 #define IOPDW_SDMA_COUNT 0x28 560 #define IOPDW_SDMA_ERROR 0x2C 561 #define IOPDW_RDMA_ADDR0 0x30 562 #define IOPDW_RDMA_ADDR1 0x34 563 #define IOPDW_RDMA_COUNT 0x38 564 #define IOPDW_RDMA_ERROR 0x3C 565 566 #define ADW_CHIP_ID_BYTE 0x25 567 #define ADW_CHIP_ID_WORD 0x04C1 568 569 #define ADW_SC_SCSI_BUS_RESET 0x2000 570 571 #define ADW_INTR_ENABLE_HOST_INTR 0x01 572 #define ADW_INTR_ENABLE_SEL_INTR 0x02 573 #define ADW_INTR_ENABLE_DPR_INTR 0x04 574 #define ADW_INTR_ENABLE_RTA_INTR 0x08 575 #define ADW_INTR_ENABLE_RMA_INTR 0x10 576 #define ADW_INTR_ENABLE_RST_INTR 0x20 577 #define ADW_INTR_ENABLE_DPE_INTR 0x40 578 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80 579 580 #define ADW_INTR_STATUS_INTRA 0x01 581 #define ADW_INTR_STATUS_INTRB 0x02 582 #define ADW_INTR_STATUS_INTRC 0x04 583 584 #define ADW_RISC_CSR_STOP (0x0000) 585 #define ADW_RISC_TEST_COND (0x2000) 586 #define ADW_RISC_CSR_RUN (0x4000) 587 #define ADW_RISC_CSR_SINGLE_STEP (0x8000) 588 589 #define ADW_CTRL_REG_HOST_INTR 0x0100 590 #define ADW_CTRL_REG_SEL_INTR 0x0200 591 #define ADW_CTRL_REG_DPR_INTR 0x0400 592 #define ADW_CTRL_REG_RTA_INTR 0x0800 593 #define ADW_CTRL_REG_RMA_INTR 0x1000 594 #define ADW_CTRL_REG_RES_BIT14 0x2000 595 #define ADW_CTRL_REG_DPE_INTR 0x4000 596 #define ADW_CTRL_REG_POWER_DONE 0x8000 597 #define ADW_CTRL_REG_ANY_INTR 0xFF00 598 599 #define ADW_CTRL_REG_CMD_RESET 0x00C6 600 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5 601 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4 602 #define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 603 #define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 604 605 #define ADV_TICKLE_NOP 0x00 606 #define ADV_TICKLE_A 0x01 607 #define ADV_TICKLE_B 0x02 608 #define ADV_TICKLE_C 0x03 609 610 #define ADW_SCSI_CTRL_RSTOUT 0x2000 611 612 #define ADW_IS_INT_PENDING(iot, ioh) \ 613 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) 614 615 /* 616 * SCSI_CFG0 Register bit definitions 617 */ 618 #define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 619 #define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 620 #define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */ 621 #define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 622 #define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 623 #define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */ 624 #define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */ 625 #define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 626 #define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 627 #define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 628 #define ADW_OUR_ID 0x000F /* SCSI ID */ 629 630 /* 631 * SCSI_CFG1 Register bit definitions 632 */ 633 #define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 634 #define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 635 #define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 636 #define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */ 637 #define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 638 #define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 639 #define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 640 #define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */ 641 #define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 642 #define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 643 #define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 644 #define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */ 645 #define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 646 #define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 647 #define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 648 649 /* 650 * Addendum for ASC-38C0800 Chip 651 * 652 * The ASC-38C1600 Chip uses the same definitions except that the 653 * bus mode override bits [12:10] have been moved to byte register 654 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 655 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 656 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 657 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 658 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 659 */ 660 #define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 661 #define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 662 #define ADW_HVD 0x1000 /* HVD Device Detect */ 663 #define ADW_LVD 0x0800 /* LVD Device Detect */ 664 #define ADW_SE 0x0400 /* SE Device Detect */ 665 #define ADW_TERM_LVD 0x00C0 /* LVD Termination Bits */ 666 #define ADW_TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 667 #define ADW_TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 668 #define ADW_TERM_SE 0x0030 /* SE Termination Bits */ 669 #define ADW_TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 670 #define ADW_TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 671 #define ADW_C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 672 #define ADW_C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 673 #define ADW_C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 674 #define ADW_C_DET_SE 0x0003 /* SE Cable Detect Bits */ 675 #define ADW_C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 676 #define ADW_C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 677 678 679 #define CABLE_ILLEGAL_A 0x7 680 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 681 682 #define CABLE_ILLEGAL_B 0xB 683 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 684 685 /* 686 The following table details the SCSI_CFG1 Termination Polarity, 687 Termination Control and Cable Detect bits. 688 689 Cable Detect | Termination 690 Bit 3 2 1 0 | 5 4 | Notes 691 _____________|________|____________________ 692 1 1 1 0 | on on | Internal wide only 693 1 1 0 1 | on on | Internal narrow only 694 1 0 1 1 | on on | External narrow only 695 0 x 1 1 | on on | External wide only 696 1 1 0 0 | on off| Internal wide and internal narrow 697 1 0 1 0 | on off| Internal wide and external narrow 698 0 x 1 0 | off off| Internal wide and external wide 699 1 0 0 1 | on off| Internal narrow and external narrow 700 0 x 0 1 | on off| Internal narrow and external wide 701 1 1 1 1 | on on | No devices are attached 702 x 0 0 0 | on on | Illegal (all 3 connectors are used) 703 0 x 0 0 | on on | Illegal (all 3 connectors are used) 704 705 x means don't-care (either '0' or '1') 706 707 If term_pol (bit 13) is '0' (active-low terminator enable), then: 708 'on' is '0' and 'off' is '1'. 709 710 If term_pol bit is '1' (meaning active-hi terminator enable), then: 711 'on' is '1' and 'off' is '0'. 712 */ 713 714 /* 715 * MEM_CFG Register bit definitions 716 */ 717 #define ADW_BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 718 #define ADW_FAST_EE_CLK 0x20 /* Diagnostic Bit */ 719 #define ADW_RAM_SZ 0x1C /* Specify size of RAM to RISC */ 720 #define ADW_RAM_SZ_2KB 0x00 /* 2 KB */ 721 #define ADW_RAM_SZ_4KB 0x04 /* 4 KB */ 722 #define ADW_RAM_SZ_8KB 0x08 /* 8 KB */ 723 #define ADW_RAM_SZ_16KB 0x0C /* 16 KB */ 724 #define ADW_RAM_SZ_32KB 0x10 /* 32 KB */ 725 #define ADW_RAM_SZ_64KB 0x14 /* 64 KB */ 726 727 /* 728 * DMA_CFG0 Register bit definitions 729 * 730 * This register is only accessible to the host. 731 */ 732 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 733 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 734 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 735 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 736 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 737 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 738 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 739 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 740 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 741 #define START_CTL 0x0C /* DMA start conditions */ 742 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 743 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 744 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 745 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 746 #define READ_CMD 0x03 /* Memory Read Method */ 747 #define READ_CMD_MR 0x00 /* Memory Read */ 748 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 749 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 750 751 /* 752 * ASC-38C0800 RAM BIST Register bit definitions 753 */ 754 #define RAM_TEST_MODE 0x80 755 #define PRE_TEST_MODE 0x40 756 #define NORMAL_MODE 0x00 757 #define RAM_TEST_DONE 0x10 758 #define RAM_TEST_STATUS 0x0F 759 #define RAM_TEST_HOST_ERROR 0x08 760 #define RAM_TEST_INTRAM_ERROR 0x04 761 #define RAM_TEST_RISC_ERROR 0x02 762 #define RAM_TEST_SCSI_ERROR 0x01 763 #define RAM_TEST_SUCCESS 0x00 764 #define PRE_TEST_VALUE 0x05 765 #define NORMAL_VALUE 0x00 766 767 /* 768 * ASC38C1600 Definitions 769 * 770 * IOPB_PCI_INT_CFG Bit Field Definitions 771 */ 772 773 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 774 775 /* 776 * Bit 1 can be set to change the interrupt for the Function to operate in 777 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 778 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 779 * mode, otherwise the operating mode is undefined. 780 */ 781 #define TOTEMPOLE 0x02 782 783 /* 784 * Bit 0 can be used to change the Int Pin for the Function. The value is 785 * 0 by default for both Functions with Function 0 using INT A and Function 786 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 787 * INT A is used. 788 * 789 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 790 * value specified in the PCI Configuration Space. 791 */ 792 #define INTAB 0x01 793 794 795 /* 796 * Adv Library Status Definitions 797 */ 798 #define ADW_TRUE 1 799 #define ADW_FALSE 0 800 #define ADW_NOERROR 1 801 #define ADW_SUCCESS 1 802 #define ADW_BUSY 0 803 #define ADW_ERROR (-1) 804 805 806 /* 807 * ASC_DVC_VAR 'warn_code' values 808 */ 809 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 810 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 811 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 812 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ 813 #define ASC_WARN_ERROR 0xFFFF /* ADW_ERROR return */ 814 815 #define ADW_MAX_TID 15 /* max. target identifier */ 816 #define ADW_MAX_LUN 7 /* max. logical unit number */ 817 818 819 /* 820 * AscInitGetConfig() and AscInitAsc1000Driver() Definitions 821 * 822 * Error code values are set in ASC_DVC_VAR 'err_code'. 823 */ 824 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ 825 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 826 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ 827 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 828 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ 829 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 830 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ 831 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 832 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ 833 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ 834 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ 835 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ 836 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ 837 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ 838 839 /* 840 * Fixed locations of microcode operating variables. 841 */ 842 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 843 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 844 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 845 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 846 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 847 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 848 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 849 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 850 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ 851 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 852 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 853 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 854 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 855 #define ASC_MC_CHIP_TYPE 0x009A 856 #define ASC_MC_INTRB_CODE 0x009B 857 #define ASC_MC_WDTR_ABLE 0x009C 858 #define ASC_MC_SDTR_ABLE 0x009E 859 #define ASC_MC_TAGQNG_ABLE 0x00A0 860 #define ASC_MC_DISC_ENABLE 0x00A2 861 #define ASC_MC_IDLE_CMD_STATUS 0x00A4 862 #define ASC_MC_IDLE_CMD 0x00A6 863 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 864 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 865 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 866 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 867 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 868 #define ASC_MC_SDTR_DONE 0x00B6 869 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 870 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 871 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 872 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 873 #define ASC_MC_WDTR_DONE 0x0124 874 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 875 #define ASC_MC_ICQ 0x0160 876 #define ASC_MC_IRQ 0x0164 877 #define ASC_MC_PPR_ABLE 0x017A 878 879 /* 880 * BIOS LRAM variable absolute offsets. 881 */ 882 #define BIOS_CODESEG 0x54 883 #define BIOS_CODELEN 0x56 884 #define BIOS_SIGNATURE 0x58 885 #define BIOS_VERSION 0x5A 886 887 /* 888 * Microcode Control Flags 889 * 890 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 891 * and handled by the microcode. 892 */ 893 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 894 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ 895 896 /* 897 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 898 */ 899 #define HSHK_CFG_WIDE_XFR 0x8000 900 #define HSHK_CFG_RATE 0x0F00 901 #define HSHK_CFG_OFFSET 0x001F 902 903 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 904 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 905 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 906 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 907 908 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ 909 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 910 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 911 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 912 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ 913 914 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 915 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 916 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ 917 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 918 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ 919 /* 920 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or 921 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 922 */ 923 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 924 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 925 926 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 927 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 928 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 929 930 /* 931 * Adapter temporary configuration structure 932 * 933 * This structure can be discarded after initialization. Don't add 934 * fields here needed after initialization. 935 * 936 * Field naming convention: 937 * 938 * *_enable indicates the field enables or disables a feature. The 939 * value of the field is never reset. 940 */ 941 typedef struct adw_dvc_cfg { 942 u_int16_t disc_enable; /* enable disconnection */ 943 u_int8_t chip_version; /* chip version */ 944 u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 945 u_int16_t pci_device_id; /* PCI device code number */ 946 u_int16_t lib_version; /* Adv Library version number */ 947 u_int16_t control_flag; /* Microcode Control Flag */ 948 u_int16_t mcode_date; /* Microcode date */ 949 u_int16_t mcode_version; /* Microcode version */ 950 u_int16_t pci_slot_info; /* high byte device/function number */ 951 /* bits 7-3 device num., bits 2-0 function num. */ 952 /* low byte bus num. */ 953 u_int16_t serial1; /* EEPROM serial number word 1 */ 954 u_int16_t serial2; /* EEPROM serial number word 2 */ 955 u_int16_t serial3; /* EEPROM serial number word 3 */ 956 } ADW_DVC_CFG; 957 958 959 #define NO_OF_SG_PER_BLOCK 15 960 961 typedef struct adw_sg_block { 962 u_int8_t reserved1; 963 u_int8_t reserved2; 964 u_int8_t reserved3; 965 u_int8_t sg_cnt; /* Valid entries in block. */ 966 u_int32_t sg_ptr; /* links to next sg block */ 967 struct { 968 u_int32_t sg_addr; /* SG element address */ 969 u_int32_t sg_count; /* SG element count */ 970 } sg_list[NO_OF_SG_PER_BLOCK]; 971 } ADW_SG_BLOCK; 972 973 974 /* 975 * Adapter operation variable structure. 976 * 977 * One structure is required per host adapter. 978 * 979 * Field naming convention: 980 * 981 * *_able indicates both whether a feature should be enabled or disabled 982 * and whether a device is capable of the feature. At initialization 983 * this field may be set, but later if a device is found to be incapable 984 * of the feature, the field is cleared. 985 */ 986 #define CCB_HASH_SIZE 32 /* hash table size for phystokv */ 987 #define CCB_HASH_SHIFT 9 988 #define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1)) 989 990 #define CARRIER_HASH_SIZE 32 /* hash table size for phystokv */ 991 #define CARRIER_HASH_SHIFT 9 992 #define CARRIER_HASH(x) ((((x)) >> CARRIER_HASH_SHIFT) & (CARRIER_HASH_SIZE - 1)) 993 994 typedef int (* ADW_CALLBACK) (int); 995 996 typedef struct adw_softc { 997 998 struct device sc_dev; 999 1000 bus_space_tag_t sc_iot; 1001 bus_space_handle_t sc_ioh; 1002 bus_dma_tag_t sc_dmat; 1003 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 1004 bus_dmamap_t sc_dmamap_carrier; /* maps the carrier structures */ 1005 void *sc_ih; 1006 1007 struct adw_control *sc_control; /* control structures */ 1008 1009 struct adw_carrier *sc_carrhash[CARRIER_HASH_SIZE]; 1010 struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE]; 1011 TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb; 1012 struct scsipi_link sc_link; /* prototype for devs */ 1013 struct scsipi_adapter sc_adapter; 1014 1015 TAILQ_HEAD(, scsipi_xfer) sc_queue; 1016 1017 ADW_CALLBACK isr_callback; /* pointer to function, called in AdvISR() */ 1018 ADW_CALLBACK async_callback; /* pointer to function, called in AdvISR() */ 1019 u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */ 1020 u_int16_t wdtr_able; /* try WDTR for a device */ 1021 u_int16_t sdtr_able; /* try SDTR for a device */ 1022 u_int16_t ultra_able; /* try SDTR Ultra speed for a device */ 1023 u_int16_t sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 1024 u_int16_t sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 1025 u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 1026 u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 1027 u_int16_t tagqng_able; /* try tagged queuing with a device */ 1028 u_int16_t ppr_able; /* PPR message capable per TID bitmask. */ 1029 u_int16_t start_motor; /* start motor command allowed */ 1030 u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */ 1031 u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */ 1032 u_int8_t chip_no; /* should be assigned by caller */ 1033 u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */ 1034 u_int8_t irq_no; /* IRQ number */ 1035 u_int8_t chip_type; /* chip SCSI target ID */ 1036 u_int16_t no_scam; /* scam_tolerant of EEPROM */ 1037 u_int32_t drv_ptr; /* driver pointer to private structure */ 1038 u_int8_t chip_scsi_id; /* chip SCSI target ID */ 1039 u_int8_t bist_err_code; 1040 u_int16_t carr_pending_cnt; /* Count of pending carriers. */ 1041 struct adw_carrier *carr_freelist; /* Carrier free list. */ 1042 struct adw_carrier *icq_sp; /* Initiator command queue stopper pointer. */ 1043 struct adw_carrier *irq_sp; /* Initiator response queue stopper pointer. */ 1044 /* 1045 * Note: The following fields will not be used after initialization. The 1046 * driver may discard the buffer after initialization is done. 1047 */ 1048 ADW_DVC_CFG cfg; /* temporary configuration structure */ 1049 } ADW_SOFTC; 1050 1051 1052 /* 1053 * ADW_SCSI_REQ_Q - microcode request structure 1054 * 1055 * All fields in this structure up to byte 60 are used by the microcode. 1056 * The microcode makes assumptions about the size and ordering of fields 1057 * in this structure. Do not change the structure definition here without 1058 * coordinating the change with the microcode. 1059 */ 1060 typedef struct adw_scsi_req_q { 1061 u_int8_t cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 1062 u_int8_t target_cmd; 1063 u_int8_t target_id; /* Device target identifier. */ 1064 u_int8_t target_lun; /* Device target logical unit number. */ 1065 u_int32_t data_addr; /* Data buffer physical address. */ 1066 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ 1067 u_int32_t sense_addr; /* Sense buffer physical address. */ 1068 u_int32_t carr_pa; /* Carrier p-address */ 1069 u_int8_t mflag; /* Adv Library flag field. */ 1070 u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */ 1071 u_int8_t cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 1072 u_int8_t scsi_cntl; 1073 u_int8_t done_status; /* Completion status. */ 1074 u_int8_t scsi_status; /* SCSI status byte. (see below) */ 1075 u_int8_t host_status; /* Ucode host status. */ 1076 u_int8_t sg_working_ix; /* Ucode working SG variable. */ 1077 u_int8_t cdb[12]; /* SCSI CDB bytes 0-11. */ 1078 u_int32_t sg_real_addr; /* SG list physical address. */ 1079 u_int32_t scsiq_rptr; /* Iternal pointer to ADW_SCSI_REQ_Q */ 1080 u_int8_t cdb16[4]; /* SCSI CDB bytes 12-15. */ 1081 u_int32_t ccb_ptr; /* CCB Physical Address */ 1082 u_int32_t carr_va; /* Carrier v-address (unused) */ 1083 /* 1084 * End of microcode structure - 60 bytes. The rest of the structure 1085 * is used by the Adv Library and ignored by the microcode. 1086 */ 1087 struct scsipi_sense_data *vsense_addr; /* Sense buffer virtual address. */ 1088 u_char *vdata_addr; /* Data buffer virtual address. */ 1089 u_int8_t orig_sense_len; /* Original length of sense buffer. */ 1090 u_int8_t pads[3]; /* padding bytes (align to long) */ 1091 } ADW_SCSI_REQ_Q; 1092 1093 /* 1094 * Microcode idle loop commands 1095 */ 1096 #define IDLE_CMD_COMPLETED 0 1097 #define IDLE_CMD_STOP_CHIP 0x0001 1098 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 1099 #define IDLE_CMD_SEND_INT 0x0004 1100 #define IDLE_CMD_ABORT 0x0008 1101 #define IDLE_CMD_DEVICE_RESET 0x0010 1102 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 1103 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 1104 #define IDLE_CMD_SCSIREQ 0x0080 1105 1106 #define IDLE_CMD_STATUS_SUCCESS 0x0001 1107 #define IDLE_CMD_STATUS_FAILURE 0x0002 1108 1109 /* 1110 * AdvSendIdleCmd() flag definitions. 1111 */ 1112 #define ADW_NOWAIT 0x01 1113 1114 /* 1115 * Wait loop time out values. 1116 */ 1117 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */ 1118 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 1119 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 1120 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */ 1121 #define SCSI_MAX_RETRY 10 /* retry count */ 1122 1123 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 1124 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 1125 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 1126 1127 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 1128 1129 1130 /* Read byte from a register. */ 1131 #define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \ 1132 bus_space_read_1((iot), (ioh), (reg_off)) 1133 1134 /* Write byte to a register. */ 1135 #define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \ 1136 bus_space_write_1((iot), (ioh), (reg_off), (byte)) 1137 1138 /* Read word (2 bytes) from a register. */ 1139 #define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \ 1140 bus_space_read_2((iot), (ioh), (reg_off)) 1141 1142 /* Write word (2 bytes) to a register. */ 1143 #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \ 1144 bus_space_write_2((iot), (ioh), (reg_off), (word)) 1145 1146 /* Write double word (4 bytes) to a register. */ 1147 #define ADW_WRITE_DWORD_REGISTER(iot, ioh, reg_off, dword) \ 1148 bus_space_write_4((iot), (ioh), (reg_off), (dword)) 1149 1150 /* Read byte from LRAM. */ 1151 #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \ 1152 do { \ 1153 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1154 (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \ 1155 } while (0) 1156 1157 /* Write byte to LRAM. */ 1158 #define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \ 1159 do { \ 1160 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1161 bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \ 1162 } while (0) 1163 1164 /* Read word (2 bytes) from LRAM. */ 1165 #define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \ 1166 do { \ 1167 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1168 (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \ 1169 } while (0) 1170 1171 /* Write word (2 bytes) to LRAM. */ 1172 #define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \ 1173 do { \ 1174 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1175 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \ 1176 } while (0) 1177 1178 /* Write double word (4 bytes) to LRAM */ 1179 /* Because of unspecified C language ordering don't use auto-increment. */ 1180 #define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \ 1181 do { \ 1182 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 1183 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 1184 (ushort) ((dword) & 0xFFFF)); \ 1185 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \ 1186 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 1187 (ushort) ((dword >> 16) & 0xFFFF)); \ 1188 } while (0) 1189 1190 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 1191 #define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \ 1192 bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \ 1193 1194 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 1195 #define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \ 1196 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)) 1197 1198 /* 1199 * Define macro to check for Condor signature. 1200 * 1201 * Evaluate to ADW_TRUE if a Condor chip is found the specified port 1202 * address 'iop_base'. Otherwise evalue to ADW_FALSE. 1203 */ 1204 #define ADW_FIND_SIGNATURE(iot, ioh) \ 1205 (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \ 1206 ADW_CHIP_ID_BYTE) && \ 1207 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \ 1208 ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE) 1209 1210 /* 1211 * Define macro to Return the version number of the chip at 'iop_base'. 1212 * 1213 * The second parameter 'bus_type' is currently unused. 1214 */ 1215 #define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \ 1216 ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV) 1217 1218 /* 1219 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must 1220 * match the ASC_SCSI_REQ_Q 'srb_ptr' field. 1221 * 1222 * If the request has not yet been sent to the device it will simply be 1223 * aborted from RISC memory. If the request is disconnected it will be 1224 * aborted on reselection by sending an Abort Message to the target ID. 1225 * 1226 * Return value: 1227 * ADW_TRUE(1) - Queue was successfully aborted. 1228 * ADW_FALSE(0) - Queue was not found on the active queue list. 1229 */ 1230 #define ADW_ABORT_CCB(sc, ccb_ptr) \ 1231 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey) 1232 1233 /* 1234 * Send a Bus Device Reset Message to the specified target ID. 1235 * 1236 * All outstanding commands will be purged if sending the 1237 * Bus Device Reset Message is successful. 1238 * 1239 * Return Value: 1240 * ADW_TRUE(1) - All requests on the target are purged. 1241 * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1242 * are not purged. 1243 */ 1244 #define ADW_RESET_DEVICE(sc, target_id) \ 1245 AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0) 1246 1247 /* 1248 * SCSI Wide Type definition. 1249 */ 1250 #define ADW_SCSI_BIT_ID_TYPE u_int16_t 1251 1252 /* 1253 * AdvInitScsiTarget() 'cntl_flag' options. 1254 */ 1255 #define ADW_SCAN_LUN 0x01 1256 #define ADW_CAPINFO_NOLUN 0x02 1257 1258 /* 1259 * Convert target id to target id bit mask. 1260 */ 1261 #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID)) 1262 1263 /* 1264 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values. 1265 */ 1266 1267 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 1268 #define QD_NO_ERROR 0x01 1269 #define QD_ABORTED_BY_HOST 0x02 1270 #define QD_WITH_ERROR 0x04 1271 1272 #define QHSTA_NO_ERROR 0x00 1273 #define QHSTA_M_SEL_TIMEOUT 0x11 1274 #define QHSTA_M_DATA_OVER_RUN 0x12 1275 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 1276 #define QHSTA_M_QUEUE_ABORTED 0x15 1277 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 1278 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 1279 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 1280 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 1281 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 1282 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 1283 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 1284 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 1285 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 1286 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 1287 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 1288 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 1289 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 1290 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 1291 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 1292 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 1293 #define QHSTA_M_WTM_TIMEOUT 0x41 1294 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 1295 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 1296 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 1297 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 1298 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 1299 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 1300 1301 /* 1302 * SCSI Iquiry structure 1303 */ 1304 1305 #define INQ_CLOCKING_ST_ONLY 0x0 1306 #define INQ_CLOCKING_DT_ONLY 0x1 1307 #define INQ_CLOCKING_ST_AND_DT 0x3 1308 1309 typedef struct { 1310 u_int8_t peri_dvc_type : 5; /* peripheral device type */ 1311 u_int8_t peri_qualifier : 3; /* peripheral qualifier */ 1312 u_int8_t dvc_type_modifier : 7; /* device type modifier (for SCSI I) */ 1313 u_int8_t rmb : 1; /* RMB - removable medium bit */ 1314 u_int8_t ansi_apr_ver : 3; /* ANSI approved version */ 1315 u_int8_t ecma_ver : 3; /* ECMA version */ 1316 u_int8_t iso_ver : 2; /* ISO version */ 1317 u_int8_t rsp_data_fmt : 4; /* response data format */ 1318 /* 0 SCSI 1 */ 1319 /* 1 CCS */ 1320 /* 2 SCSI-2 */ 1321 /* 3-F reserved */ 1322 u_int8_t res1 : 2; /* reserved */ 1323 u_int8_t TemIOP : 1; /* terminate I/O process bit (see 5.6.22) */ 1324 u_int8_t aenc : 1; /* asynch. event notification (processor) */ 1325 u_int8_t add_len; /* additional length */ 1326 u_int8_t res2; /* reserved */ 1327 u_int8_t res3; /* reserved */ 1328 u_int8_t StfRe : 1; /* soft reset implemented */ 1329 u_int8_t CmdQue : 1; /* command queuing */ 1330 u_int8_t res4 : 1; /* reserved */ 1331 u_int8_t Linked : 1; /* linked command for this logical unit */ 1332 u_int8_t Sync : 1; /* synchronous data transfer */ 1333 u_int8_t WBus16 : 1; /* wide bus 16 bit data transfer */ 1334 u_int8_t WBus32 : 1; /* wide bus 32 bit data transfer */ 1335 u_int8_t RelAdr : 1; /* relative addressing mode */ 1336 u_int8_t vendor_id[8]; /* vendor identification */ 1337 u_int8_t product_id[16]; /* product identification */ 1338 u_int8_t product_rev_level[4]; /* product revision level */ 1339 u_int8_t vendor_specific[20]; /* vendor specific */ 1340 u_int8_t IUS : 1; /* information unit supported */ 1341 u_int8_t QAS : 1; /* quick arbitrate supported */ 1342 u_int8_t Clocking : 2; /* clocking field */ 1343 u_int8_t res5 : 4; /* reserved */ 1344 u_int8_t res6; /* reserved */ 1345 } ADW_SCSI_INQUIRY; /* 58 bytes */ 1346 1347 #define SS_GOOD 0x00 1348 #define SS_CHK_CONDITION 0x02 1349 #define SS_CONDITION_MET 0x04 1350 #define SS_TARGET_BUSY 0x08 1351 #define SS_INTERMID 0x10 1352 #define SS_INTERMID_COND_MET 0x14 1353 #define SS_RSERV_CONFLICT 0x18 1354 #define SS_CMD_TERMINATED 0x22 1355 #define SS_QUEUE_FULL 0x28 1356 #define MS_CMD_DONE 0x00 1357 #define MS_EXTEND 0x01 1358 #define MS_SDTR_LEN 0x03 1359 #define MS_SDTR_CODE 0x01 1360 #define MS_WDTR_LEN 0x02 1361 #define MS_WDTR_CODE 0x03 1362 #define MS_MDP_LEN 0x05 1363 #define MS_MDP_CODE 0x00 1364 #define M1_SAVE_DATA_PTR 0x02 1365 #define M1_RESTORE_PTRS 0x03 1366 #define M1_DISCONNECT 0x04 1367 #define M1_INIT_DETECTED_ERR 0x05 1368 #define M1_ABORT 0x06 1369 #define M1_MSG_REJECT 0x07 1370 #define M1_NO_OP 0x08 1371 #define M1_MSG_PARITY_ERR 0x09 1372 #define M1_LINK_CMD_DONE 0x0A 1373 #define M1_LINK_CMD_DONE_WFLAG 0x0B 1374 #define M1_BUS_DVC_RESET 0x0C 1375 #define M1_ABORT_TAG 0x0D 1376 #define M1_CLR_QUEUE 0x0E 1377 #define M1_INIT_RECOVERY 0x0F 1378 #define M1_RELEASE_RECOVERY 0x10 1379 #define M1_KILL_IO_PROC 0x11 1380 #define M2_QTAG_MSG_SIMPLE 0x20 1381 #define M2_QTAG_MSG_HEAD 0x21 1382 #define M2_QTAG_MSG_ORDERED 0x22 1383 #define M2_IGNORE_WIDE_RESIDUE 0x23 1384 1385 1386 #define ASC_MAX_SENSE_LEN 32 1387 #define ASC_MIN_SENSE_LEN 14 1388 1389 typedef struct asc_req_sense { 1390 u_int8_t err_code:7; 1391 u_int8_t info_valid:1; 1392 u_int8_t segment_no; 1393 u_int8_t sense_key:4; 1394 u_int8_t reserved_bit:1; 1395 u_int8_t sense_ILI:1; 1396 u_int8_t sense_EOM:1; 1397 u_int8_t file_mark:1; 1398 u_int8_t info1[4]; 1399 u_int8_t add_sense_len; 1400 u_int8_t cmd_sp_info[4]; 1401 u_int8_t asc; 1402 u_int8_t ascq; 1403 u_int8_t fruc; 1404 u_int8_t sks_byte0:7; 1405 u_int8_t sks_valid:1; 1406 u_int8_t sks_bytes[2]; 1407 u_int8_t notused[2]; 1408 u_int8_t ex_sense_code; 1409 u_int8_t info2[4]; 1410 } ASC_REQ_SENSE; 1411 1412 1413 /* 1414 * Adv Library functions available to drivers. 1415 */ 1416 1417 int AdvInitAsc3550Driver __P((ADW_SOFTC *)); 1418 int AdvInitAsc38C0800Driver __P((ADW_SOFTC *)); 1419 int AdvInitAsc38C1600Driver __P((ADW_SOFTC *)); 1420 int AdvInitFrom3550EEP __P((ADW_SOFTC *)); 1421 int AdvInitFrom38C0800EEP __P((ADW_SOFTC *)); 1422 int AdvInitFrom38C1600EEP __P((ADW_SOFTC *)); 1423 int AdvExeScsiQueue __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 1424 int AdvISR __P((ADW_SOFTC *)); 1425 void AdvResetChip __P((bus_space_tag_t, bus_space_handle_t)); 1426 int AdvSendIdleCmd __P((ADW_SOFTC *, u_int16_t, u_int32_t)); 1427 int AdvResetSCSIBus __P((ADW_SOFTC *)); 1428 int AdvResetCCB __P((ADW_SOFTC *)); 1429 1430 #endif /* _ADVANSYS_WIDE_LIBRARY_H_ */ 1431
Indexes created Tue Sep 23 14:10:03 GMT 2025