ahcisata_core.c revision 1.103
1 /* $NetBSD: ahcisata_core.c,v 1.103 2021/10/11 12:48:10 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.103 2021/10/11 12:48:10 jmcneill Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #include "opt_ahcisata.h" 54 55 #ifdef AHCI_DEBUG 56 int ahcidebug_mask = 0; 57 #endif 58 59 static void ahci_probe_drive(struct ata_channel *); 60 static void ahci_setup_channel(struct ata_channel *); 61 62 static void ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 63 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 64 uint8_t); 65 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 66 static void ahci_reset_channel(struct ata_channel *, int); 67 static void ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 68 static int ahci_ata_addref(struct ata_drive_datas *); 69 static void ahci_ata_delref(struct ata_drive_datas *); 70 static void ahci_killpending(struct ata_drive_datas *); 71 72 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 73 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 74 static int ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 77 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 78 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 79 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 81 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 82 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 83 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 84 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 85 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 86 int, int); 87 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 88 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 89 static int ahci_intr_port_common(struct ata_channel *); 90 91 #if NATAPIBUS > 0 92 static void ahci_atapibus_attach(struct atabus_softc *); 93 static void ahci_atapi_kill_pending(struct scsipi_periph *); 94 static void ahci_atapi_minphys(struct buf *); 95 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 96 scsipi_adapter_req_t, void *); 97 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 98 static int ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 99 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 100 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 101 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 102 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 103 104 static const struct scsipi_bustype ahci_atapi_bustype = { 105 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 106 .bustype_cmd = atapi_scsipi_cmd, 107 .bustype_interpret_sense = atapi_interpret_sense, 108 .bustype_printaddr = atapi_print_addr, 109 .bustype_kill_pending = ahci_atapi_kill_pending, 110 .bustype_async_event_xfer_mode = NULL, 111 }; 112 #endif /* NATAPIBUS */ 113 114 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 115 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 116 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 117 118 const struct ata_bustype ahci_ata_bustype = { 119 .bustype_type = SCSIPI_BUSTYPE_ATA, 120 .ata_bio = ahci_ata_bio, 121 .ata_reset_drive = ahci_reset_drive, 122 .ata_reset_channel = ahci_reset_channel, 123 .ata_exec_command = ahci_exec_command, 124 .ata_get_params = ata_get_params, 125 .ata_addref = ahci_ata_addref, 126 .ata_delref = ahci_ata_delref, 127 .ata_killpending = ahci_killpending, 128 .ata_recovery = ahci_channel_recover, 129 }; 130 131 static void ahci_setup_port(struct ahci_softc *sc, int i); 132 133 static void 134 ahci_enable(struct ahci_softc *sc) 135 { 136 uint32_t ghc; 137 138 ghc = AHCI_READ(sc, AHCI_GHC); 139 if (!(ghc & AHCI_GHC_AE)) { 140 ghc |= AHCI_GHC_AE; 141 AHCI_WRITE(sc, AHCI_GHC, ghc); 142 } 143 } 144 145 static int 146 ahci_reset(struct ahci_softc *sc) 147 { 148 int i; 149 150 /* reset controller */ 151 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 152 /* wait up to 1s for reset to complete */ 153 for (i = 0; i < 1000; i++) { 154 delay(1000); 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 156 break; 157 } 158 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 159 aprint_error("%s: reset failed\n", AHCINAME(sc)); 160 return -1; 161 } 162 /* enable ahci mode */ 163 ahci_enable(sc); 164 165 if (sc->sc_save_init_data) { 166 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 167 if (sc->sc_init_data.cap2) 168 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 169 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 170 } 171 172 /* Check if hardware reverted to single message MSI */ 173 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 174 175 return 0; 176 } 177 178 static void 179 ahci_setup_ports(struct ahci_softc *sc) 180 { 181 int i, port; 182 183 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 184 if ((sc->sc_ahci_ports & (1U << i)) == 0) 185 continue; 186 if (port >= sc->sc_atac.atac_nchannels) { 187 aprint_error("%s: more ports than announced\n", 188 AHCINAME(sc)); 189 break; 190 } 191 ahci_setup_port(sc, i); 192 port++; 193 } 194 } 195 196 static void 197 ahci_reprobe_drives(struct ahci_softc *sc) 198 { 199 int i, port; 200 struct ahci_channel *achp; 201 struct ata_channel *chp; 202 203 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 204 if ((sc->sc_ahci_ports & (1U << i)) == 0) 205 continue; 206 if (port >= sc->sc_atac.atac_nchannels) { 207 aprint_error("%s: more ports than announced\n", 208 AHCINAME(sc)); 209 break; 210 } 211 achp = &sc->sc_channels[i]; 212 chp = &achp->ata_channel; 213 214 ahci_probe_drive(chp); 215 port++; 216 } 217 } 218 219 static void 220 ahci_setup_port(struct ahci_softc *sc, int i) 221 { 222 struct ahci_channel *achp; 223 224 achp = &sc->sc_channels[i]; 225 226 AHCI_WRITE(sc, AHCI_P_CLB(i), BUS_ADDR_LO32(achp->ahcic_bus_cmdh)); 227 AHCI_WRITE(sc, AHCI_P_CLBU(i), BUS_ADDR_HI32(achp->ahcic_bus_cmdh)); 228 AHCI_WRITE(sc, AHCI_P_FB(i), BUS_ADDR_LO32(achp->ahcic_bus_rfis)); 229 AHCI_WRITE(sc, AHCI_P_FBU(i), BUS_ADDR_HI32(achp->ahcic_bus_rfis)); 230 } 231 232 static void 233 ahci_enable_intrs(struct ahci_softc *sc) 234 { 235 236 /* clear interrupts */ 237 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 238 /* enable interrupts */ 239 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 240 } 241 242 void 243 ahci_attach(struct ahci_softc *sc) 244 { 245 uint32_t ahci_rev; 246 int i, j, port; 247 struct ahci_channel *achp; 248 struct ata_channel *chp; 249 int error; 250 int dmasize; 251 char buf[128]; 252 void *cmdhp; 253 void *cmdtblp; 254 255 if (sc->sc_save_init_data) { 256 ahci_enable(sc); 257 258 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 259 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 260 261 ahci_rev = AHCI_READ(sc, AHCI_VS); 262 if (AHCI_VS_MJR(ahci_rev) > 1 || 263 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 264 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 265 } else { 266 sc->sc_init_data.cap2 = 0; 267 } 268 if (sc->sc_init_data.ports == 0) { 269 sc->sc_init_data.ports = sc->sc_ahci_ports; 270 } 271 } 272 273 if (ahci_reset(sc) != 0) 274 return; 275 276 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 277 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 278 aprint_verbose_dev(sc->sc_atac.atac_dev, 279 "ignoring broken port multiplier support\n"); 280 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 281 } 282 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADNCQ) { 283 aprint_verbose_dev(sc->sc_atac.atac_dev, 284 "ignoring broken NCQ support\n"); 285 sc->sc_ahci_cap &= ~AHCI_CAP_NCQ; 286 } 287 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 288 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 289 ahci_rev = AHCI_READ(sc, AHCI_VS); 290 snprintb(buf, sizeof(buf), "\177\020" 291 /* "f\000\005NP\0" */ 292 "b\005SXS\0" 293 "b\006EMS\0" 294 "b\007CCCS\0" 295 /* "f\010\005NCS\0" */ 296 "b\015PSC\0" 297 "b\016SSC\0" 298 "b\017PMD\0" 299 "b\020FBSS\0" 300 "b\021SPM\0" 301 "b\022SAM\0" 302 "b\023SNZO\0" 303 "f\024\003ISS\0" 304 "=\001Gen1\0" 305 "=\002Gen2\0" 306 "=\003Gen3\0" 307 "b\030SCLO\0" 308 "b\031SAL\0" 309 "b\032SALP\0" 310 "b\033SSS\0" 311 "b\034SMPS\0" 312 "b\035SSNTF\0" 313 "b\036SNCQ\0" 314 "b\037S64A\0" 315 "\0", sc->sc_ahci_cap); 316 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 317 ", %d port%s, %d slot%s, CAP %s\n", 318 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 319 sc->sc_atac.atac_nchannels, 320 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 321 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 322 323 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 324 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 325 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 326 sc->sc_atac.atac_pio_cap = 4; 327 sc->sc_atac.atac_dma_cap = 2; 328 sc->sc_atac.atac_udma_cap = 6; 329 sc->sc_atac.atac_channels = sc->sc_chanarray; 330 sc->sc_atac.atac_probe = ahci_probe_drive; 331 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 332 sc->sc_atac.atac_set_modes = ahci_setup_channel; 333 #if NATAPIBUS > 0 334 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 335 #endif 336 337 dmasize = 338 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 339 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 340 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error("%s: unable to allocate command header memory" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 347 sc->sc_cmd_hdr_nseg, dmasize, 348 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 349 if (error) { 350 aprint_error("%s: unable to map command header memory" 351 ", error=%d\n", AHCINAME(sc), error); 352 return; 353 } 354 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 355 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 356 if (error) { 357 aprint_error("%s: unable to create command header map" 358 ", error=%d\n", AHCINAME(sc), error); 359 return; 360 } 361 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 362 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 363 if (error) { 364 aprint_error("%s: unable to load command header map" 365 ", error=%d\n", AHCINAME(sc), error); 366 return; 367 } 368 sc->sc_cmd_hdr = cmdhp; 369 memset(cmdhp, 0, dmasize); 370 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_hdrd, 0, dmasize, 371 BUS_DMASYNC_PREWRITE); 372 373 ahci_enable_intrs(sc); 374 375 if (sc->sc_ahci_ports == 0) { 376 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 377 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 378 DEBUG_PROBE); 379 } 380 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 381 if ((sc->sc_ahci_ports & (1U << i)) == 0) 382 continue; 383 if (port >= sc->sc_atac.atac_nchannels) { 384 aprint_error("%s: more ports than announced\n", 385 AHCINAME(sc)); 386 break; 387 } 388 389 /* Optional intr establish per active port */ 390 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 391 aprint_error("%s: intr establish hook failed\n", 392 AHCINAME(sc)); 393 break; 394 } 395 396 achp = &sc->sc_channels[i]; 397 chp = &achp->ata_channel; 398 sc->sc_chanarray[i] = chp; 399 chp->ch_channel = i; 400 chp->ch_atac = &sc->sc_atac; 401 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 402 if (chp->ch_queue == NULL) { 403 aprint_error("%s port %d: can't allocate memory for " 404 "command queue", AHCINAME(sc), i); 405 break; 406 } 407 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 408 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 409 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 410 BUS_DMA_NOWAIT); 411 if (error) { 412 aprint_error("%s: unable to allocate command table " 413 "memory, error=%d\n", AHCINAME(sc), error); 414 break; 415 } 416 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 417 achp->ahcic_cmd_tbl_nseg, dmasize, 418 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 419 if (error) { 420 aprint_error("%s: unable to map command table memory" 421 ", error=%d\n", AHCINAME(sc), error); 422 break; 423 } 424 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 425 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 426 if (error) { 427 aprint_error("%s: unable to create command table map" 428 ", error=%d\n", AHCINAME(sc), error); 429 break; 430 } 431 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 432 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 433 if (error) { 434 aprint_error("%s: unable to load command table map" 435 ", error=%d\n", AHCINAME(sc), error); 436 break; 437 } 438 memset(cmdtblp, 0, dmasize); 439 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_cmd_tbld, 0, 440 dmasize, BUS_DMASYNC_PREWRITE); 441 achp->ahcic_cmdh = (struct ahci_cmd_header *) 442 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 443 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 444 AHCI_CMDH_SIZE * port; 445 achp->ahcic_rfis = (struct ahci_r_fis *) 446 ((char *)cmdhp + 447 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 448 AHCI_RFIS_SIZE * port); 449 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 450 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 451 AHCI_RFIS_SIZE * port; 452 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 453 "rfis %p (0x%" PRIx64 ")\n", i, 454 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 455 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 456 DEBUG_PROBE); 457 458 for (j = 0; j < sc->sc_ncmds; j++) { 459 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 460 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 461 achp->ahcic_bus_cmd_tbl[j] = 462 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 463 AHCI_CMDTBL_SIZE * j; 464 achp->ahcic_cmdh[j].cmdh_cmdtba = 465 htole64(achp->ahcic_bus_cmd_tbl[j]); 466 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 467 achp->ahcic_cmd_tbl[j], 468 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 469 /* The xfer DMA map */ 470 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 471 AHCI_NPRD, 0x400000 /* 4MB */, 0, 472 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 473 &achp->ahcic_datad[j]); 474 if (error) { 475 aprint_error("%s: couldn't alloc xfer DMA map, " 476 "error=%d\n", AHCINAME(sc), error); 477 goto end; 478 } 479 } 480 ahci_setup_port(sc, i); 481 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 482 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 483 aprint_error("%s: couldn't map port %d " 484 "sata_status regs\n", AHCINAME(sc), i); 485 break; 486 } 487 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 488 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 489 aprint_error("%s: couldn't map port %d " 490 "sata_control regs\n", AHCINAME(sc), i); 491 break; 492 } 493 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 494 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 495 aprint_error("%s: couldn't map port %d " 496 "sata_error regs\n", AHCINAME(sc), i); 497 break; 498 } 499 ata_channel_attach(chp); 500 port++; 501 end: 502 continue; 503 } 504 } 505 506 void 507 ahci_childdetached(struct ahci_softc *sc, device_t child) 508 { 509 struct ahci_channel *achp; 510 struct ata_channel *chp; 511 512 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 513 achp = &sc->sc_channels[i]; 514 chp = &achp->ata_channel; 515 516 if ((sc->sc_ahci_ports & (1U << i)) == 0) 517 continue; 518 519 if (child == chp->atabus) 520 chp->atabus = NULL; 521 } 522 } 523 524 int 525 ahci_detach(struct ahci_softc *sc, int flags) 526 { 527 struct atac_softc *atac; 528 struct ahci_channel *achp; 529 struct ata_channel *chp; 530 struct scsipi_adapter *adapt; 531 int i, j, port; 532 int error; 533 534 atac = &sc->sc_atac; 535 adapt = &atac->atac_atapi_adapter._generic; 536 537 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 538 achp = &sc->sc_channels[i]; 539 chp = &achp->ata_channel; 540 541 if ((sc->sc_ahci_ports & (1U << i)) == 0) 542 continue; 543 if (port >= sc->sc_atac.atac_nchannels) { 544 aprint_error("%s: more ports than announced\n", 545 AHCINAME(sc)); 546 break; 547 } 548 549 if (chp->atabus != NULL) { 550 if ((error = config_detach(chp->atabus, flags)) != 0) 551 return error; 552 553 KASSERT(chp->atabus == NULL); 554 } 555 556 if (chp->ch_flags & ATACH_DETACHED) 557 continue; 558 559 for (j = 0; j < sc->sc_ncmds; j++) 560 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 561 562 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 563 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 564 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 565 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 566 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 567 achp->ahcic_cmd_tbl_nseg); 568 569 ata_channel_detach(chp); 570 port++; 571 } 572 573 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 574 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 575 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 576 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 577 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 578 579 if (adapt->adapt_refcnt != 0) 580 return EBUSY; 581 582 return 0; 583 } 584 585 void 586 ahci_resume(struct ahci_softc *sc) 587 { 588 ahci_reset(sc); 589 ahci_setup_ports(sc); 590 ahci_reprobe_drives(sc); 591 ahci_enable_intrs(sc); 592 } 593 594 int 595 ahci_intr(void *v) 596 { 597 struct ahci_softc *sc = v; 598 uint32_t is, ports; 599 int bit, r = 0; 600 601 while ((is = AHCI_READ(sc, AHCI_IS))) { 602 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 603 DEBUG_INTR); 604 r = 1; 605 ports = is; 606 while ((bit = ffs(ports)) != 0) { 607 bit--; 608 ahci_intr_port_common(&sc->sc_channels[bit].ata_channel); 609 ports &= ~__BIT(bit); 610 } 611 AHCI_WRITE(sc, AHCI_IS, is); 612 } 613 614 return r; 615 } 616 617 int 618 ahci_intr_port(void *v) 619 { 620 struct ahci_channel *achp = v; 621 struct ata_channel *chp = &achp->ata_channel; 622 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 623 int ret; 624 625 ret = ahci_intr_port_common(chp); 626 if (ret) { 627 AHCI_WRITE(sc, AHCI_IS, 1U << chp->ch_channel); 628 } 629 630 return ret; 631 } 632 633 static int 634 ahci_intr_port_common(struct ata_channel *chp) 635 { 636 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 637 uint32_t is, tfd, sact; 638 struct ata_xfer *xfer; 639 int slot = -1; 640 bool recover = false; 641 uint32_t aslots; 642 643 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 644 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 645 646 AHCIDEBUG_PRINT(("ahci_intr_port_common %s port %d " 647 "is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 648 AHCINAME(sc), 649 chp->ch_channel, is, 650 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 651 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 652 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 653 DEBUG_INTR); 654 655 if ((chp->ch_flags & ATACH_NCQ) == 0) { 656 /* Non-NCQ operation */ 657 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 658 } else { 659 /* NCQ operation */ 660 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 661 } 662 663 /* Handle errors */ 664 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 665 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 666 /* Fatal errors */ 667 if (is & AHCI_P_IX_TFES) { 668 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 669 670 if ((chp->ch_flags & ATACH_NCQ) == 0) { 671 /* Slot valid only for Non-NCQ operation */ 672 slot = (AHCI_READ(sc, 673 AHCI_P_CMD(chp->ch_channel)) 674 & AHCI_P_CMD_CCS_MASK) 675 >> AHCI_P_CMD_CCS_SHIFT; 676 } 677 678 AHCIDEBUG_PRINT(( 679 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 680 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 681 DEBUG_INTR); 682 } else { 683 /* mark an error, and set BSY */ 684 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 685 WDCS_ERR | WDCS_BSY; 686 } 687 688 if (is & AHCI_P_IX_IFS) { 689 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 690 AHCINAME(sc), chp->ch_channel, 691 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 692 DEBUG_INTR); 693 } 694 695 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 696 recover = true; 697 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 698 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 699 700 /* D2H Register FIS or Set Device Bits */ 701 if ((tfd & WDCS_ERR) != 0) { 702 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 703 recover = true; 704 705 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 706 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 707 } 708 } else { 709 tfd = 0; 710 } 711 712 if (__predict_false(recover)) 713 ata_channel_freeze(chp); 714 715 aslots = ata_queue_active(chp); 716 717 if (slot >= 0) { 718 if ((aslots & __BIT(slot)) != 0 && 719 (sact & __BIT(slot)) == 0) { 720 xfer = ata_queue_hwslot_to_xfer(chp, slot); 721 xfer->ops->c_intr(chp, xfer, tfd); 722 } 723 } else { 724 /* 725 * For NCQ, HBA halts processing when error is notified, 726 * and any further D2H FISes are ignored until the error 727 * condition is cleared. Hence if a command is inactive, 728 * it means it actually already finished successfully. 729 * Note: active slots can change as c_intr() callback 730 * can activate another command(s), so must only process 731 * commands active before we start processing. 732 */ 733 734 for (slot = 0; slot < sc->sc_ncmds; slot++) { 735 if ((aslots & __BIT(slot)) != 0 && 736 (sact & __BIT(slot)) == 0) { 737 xfer = ata_queue_hwslot_to_xfer(chp, slot); 738 xfer->ops->c_intr(chp, xfer, tfd); 739 } 740 } 741 } 742 743 if (__predict_false(recover)) { 744 ata_channel_lock(chp); 745 ata_channel_thaw_locked(chp); 746 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 747 ata_channel_unlock(chp); 748 } 749 750 return 1; 751 } 752 753 static void 754 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 755 { 756 struct ata_channel *chp = drvp->chnl_softc; 757 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 758 uint8_t c_slot; 759 760 ata_channel_lock_owned(chp); 761 762 /* get a slot for running the command on */ 763 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 764 panic("%s: %s: failed to get xfer for reset, port %d\n", 765 device_xname(sc->sc_atac.atac_dev), 766 __func__, chp->ch_channel); 767 /* NOTREACHED */ 768 } 769 770 AHCI_WRITE(sc, AHCI_GHC, 771 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 772 ahci_channel_stop(sc, chp, flags); 773 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 774 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 775 776 ata_queue_free_slot(chp, c_slot); 777 } 778 779 /* return error code from ata_bio */ 780 static int 781 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 782 { 783 struct ahci_channel *achp = (struct ahci_channel *)chp; 784 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 785 int i; 786 uint32_t is; 787 788 /* 789 * Base timeout is specified in ms. Delay for 10ms 790 * on each round. 791 */ 792 timeout = timeout / 10; 793 794 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 795 AHCI_CMDH_SYNC(sc, achp, slot, 796 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 797 /* start command */ 798 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 799 for (i = 0; i < timeout; i++) { 800 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 801 0) 802 return 0; 803 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 804 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 805 AHCI_P_IX_IFS | 806 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 807 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 808 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 809 /* 810 * we got the D2H FIS anyway, 811 * assume sig is valid. 812 * channel is restarted later 813 */ 814 return ERROR; 815 } 816 aprint_debug("%s port %d: error 0x%x sending FIS\n", 817 AHCINAME(sc), chp->ch_channel, is); 818 return ERR_DF; 819 } 820 ata_delay(chp, 10, "ahcifis", flags); 821 } 822 823 aprint_debug("%s port %d: timeout sending FIS\n", 824 AHCINAME(sc), chp->ch_channel); 825 return TIMEOUT; 826 } 827 828 static int 829 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 830 uint32_t *sigp, uint8_t c_slot) 831 { 832 struct ahci_channel *achp = (struct ahci_channel *)chp; 833 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 834 struct ahci_cmd_tbl *cmd_tbl; 835 struct ahci_cmd_header *cmd_h; 836 int i, error = 0; 837 uint32_t sig, cmd; 838 int noclo_retry = 0, retry; 839 840 ata_channel_lock_owned(chp); 841 842 again: 843 /* clear port interrupt register */ 844 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 845 /* clear SErrors and start operations */ 846 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 847 /* 848 * issue a command list override to clear BSY. 849 * This is needed if there's a PMP with no drive 850 * on port 0 851 */ 852 ahci_channel_start(sc, chp, flags, 1); 853 } else { 854 /* Can't handle command still running without CLO */ 855 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 856 if ((cmd & AHCI_P_CMD_CR) != 0) { 857 ahci_channel_stop(sc, chp, flags); 858 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 859 if ((cmd & AHCI_P_CMD_CR) != 0) { 860 aprint_error("%s port %d: DMA engine busy " 861 "for drive %d\n", AHCINAME(sc), 862 chp->ch_channel, drive); 863 error = EBUSY; 864 goto end; 865 } 866 } 867 868 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 869 870 ahci_channel_start(sc, chp, flags, 0); 871 } 872 if (drive > 0) { 873 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 874 } 875 876 /* polled command, assume interrupts are disabled */ 877 878 cmd_h = &achp->ahcic_cmdh[c_slot]; 879 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 880 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 881 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 882 cmd_h->cmdh_prdtl = 0; 883 cmd_h->cmdh_prdbc = 0; 884 memset(cmd_tbl->cmdt_cfis, 0, 64); 885 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 886 cmd_tbl->cmdt_cfis[rhd_c] = drive; 887 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 888 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 889 case ERR_DF: 890 case TIMEOUT: 891 /* 892 * without CLO we can't make sure a software reset will 893 * success, as the drive may still have BSY or DRQ set. 894 * in this case, reset the whole channel and retry the 895 * drive reset. The channel reset should clear BSY and DRQ 896 */ 897 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 898 noclo_retry++; 899 ahci_reset_channel(chp, flags); 900 goto again; 901 } 902 aprint_error("%s port %d: setting WDCTL_RST failed " 903 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 904 error = EBUSY; 905 goto end; 906 default: 907 break; 908 } 909 910 /* 911 * SATA specification has toggle period for SRST bit of 5 usec. Some 912 * controllers fail to process the SRST clear operation unless 913 * we wait for at least this period between the set and clear commands. 914 */ 915 ata_delay(chp, 10, "ahcirstw", flags); 916 917 /* 918 * Try to clear WDCTL_RST a few times before giving up. 919 */ 920 for (error = EBUSY, retry = 0; error != 0 && retry < 5; retry++) { 921 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 922 (drive << AHCI_CMDH_F_PMP_SHIFT)); 923 cmd_h->cmdh_prdbc = 0; 924 memset(cmd_tbl->cmdt_cfis, 0, 64); 925 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 926 cmd_tbl->cmdt_cfis[rhd_c] = drive; 927 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 928 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 929 case ERR_DF: 930 case TIMEOUT: 931 error = EBUSY; 932 break; 933 default: 934 error = 0; 935 break; 936 } 937 if (error == 0) { 938 break; 939 } 940 } 941 if (error == EBUSY) { 942 aprint_error("%s port %d: clearing WDCTL_RST failed " 943 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 944 goto end; 945 } 946 947 /* 948 * wait 31s for BSY to clear 949 * This should not be needed, but some controllers clear the 950 * command slot before receiving the D2H FIS ... 951 */ 952 for (i = 0; i < AHCI_RST_WAIT; i++) { 953 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 954 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 955 break; 956 ata_delay(chp, 10, "ahcid2h", flags); 957 } 958 if (i == AHCI_RST_WAIT) { 959 aprint_error("%s: BSY never cleared, TD 0x%x\n", 960 AHCINAME(sc), sig); 961 goto end; 962 } 963 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 964 DEBUG_PROBE); 965 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 966 if (sigp) 967 *sigp = sig; 968 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 969 AHCINAME(sc), chp->ch_channel, sig, 970 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 971 end: 972 ahci_channel_stop(sc, chp, flags); 973 #ifdef AHCISATA_EXTRA_DELAY 974 ata_delay(chp, 500, "ahcirst", flags); 975 #endif 976 /* clear port interrupt register */ 977 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 978 ahci_channel_start(sc, chp, flags, 979 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 980 return error; 981 } 982 983 static void 984 ahci_reset_channel(struct ata_channel *chp, int flags) 985 { 986 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 987 struct ahci_channel *achp = (struct ahci_channel *)chp; 988 int i, tfd; 989 990 ata_channel_lock_owned(chp); 991 992 ahci_channel_stop(sc, chp, flags); 993 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 994 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 995 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 996 /* XXX and then ? */ 997 } 998 ata_kill_active(chp, KILL_RESET, flags); 999 #ifdef AHCISATA_EXTRA_DELAY 1000 ata_delay(chp, 500, "ahcirst", flags); 1001 #endif 1002 /* clear port interrupt register */ 1003 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1004 /* clear SErrors and start operations */ 1005 ahci_channel_start(sc, chp, flags, 1006 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1007 /* wait 31s for BSY to clear */ 1008 for (i = 0; i < AHCI_RST_WAIT; i++) { 1009 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 1010 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 1011 break; 1012 ata_delay(chp, 10, "ahcid2h", flags); 1013 } 1014 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 1015 aprint_error("%s: BSY never cleared, TD 0x%x\n", 1016 AHCINAME(sc), tfd); 1017 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 1018 DEBUG_PROBE); 1019 /* clear port interrupt register */ 1020 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1021 1022 return; 1023 } 1024 1025 static int 1026 ahci_ata_addref(struct ata_drive_datas *drvp) 1027 { 1028 return 0; 1029 } 1030 1031 static void 1032 ahci_ata_delref(struct ata_drive_datas *drvp) 1033 { 1034 return; 1035 } 1036 1037 static void 1038 ahci_killpending(struct ata_drive_datas *drvp) 1039 { 1040 return; 1041 } 1042 1043 static void 1044 ahci_probe_drive(struct ata_channel *chp) 1045 { 1046 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1047 struct ahci_channel *achp = (struct ahci_channel *)chp; 1048 uint32_t sig; 1049 uint8_t c_slot; 1050 int error; 1051 1052 ata_channel_lock(chp); 1053 1054 /* get a slot for running the command on */ 1055 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1056 aprint_error_dev(sc->sc_atac.atac_dev, 1057 "%s: failed to get xfer port %d\n", 1058 __func__, chp->ch_channel); 1059 ata_channel_unlock(chp); 1060 return; 1061 } 1062 1063 /* bring interface up, accept FISs, power up and spin up device */ 1064 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1065 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1066 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1067 /* reset the PHY and bring online */ 1068 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1069 achp->ahcic_sstatus, AT_WAIT)) { 1070 case SStatus_DET_DEV: 1071 #ifdef AHCISATA_EXTRA_DELAY 1072 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1073 #endif 1074 1075 /* Initial value, used in case the soft reset fails */ 1076 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1077 1078 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1079 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1080 &sig, c_slot); 1081 1082 /* If probe for PMP failed, just fallback to drive 0 */ 1083 if (error) { 1084 aprint_error("%s port %d: drive %d reset " 1085 "failed, disabling PMP\n", 1086 AHCINAME(sc), chp->ch_channel, 1087 PMP_PORT_CTL); 1088 1089 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1090 ahci_reset_channel(chp, AT_WAIT); 1091 } 1092 } else { 1093 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1094 } 1095 sata_interpret_sig(chp, 0, sig); 1096 /* if we have a PMP attached, inform the controller */ 1097 if (chp->ch_ndrives > PMP_PORT_CTL && 1098 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1099 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1100 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1101 AHCI_P_CMD_PMA); 1102 } 1103 /* clear port interrupt register */ 1104 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1105 1106 /* and enable interrupts */ 1107 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1108 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1109 AHCI_P_IX_IFS | 1110 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1111 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1112 #ifdef AHCISATA_EXTRA_DELAY 1113 /* wait 500ms before actually starting operations */ 1114 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1115 #endif 1116 break; 1117 1118 default: 1119 break; 1120 } 1121 1122 ata_queue_free_slot(chp, c_slot); 1123 1124 ata_channel_unlock(chp); 1125 } 1126 1127 static void 1128 ahci_setup_channel(struct ata_channel *chp) 1129 { 1130 return; 1131 } 1132 1133 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1134 .c_start = ahci_cmd_start, 1135 .c_poll = ahci_cmd_poll, 1136 .c_abort = ahci_cmd_abort, 1137 .c_intr = ahci_cmd_complete, 1138 .c_kill_xfer = ahci_cmd_kill_xfer, 1139 }; 1140 1141 static void 1142 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1143 { 1144 struct ata_channel *chp = drvp->chnl_softc; 1145 struct ata_command *ata_c = &xfer->c_ata_c; 1146 1147 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1148 chp->ch_channel, 1149 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1150 DEBUG_XFERS); 1151 if (ata_c->flags & AT_POLL) 1152 xfer->c_flags |= C_POLL; 1153 if (ata_c->flags & AT_WAIT) 1154 xfer->c_flags |= C_WAIT; 1155 xfer->c_drive = drvp->drive; 1156 xfer->c_databuf = ata_c->data; 1157 xfer->c_bcount = ata_c->bcount; 1158 xfer->ops = &ahci_cmd_xfer_ops; 1159 1160 ata_exec_xfer(chp, xfer); 1161 } 1162 1163 static int 1164 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1165 { 1166 struct ahci_softc *sc = AHCI_CH2SC(chp); 1167 struct ahci_channel *achp = (struct ahci_channel *)chp; 1168 struct ata_command *ata_c = &xfer->c_ata_c; 1169 int slot = xfer->c_slot; 1170 struct ahci_cmd_tbl *cmd_tbl; 1171 struct ahci_cmd_header *cmd_h; 1172 1173 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1174 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1175 ata_c->timeout, slot), 1176 DEBUG_XFERS); 1177 1178 ata_channel_lock_owned(chp); 1179 1180 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1181 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1182 cmd_tbl), DEBUG_XFERS); 1183 1184 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1185 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1186 1187 cmd_h = &achp->ahcic_cmdh[slot]; 1188 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1189 chp->ch_channel, cmd_h), DEBUG_XFERS); 1190 if (ahci_dma_setup(chp, slot, 1191 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1192 ata_c->data : NULL, 1193 ata_c->bcount, 1194 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1195 ata_c->flags |= AT_DF; 1196 return ATASTART_ABORT; 1197 } 1198 cmd_h->cmdh_flags = htole16( 1199 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1200 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1201 cmd_h->cmdh_prdbc = 0; 1202 AHCI_CMDH_SYNC(sc, achp, slot, 1203 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1204 1205 if (ata_c->flags & AT_POLL) { 1206 /* polled command, disable interrupts */ 1207 AHCI_WRITE(sc, AHCI_GHC, 1208 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1209 } 1210 /* start command */ 1211 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1212 1213 if ((ata_c->flags & AT_POLL) == 0) { 1214 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1215 ata_timeout, chp); 1216 return ATASTART_STARTED; 1217 } else 1218 return ATASTART_POLL; 1219 } 1220 1221 static int 1222 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1223 { 1224 struct ahci_softc *sc = AHCI_CH2SC(chp); 1225 struct ahci_channel *achp = (struct ahci_channel *)chp; 1226 1227 ata_channel_lock(chp); 1228 1229 /* 1230 * Polled command. 1231 */ 1232 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1233 if (xfer->c_ata_c.flags & AT_DONE) 1234 break; 1235 ata_channel_unlock(chp); 1236 ahci_intr_port(achp); 1237 ata_channel_lock(chp); 1238 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1239 } 1240 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1241 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1242 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1243 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1244 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1245 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1246 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1247 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1248 DEBUG_XFERS); 1249 1250 ata_channel_unlock(chp); 1251 1252 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1253 xfer->c_ata_c.flags |= AT_TIMEOU; 1254 xfer->ops->c_intr(chp, xfer, 0); 1255 } 1256 /* reenable interrupts */ 1257 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1258 1259 return ATAPOLL_DONE; 1260 } 1261 1262 static void 1263 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1264 { 1265 ahci_cmd_complete(chp, xfer, 0); 1266 } 1267 1268 static void 1269 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1270 { 1271 struct ata_command *ata_c = &xfer->c_ata_c; 1272 bool deactivate = true; 1273 1274 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1275 DEBUG_FUNCS); 1276 1277 switch (reason) { 1278 case KILL_GONE_INACTIVE: 1279 deactivate = false; 1280 /* FALLTHROUGH */ 1281 case KILL_GONE: 1282 ata_c->flags |= AT_GONE; 1283 break; 1284 case KILL_RESET: 1285 ata_c->flags |= AT_RESET; 1286 break; 1287 case KILL_REQUEUE: 1288 panic("%s: not supposed to be requeued\n", __func__); 1289 break; 1290 default: 1291 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1292 panic("ahci_cmd_kill_xfer"); 1293 } 1294 1295 ahci_cmd_done_end(chp, xfer); 1296 1297 if (deactivate) 1298 ata_deactivate_xfer(chp, xfer); 1299 } 1300 1301 static int 1302 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1303 { 1304 struct ata_command *ata_c = &xfer->c_ata_c; 1305 struct ahci_channel *achp = (struct ahci_channel *)chp; 1306 struct ahci_softc *sc = AHCI_CH2SC(chp); 1307 1308 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1309 chp->ch_channel, 1310 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1311 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1312 DEBUG_FUNCS); 1313 1314 if (ata_waitdrain_xfer_check(chp, xfer)) 1315 return 0; 1316 1317 if (xfer->c_flags & C_TIMEOU) { 1318 ata_c->flags |= AT_TIMEOU; 1319 } 1320 1321 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1322 ata_c->flags |= AT_TIMEOU; 1323 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1324 ata_c->r_error = AHCI_TFD_ERR(tfd); 1325 ata_c->flags |= AT_ERROR; 1326 } 1327 1328 if (ata_c->flags & AT_READREG) { 1329 AHCI_RFIS_SYNC(sc, achp, BUS_DMASYNC_POSTREAD); 1330 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1331 } 1332 1333 ahci_cmd_done(chp, xfer); 1334 1335 ata_deactivate_xfer(chp, xfer); 1336 1337 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1338 atastart(chp); 1339 1340 return 0; 1341 } 1342 1343 static void 1344 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1345 { 1346 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1347 struct ahci_channel *achp = (struct ahci_channel *)chp; 1348 struct ata_command *ata_c = &xfer->c_ata_c; 1349 uint16_t *idwordbuf; 1350 int i; 1351 1352 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1353 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1354 1355 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1356 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1357 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1358 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1359 BUS_DMASYNC_POSTWRITE); 1360 bus_dmamap_unload(sc->sc_dmat, map); 1361 } 1362 1363 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1364 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1365 1366 /* ata(4) expects IDENTIFY data to be in host endianess */ 1367 if (ata_c->r_command == WDCC_IDENTIFY || 1368 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1369 idwordbuf = xfer->c_databuf; 1370 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1371 idwordbuf[i] = le16toh(idwordbuf[i]); 1372 } 1373 } 1374 1375 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1376 ata_c->flags |= AT_XFDONE; 1377 1378 ahci_cmd_done_end(chp, xfer); 1379 } 1380 1381 static void 1382 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1383 { 1384 struct ata_command *ata_c = &xfer->c_ata_c; 1385 1386 ata_c->flags |= AT_DONE; 1387 } 1388 1389 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1390 .c_start = ahci_bio_start, 1391 .c_poll = ahci_bio_poll, 1392 .c_abort = ahci_bio_abort, 1393 .c_intr = ahci_bio_complete, 1394 .c_kill_xfer = ahci_bio_kill_xfer, 1395 }; 1396 1397 static void 1398 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1399 { 1400 struct ata_channel *chp = drvp->chnl_softc; 1401 struct ata_bio *ata_bio = &xfer->c_bio; 1402 1403 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1404 chp->ch_channel, 1405 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1406 DEBUG_XFERS); 1407 if (ata_bio->flags & ATA_POLL) 1408 xfer->c_flags |= C_POLL; 1409 xfer->c_drive = drvp->drive; 1410 xfer->c_databuf = ata_bio->databuf; 1411 xfer->c_bcount = ata_bio->bcount; 1412 xfer->ops = &ahci_bio_xfer_ops; 1413 ata_exec_xfer(chp, xfer); 1414 } 1415 1416 static int 1417 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1418 { 1419 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1420 struct ahci_channel *achp = (struct ahci_channel *)chp; 1421 struct ata_bio *ata_bio = &xfer->c_bio; 1422 struct ahci_cmd_tbl *cmd_tbl; 1423 struct ahci_cmd_header *cmd_h; 1424 1425 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1426 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1427 1428 ata_channel_lock_owned(chp); 1429 1430 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1431 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1432 cmd_tbl), DEBUG_XFERS); 1433 1434 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1435 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1436 1437 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1438 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1439 chp->ch_channel, cmd_h), DEBUG_XFERS); 1440 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1441 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1442 ata_bio->error = ERR_DMA; 1443 ata_bio->r_error = 0; 1444 return ATASTART_ABORT; 1445 } 1446 cmd_h->cmdh_flags = htole16( 1447 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1448 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1449 cmd_h->cmdh_prdbc = 0; 1450 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1451 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1452 1453 if (xfer->c_flags & C_POLL) { 1454 /* polled command, disable interrupts */ 1455 AHCI_WRITE(sc, AHCI_GHC, 1456 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1457 } 1458 if (xfer->c_flags & C_NCQ) 1459 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1460 /* start command */ 1461 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1462 1463 if ((xfer->c_flags & C_POLL) == 0) { 1464 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1465 ata_timeout, chp); 1466 return ATASTART_STARTED; 1467 } else 1468 return ATASTART_POLL; 1469 } 1470 1471 static int 1472 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1473 { 1474 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1475 struct ahci_channel *achp = (struct ahci_channel *)chp; 1476 1477 /* 1478 * Polled command. 1479 */ 1480 for (int i = 0; i < ATA_DELAY * 10; i++) { 1481 if (xfer->c_bio.flags & ATA_ITSDONE) 1482 break; 1483 ahci_intr_port(achp); 1484 delay(100); 1485 } 1486 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1487 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1488 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1489 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1490 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1491 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1492 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1493 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1494 DEBUG_XFERS); 1495 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1496 xfer->c_bio.error = TIMEOUT; 1497 xfer->ops->c_intr(chp, xfer, 0); 1498 } 1499 /* reenable interrupts */ 1500 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1501 return ATAPOLL_DONE; 1502 } 1503 1504 static void 1505 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1506 { 1507 ahci_bio_complete(chp, xfer, 0); 1508 } 1509 1510 static void 1511 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1512 { 1513 int drive = xfer->c_drive; 1514 struct ata_bio *ata_bio = &xfer->c_bio; 1515 bool deactivate = true; 1516 1517 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1518 DEBUG_FUNCS); 1519 1520 ata_bio->flags |= ATA_ITSDONE; 1521 switch (reason) { 1522 case KILL_GONE_INACTIVE: 1523 deactivate = false; 1524 /* FALLTHROUGH */ 1525 case KILL_GONE: 1526 ata_bio->error = ERR_NODEV; 1527 break; 1528 case KILL_RESET: 1529 ata_bio->error = ERR_RESET; 1530 break; 1531 case KILL_REQUEUE: 1532 ata_bio->error = REQUEUE; 1533 break; 1534 default: 1535 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1536 panic("ahci_bio_kill_xfer"); 1537 } 1538 ata_bio->r_error = WDCE_ABRT; 1539 1540 if (deactivate) 1541 ata_deactivate_xfer(chp, xfer); 1542 1543 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1544 } 1545 1546 static int 1547 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1548 { 1549 struct ata_bio *ata_bio = &xfer->c_bio; 1550 int drive = xfer->c_drive; 1551 struct ahci_channel *achp = (struct ahci_channel *)chp; 1552 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1553 1554 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1555 DEBUG_FUNCS); 1556 1557 if (ata_waitdrain_xfer_check(chp, xfer)) 1558 return 0; 1559 1560 if (xfer->c_flags & C_TIMEOU) { 1561 ata_bio->error = TIMEOUT; 1562 } 1563 1564 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1565 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1566 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1567 BUS_DMASYNC_POSTWRITE); 1568 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1569 1570 ata_bio->flags |= ATA_ITSDONE; 1571 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1572 ata_bio->error = ERR_DF; 1573 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1574 ata_bio->error = ERROR; 1575 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1576 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1577 ata_bio->flags |= ATA_CORR; 1578 1579 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1580 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1581 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1582 ata_bio->bcount), DEBUG_XFERS); 1583 /* 1584 * If it was a write, complete data buffer may have been transferred 1585 * before error detection; in this case don't use cmdh_prdbc 1586 * as it won't reflect what was written to media. Assume nothing 1587 * was transferred and leave bcount as-is. 1588 * For queued commands, PRD Byte Count should not be used, and is 1589 * not required to be valid; in that case underflow is always illegal. 1590 */ 1591 if ((xfer->c_flags & C_NCQ) != 0) { 1592 if (ata_bio->error == NOERROR) 1593 ata_bio->bcount = 0; 1594 } else { 1595 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1596 ata_bio->bcount -= 1597 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1598 } 1599 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1600 1601 ata_deactivate_xfer(chp, xfer); 1602 1603 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1604 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1605 atastart(chp); 1606 return 0; 1607 } 1608 1609 static void 1610 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1611 { 1612 int i; 1613 /* stop channel */ 1614 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1615 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1616 /* wait 1s for channel to stop */ 1617 for (i = 0; i <100; i++) { 1618 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1619 == 0) 1620 break; 1621 ata_delay(chp, 10, "ahcistop", flags); 1622 } 1623 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1624 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1625 /* XXX controller reset ? */ 1626 return; 1627 } 1628 1629 if (sc->sc_channel_stop) 1630 sc->sc_channel_stop(sc, chp); 1631 } 1632 1633 static void 1634 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1635 int flags, int clo) 1636 { 1637 int i; 1638 uint32_t p_cmd; 1639 /* clear error */ 1640 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1641 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1642 1643 if (clo) { 1644 /* issue command list override */ 1645 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1646 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1647 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1648 /* wait 1s for AHCI_CAP_CLO to clear */ 1649 for (i = 0; i <100; i++) { 1650 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1651 AHCI_P_CMD_CLO) == 0) 1652 break; 1653 ata_delay(chp, 10, "ahciclo", flags); 1654 } 1655 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1656 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1657 /* XXX controller reset ? */ 1658 return; 1659 } 1660 } 1661 1662 if (sc->sc_channel_start) 1663 sc->sc_channel_start(sc, chp); 1664 1665 /* and start controller */ 1666 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1667 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1668 if (chp->ch_ndrives > PMP_PORT_CTL && 1669 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1670 p_cmd |= AHCI_P_CMD_PMA; 1671 } 1672 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1673 } 1674 1675 /* Recover channel after command failure */ 1676 static void 1677 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1678 { 1679 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1680 int drive = ATACH_NODRIVE; 1681 bool reset = false; 1682 1683 ata_channel_lock_owned(chp); 1684 1685 /* 1686 * Read FBS to get the drive which caused the error, if PM is in use. 1687 * According to AHCI 1.3 spec, this register is available regardless 1688 * if FIS-based switching (FBSS) feature is supported, or disabled. 1689 * If FIS-based switching is not in use, it merely maintains single 1690 * pair of DRQ/BSY state, but it is enough since in that case we 1691 * never issue commands for more than one device at the time anyway. 1692 * XXX untested 1693 */ 1694 if (chp->ch_ndrives > PMP_PORT_CTL) { 1695 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1696 if (fbs & AHCI_P_FBS_SDE) { 1697 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1698 1699 /* 1700 * Tell HBA to reset PM port X (value in DWE) state, 1701 * and resume processing commands for other ports. 1702 */ 1703 fbs |= AHCI_P_FBS_DEC; 1704 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1705 for (int i = 0; i < 1000; i++) { 1706 fbs = AHCI_READ(sc, 1707 AHCI_P_FBS(chp->ch_channel)); 1708 if ((fbs & AHCI_P_FBS_DEC) == 0) 1709 break; 1710 DELAY(1000); 1711 } 1712 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1713 /* follow non-device specific recovery */ 1714 drive = ATACH_NODRIVE; 1715 reset = true; 1716 } 1717 } else { 1718 /* not device specific, reset channel */ 1719 drive = ATACH_NODRIVE; 1720 reset = true; 1721 } 1722 } else 1723 drive = 0; 1724 1725 /* 1726 * If BSY or DRQ bits are set, must execute COMRESET to return 1727 * device to idle state. If drive is idle, it's enough to just 1728 * reset CMD.ST, it's not necessary to do software reset. 1729 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1730 * to unblock device processing if COMRESET was not done. 1731 */ 1732 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1733 ahci_reset_channel(chp, flags); 1734 goto out; 1735 } 1736 1737 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1738 ahci_channel_stop(sc, chp, flags); 1739 ahci_channel_start(sc, chp, flags, 1740 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1741 1742 ata_recovery_resume(chp, drive, tfd, flags); 1743 1744 out: 1745 /* Drive unblocked, back to normal operation */ 1746 return; 1747 } 1748 1749 static int 1750 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1751 size_t count, int op) 1752 { 1753 int error, seg; 1754 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1755 struct ahci_channel *achp = (struct ahci_channel *)chp; 1756 struct ahci_cmd_tbl *cmd_tbl; 1757 struct ahci_cmd_header *cmd_h; 1758 1759 cmd_h = &achp->ahcic_cmdh[slot]; 1760 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1761 1762 if (data == NULL) { 1763 cmd_h->cmdh_prdtl = 0; 1764 goto end; 1765 } 1766 1767 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1768 data, count, NULL, 1769 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1770 if (error) { 1771 printf("%s port %d: failed to load xfer: %d\n", 1772 AHCINAME(sc), chp->ch_channel, error); 1773 return error; 1774 } 1775 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1776 achp->ahcic_datad[slot]->dm_mapsize, 1777 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1778 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1779 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1780 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1781 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1782 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1783 } 1784 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1785 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1786 end: 1787 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1788 return 0; 1789 } 1790 1791 #if NATAPIBUS > 0 1792 static void 1793 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1794 { 1795 struct ata_channel *chp = ata_sc->sc_chan; 1796 struct atac_softc *atac = chp->ch_atac; 1797 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1798 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1799 /* 1800 * Fill in the scsipi_adapter. 1801 */ 1802 adapt->adapt_dev = atac->atac_dev; 1803 adapt->adapt_nchannels = atac->atac_nchannels; 1804 adapt->adapt_request = ahci_atapi_scsipi_request; 1805 adapt->adapt_minphys = ahci_atapi_minphys; 1806 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1807 1808 /* 1809 * Fill in the scsipi_channel. 1810 */ 1811 memset(chan, 0, sizeof(*chan)); 1812 chan->chan_adapter = adapt; 1813 chan->chan_bustype = &ahci_atapi_bustype; 1814 chan->chan_channel = chp->ch_channel; 1815 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1816 chan->chan_openings = 1; 1817 chan->chan_max_periph = 1; 1818 chan->chan_ntargets = 1; 1819 chan->chan_nluns = 1; 1820 chp->atapibus = config_found(ata_sc->sc_dev, chan, atapiprint, 1821 CFARGS(.iattr = "atapi")); 1822 } 1823 1824 static void 1825 ahci_atapi_minphys(struct buf *bp) 1826 { 1827 if (bp->b_bcount > MAXPHYS) 1828 bp->b_bcount = MAXPHYS; 1829 minphys(bp); 1830 } 1831 1832 /* 1833 * Kill off all pending xfers for a periph. 1834 * 1835 * Must be called at splbio(). 1836 */ 1837 static void 1838 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1839 { 1840 struct atac_softc *atac = 1841 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1842 struct ata_channel *chp = 1843 atac->atac_channels[periph->periph_channel->chan_channel]; 1844 1845 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1846 } 1847 1848 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1849 .c_start = ahci_atapi_start, 1850 .c_poll = ahci_atapi_poll, 1851 .c_abort = ahci_atapi_abort, 1852 .c_intr = ahci_atapi_complete, 1853 .c_kill_xfer = ahci_atapi_kill_xfer, 1854 }; 1855 1856 static void 1857 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1858 scsipi_adapter_req_t req, void *arg) 1859 { 1860 struct scsipi_adapter *adapt = chan->chan_adapter; 1861 struct scsipi_periph *periph; 1862 struct scsipi_xfer *sc_xfer; 1863 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1864 struct atac_softc *atac = &sc->sc_atac; 1865 struct ata_xfer *xfer; 1866 int channel = chan->chan_channel; 1867 int drive, s; 1868 1869 switch (req) { 1870 case ADAPTER_REQ_RUN_XFER: 1871 sc_xfer = arg; 1872 periph = sc_xfer->xs_periph; 1873 drive = periph->periph_target; 1874 if (!device_is_active(atac->atac_dev)) { 1875 sc_xfer->error = XS_DRIVER_STUFFUP; 1876 scsipi_done(sc_xfer); 1877 return; 1878 } 1879 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1880 if (xfer == NULL) { 1881 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1882 scsipi_done(sc_xfer); 1883 return; 1884 } 1885 1886 if (sc_xfer->xs_control & XS_CTL_POLL) 1887 xfer->c_flags |= C_POLL; 1888 xfer->c_drive = drive; 1889 xfer->c_flags |= C_ATAPI; 1890 xfer->c_databuf = sc_xfer->data; 1891 xfer->c_bcount = sc_xfer->datalen; 1892 xfer->ops = &ahci_atapi_xfer_ops; 1893 xfer->c_scsipi = sc_xfer; 1894 xfer->c_atapi.c_dscpoll = 0; 1895 s = splbio(); 1896 ata_exec_xfer(atac->atac_channels[channel], xfer); 1897 #ifdef DIAGNOSTIC 1898 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1899 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1900 panic("ahci_atapi_scsipi_request: polled command " 1901 "not done"); 1902 #endif 1903 splx(s); 1904 return; 1905 default: 1906 /* Not supported, nothing to do. */ 1907 ; 1908 } 1909 } 1910 1911 static int 1912 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1913 { 1914 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1915 struct ahci_channel *achp = (struct ahci_channel *)chp; 1916 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1917 struct ahci_cmd_tbl *cmd_tbl; 1918 struct ahci_cmd_header *cmd_h; 1919 1920 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1921 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1922 1923 ata_channel_lock_owned(chp); 1924 1925 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1926 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1927 cmd_tbl), DEBUG_XFERS); 1928 1929 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1930 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1931 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1932 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1933 1934 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1935 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1936 chp->ch_channel, cmd_h), DEBUG_XFERS); 1937 if (ahci_dma_setup(chp, xfer->c_slot, 1938 sc_xfer->datalen ? sc_xfer->data : NULL, 1939 sc_xfer->datalen, 1940 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1941 BUS_DMA_READ : BUS_DMA_WRITE)) { 1942 sc_xfer->error = XS_DRIVER_STUFFUP; 1943 return ATASTART_ABORT; 1944 } 1945 cmd_h->cmdh_flags = htole16( 1946 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1947 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1948 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1949 cmd_h->cmdh_prdbc = 0; 1950 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1952 1953 if (xfer->c_flags & C_POLL) { 1954 /* polled command, disable interrupts */ 1955 AHCI_WRITE(sc, AHCI_GHC, 1956 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1957 } 1958 /* start command */ 1959 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1960 1961 if ((xfer->c_flags & C_POLL) == 0) { 1962 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1963 ata_timeout, chp); 1964 return ATASTART_STARTED; 1965 } else 1966 return ATASTART_POLL; 1967 } 1968 1969 static int 1970 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1971 { 1972 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1973 struct ahci_channel *achp = (struct ahci_channel *)chp; 1974 1975 /* 1976 * Polled command. 1977 */ 1978 for (int i = 0; i < ATA_DELAY / 10; i++) { 1979 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1980 break; 1981 ahci_intr_port(achp); 1982 delay(10000); 1983 } 1984 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1985 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1986 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1987 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1988 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1989 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1990 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1991 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1992 DEBUG_XFERS); 1993 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1994 xfer->c_scsipi->error = XS_TIMEOUT; 1995 xfer->ops->c_intr(chp, xfer, 0); 1996 } 1997 /* reenable interrupts */ 1998 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1999 return ATAPOLL_DONE; 2000 } 2001 2002 static void 2003 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 2004 { 2005 ahci_atapi_complete(chp, xfer, 0); 2006 } 2007 2008 static int 2009 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 2010 { 2011 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2012 struct ahci_channel *achp = (struct ahci_channel *)chp; 2013 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 2014 2015 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 2016 DEBUG_FUNCS); 2017 2018 if (ata_waitdrain_xfer_check(chp, xfer)) 2019 return 0; 2020 2021 if (xfer->c_flags & C_TIMEOU) { 2022 sc_xfer->error = XS_TIMEOUT; 2023 } 2024 2025 if (xfer->c_bcount > 0) { 2026 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2027 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2028 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2029 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2030 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2031 } 2032 2033 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2034 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2035 sc_xfer->resid = sc_xfer->datalen; 2036 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2037 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2038 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2039 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2040 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2041 sc_xfer->resid == sc_xfer->datalen)) { 2042 sc_xfer->error = XS_SHORTSENSE; 2043 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2044 if ((sc_xfer->xs_periph->periph_quirks & 2045 PQUIRK_NOSENSE) == 0) { 2046 /* ask scsipi to send a REQUEST_SENSE */ 2047 sc_xfer->error = XS_BUSY; 2048 sc_xfer->status = SCSI_CHECK; 2049 } 2050 } 2051 2052 ata_deactivate_xfer(chp, xfer); 2053 2054 ata_free_xfer(chp, xfer); 2055 scsipi_done(sc_xfer); 2056 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2057 atastart(chp); 2058 return 0; 2059 } 2060 2061 static void 2062 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2063 { 2064 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2065 bool deactivate = true; 2066 2067 /* remove this command from xfer queue */ 2068 switch (reason) { 2069 case KILL_GONE_INACTIVE: 2070 deactivate = false; 2071 /* FALLTHROUGH */ 2072 case KILL_GONE: 2073 sc_xfer->error = XS_DRIVER_STUFFUP; 2074 break; 2075 case KILL_RESET: 2076 sc_xfer->error = XS_RESET; 2077 break; 2078 case KILL_REQUEUE: 2079 sc_xfer->error = XS_REQUEUE; 2080 break; 2081 default: 2082 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2083 panic("ahci_ata_atapi_kill_xfer"); 2084 } 2085 2086 if (deactivate) 2087 ata_deactivate_xfer(chp, xfer); 2088 2089 ata_free_xfer(chp, xfer); 2090 scsipi_done(sc_xfer); 2091 } 2092 2093 static void 2094 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2095 { 2096 struct scsipi_channel *chan = sc->sc_channel; 2097 struct scsipi_periph *periph; 2098 struct ataparams ids; 2099 struct ataparams *id = &ids; 2100 struct ahci_softc *ahcic = 2101 device_private(chan->chan_adapter->adapt_dev); 2102 struct atac_softc *atac = &ahcic->sc_atac; 2103 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2104 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2105 struct scsipibus_attach_args sa; 2106 char serial_number[21], model[41], firmware_revision[9]; 2107 int s; 2108 2109 /* skip if already attached */ 2110 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2111 return; 2112 2113 /* if no ATAPI device detected at attach time, skip */ 2114 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2115 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2116 "not present\n", target), DEBUG_PROBE); 2117 return; 2118 } 2119 2120 /* Some ATAPI devices need a bit more time after software reset. */ 2121 delay(5000); 2122 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2123 #ifdef ATAPI_DEBUG_PROBE 2124 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2125 AHCINAME(ahcic), target, 2126 id->atap_config & ATAPI_CFG_CMD_MASK, 2127 id->atap_config & ATAPI_CFG_DRQ_MASK); 2128 #endif 2129 periph = scsipi_alloc_periph(M_NOWAIT); 2130 if (periph == NULL) { 2131 aprint_error_dev(sc->sc_dev, 2132 "unable to allocate periph for drive %d\n", 2133 target); 2134 return; 2135 } 2136 periph->periph_dev = NULL; 2137 periph->periph_channel = chan; 2138 periph->periph_switch = &atapi_probe_periphsw; 2139 periph->periph_target = target; 2140 periph->periph_lun = 0; 2141 periph->periph_quirks = PQUIRK_ONLYBIG; 2142 2143 #ifdef SCSIPI_DEBUG 2144 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2145 SCSIPI_DEBUG_TARGET == target) 2146 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2147 #endif 2148 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2149 if (id->atap_config & ATAPI_CFG_REMOV) 2150 periph->periph_flags |= PERIPH_REMOVABLE; 2151 if (periph->periph_type == T_SEQUENTIAL) { 2152 s = splbio(); 2153 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2154 splx(s); 2155 } 2156 2157 sa.sa_periph = periph; 2158 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2159 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2160 T_REMOV : T_FIXED; 2161 strnvisx(model, sizeof(model), id->atap_model, 40, 2162 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2163 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2164 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2165 strnvisx(firmware_revision, sizeof(firmware_revision), 2166 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2167 sa.sa_inqbuf.vendor = model; 2168 sa.sa_inqbuf.product = serial_number; 2169 sa.sa_inqbuf.revision = firmware_revision; 2170 2171 /* 2172 * Determine the operating mode capabilities of the device. 2173 */ 2174 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2175 periph->periph_cap |= PERIPH_CAP_CMD16; 2176 /* XXX This is gross. */ 2177 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2178 2179 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2180 2181 if (drvp->drv_softc) 2182 ata_probe_caps(drvp); 2183 else { 2184 s = splbio(); 2185 drvp->drive_type = ATA_DRIVET_NONE; 2186 splx(s); 2187 } 2188 } else { 2189 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2190 "failed for drive %s:%d:%d\n", 2191 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2192 s = splbio(); 2193 drvp->drive_type = ATA_DRIVET_NONE; 2194 splx(s); 2195 } 2196 } 2197 #endif /* NATAPIBUS */ 2198
Indexes created Wed Sep 24 05:09:52 GMT 2025