ahcisata_core.c revision 1.14
1 /* $NetBSD: ahcisata_core.c,v 1.14 2008/03/24 14:44:26 cube Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.14 2008/03/24 14:44:26 cube Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 #include <sys/buf.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/ic/wdcreg.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/satavar.h> 50 #include <dev/ata/satareg.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 #include "atapibus.h" 54 55 #ifdef AHCI_DEBUG 56 int ahcidebug_mask = 0x0; 57 #endif 58 59 void ahci_probe_drive(struct ata_channel *); 60 void ahci_setup_channel(struct ata_channel *); 61 62 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 63 void ahci_reset_drive(struct ata_drive_datas *, int); 64 void ahci_reset_channel(struct ata_channel *, int); 65 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 66 int ahci_ata_addref(struct ata_drive_datas *); 67 void ahci_ata_delref(struct ata_drive_datas *); 68 void ahci_killpending(struct ata_drive_datas *); 69 70 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 73 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 75 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 76 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 77 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 78 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 79 void ahci_timeout(void *); 80 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 void ahci_atapibus_attach(struct atabus_softc *); 84 void ahci_atapi_kill_pending(struct scsipi_periph *); 85 void ahci_atapi_minphys(struct buf *); 86 void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 }; 100 #endif /* NATAPIBUS */ 101 102 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 103 104 const struct ata_bustype ahci_ata_bustype = { 105 SCSIPI_BUSTYPE_ATA, 106 ahci_ata_bio, 107 ahci_reset_drive, 108 ahci_reset_channel, 109 ahci_exec_command, 110 ata_get_params, 111 ahci_ata_addref, 112 ahci_ata_delref, 113 ahci_killpending 114 }; 115 116 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 117 118 static void ahci_setup_port(struct ahci_softc *sc, int i); 119 120 int 121 ahci_reset(struct ahci_softc *sc) 122 { 123 int i; 124 125 /* reset controller */ 126 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 127 /* wait up to 1s for reset to complete */ 128 for (i = 0; i < 1000; i++) { 129 delay(1000); 130 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 131 break; 132 } 133 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 134 aprint_error("%s: reset failed\n", AHCINAME(sc)); 135 return -1; 136 } 137 /* enable ahci mode */ 138 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 139 return 0; 140 } 141 142 void 143 ahci_setup_ports(struct ahci_softc *sc) 144 { 145 u_int32_t ahci_ports; 146 int i, port; 147 148 ahci_ports = AHCI_READ(sc, AHCI_PI); 149 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 150 if ((ahci_ports & (1 << i)) == 0) 151 continue; 152 if (port >= sc->sc_atac.atac_nchannels) { 153 aprint_error("%s: more ports than announced\n", 154 AHCINAME(sc)); 155 break; 156 } 157 ahci_setup_port(sc, i); 158 } 159 } 160 161 void 162 ahci_reprobe_drives(struct ahci_softc *sc) 163 { 164 u_int32_t ahci_ports; 165 int i, port; 166 struct ahci_channel *achp; 167 struct ata_channel *chp; 168 169 ahci_ports = AHCI_READ(sc, AHCI_PI); 170 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 171 if ((ahci_ports & (1 << i)) == 0) 172 continue; 173 if (port >= sc->sc_atac.atac_nchannels) { 174 aprint_error("%s: more ports than announced\n", 175 AHCINAME(sc)); 176 break; 177 } 178 achp = &sc->sc_channels[i]; 179 chp = &achp->ata_channel; 180 181 ahci_probe_drive(chp); 182 } 183 } 184 185 static void 186 ahci_setup_port(struct ahci_softc *sc, int i) 187 { 188 struct ahci_channel *achp; 189 190 achp = &sc->sc_channels[i]; 191 192 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 193 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 194 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 195 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 196 } 197 198 void 199 ahci_enable_intrs(struct ahci_softc *sc) 200 { 201 202 /* clear interrupts */ 203 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 204 /* enable interrupts */ 205 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 206 } 207 208 void 209 ahci_attach(struct ahci_softc *sc) 210 { 211 u_int32_t ahci_cap, ahci_rev, ahci_ports; 212 int i, j, port; 213 struct ahci_channel *achp; 214 struct ata_channel *chp; 215 int error; 216 bus_dma_segment_t seg; 217 int rseg; 218 int dmasize; 219 void *cmdhp; 220 void *cmdtblp; 221 222 if (ahci_reset(sc) != 0) 223 return; 224 225 ahci_cap = AHCI_READ(sc, AHCI_CAP); 226 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 227 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 228 ahci_rev = AHCI_READ(sc, AHCI_VS); 229 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 230 switch(ahci_rev) { 231 case AHCI_VS_10: 232 aprint_normal("1.0"); 233 break; 234 case AHCI_VS_11: 235 aprint_normal("1.1"); 236 break; 237 case AHCI_VS_12: 238 aprint_normal("1.2"); 239 break; 240 default: 241 aprint_normal("0x%x", ahci_rev); 242 break; 243 } 244 245 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 246 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 247 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 248 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 249 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 250 sc->sc_atac.atac_pio_cap = 4; 251 sc->sc_atac.atac_dma_cap = 2; 252 sc->sc_atac.atac_udma_cap = 6; 253 sc->sc_atac.atac_channels = sc->sc_chanarray; 254 sc->sc_atac.atac_probe = ahci_probe_drive; 255 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 256 sc->sc_atac.atac_set_modes = ahci_setup_channel; 257 #if NATAPIBUS > 0 258 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 259 #endif 260 261 dmasize = 262 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 263 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 264 &seg, 1, &rseg, BUS_DMA_NOWAIT); 265 if (error) { 266 aprint_error("%s: unable to allocate command header memory" 267 ", error=%d\n", AHCINAME(sc), error); 268 return; 269 } 270 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 271 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 272 if (error) { 273 aprint_error("%s: unable to map command header memory" 274 ", error=%d\n", AHCINAME(sc), error); 275 return; 276 } 277 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 278 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 279 if (error) { 280 aprint_error("%s: unable to create command header map" 281 ", error=%d\n", AHCINAME(sc), error); 282 return; 283 } 284 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 285 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 286 if (error) { 287 aprint_error("%s: unable to load command header map" 288 ", error=%d\n", AHCINAME(sc), error); 289 return; 290 } 291 sc->sc_cmd_hdr = cmdhp; 292 293 ahci_enable_intrs(sc); 294 295 ahci_ports = AHCI_READ(sc, AHCI_PI); 296 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 297 if ((ahci_ports & (1 << i)) == 0) 298 continue; 299 if (port >= sc->sc_atac.atac_nchannels) { 300 aprint_error("%s: more ports than announced\n", 301 AHCINAME(sc)); 302 break; 303 } 304 achp = &sc->sc_channels[i]; 305 chp = (struct ata_channel *)achp; 306 sc->sc_chanarray[i] = chp; 307 chp->ch_channel = i; 308 chp->ch_atac = &sc->sc_atac; 309 chp->ch_queue = malloc(sizeof(struct ata_queue), 310 M_DEVBUF, M_NOWAIT); 311 if (chp->ch_queue == NULL) { 312 aprint_error("%s port %d: can't allocate memory for " 313 "command queue", AHCINAME(sc), i); 314 break; 315 } 316 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 318 &seg, 1, &rseg, BUS_DMA_NOWAIT); 319 if (error) { 320 aprint_error("%s: unable to allocate command table " 321 "memory, error=%d\n", AHCINAME(sc), error); 322 break; 323 } 324 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 325 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 326 if (error) { 327 aprint_error("%s: unable to map command table memory" 328 ", error=%d\n", AHCINAME(sc), error); 329 break; 330 } 331 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 332 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 333 if (error) { 334 aprint_error("%s: unable to create command table map" 335 ", error=%d\n", AHCINAME(sc), error); 336 break; 337 } 338 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 339 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error("%s: unable to load command table map" 342 ", error=%d\n", AHCINAME(sc), error); 343 break; 344 } 345 achp->ahcic_cmdh = (struct ahci_cmd_header *) 346 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 347 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 348 AHCI_CMDH_SIZE * port; 349 achp->ahcic_rfis = (struct ahci_r_fis *) 350 ((char *)cmdhp + 351 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 352 AHCI_RFIS_SIZE * port); 353 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 354 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 355 AHCI_RFIS_SIZE * port; 356 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 357 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 358 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 359 DEBUG_PROBE); 360 361 for (j = 0; j < sc->sc_ncmds; j++) { 362 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 363 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 364 achp->ahcic_bus_cmd_tbl[j] = 365 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 366 AHCI_CMDTBL_SIZE * j; 367 achp->ahcic_cmdh[j].cmdh_cmdtba = 368 htole32(achp->ahcic_bus_cmd_tbl[j]); 369 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 370 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 371 achp->ahcic_cmd_tbl[j], 372 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 373 /* The xfer DMA map */ 374 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 375 AHCI_NPRD, 0x400000 /* 4MB */, 0, 376 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 377 &achp->ahcic_datad[j]); 378 if (error) { 379 aprint_error("%s: couldn't alloc xfer DMA map, " 380 "error=%d\n", AHCINAME(sc), error); 381 goto end; 382 } 383 } 384 ahci_setup_port(sc, i); 385 chp->ch_ndrive = 1; 386 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 387 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 388 aprint_error("%s: couldn't map channel %d " 389 "sata_status regs\n", AHCINAME(sc), i); 390 break; 391 } 392 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 393 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 394 aprint_error("%s: couldn't map channel %d " 395 "sata_control regs\n", AHCINAME(sc), i); 396 break; 397 } 398 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 399 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 400 aprint_error("%s: couldn't map channel %d " 401 "sata_error regs\n", AHCINAME(sc), i); 402 break; 403 } 404 ata_channel_attach(chp); 405 port++; 406 end: 407 continue; 408 } 409 } 410 411 int 412 ahci_intr(void *v) 413 { 414 struct ahci_softc *sc = v; 415 u_int32_t is; 416 int i, r = 0; 417 418 while ((is = AHCI_READ(sc, AHCI_IS))) { 419 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 420 DEBUG_INTR); 421 r = 1; 422 AHCI_WRITE(sc, AHCI_IS, is); 423 for (i = 0; i < AHCI_MAX_PORTS; i++) 424 if (is & (1 << i)) 425 ahci_intr_port(sc, &sc->sc_channels[i]); 426 } 427 return r; 428 } 429 430 void 431 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 432 { 433 u_int32_t is, tfd; 434 struct ata_channel *chp = &achp->ata_channel; 435 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 436 int slot; 437 438 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 439 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 440 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 441 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 442 DEBUG_INTR); 443 444 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 445 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 446 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 447 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 448 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 449 return; 450 /* stop channel */ 451 ahci_channel_stop(sc, chp, 0); 452 if (slot != 0) { 453 printf("ahci_intr_port: slot %d\n", slot); 454 panic("ahci_intr_port"); 455 } 456 if (is & AHCI_P_IX_TFES) { 457 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 458 chp->ch_error = 459 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 460 chp->ch_status = (tfd & 0xff); 461 } else { 462 /* emulate a CRC error */ 463 chp->ch_error = WDCE_CRC; 464 chp->ch_status = WDCS_ERR; 465 } 466 xfer->c_intr(chp, xfer, is); 467 /* if channel has not been restarted, do it now */ 468 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 469 == 0) 470 ahci_channel_start(sc, chp); 471 } else { 472 slot = 0; /* XXX */ 473 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 474 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 475 chp->ch_channel, is, achp->ahcic_cmds_active, 476 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 477 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 478 return; 479 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 480 == 0) { 481 xfer->c_intr(chp, xfer, 0); 482 } 483 } 484 } 485 486 void 487 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 488 { 489 struct ata_channel *chp = drvp->chnl_softc; 490 ata_reset_channel(chp, flags); 491 return; 492 } 493 494 void 495 ahci_reset_channel(struct ata_channel *chp, int flags) 496 { 497 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 498 struct ahci_channel *achp = (struct ahci_channel *)chp; 499 500 ahci_channel_stop(sc, chp, flags); 501 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 502 achp->ahcic_sstatus) != SStatus_DET_DEV) { 503 printf("%s: port reset failed\n", AHCINAME(sc)); 504 /* XXX and then ? */ 505 } 506 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 507 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 508 if (chp->ch_queue->active_xfer) { 509 chp->ch_queue->active_xfer->c_kill_xfer(chp, 510 chp->ch_queue->active_xfer, KILL_RESET); 511 } 512 ahci_channel_start(sc, chp); 513 #if 0 514 /* Wait 15s for device to host FIS to arrive. */ 515 for (i = 0; i <1500; i++) { 516 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) & AHCI_P_IX_DHRS) 517 break; 518 if (flags & AT_WAIT) 519 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 520 else 521 delay (10000); 522 } 523 if (i == 1500) 524 aprint_error("%s port %d: D2H FIS never arrived\n", AHCINAME(sc)); 525 #endif 526 /* clear port interrupt register */ 527 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 528 529 return; 530 } 531 532 int 533 ahci_ata_addref(struct ata_drive_datas *drvp) 534 { 535 return 0; 536 } 537 538 void 539 ahci_ata_delref(struct ata_drive_datas *drvp) 540 { 541 return; 542 } 543 544 void 545 ahci_killpending(struct ata_drive_datas *drvp) 546 { 547 return; 548 } 549 550 void 551 ahci_probe_drive(struct ata_channel *chp) 552 { 553 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 554 struct ahci_channel *achp = (struct ahci_channel *)chp; 555 int i, s; 556 u_int32_t sig; 557 558 /* XXX This should be done by other code. */ 559 for (i = 0; i < chp->ch_ndrive; i++) { 560 chp->ch_drive[i].chnl_softc = chp; 561 chp->ch_drive[i].drive = i; 562 } 563 564 /* bring interface up, power up and spin up device */ 565 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 566 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 567 /* reset the PHY and bring online */ 568 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 569 achp->ahcic_sstatus)) { 570 case SStatus_DET_DEV: 571 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 572 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 573 #if 0 574 /* wait 15s for d2h FIS */ 575 for (i = 0; i <1500; i++) { 576 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) 577 & AHCI_P_IX_DHRS) 578 break; 579 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 580 } 581 if (i == 1500) 582 aprint_error("%s: D2H FIS never arrived\n", 583 AHCINAME(sc)); 584 #endif 585 586 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 587 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 588 AHCINAME(sc), chp->ch_channel, sig, 589 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 590 /* 591 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 592 * cases we get wrong values here, so ignore it. 593 */ 594 s = splbio(); 595 if ((sig & 0xffff0000) == 0xeb140000) { 596 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 597 } else 598 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 599 splx(s); 600 /* enable interrupts */ 601 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 602 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 603 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 604 AHCI_P_IX_DHRS); 605 /* and start operations */ 606 ahci_channel_start(sc, chp); 607 break; 608 609 default: 610 break; 611 } 612 } 613 614 void 615 ahci_setup_channel(struct ata_channel *chp) 616 { 617 return; 618 } 619 620 int 621 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 622 { 623 struct ata_channel *chp = drvp->chnl_softc; 624 struct ata_xfer *xfer; 625 int ret; 626 int s; 627 628 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 629 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 630 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 631 DEBUG_XFERS); 632 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 633 ATAXF_NOSLEEP); 634 if (xfer == NULL) { 635 return ATACMD_TRY_AGAIN; 636 } 637 if (ata_c->flags & AT_POLL) 638 xfer->c_flags |= C_POLL; 639 if (ata_c->flags & AT_WAIT) 640 xfer->c_flags |= C_WAIT; 641 xfer->c_drive = drvp->drive; 642 xfer->c_databuf = ata_c->data; 643 xfer->c_bcount = ata_c->bcount; 644 xfer->c_cmd = ata_c; 645 xfer->c_start = ahci_cmd_start; 646 xfer->c_intr = ahci_cmd_complete; 647 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 648 s = splbio(); 649 ata_exec_xfer(chp, xfer); 650 #ifdef DIAGNOSTIC 651 if ((ata_c->flags & AT_POLL) != 0 && 652 (ata_c->flags & AT_DONE) == 0) 653 panic("ahci_exec_command: polled command not done"); 654 #endif 655 if (ata_c->flags & AT_DONE) { 656 ret = ATACMD_COMPLETE; 657 } else { 658 if (ata_c->flags & AT_WAIT) { 659 while ((ata_c->flags & AT_DONE) == 0) { 660 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 661 } 662 ret = ATACMD_COMPLETE; 663 } else { 664 ret = ATACMD_QUEUED; 665 } 666 } 667 splx(s); 668 return ret; 669 } 670 671 void 672 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 673 { 674 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 675 struct ahci_channel *achp = (struct ahci_channel *)chp; 676 struct ata_command *ata_c = xfer->c_cmd; 677 int slot = 0 /* XXX slot */; 678 struct ahci_cmd_tbl *cmd_tbl; 679 struct ahci_cmd_header *cmd_h; 680 u_int8_t *fis; 681 int i; 682 int channel = chp->ch_channel; 683 684 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 685 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 686 687 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 688 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 689 cmd_tbl), DEBUG_XFERS); 690 fis = cmd_tbl->cmdt_cfis; 691 692 fis[0] = 0x27; /* host to device */ 693 fis[1] = 0x80; /* command FIS */ 694 fis[2] = ata_c->r_command; 695 fis[3] = ata_c->r_features; 696 fis[4] = ata_c->r_sector; 697 fis[5] = ata_c->r_cyl & 0xff; 698 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 699 fis[7] = ata_c->r_head & 0x0f; 700 fis[8] = 0; 701 fis[9] = 0; 702 fis[10] = 0; 703 fis[11] = 0; 704 fis[12] = ata_c->r_count; 705 fis[13] = 0; 706 fis[14] = 0; 707 fis[15] = WDCTL_4BIT; 708 fis[16] = 0; 709 fis[17] = 0; 710 fis[18] = 0; 711 fis[19] = 0; 712 713 cmd_h = &achp->ahcic_cmdh[slot]; 714 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 715 chp->ch_channel, cmd_h), DEBUG_XFERS); 716 if (ahci_dma_setup(chp, slot, 717 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 718 ata_c->bcount, 719 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 720 ata_c->flags |= AT_DF; 721 ahci_cmd_complete(chp, xfer, slot); 722 return; 723 } 724 cmd_h->cmdh_flags = htole16( 725 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 726 20 /* fis lenght */ / 4); 727 cmd_h->cmdh_prdbc = 0; 728 AHCI_CMDH_SYNC(sc, achp, slot, 729 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 730 731 if (ata_c->flags & AT_POLL) { 732 /* polled command, disable interrupts */ 733 AHCI_WRITE(sc, AHCI_GHC, 734 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 735 } 736 chp->ch_flags |= ATACH_IRQ_WAIT; 737 chp->ch_status = 0; 738 /* start command */ 739 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 740 /* and says we started this command */ 741 achp->ahcic_cmds_active |= 1 << slot; 742 743 if ((ata_c->flags & AT_POLL) == 0) { 744 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 745 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 746 ahci_timeout, chp); 747 return; 748 } 749 /* 750 * Polled command. 751 */ 752 for (i = 0; i < ata_c->timeout / 10; i++) { 753 if (ata_c->flags & AT_DONE) 754 break; 755 ahci_intr_port(sc, achp); 756 if (ata_c->flags & AT_WAIT) 757 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 758 else 759 delay(10000); 760 } 761 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 762 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 763 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 764 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 765 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 766 DEBUG_XFERS); 767 if ((ata_c->flags & AT_DONE) == 0) { 768 ata_c->flags |= AT_TIMEOU; 769 ahci_cmd_complete(chp, xfer, slot); 770 } 771 /* reenable interrupts */ 772 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 773 } 774 775 void 776 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 777 { 778 struct ata_command *ata_c = xfer->c_cmd; 779 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 780 DEBUG_FUNCS); 781 782 switch (reason) { 783 case KILL_GONE: 784 ata_c->flags |= AT_GONE; 785 break; 786 case KILL_RESET: 787 ata_c->flags |= AT_RESET; 788 break; 789 default: 790 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 791 panic("ahci_cmd_kill_xfer"); 792 } 793 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 794 } 795 796 int 797 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 798 { 799 int slot = 0; /* XXX slot */ 800 struct ata_command *ata_c = xfer->c_cmd; 801 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 802 803 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 804 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 805 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 806 DEBUG_FUNCS); 807 chp->ch_flags &= ~ATACH_IRQ_WAIT; 808 if (xfer->c_flags & C_TIMEOU) { 809 ata_c->flags |= AT_TIMEOU; 810 } else 811 callout_stop(&chp->ch_callout); 812 813 chp->ch_queue->active_xfer = NULL; 814 815 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 816 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 817 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 818 wakeup(&chp->ch_queue->active_xfer); 819 return 0; 820 } 821 if (is) { 822 ata_c->r_head = 0; 823 ata_c->r_count = 0; 824 ata_c->r_sector = 0; 825 ata_c->r_cyl = 0; 826 if (chp->ch_status & WDCS_BSY) { 827 ata_c->flags |= AT_TIMEOU; 828 } else if (chp->ch_status & WDCS_ERR) { 829 ata_c->r_error = chp->ch_error; 830 ata_c->flags |= AT_ERROR; 831 } 832 } 833 ahci_cmd_done(chp, xfer, slot); 834 return 0; 835 } 836 837 void 838 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 839 { 840 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 841 struct ahci_channel *achp = (struct ahci_channel *)chp; 842 struct ata_command *ata_c = xfer->c_cmd; 843 844 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 845 DEBUG_FUNCS); 846 847 /* this comamnd is not active any more */ 848 achp->ahcic_cmds_active &= ~(1 << slot); 849 850 if (ata_c->flags & (AT_READ|AT_WRITE)) { 851 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 852 achp->ahcic_datad[slot]->dm_mapsize, 853 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 854 BUS_DMASYNC_POSTWRITE); 855 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 856 } 857 858 AHCI_CMDH_SYNC(sc, achp, slot, 859 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 860 861 ata_c->flags |= AT_DONE; 862 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 863 ata_c->flags |= AT_XFDONE; 864 865 ata_free_xfer(chp, xfer); 866 if (ata_c->flags & AT_WAIT) 867 wakeup(ata_c); 868 else if (ata_c->callback) 869 ata_c->callback(ata_c->callback_arg); 870 atastart(chp); 871 return; 872 } 873 874 int 875 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 876 { 877 struct ata_channel *chp = drvp->chnl_softc; 878 struct ata_xfer *xfer; 879 880 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 881 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 882 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 883 DEBUG_XFERS); 884 xfer = ata_get_xfer(ATAXF_NOSLEEP); 885 if (xfer == NULL) { 886 return ATACMD_TRY_AGAIN; 887 } 888 if (ata_bio->flags & ATA_POLL) 889 xfer->c_flags |= C_POLL; 890 xfer->c_drive = drvp->drive; 891 xfer->c_cmd = ata_bio; 892 xfer->c_databuf = ata_bio->databuf; 893 xfer->c_bcount = ata_bio->bcount; 894 xfer->c_start = ahci_bio_start; 895 xfer->c_intr = ahci_bio_complete; 896 xfer->c_kill_xfer = ahci_bio_kill_xfer; 897 ata_exec_xfer(chp, xfer); 898 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 899 } 900 901 void 902 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 903 { 904 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 905 struct ahci_channel *achp = (struct ahci_channel *)chp; 906 struct ata_bio *ata_bio = xfer->c_cmd; 907 int slot = 0 /* XXX slot */; 908 struct ahci_cmd_tbl *cmd_tbl; 909 struct ahci_cmd_header *cmd_h; 910 u_int8_t *fis; 911 int i, nblks; 912 int channel = chp->ch_channel; 913 914 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 915 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 916 917 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 918 919 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 920 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 921 cmd_tbl), DEBUG_XFERS); 922 fis = cmd_tbl->cmdt_cfis; 923 924 fis[0] = 0x27; /* host to device */ 925 fis[1] = 0x80; /* command FIS */ 926 if (ata_bio->flags & ATA_LBA48) { 927 fis[2] = (ata_bio->flags & ATA_READ) ? 928 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 929 } else { 930 fis[2] = 931 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 932 } 933 fis[3] = 0; /* features */ 934 fis[4] = ata_bio->blkno & 0xff; 935 fis[5] = (ata_bio->blkno >> 8) & 0xff; 936 fis[6] = (ata_bio->blkno >> 16) & 0xff; 937 if (ata_bio->flags & ATA_LBA48) { 938 fis[7] = WDSD_LBA; 939 fis[8] = (ata_bio->blkno >> 24) & 0xff; 940 fis[9] = (ata_bio->blkno >> 32) & 0xff; 941 fis[10] = (ata_bio->blkno >> 40) & 0xff; 942 } else { 943 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 944 fis[8] = 0; 945 fis[9] = 0; 946 fis[10] = 0; 947 } 948 fis[11] = 0; /* ext features */ 949 fis[12] = nblks & 0xff; 950 fis[13] = (ata_bio->flags & ATA_LBA48) ? 951 ((nblks >> 8) & 0xff) : 0; 952 fis[14] = 0; 953 fis[15] = WDCTL_4BIT; 954 fis[16] = 0; 955 fis[17] = 0; 956 fis[18] = 0; 957 fis[19] = 0; 958 959 cmd_h = &achp->ahcic_cmdh[slot]; 960 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 961 chp->ch_channel, cmd_h), DEBUG_XFERS); 962 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 963 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 964 ata_bio->error = ERR_DMA; 965 ata_bio->r_error = 0; 966 ahci_bio_complete(chp, xfer, slot); 967 return; 968 } 969 cmd_h->cmdh_flags = htole16( 970 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 971 20 /* fis lenght */ / 4); 972 cmd_h->cmdh_prdbc = 0; 973 AHCI_CMDH_SYNC(sc, achp, slot, 974 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 975 976 if (xfer->c_flags & C_POLL) { 977 /* polled command, disable interrupts */ 978 AHCI_WRITE(sc, AHCI_GHC, 979 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 980 } 981 chp->ch_flags |= ATACH_IRQ_WAIT; 982 chp->ch_status = 0; 983 /* start command */ 984 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 985 /* and says we started this command */ 986 achp->ahcic_cmds_active |= 1 << slot; 987 988 if ((xfer->c_flags & C_POLL) == 0) { 989 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 990 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 991 ahci_timeout, chp); 992 return; 993 } 994 /* 995 * Polled command. 996 */ 997 for (i = 0; i < ATA_DELAY / 10; i++) { 998 if (ata_bio->flags & ATA_ITSDONE) 999 break; 1000 ahci_intr_port(sc, achp); 1001 if (ata_bio->flags & ATA_NOSLEEP) 1002 delay(10000); 1003 else 1004 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1005 } 1006 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1007 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1008 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1009 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1010 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1011 DEBUG_XFERS); 1012 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1013 ata_bio->error = TIMEOUT; 1014 ahci_bio_complete(chp, xfer, slot); 1015 } 1016 /* reenable interrupts */ 1017 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1018 } 1019 1020 void 1021 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1022 { 1023 int slot = 0; /* XXX slot */ 1024 int drive = xfer->c_drive; 1025 struct ata_bio *ata_bio = xfer->c_cmd; 1026 struct ahci_channel *achp = (struct ahci_channel *)chp; 1027 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1028 DEBUG_FUNCS); 1029 1030 achp->ahcic_cmds_active &= ~(1 << slot); 1031 ata_free_xfer(chp, xfer); 1032 ata_bio->flags |= ATA_ITSDONE; 1033 switch (reason) { 1034 case KILL_GONE: 1035 ata_bio->error = ERR_NODEV; 1036 break; 1037 case KILL_RESET: 1038 ata_bio->error = ERR_RESET; 1039 break; 1040 default: 1041 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1042 panic("ahci_bio_kill_xfer"); 1043 } 1044 ata_bio->r_error = WDCE_ABRT; 1045 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1046 } 1047 1048 int 1049 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1050 { 1051 int slot = 0; /* XXX slot */ 1052 struct ata_bio *ata_bio = xfer->c_cmd; 1053 int drive = xfer->c_drive; 1054 struct ahci_channel *achp = (struct ahci_channel *)chp; 1055 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1056 1057 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1058 DEBUG_FUNCS); 1059 1060 achp->ahcic_cmds_active &= ~(1 << slot); 1061 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1062 if (xfer->c_flags & C_TIMEOU) { 1063 ata_bio->error = TIMEOUT; 1064 } else { 1065 callout_stop(&chp->ch_callout); 1066 ata_bio->error = 0; 1067 } 1068 1069 chp->ch_queue->active_xfer = NULL; 1070 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1071 achp->ahcic_datad[slot]->dm_mapsize, 1072 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1073 BUS_DMASYNC_POSTWRITE); 1074 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1075 1076 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1077 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1078 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1079 wakeup(&chp->ch_queue->active_xfer); 1080 return 0; 1081 } 1082 ata_free_xfer(chp, xfer); 1083 ata_bio->flags |= ATA_ITSDONE; 1084 if (chp->ch_status & WDCS_DWF) { 1085 ata_bio->error = ERR_DF; 1086 } else if (chp->ch_status & WDCS_ERR) { 1087 ata_bio->error = ERROR; 1088 ata_bio->r_error = chp->ch_error; 1089 } else if (chp->ch_status & WDCS_CORR) 1090 ata_bio->flags |= ATA_CORR; 1091 1092 AHCI_CMDH_SYNC(sc, achp, slot, 1093 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1094 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1095 ata_bio->bcount), DEBUG_XFERS); 1096 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1097 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1098 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1099 atastart(chp); 1100 return 0; 1101 } 1102 1103 void 1104 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1105 { 1106 int i; 1107 /* stop channel */ 1108 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1109 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1110 /* wait 1s for channel to stop */ 1111 for (i = 0; i <100; i++) { 1112 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1113 == 0) 1114 break; 1115 if (flags & AT_WAIT) 1116 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1117 else 1118 delay(10000); 1119 } 1120 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1121 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1122 /* XXX controller reset ? */ 1123 return; 1124 } 1125 } 1126 1127 void 1128 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1129 { 1130 /* clear error */ 1131 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1132 1133 /* and start controller */ 1134 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1135 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1136 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1137 } 1138 1139 void 1140 ahci_timeout(void *v) 1141 { 1142 struct ata_channel *chp = (struct ata_channel *)v; 1143 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1144 int s = splbio(); 1145 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1146 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1147 xfer->c_flags |= C_TIMEOU; 1148 xfer->c_intr(chp, xfer, 0); 1149 } 1150 splx(s); 1151 } 1152 1153 int 1154 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1155 size_t count, int op) 1156 { 1157 int error, seg; 1158 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1159 struct ahci_channel *achp = (struct ahci_channel *)chp; 1160 struct ahci_cmd_tbl *cmd_tbl; 1161 struct ahci_cmd_header *cmd_h; 1162 1163 cmd_h = &achp->ahcic_cmdh[slot]; 1164 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1165 1166 if (data == NULL) { 1167 cmd_h->cmdh_prdtl = 0; 1168 goto end; 1169 } 1170 1171 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1172 data, count, NULL, 1173 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1174 if (error) { 1175 printf("%s port %d: failed to load xfer: %d\n", 1176 AHCINAME(sc), chp->ch_channel, error); 1177 return error; 1178 } 1179 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1180 achp->ahcic_datad[slot]->dm_mapsize, 1181 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1182 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1183 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1184 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1185 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1186 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1187 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1188 } 1189 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1190 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1191 end: 1192 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1193 return 0; 1194 } 1195 1196 #if NATAPIBUS > 0 1197 void 1198 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1199 { 1200 struct ata_channel *chp = ata_sc->sc_chan; 1201 struct atac_softc *atac = chp->ch_atac; 1202 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1203 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1204 /* 1205 * Fill in the scsipi_adapter. 1206 */ 1207 adapt->adapt_dev = atac->atac_dev; 1208 adapt->adapt_nchannels = atac->atac_nchannels; 1209 adapt->adapt_request = ahci_atapi_scsipi_request; 1210 adapt->adapt_minphys = ahci_atapi_minphys; 1211 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1212 1213 /* 1214 * Fill in the scsipi_channel. 1215 */ 1216 memset(chan, 0, sizeof(*chan)); 1217 chan->chan_adapter = adapt; 1218 chan->chan_bustype = &ahci_atapi_bustype; 1219 chan->chan_channel = chp->ch_channel; 1220 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1221 chan->chan_openings = 1; 1222 chan->chan_max_periph = 1; 1223 chan->chan_ntargets = 1; 1224 chan->chan_nluns = 1; 1225 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1226 atapiprint); 1227 } 1228 1229 void 1230 ahci_atapi_minphys(struct buf *bp) 1231 { 1232 if (bp->b_bcount > MAXPHYS) 1233 bp->b_bcount = MAXPHYS; 1234 minphys(bp); 1235 } 1236 1237 /* 1238 * Kill off all pending xfers for a periph. 1239 * 1240 * Must be called at splbio(). 1241 */ 1242 void 1243 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1244 { 1245 struct atac_softc *atac = 1246 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1247 struct ata_channel *chp = 1248 atac->atac_channels[periph->periph_channel->chan_channel]; 1249 1250 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1251 } 1252 1253 void 1254 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1255 scsipi_adapter_req_t req, void *arg) 1256 { 1257 struct scsipi_adapter *adapt = chan->chan_adapter; 1258 struct scsipi_periph *periph; 1259 struct scsipi_xfer *sc_xfer; 1260 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1261 struct atac_softc *atac = &sc->sc_atac; 1262 struct ata_xfer *xfer; 1263 int channel = chan->chan_channel; 1264 int drive, s; 1265 1266 switch (req) { 1267 case ADAPTER_REQ_RUN_XFER: 1268 sc_xfer = arg; 1269 periph = sc_xfer->xs_periph; 1270 drive = periph->periph_target; 1271 if (!device_is_active(atac->atac_dev)) { 1272 sc_xfer->error = XS_DRIVER_STUFFUP; 1273 scsipi_done(sc_xfer); 1274 return; 1275 } 1276 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1277 if (xfer == NULL) { 1278 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1279 scsipi_done(sc_xfer); 1280 return; 1281 } 1282 1283 if (sc_xfer->xs_control & XS_CTL_POLL) 1284 xfer->c_flags |= C_POLL; 1285 xfer->c_drive = drive; 1286 xfer->c_flags |= C_ATAPI; 1287 xfer->c_cmd = sc_xfer; 1288 xfer->c_databuf = sc_xfer->data; 1289 xfer->c_bcount = sc_xfer->datalen; 1290 xfer->c_start = ahci_atapi_start; 1291 xfer->c_intr = ahci_atapi_complete; 1292 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1293 xfer->c_dscpoll = 0; 1294 s = splbio(); 1295 ata_exec_xfer(atac->atac_channels[channel], xfer); 1296 #ifdef DIAGNOSTIC 1297 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1298 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1299 panic("ahci_atapi_scsipi_request: polled command " 1300 "not done"); 1301 #endif 1302 splx(s); 1303 return; 1304 default: 1305 /* Not supported, nothing to do. */ 1306 ; 1307 } 1308 } 1309 1310 void 1311 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1312 { 1313 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1314 struct ahci_channel *achp = (struct ahci_channel *)chp; 1315 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1316 int slot = 0 /* XXX slot */; 1317 struct ahci_cmd_tbl *cmd_tbl; 1318 struct ahci_cmd_header *cmd_h; 1319 u_int8_t *fis; 1320 int i; 1321 int channel = chp->ch_channel; 1322 1323 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1324 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1325 1326 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1327 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1328 cmd_tbl), DEBUG_XFERS); 1329 fis = cmd_tbl->cmdt_cfis; 1330 1331 fis[0] = 0x27; /* host to device */ 1332 fis[1] = 0x80; /* command FIS */ 1333 fis[2] = ATAPI_PKT_CMD; 1334 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1335 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1336 fis[3] = (sc_xfer->datalen ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1337 fis[4] = 0; 1338 fis[5] = 0; 1339 fis[6] = 0; 1340 fis[7] = WDSD_LBA; 1341 fis[8] = 0; 1342 fis[9] = 0; 1343 fis[10] = 0; 1344 fis[11] = 0; /* ext features */ 1345 fis[12] = 0; 1346 fis[13] = 0; 1347 fis[14] = 0; 1348 fis[15] = WDCTL_4BIT; 1349 fis[16] = 0; 1350 fis[17] = 0; 1351 fis[18] = 0; 1352 fis[19] = 0; 1353 1354 cmd_h = &achp->ahcic_cmdh[slot]; 1355 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1356 chp->ch_channel, cmd_h), DEBUG_XFERS); 1357 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1358 sc_xfer->datalen, 1359 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1360 BUS_DMA_READ : BUS_DMA_WRITE)) { 1361 sc_xfer->error = XS_DRIVER_STUFFUP; 1362 ahci_atapi_complete(chp, xfer, slot); 1363 return; 1364 } 1365 cmd_h->cmdh_flags = htole16( 1366 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1367 20 /* fis lenght */ / 4 | AHCI_CMDH_F_A); 1368 cmd_h->cmdh_prdbc = 0; 1369 AHCI_CMDH_SYNC(sc, achp, slot, 1370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1371 1372 if (xfer->c_flags & C_POLL) { 1373 /* polled command, disable interrupts */ 1374 AHCI_WRITE(sc, AHCI_GHC, 1375 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1376 } 1377 chp->ch_flags |= ATACH_IRQ_WAIT; 1378 chp->ch_status = 0; 1379 /* start command */ 1380 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1381 /* and says we started this command */ 1382 achp->ahcic_cmds_active |= 1 << slot; 1383 1384 if ((xfer->c_flags & C_POLL) == 0) { 1385 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1386 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1387 ahci_timeout, chp); 1388 return; 1389 } 1390 /* 1391 * Polled command. 1392 */ 1393 for (i = 0; i < ATA_DELAY / 10; i++) { 1394 if (sc_xfer->xs_status & XS_STS_DONE) 1395 break; 1396 ahci_intr_port(sc, achp); 1397 delay(10000); 1398 } 1399 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1400 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1401 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1402 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1403 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1404 DEBUG_XFERS); 1405 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1406 sc_xfer->error = XS_TIMEOUT; 1407 ahci_atapi_complete(chp, xfer, slot); 1408 } 1409 /* reenable interrupts */ 1410 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1411 } 1412 1413 int 1414 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1415 { 1416 int slot = 0; /* XXX slot */ 1417 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1418 int drive = xfer->c_drive; 1419 struct ahci_channel *achp = (struct ahci_channel *)chp; 1420 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1421 1422 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1423 DEBUG_FUNCS); 1424 1425 achp->ahcic_cmds_active &= ~(1 << slot); 1426 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1427 if (xfer->c_flags & C_TIMEOU) { 1428 sc_xfer->error = XS_TIMEOUT; 1429 } else { 1430 callout_stop(&chp->ch_callout); 1431 sc_xfer->error = 0; 1432 } 1433 1434 chp->ch_queue->active_xfer = NULL; 1435 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1436 achp->ahcic_datad[slot]->dm_mapsize, 1437 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1438 BUS_DMASYNC_POSTWRITE); 1439 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1440 1441 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1442 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1443 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1444 wakeup(&chp->ch_queue->active_xfer); 1445 return 0; 1446 } 1447 ata_free_xfer(chp, xfer); 1448 1449 if (chp->ch_status & WDCS_ERR) { 1450 sc_xfer->error = XS_SHORTSENSE; 1451 sc_xfer->sense.atapi_sense = chp->ch_error; 1452 } 1453 1454 AHCI_CMDH_SYNC(sc, achp, slot, 1455 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1456 sc_xfer->resid = sc_xfer->datalen; 1457 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1458 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1459 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1460 scsipi_done(sc_xfer); 1461 atastart(chp); 1462 return 0; 1463 } 1464 1465 void 1466 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1467 { 1468 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1469 struct ahci_channel *achp = (struct ahci_channel *)chp; 1470 int slot = 0; /* XXX slot */ 1471 1472 achp->ahcic_cmds_active &= ~(1 << slot); 1473 1474 /* remove this command from xfer queue */ 1475 switch (reason) { 1476 case KILL_GONE: 1477 sc_xfer->error = XS_DRIVER_STUFFUP; 1478 break; 1479 case KILL_RESET: 1480 sc_xfer->error = XS_RESET; 1481 break; 1482 default: 1483 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1484 panic("ahci_ata_atapi_kill_xfer"); 1485 } 1486 ata_free_xfer(chp, xfer); 1487 scsipi_done(sc_xfer); 1488 } 1489 1490 void 1491 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1492 { 1493 struct scsipi_channel *chan = sc->sc_channel; 1494 struct scsipi_periph *periph; 1495 struct ataparams ids; 1496 struct ataparams *id = &ids; 1497 struct ahci_softc *ahcic = 1498 device_private(chan->chan_adapter->adapt_dev); 1499 struct atac_softc *atac = &ahcic->sc_atac; 1500 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1501 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1502 struct scsipibus_attach_args sa; 1503 char serial_number[21], model[41], firmware_revision[9]; 1504 int s; 1505 1506 /* skip if already attached */ 1507 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1508 return; 1509 1510 /* if no ATAPI device detected at attach time, skip */ 1511 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1512 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1513 "not present\n", target), DEBUG_PROBE); 1514 return; 1515 } 1516 1517 /* Some ATAPI devices need a bit more time after software reset. */ 1518 delay(5000); 1519 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1520 #ifdef ATAPI_DEBUG_PROBE 1521 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1522 AHCINAME(ahcic), target, 1523 id->atap_config & ATAPI_CFG_CMD_MASK, 1524 id->atap_config & ATAPI_CFG_DRQ_MASK); 1525 #endif 1526 periph = scsipi_alloc_periph(M_NOWAIT); 1527 if (periph == NULL) { 1528 aprint_error_dev(sc->sc_dev, 1529 "unable to allocate periph for drive %d\n", 1530 target); 1531 return; 1532 } 1533 periph->periph_dev = NULL; 1534 periph->periph_channel = chan; 1535 periph->periph_switch = &atapi_probe_periphsw; 1536 periph->periph_target = target; 1537 periph->periph_lun = 0; 1538 periph->periph_quirks = PQUIRK_ONLYBIG; 1539 1540 #ifdef SCSIPI_DEBUG 1541 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1542 SCSIPI_DEBUG_TARGET == target) 1543 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1544 #endif 1545 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1546 if (id->atap_config & ATAPI_CFG_REMOV) 1547 periph->periph_flags |= PERIPH_REMOVABLE; 1548 if (periph->periph_type == T_SEQUENTIAL) { 1549 s = splbio(); 1550 drvp->drive_flags |= DRIVE_ATAPIST; 1551 splx(s); 1552 } 1553 1554 sa.sa_periph = periph; 1555 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1556 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1557 T_REMOV : T_FIXED; 1558 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1559 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1560 20); 1561 scsipi_strvis((u_char *)firmware_revision, 8, 1562 id->atap_revision, 8); 1563 sa.sa_inqbuf.vendor = model; 1564 sa.sa_inqbuf.product = serial_number; 1565 sa.sa_inqbuf.revision = firmware_revision; 1566 1567 /* 1568 * Determine the operating mode capabilities of the device. 1569 */ 1570 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1571 periph->periph_cap |= PERIPH_CAP_CMD16; 1572 /* XXX This is gross. */ 1573 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1574 1575 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1576 1577 if (drvp->drv_softc) 1578 ata_probe_caps(drvp); 1579 else { 1580 s = splbio(); 1581 drvp->drive_flags &= ~DRIVE_ATAPI; 1582 splx(s); 1583 } 1584 } else { 1585 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1586 "failed for drive %s:%d:%d: error 0x%x\n", 1587 AHCINAME(ahcic), chp->ch_channel, target, 1588 chp->ch_error), DEBUG_PROBE); 1589 s = splbio(); 1590 drvp->drive_flags &= ~DRIVE_ATAPI; 1591 splx(s); 1592 } 1593 } 1594 #endif /* NATAPIBUS */ 1595
Indexes created Tue Sep 23 07:09:52 GMT 2025