ahcisata_core.c revision 1.14.4.5
1 /* $NetBSD: ahcisata_core.c,v 1.14.4.5 2010/08/11 22:53:22 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.14.4.5 2010/08/11 22:53:22 yamt Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/ata/atareg.h> 43 #include <dev/ata/satavar.h> 44 #include <dev/ata/satareg.h> 45 #include <dev/ata/satafisvar.h> 46 #include <dev/ata/satafisreg.h> 47 #include <dev/ic/ahcisatavar.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0x0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static void ahci_reset_drive(struct ata_drive_datas *, int); 62 static void ahci_reset_channel(struct ata_channel *, int); 63 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 64 static int ahci_ata_addref(struct ata_drive_datas *); 65 static void ahci_ata_delref(struct ata_drive_datas *); 66 static void ahci_killpending(struct ata_drive_datas *); 67 68 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 69 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 70 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 72 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 73 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 74 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 75 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 76 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 77 static void ahci_timeout(void *); 78 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 79 80 #if NATAPIBUS > 0 81 static void ahci_atapibus_attach(struct atabus_softc *); 82 static void ahci_atapi_kill_pending(struct scsipi_periph *); 83 static void ahci_atapi_minphys(struct buf *); 84 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 85 scsipi_adapter_req_t, void *); 86 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 87 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 88 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 89 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 90 91 static const struct scsipi_bustype ahci_atapi_bustype = { 92 SCSIPI_BUSTYPE_ATAPI, 93 atapi_scsipi_cmd, 94 atapi_interpret_sense, 95 atapi_print_addr, 96 ahci_atapi_kill_pending, 97 }; 98 #endif /* NATAPIBUS */ 99 100 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 101 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 102 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 103 104 const struct ata_bustype ahci_ata_bustype = { 105 SCSIPI_BUSTYPE_ATA, 106 ahci_ata_bio, 107 ahci_reset_drive, 108 ahci_reset_channel, 109 ahci_exec_command, 110 ata_get_params, 111 ahci_ata_addref, 112 ahci_ata_delref, 113 ahci_killpending 114 }; 115 116 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 117 static void ahci_setup_port(struct ahci_softc *sc, int i); 118 119 static int 120 ahci_reset(struct ahci_softc *sc) 121 { 122 int i; 123 124 /* reset controller */ 125 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 126 /* wait up to 1s for reset to complete */ 127 for (i = 0; i < 1000; i++) { 128 delay(1000); 129 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 130 break; 131 } 132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 133 aprint_error("%s: reset failed\n", AHCINAME(sc)); 134 return -1; 135 } 136 /* enable ahci mode */ 137 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 138 return 0; 139 } 140 141 static void 142 ahci_setup_ports(struct ahci_softc *sc) 143 { 144 uint32_t ahci_ports; 145 int i, port; 146 147 ahci_ports = AHCI_READ(sc, AHCI_PI); 148 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 149 if ((ahci_ports & (1 << i)) == 0) 150 continue; 151 if (port >= sc->sc_atac.atac_nchannels) { 152 aprint_error("%s: more ports than announced\n", 153 AHCINAME(sc)); 154 break; 155 } 156 ahci_setup_port(sc, i); 157 } 158 } 159 160 static void 161 ahci_reprobe_drives(struct ahci_softc *sc) 162 { 163 uint32_t ahci_ports; 164 int i, port; 165 struct ahci_channel *achp; 166 struct ata_channel *chp; 167 168 ahci_ports = AHCI_READ(sc, AHCI_PI); 169 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 170 if ((ahci_ports & (1 << i)) == 0) 171 continue; 172 if (port >= sc->sc_atac.atac_nchannels) { 173 aprint_error("%s: more ports than announced\n", 174 AHCINAME(sc)); 175 break; 176 } 177 achp = &sc->sc_channels[i]; 178 chp = &achp->ata_channel; 179 180 ahci_probe_drive(chp); 181 } 182 } 183 184 static void 185 ahci_setup_port(struct ahci_softc *sc, int i) 186 { 187 struct ahci_channel *achp; 188 189 achp = &sc->sc_channels[i]; 190 191 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 192 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 193 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 194 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 195 } 196 197 static void 198 ahci_enable_intrs(struct ahci_softc *sc) 199 { 200 201 /* clear interrupts */ 202 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 203 /* enable interrupts */ 204 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 205 } 206 207 void 208 ahci_attach(struct ahci_softc *sc) 209 { 210 uint32_t ahci_cap, ahci_rev, ahci_ports; 211 int i, j, port; 212 struct ahci_channel *achp; 213 struct ata_channel *chp; 214 int error; 215 int dmasize; 216 void *cmdhp; 217 void *cmdtblp; 218 219 if (ahci_reset(sc) != 0) 220 return; 221 222 ahci_cap = AHCI_READ(sc, AHCI_CAP); 223 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 224 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 225 ahci_rev = AHCI_READ(sc, AHCI_VS); 226 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 227 switch(ahci_rev) { 228 case AHCI_VS_10: 229 aprint_normal("1.0"); 230 break; 231 case AHCI_VS_11: 232 aprint_normal("1.1"); 233 break; 234 case AHCI_VS_12: 235 aprint_normal("1.2"); 236 break; 237 default: 238 aprint_normal("0x%x", ahci_rev); 239 break; 240 } 241 242 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 243 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 244 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 245 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 246 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 247 sc->sc_atac.atac_pio_cap = 4; 248 sc->sc_atac.atac_dma_cap = 2; 249 sc->sc_atac.atac_udma_cap = 6; 250 sc->sc_atac.atac_channels = sc->sc_chanarray; 251 sc->sc_atac.atac_probe = ahci_probe_drive; 252 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 253 sc->sc_atac.atac_set_modes = ahci_setup_channel; 254 #if NATAPIBUS > 0 255 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 256 #endif 257 258 dmasize = 259 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 260 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 261 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 262 if (error) { 263 aprint_error("%s: unable to allocate command header memory" 264 ", error=%d\n", AHCINAME(sc), error); 265 return; 266 } 267 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 268 sc->sc_cmd_hdr_nseg, dmasize, 269 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 270 if (error) { 271 aprint_error("%s: unable to map command header memory" 272 ", error=%d\n", AHCINAME(sc), error); 273 return; 274 } 275 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 276 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 277 if (error) { 278 aprint_error("%s: unable to create command header map" 279 ", error=%d\n", AHCINAME(sc), error); 280 return; 281 } 282 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 283 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 284 if (error) { 285 aprint_error("%s: unable to load command header map" 286 ", error=%d\n", AHCINAME(sc), error); 287 return; 288 } 289 sc->sc_cmd_hdr = cmdhp; 290 291 ahci_enable_intrs(sc); 292 293 ahci_ports = AHCI_READ(sc, AHCI_PI); 294 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 295 if ((ahci_ports & (1 << i)) == 0) 296 continue; 297 if (port >= sc->sc_atac.atac_nchannels) { 298 aprint_error("%s: more ports than announced\n", 299 AHCINAME(sc)); 300 break; 301 } 302 achp = &sc->sc_channels[i]; 303 chp = &achp->ata_channel; 304 sc->sc_chanarray[i] = chp; 305 chp->ch_channel = i; 306 chp->ch_atac = &sc->sc_atac; 307 chp->ch_queue = malloc(sizeof(struct ata_queue), 308 M_DEVBUF, M_NOWAIT); 309 if (chp->ch_queue == NULL) { 310 aprint_error("%s port %d: can't allocate memory for " 311 "command queue", AHCINAME(sc), i); 312 break; 313 } 314 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 315 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 316 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 317 BUS_DMA_NOWAIT); 318 if (error) { 319 aprint_error("%s: unable to allocate command table " 320 "memory, error=%d\n", AHCINAME(sc), error); 321 break; 322 } 323 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 324 achp->ahcic_cmd_tbl_nseg, dmasize, 325 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 326 if (error) { 327 aprint_error("%s: unable to map command table memory" 328 ", error=%d\n", AHCINAME(sc), error); 329 break; 330 } 331 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 332 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 333 if (error) { 334 aprint_error("%s: unable to create command table map" 335 ", error=%d\n", AHCINAME(sc), error); 336 break; 337 } 338 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 339 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error("%s: unable to load command table map" 342 ", error=%d\n", AHCINAME(sc), error); 343 break; 344 } 345 achp->ahcic_cmdh = (struct ahci_cmd_header *) 346 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 347 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 348 AHCI_CMDH_SIZE * port; 349 achp->ahcic_rfis = (struct ahci_r_fis *) 350 ((char *)cmdhp + 351 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 352 AHCI_RFIS_SIZE * port); 353 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 354 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 355 AHCI_RFIS_SIZE * port; 356 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 357 "rfis %p (0x%" PRIx64 ")\n", i, 358 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 359 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 360 DEBUG_PROBE); 361 362 for (j = 0; j < sc->sc_ncmds; j++) { 363 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 364 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 365 achp->ahcic_bus_cmd_tbl[j] = 366 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 367 AHCI_CMDTBL_SIZE * j; 368 achp->ahcic_cmdh[j].cmdh_cmdtba = 369 htole64(achp->ahcic_bus_cmd_tbl[j]); 370 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 371 achp->ahcic_cmd_tbl[j], 372 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 373 /* The xfer DMA map */ 374 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 375 AHCI_NPRD, 0x400000 /* 4MB */, 0, 376 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 377 &achp->ahcic_datad[j]); 378 if (error) { 379 aprint_error("%s: couldn't alloc xfer DMA map, " 380 "error=%d\n", AHCINAME(sc), error); 381 goto end; 382 } 383 } 384 ahci_setup_port(sc, i); 385 chp->ch_ndrive = 1; 386 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 387 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 388 aprint_error("%s: couldn't map channel %d " 389 "sata_status regs\n", AHCINAME(sc), i); 390 break; 391 } 392 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 393 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 394 aprint_error("%s: couldn't map channel %d " 395 "sata_control regs\n", AHCINAME(sc), i); 396 break; 397 } 398 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 399 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 400 aprint_error("%s: couldn't map channel %d " 401 "sata_error regs\n", AHCINAME(sc), i); 402 break; 403 } 404 ata_channel_attach(chp); 405 port++; 406 end: 407 continue; 408 } 409 } 410 411 int 412 ahci_detach(struct ahci_softc *sc, int flags) 413 { 414 struct atac_softc *atac; 415 struct ahci_channel *achp; 416 struct ata_channel *chp; 417 struct scsipi_adapter *adapt; 418 uint32_t ahci_ports; 419 int i, j; 420 int error; 421 422 atac = &sc->sc_atac; 423 adapt = &atac->atac_atapi_adapter._generic; 424 425 ahci_ports = AHCI_READ(sc, AHCI_PI); 426 for (i = 0; i < AHCI_MAX_PORTS; i++) { 427 achp = &sc->sc_channels[i]; 428 chp = &achp->ata_channel; 429 430 if ((ahci_ports & (1 << i)) == 0) 431 continue; 432 if (i >= sc->sc_atac.atac_nchannels) { 433 aprint_error("%s: more ports than announced\n", 434 AHCINAME(sc)); 435 break; 436 } 437 438 if (chp->atabus == NULL) 439 continue; 440 if ((error = config_detach(chp->atabus, flags)) != 0) 441 return error; 442 443 for (j = 0; j < sc->sc_ncmds; j++) 444 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 445 446 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 447 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 448 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 449 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 450 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 451 achp->ahcic_cmd_tbl_nseg); 452 453 free(chp->ch_queue, M_DEVBUF); 454 chp->atabus = NULL; 455 } 456 457 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 458 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 459 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 460 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 461 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 462 463 if (adapt->adapt_refcnt != 0) 464 return EBUSY; 465 466 return 0; 467 } 468 469 void 470 ahci_resume(struct ahci_softc *sc) 471 { 472 ahci_reset(sc); 473 ahci_setup_ports(sc); 474 ahci_reprobe_drives(sc); 475 ahci_enable_intrs(sc); 476 } 477 478 int 479 ahci_intr(void *v) 480 { 481 struct ahci_softc *sc = v; 482 uint32_t is; 483 int i, r = 0; 484 485 while ((is = AHCI_READ(sc, AHCI_IS))) { 486 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 487 DEBUG_INTR); 488 r = 1; 489 AHCI_WRITE(sc, AHCI_IS, is); 490 for (i = 0; i < AHCI_MAX_PORTS; i++) 491 if (is & (1 << i)) 492 ahci_intr_port(sc, &sc->sc_channels[i]); 493 } 494 return r; 495 } 496 497 static void 498 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 499 { 500 uint32_t is, tfd; 501 struct ata_channel *chp = &achp->ata_channel; 502 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 503 int slot; 504 505 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 506 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 507 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 508 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 509 DEBUG_INTR); 510 511 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 512 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 513 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 514 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 515 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 516 return; 517 /* stop channel */ 518 ahci_channel_stop(sc, chp, 0); 519 if (slot != 0) { 520 printf("ahci_intr_port: slot %d\n", slot); 521 panic("ahci_intr_port"); 522 } 523 if (is & AHCI_P_IX_TFES) { 524 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 525 chp->ch_error = 526 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 527 chp->ch_status = (tfd & 0xff); 528 } else { 529 /* emulate a CRC error */ 530 chp->ch_error = WDCE_CRC; 531 chp->ch_status = WDCS_ERR; 532 } 533 xfer->c_intr(chp, xfer, is); 534 /* if channel has not been restarted, do it now */ 535 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 536 == 0) 537 ahci_channel_start(sc, chp); 538 } else { 539 slot = 0; /* XXX */ 540 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 541 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 542 chp->ch_channel, is, achp->ahcic_cmds_active, 543 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 544 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 545 return; 546 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 547 == 0) { 548 xfer->c_intr(chp, xfer, 0); 549 } 550 } 551 } 552 553 static void 554 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 555 { 556 struct ata_channel *chp = drvp->chnl_softc; 557 ata_reset_channel(chp, flags); 558 return; 559 } 560 561 static void 562 ahci_reset_channel(struct ata_channel *chp, int flags) 563 { 564 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 565 struct ahci_channel *achp = (struct ahci_channel *)chp; 566 int i, tfd; 567 568 ahci_channel_stop(sc, chp, flags); 569 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 570 achp->ahcic_sstatus) != SStatus_DET_DEV) { 571 printf("%s: port reset failed\n", AHCINAME(sc)); 572 /* XXX and then ? */ 573 } 574 if (chp->ch_queue->active_xfer) { 575 chp->ch_queue->active_xfer->c_kill_xfer(chp, 576 chp->ch_queue->active_xfer, KILL_RESET); 577 } 578 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 579 /* clear port interrupt register */ 580 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 581 /* clear SErrors and start operations */ 582 ahci_channel_start(sc, chp); 583 /* wait 31s for BSY to clear */ 584 for (i = 0; i <AHCI_RST_WAIT; i++) { 585 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 586 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 587 & WDCS_BSY) == 0) 588 break; 589 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 590 } 591 if (i == AHCI_RST_WAIT) 592 aprint_error("%s: BSY never cleared, TD 0x%x\n", 593 AHCINAME(sc), tfd); 594 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 595 DEBUG_PROBE); 596 /* clear port interrupt register */ 597 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 598 599 return; 600 } 601 602 static int 603 ahci_ata_addref(struct ata_drive_datas *drvp) 604 { 605 return 0; 606 } 607 608 static void 609 ahci_ata_delref(struct ata_drive_datas *drvp) 610 { 611 return; 612 } 613 614 static void 615 ahci_killpending(struct ata_drive_datas *drvp) 616 { 617 return; 618 } 619 620 static void 621 ahci_probe_drive(struct ata_channel *chp) 622 { 623 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 624 struct ahci_channel *achp = (struct ahci_channel *)chp; 625 int i, s; 626 uint32_t sig; 627 628 /* XXX This should be done by other code. */ 629 for (i = 0; i < chp->ch_ndrive; i++) { 630 chp->ch_drive[i].chnl_softc = chp; 631 chp->ch_drive[i].drive = i; 632 } 633 634 /* bring interface up, accept FISs, power up and spin up device */ 635 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 636 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 637 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 638 /* reset the PHY and bring online */ 639 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 640 achp->ahcic_sstatus)) { 641 case SStatus_DET_DEV: 642 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 643 /* clear port interrupt register */ 644 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 645 /* clear SErrors and start operations */ 646 ahci_channel_start(sc, chp); 647 /* wait 31s for BSY to clear */ 648 for (i = 0; i <AHCI_RST_WAIT; i++) { 649 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 650 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 651 & WDCS_BSY) == 0) 652 break; 653 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 654 } 655 if (i == AHCI_RST_WAIT) { 656 aprint_error("%s: BSY never cleared, TD 0x%x\n", 657 AHCINAME(sc), sig); 658 return; 659 } 660 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 661 DEBUG_PROBE); 662 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 663 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 664 AHCINAME(sc), chp->ch_channel, sig, 665 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 666 /* 667 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 668 * cases we get wrong values here, so ignore it. 669 */ 670 s = splbio(); 671 if ((sig & 0xffff0000) == 0xeb140000) { 672 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 673 } else 674 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 675 splx(s); 676 /* clear port interrupt register */ 677 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 678 /* and enable interrupts */ 679 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 680 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 681 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 682 AHCI_P_IX_DHRS); 683 /* wait 500ms before actually starting operations */ 684 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 685 break; 686 687 default: 688 break; 689 } 690 } 691 692 static void 693 ahci_setup_channel(struct ata_channel *chp) 694 { 695 return; 696 } 697 698 static int 699 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 700 { 701 struct ata_channel *chp = drvp->chnl_softc; 702 struct ata_xfer *xfer; 703 int ret; 704 int s; 705 706 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 707 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 708 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 709 DEBUG_XFERS); 710 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 711 ATAXF_NOSLEEP); 712 if (xfer == NULL) { 713 return ATACMD_TRY_AGAIN; 714 } 715 if (ata_c->flags & AT_POLL) 716 xfer->c_flags |= C_POLL; 717 if (ata_c->flags & AT_WAIT) 718 xfer->c_flags |= C_WAIT; 719 xfer->c_drive = drvp->drive; 720 xfer->c_databuf = ata_c->data; 721 xfer->c_bcount = ata_c->bcount; 722 xfer->c_cmd = ata_c; 723 xfer->c_start = ahci_cmd_start; 724 xfer->c_intr = ahci_cmd_complete; 725 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 726 s = splbio(); 727 ata_exec_xfer(chp, xfer); 728 #ifdef DIAGNOSTIC 729 if ((ata_c->flags & AT_POLL) != 0 && 730 (ata_c->flags & AT_DONE) == 0) 731 panic("ahci_exec_command: polled command not done"); 732 #endif 733 if (ata_c->flags & AT_DONE) { 734 ret = ATACMD_COMPLETE; 735 } else { 736 if (ata_c->flags & AT_WAIT) { 737 while ((ata_c->flags & AT_DONE) == 0) { 738 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 739 } 740 ret = ATACMD_COMPLETE; 741 } else { 742 ret = ATACMD_QUEUED; 743 } 744 } 745 splx(s); 746 return ret; 747 } 748 749 static void 750 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 751 { 752 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 753 struct ahci_channel *achp = (struct ahci_channel *)chp; 754 struct ata_command *ata_c = xfer->c_cmd; 755 int slot = 0 /* XXX slot */; 756 struct ahci_cmd_tbl *cmd_tbl; 757 struct ahci_cmd_header *cmd_h; 758 int i; 759 int channel = chp->ch_channel; 760 761 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 762 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 763 764 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 765 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 766 cmd_tbl), DEBUG_XFERS); 767 768 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 769 770 cmd_h = &achp->ahcic_cmdh[slot]; 771 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 772 chp->ch_channel, cmd_h), DEBUG_XFERS); 773 if (ahci_dma_setup(chp, slot, 774 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 775 ata_c->bcount, 776 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 777 ata_c->flags |= AT_DF; 778 ahci_cmd_complete(chp, xfer, slot); 779 return; 780 } 781 cmd_h->cmdh_flags = htole16( 782 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 783 RHD_FISLEN / 4); 784 cmd_h->cmdh_prdbc = 0; 785 AHCI_CMDH_SYNC(sc, achp, slot, 786 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 787 788 if (ata_c->flags & AT_POLL) { 789 /* polled command, disable interrupts */ 790 AHCI_WRITE(sc, AHCI_GHC, 791 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 792 } 793 chp->ch_flags |= ATACH_IRQ_WAIT; 794 chp->ch_status = 0; 795 /* start command */ 796 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 797 /* and says we started this command */ 798 achp->ahcic_cmds_active |= 1 << slot; 799 800 if ((ata_c->flags & AT_POLL) == 0) { 801 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 802 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 803 ahci_timeout, chp); 804 return; 805 } 806 /* 807 * Polled command. 808 */ 809 for (i = 0; i < ata_c->timeout / 10; i++) { 810 if (ata_c->flags & AT_DONE) 811 break; 812 ahci_intr_port(sc, achp); 813 if (ata_c->flags & AT_WAIT) 814 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 815 else 816 delay(10000); 817 } 818 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 819 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 820 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 821 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 822 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 823 DEBUG_XFERS); 824 if ((ata_c->flags & AT_DONE) == 0) { 825 ata_c->flags |= AT_TIMEOU; 826 ahci_cmd_complete(chp, xfer, slot); 827 } 828 /* reenable interrupts */ 829 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 830 } 831 832 static void 833 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 834 { 835 struct ata_command *ata_c = xfer->c_cmd; 836 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 837 DEBUG_FUNCS); 838 839 switch (reason) { 840 case KILL_GONE: 841 ata_c->flags |= AT_GONE; 842 break; 843 case KILL_RESET: 844 ata_c->flags |= AT_RESET; 845 break; 846 default: 847 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 848 panic("ahci_cmd_kill_xfer"); 849 } 850 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 851 } 852 853 static int 854 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 855 { 856 int slot = 0; /* XXX slot */ 857 struct ata_command *ata_c = xfer->c_cmd; 858 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 859 struct ahci_channel *achp = (struct ahci_channel *)chp; 860 861 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 862 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 863 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 864 DEBUG_FUNCS); 865 chp->ch_flags &= ~ATACH_IRQ_WAIT; 866 if (xfer->c_flags & C_TIMEOU) { 867 ata_c->flags |= AT_TIMEOU; 868 } else 869 callout_stop(&chp->ch_callout); 870 871 chp->ch_queue->active_xfer = NULL; 872 873 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 874 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 875 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 876 wakeup(&chp->ch_queue->active_xfer); 877 return 0; 878 } 879 880 if (chp->ch_status & WDCS_BSY) { 881 ata_c->flags |= AT_TIMEOU; 882 } else if (chp->ch_status & WDCS_ERR) { 883 ata_c->r_error = chp->ch_error; 884 ata_c->flags |= AT_ERROR; 885 } 886 887 if (ata_c->flags & AT_READREG) 888 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 889 890 ahci_cmd_done(chp, xfer, slot); 891 return 0; 892 } 893 894 static void 895 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 896 { 897 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 898 struct ahci_channel *achp = (struct ahci_channel *)chp; 899 struct ata_command *ata_c = xfer->c_cmd; 900 uint16_t *idwordbuf; 901 int i; 902 903 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 904 DEBUG_FUNCS); 905 906 /* this comamnd is not active any more */ 907 achp->ahcic_cmds_active &= ~(1 << slot); 908 909 if (ata_c->flags & (AT_READ|AT_WRITE)) { 910 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 911 achp->ahcic_datad[slot]->dm_mapsize, 912 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 913 BUS_DMASYNC_POSTWRITE); 914 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 915 } 916 917 AHCI_CMDH_SYNC(sc, achp, slot, 918 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 919 920 /* ata(4) expects IDENTIFY data to be in host endianess */ 921 if (ata_c->r_command == WDCC_IDENTIFY || 922 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 923 idwordbuf = xfer->c_databuf; 924 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 925 idwordbuf[i] = le16toh(idwordbuf[i]); 926 } 927 } 928 929 ata_c->flags |= AT_DONE; 930 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 931 ata_c->flags |= AT_XFDONE; 932 933 ata_free_xfer(chp, xfer); 934 if (ata_c->flags & AT_WAIT) 935 wakeup(ata_c); 936 else if (ata_c->callback) 937 ata_c->callback(ata_c->callback_arg); 938 atastart(chp); 939 return; 940 } 941 942 static int 943 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 944 { 945 struct ata_channel *chp = drvp->chnl_softc; 946 struct ata_xfer *xfer; 947 948 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 949 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 950 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 951 DEBUG_XFERS); 952 xfer = ata_get_xfer(ATAXF_NOSLEEP); 953 if (xfer == NULL) { 954 return ATACMD_TRY_AGAIN; 955 } 956 if (ata_bio->flags & ATA_POLL) 957 xfer->c_flags |= C_POLL; 958 xfer->c_drive = drvp->drive; 959 xfer->c_cmd = ata_bio; 960 xfer->c_databuf = ata_bio->databuf; 961 xfer->c_bcount = ata_bio->bcount; 962 xfer->c_start = ahci_bio_start; 963 xfer->c_intr = ahci_bio_complete; 964 xfer->c_kill_xfer = ahci_bio_kill_xfer; 965 ata_exec_xfer(chp, xfer); 966 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 967 } 968 969 static void 970 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 971 { 972 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 973 struct ahci_channel *achp = (struct ahci_channel *)chp; 974 struct ata_bio *ata_bio = xfer->c_cmd; 975 int slot = 0 /* XXX slot */; 976 struct ahci_cmd_tbl *cmd_tbl; 977 struct ahci_cmd_header *cmd_h; 978 int i; 979 int channel = chp->ch_channel; 980 981 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 982 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 983 984 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 985 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 986 cmd_tbl), DEBUG_XFERS); 987 988 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 989 990 cmd_h = &achp->ahcic_cmdh[slot]; 991 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 992 chp->ch_channel, cmd_h), DEBUG_XFERS); 993 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 994 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 995 ata_bio->error = ERR_DMA; 996 ata_bio->r_error = 0; 997 ahci_bio_complete(chp, xfer, slot); 998 return; 999 } 1000 cmd_h->cmdh_flags = htole16( 1001 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1002 RHD_FISLEN / 4); 1003 cmd_h->cmdh_prdbc = 0; 1004 AHCI_CMDH_SYNC(sc, achp, slot, 1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1006 1007 if (xfer->c_flags & C_POLL) { 1008 /* polled command, disable interrupts */ 1009 AHCI_WRITE(sc, AHCI_GHC, 1010 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1011 } 1012 chp->ch_flags |= ATACH_IRQ_WAIT; 1013 chp->ch_status = 0; 1014 /* start command */ 1015 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1016 /* and says we started this command */ 1017 achp->ahcic_cmds_active |= 1 << slot; 1018 1019 if ((xfer->c_flags & C_POLL) == 0) { 1020 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1021 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1022 ahci_timeout, chp); 1023 return; 1024 } 1025 /* 1026 * Polled command. 1027 */ 1028 for (i = 0; i < ATA_DELAY / 10; i++) { 1029 if (ata_bio->flags & ATA_ITSDONE) 1030 break; 1031 ahci_intr_port(sc, achp); 1032 if (ata_bio->flags & ATA_NOSLEEP) 1033 delay(10000); 1034 else 1035 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1036 } 1037 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1038 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1039 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1040 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1041 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1042 DEBUG_XFERS); 1043 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1044 ata_bio->error = TIMEOUT; 1045 ahci_bio_complete(chp, xfer, slot); 1046 } 1047 /* reenable interrupts */ 1048 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1049 } 1050 1051 static void 1052 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1053 { 1054 int slot = 0; /* XXX slot */ 1055 int drive = xfer->c_drive; 1056 struct ata_bio *ata_bio = xfer->c_cmd; 1057 struct ahci_channel *achp = (struct ahci_channel *)chp; 1058 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1059 DEBUG_FUNCS); 1060 1061 achp->ahcic_cmds_active &= ~(1 << slot); 1062 ata_free_xfer(chp, xfer); 1063 ata_bio->flags |= ATA_ITSDONE; 1064 switch (reason) { 1065 case KILL_GONE: 1066 ata_bio->error = ERR_NODEV; 1067 break; 1068 case KILL_RESET: 1069 ata_bio->error = ERR_RESET; 1070 break; 1071 default: 1072 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1073 panic("ahci_bio_kill_xfer"); 1074 } 1075 ata_bio->r_error = WDCE_ABRT; 1076 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1077 } 1078 1079 static int 1080 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1081 { 1082 int slot = 0; /* XXX slot */ 1083 struct ata_bio *ata_bio = xfer->c_cmd; 1084 int drive = xfer->c_drive; 1085 struct ahci_channel *achp = (struct ahci_channel *)chp; 1086 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1087 1088 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1089 DEBUG_FUNCS); 1090 1091 achp->ahcic_cmds_active &= ~(1 << slot); 1092 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1093 if (xfer->c_flags & C_TIMEOU) { 1094 ata_bio->error = TIMEOUT; 1095 } else { 1096 callout_stop(&chp->ch_callout); 1097 ata_bio->error = NOERROR; 1098 } 1099 1100 chp->ch_queue->active_xfer = NULL; 1101 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1102 achp->ahcic_datad[slot]->dm_mapsize, 1103 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1104 BUS_DMASYNC_POSTWRITE); 1105 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1106 1107 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1108 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1109 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1110 wakeup(&chp->ch_queue->active_xfer); 1111 return 0; 1112 } 1113 ata_free_xfer(chp, xfer); 1114 ata_bio->flags |= ATA_ITSDONE; 1115 if (chp->ch_status & WDCS_DWF) { 1116 ata_bio->error = ERR_DF; 1117 } else if (chp->ch_status & WDCS_ERR) { 1118 ata_bio->error = ERROR; 1119 ata_bio->r_error = chp->ch_error; 1120 } else if (chp->ch_status & WDCS_CORR) 1121 ata_bio->flags |= ATA_CORR; 1122 1123 AHCI_CMDH_SYNC(sc, achp, slot, 1124 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1125 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1126 ata_bio->bcount), DEBUG_XFERS); 1127 /* 1128 * if it was a write, complete data buffer may have been transfered 1129 * before error detection; in this case don't use cmdh_prdbc 1130 * as it won't reflect what was written to media. Assume nothing 1131 * was transfered and leave bcount as-is. 1132 */ 1133 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1134 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1135 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1136 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1137 atastart(chp); 1138 return 0; 1139 } 1140 1141 static void 1142 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1143 { 1144 int i; 1145 /* stop channel */ 1146 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1147 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1148 /* wait 1s for channel to stop */ 1149 for (i = 0; i <100; i++) { 1150 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1151 == 0) 1152 break; 1153 if (flags & AT_WAIT) 1154 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1155 else 1156 delay(10000); 1157 } 1158 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1159 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1160 /* XXX controller reset ? */ 1161 return; 1162 } 1163 } 1164 1165 static void 1166 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1167 { 1168 /* clear error */ 1169 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1170 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1171 1172 /* and start controller */ 1173 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1174 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1175 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1176 } 1177 1178 static void 1179 ahci_timeout(void *v) 1180 { 1181 struct ata_channel *chp = (struct ata_channel *)v; 1182 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1183 int s = splbio(); 1184 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1185 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1186 xfer->c_flags |= C_TIMEOU; 1187 xfer->c_intr(chp, xfer, 0); 1188 } 1189 splx(s); 1190 } 1191 1192 static int 1193 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1194 size_t count, int op) 1195 { 1196 int error, seg; 1197 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1198 struct ahci_channel *achp = (struct ahci_channel *)chp; 1199 struct ahci_cmd_tbl *cmd_tbl; 1200 struct ahci_cmd_header *cmd_h; 1201 1202 cmd_h = &achp->ahcic_cmdh[slot]; 1203 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1204 1205 if (data == NULL) { 1206 cmd_h->cmdh_prdtl = 0; 1207 goto end; 1208 } 1209 1210 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1211 data, count, NULL, 1212 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1213 if (error) { 1214 printf("%s port %d: failed to load xfer: %d\n", 1215 AHCINAME(sc), chp->ch_channel, error); 1216 return error; 1217 } 1218 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1219 achp->ahcic_datad[slot]->dm_mapsize, 1220 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1221 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1222 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1223 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1224 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1225 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1226 } 1227 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1228 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1229 end: 1230 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1231 return 0; 1232 } 1233 1234 #if NATAPIBUS > 0 1235 static void 1236 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1237 { 1238 struct ata_channel *chp = ata_sc->sc_chan; 1239 struct atac_softc *atac = chp->ch_atac; 1240 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1241 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1242 /* 1243 * Fill in the scsipi_adapter. 1244 */ 1245 adapt->adapt_dev = atac->atac_dev; 1246 adapt->adapt_nchannels = atac->atac_nchannels; 1247 adapt->adapt_request = ahci_atapi_scsipi_request; 1248 adapt->adapt_minphys = ahci_atapi_minphys; 1249 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1250 1251 /* 1252 * Fill in the scsipi_channel. 1253 */ 1254 memset(chan, 0, sizeof(*chan)); 1255 chan->chan_adapter = adapt; 1256 chan->chan_bustype = &ahci_atapi_bustype; 1257 chan->chan_channel = chp->ch_channel; 1258 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1259 chan->chan_openings = 1; 1260 chan->chan_max_periph = 1; 1261 chan->chan_ntargets = 1; 1262 chan->chan_nluns = 1; 1263 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1264 atapiprint); 1265 } 1266 1267 static void 1268 ahci_atapi_minphys(struct buf *bp) 1269 { 1270 if (bp->b_bcount > MAXPHYS) 1271 bp->b_bcount = MAXPHYS; 1272 minphys(bp); 1273 } 1274 1275 /* 1276 * Kill off all pending xfers for a periph. 1277 * 1278 * Must be called at splbio(). 1279 */ 1280 static void 1281 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1282 { 1283 struct atac_softc *atac = 1284 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1285 struct ata_channel *chp = 1286 atac->atac_channels[periph->periph_channel->chan_channel]; 1287 1288 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1289 } 1290 1291 static void 1292 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1293 scsipi_adapter_req_t req, void *arg) 1294 { 1295 struct scsipi_adapter *adapt = chan->chan_adapter; 1296 struct scsipi_periph *periph; 1297 struct scsipi_xfer *sc_xfer; 1298 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1299 struct atac_softc *atac = &sc->sc_atac; 1300 struct ata_xfer *xfer; 1301 int channel = chan->chan_channel; 1302 int drive, s; 1303 1304 switch (req) { 1305 case ADAPTER_REQ_RUN_XFER: 1306 sc_xfer = arg; 1307 periph = sc_xfer->xs_periph; 1308 drive = periph->periph_target; 1309 if (!device_is_active(atac->atac_dev)) { 1310 sc_xfer->error = XS_DRIVER_STUFFUP; 1311 scsipi_done(sc_xfer); 1312 return; 1313 } 1314 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1315 if (xfer == NULL) { 1316 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1317 scsipi_done(sc_xfer); 1318 return; 1319 } 1320 1321 if (sc_xfer->xs_control & XS_CTL_POLL) 1322 xfer->c_flags |= C_POLL; 1323 xfer->c_drive = drive; 1324 xfer->c_flags |= C_ATAPI; 1325 xfer->c_cmd = sc_xfer; 1326 xfer->c_databuf = sc_xfer->data; 1327 xfer->c_bcount = sc_xfer->datalen; 1328 xfer->c_start = ahci_atapi_start; 1329 xfer->c_intr = ahci_atapi_complete; 1330 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1331 xfer->c_dscpoll = 0; 1332 s = splbio(); 1333 ata_exec_xfer(atac->atac_channels[channel], xfer); 1334 #ifdef DIAGNOSTIC 1335 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1336 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1337 panic("ahci_atapi_scsipi_request: polled command " 1338 "not done"); 1339 #endif 1340 splx(s); 1341 return; 1342 default: 1343 /* Not supported, nothing to do. */ 1344 ; 1345 } 1346 } 1347 1348 static void 1349 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1350 { 1351 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1352 struct ahci_channel *achp = (struct ahci_channel *)chp; 1353 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1354 int slot = 0 /* XXX slot */; 1355 struct ahci_cmd_tbl *cmd_tbl; 1356 struct ahci_cmd_header *cmd_h; 1357 int i; 1358 int channel = chp->ch_channel; 1359 1360 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1361 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1362 1363 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1364 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1365 cmd_tbl), DEBUG_XFERS); 1366 1367 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1368 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1369 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1370 1371 cmd_h = &achp->ahcic_cmdh[slot]; 1372 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1373 chp->ch_channel, cmd_h), DEBUG_XFERS); 1374 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1375 sc_xfer->datalen, 1376 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1377 BUS_DMA_READ : BUS_DMA_WRITE)) { 1378 sc_xfer->error = XS_DRIVER_STUFFUP; 1379 ahci_atapi_complete(chp, xfer, slot); 1380 return; 1381 } 1382 cmd_h->cmdh_flags = htole16( 1383 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1384 RHD_FISLEN / 4 | AHCI_CMDH_F_A); 1385 cmd_h->cmdh_prdbc = 0; 1386 AHCI_CMDH_SYNC(sc, achp, slot, 1387 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1388 1389 if (xfer->c_flags & C_POLL) { 1390 /* polled command, disable interrupts */ 1391 AHCI_WRITE(sc, AHCI_GHC, 1392 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1393 } 1394 chp->ch_flags |= ATACH_IRQ_WAIT; 1395 chp->ch_status = 0; 1396 /* start command */ 1397 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1398 /* and says we started this command */ 1399 achp->ahcic_cmds_active |= 1 << slot; 1400 1401 if ((xfer->c_flags & C_POLL) == 0) { 1402 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1403 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1404 ahci_timeout, chp); 1405 return; 1406 } 1407 /* 1408 * Polled command. 1409 */ 1410 for (i = 0; i < ATA_DELAY / 10; i++) { 1411 if (sc_xfer->xs_status & XS_STS_DONE) 1412 break; 1413 ahci_intr_port(sc, achp); 1414 delay(10000); 1415 } 1416 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1417 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1418 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1419 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1420 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1421 DEBUG_XFERS); 1422 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1423 sc_xfer->error = XS_TIMEOUT; 1424 ahci_atapi_complete(chp, xfer, slot); 1425 } 1426 /* reenable interrupts */ 1427 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1428 } 1429 1430 static int 1431 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1432 { 1433 int slot = 0; /* XXX slot */ 1434 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1435 int drive = xfer->c_drive; 1436 struct ahci_channel *achp = (struct ahci_channel *)chp; 1437 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1438 1439 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1440 DEBUG_FUNCS); 1441 1442 achp->ahcic_cmds_active &= ~(1 << slot); 1443 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1444 if (xfer->c_flags & C_TIMEOU) { 1445 sc_xfer->error = XS_TIMEOUT; 1446 } else { 1447 callout_stop(&chp->ch_callout); 1448 sc_xfer->error = 0; 1449 } 1450 1451 chp->ch_queue->active_xfer = NULL; 1452 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1453 achp->ahcic_datad[slot]->dm_mapsize, 1454 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1455 BUS_DMASYNC_POSTWRITE); 1456 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1457 1458 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1459 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1460 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1461 wakeup(&chp->ch_queue->active_xfer); 1462 return 0; 1463 } 1464 ata_free_xfer(chp, xfer); 1465 1466 AHCI_CMDH_SYNC(sc, achp, slot, 1467 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1468 sc_xfer->resid = sc_xfer->datalen; 1469 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1470 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1471 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1472 if (chp->ch_status & WDCS_ERR && 1473 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1474 sc_xfer->resid == sc_xfer->datalen)) { 1475 sc_xfer->error = XS_SHORTSENSE; 1476 sc_xfer->sense.atapi_sense = chp->ch_error; 1477 if ((sc_xfer->xs_periph->periph_quirks & 1478 PQUIRK_NOSENSE) == 0) { 1479 /* ask scsipi to send a REQUEST_SENSE */ 1480 sc_xfer->error = XS_BUSY; 1481 sc_xfer->status = SCSI_CHECK; 1482 } 1483 } 1484 scsipi_done(sc_xfer); 1485 atastart(chp); 1486 return 0; 1487 } 1488 1489 static void 1490 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1491 { 1492 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1493 struct ahci_channel *achp = (struct ahci_channel *)chp; 1494 int slot = 0; /* XXX slot */ 1495 1496 achp->ahcic_cmds_active &= ~(1 << slot); 1497 1498 /* remove this command from xfer queue */ 1499 switch (reason) { 1500 case KILL_GONE: 1501 sc_xfer->error = XS_DRIVER_STUFFUP; 1502 break; 1503 case KILL_RESET: 1504 sc_xfer->error = XS_RESET; 1505 break; 1506 default: 1507 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1508 panic("ahci_ata_atapi_kill_xfer"); 1509 } 1510 ata_free_xfer(chp, xfer); 1511 scsipi_done(sc_xfer); 1512 } 1513 1514 static void 1515 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1516 { 1517 struct scsipi_channel *chan = sc->sc_channel; 1518 struct scsipi_periph *periph; 1519 struct ataparams ids; 1520 struct ataparams *id = &ids; 1521 struct ahci_softc *ahcic = 1522 device_private(chan->chan_adapter->adapt_dev); 1523 struct atac_softc *atac = &ahcic->sc_atac; 1524 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1525 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1526 struct scsipibus_attach_args sa; 1527 char serial_number[21], model[41], firmware_revision[9]; 1528 int s; 1529 1530 /* skip if already attached */ 1531 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1532 return; 1533 1534 /* if no ATAPI device detected at attach time, skip */ 1535 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1536 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1537 "not present\n", target), DEBUG_PROBE); 1538 return; 1539 } 1540 1541 /* Some ATAPI devices need a bit more time after software reset. */ 1542 delay(5000); 1543 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1544 #ifdef ATAPI_DEBUG_PROBE 1545 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1546 AHCINAME(ahcic), target, 1547 id->atap_config & ATAPI_CFG_CMD_MASK, 1548 id->atap_config & ATAPI_CFG_DRQ_MASK); 1549 #endif 1550 periph = scsipi_alloc_periph(M_NOWAIT); 1551 if (periph == NULL) { 1552 aprint_error_dev(sc->sc_dev, 1553 "unable to allocate periph for drive %d\n", 1554 target); 1555 return; 1556 } 1557 periph->periph_dev = NULL; 1558 periph->periph_channel = chan; 1559 periph->periph_switch = &atapi_probe_periphsw; 1560 periph->periph_target = target; 1561 periph->periph_lun = 0; 1562 periph->periph_quirks = PQUIRK_ONLYBIG; 1563 1564 #ifdef SCSIPI_DEBUG 1565 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1566 SCSIPI_DEBUG_TARGET == target) 1567 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1568 #endif 1569 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1570 if (id->atap_config & ATAPI_CFG_REMOV) 1571 periph->periph_flags |= PERIPH_REMOVABLE; 1572 if (periph->periph_type == T_SEQUENTIAL) { 1573 s = splbio(); 1574 drvp->drive_flags |= DRIVE_ATAPIST; 1575 splx(s); 1576 } 1577 1578 sa.sa_periph = periph; 1579 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1580 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1581 T_REMOV : T_FIXED; 1582 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1583 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1584 20); 1585 scsipi_strvis((u_char *)firmware_revision, 8, 1586 id->atap_revision, 8); 1587 sa.sa_inqbuf.vendor = model; 1588 sa.sa_inqbuf.product = serial_number; 1589 sa.sa_inqbuf.revision = firmware_revision; 1590 1591 /* 1592 * Determine the operating mode capabilities of the device. 1593 */ 1594 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1595 periph->periph_cap |= PERIPH_CAP_CMD16; 1596 /* XXX This is gross. */ 1597 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1598 1599 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1600 1601 if (drvp->drv_softc) 1602 ata_probe_caps(drvp); 1603 else { 1604 s = splbio(); 1605 drvp->drive_flags &= ~DRIVE_ATAPI; 1606 splx(s); 1607 } 1608 } else { 1609 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1610 "failed for drive %s:%d:%d: error 0x%x\n", 1611 AHCINAME(ahcic), chp->ch_channel, target, 1612 chp->ch_error), DEBUG_PROBE); 1613 s = splbio(); 1614 drvp->drive_flags &= ~DRIVE_ATAPI; 1615 splx(s); 1616 } 1617 } 1618 #endif /* NATAPIBUS */ 1619
Indexes created Fri Oct 17 00:09:41 GMT 2025