ahcisata_core.c revision 1.17
1 /* $NetBSD: ahcisata_core.c,v 1.17 2008/08/01 17:41:54 dillo Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.17 2008/08/01 17:41:54 dillo Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 #include <sys/buf.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/ic/wdcreg.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/satavar.h> 50 #include <dev/ata/satareg.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 54 55 #include "atapibus.h" 56 57 #ifdef AHCI_DEBUG 58 int ahcidebug_mask = 0x0; 59 #endif 60 61 void ahci_probe_drive(struct ata_channel *); 62 void ahci_setup_channel(struct ata_channel *); 63 64 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 65 void ahci_reset_drive(struct ata_drive_datas *, int); 66 void ahci_reset_channel(struct ata_channel *, int); 67 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 68 int ahci_ata_addref(struct ata_drive_datas *); 69 void ahci_ata_delref(struct ata_drive_datas *); 70 void ahci_killpending(struct ata_drive_datas *); 71 72 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 73 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 74 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 75 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 77 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 78 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 79 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 80 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 81 void ahci_timeout(void *); 82 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 83 84 #if NATAPIBUS > 0 85 void ahci_atapibus_attach(struct atabus_softc *); 86 void ahci_atapi_kill_pending(struct scsipi_periph *); 87 void ahci_atapi_minphys(struct buf *); 88 void ahci_atapi_scsipi_request(struct scsipi_channel *, 89 scsipi_adapter_req_t, void *); 90 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 91 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 92 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 93 void ahci_atapi_probe_device(struct atapibus_softc *, int); 94 95 static const struct scsipi_bustype ahci_atapi_bustype = { 96 SCSIPI_BUSTYPE_ATAPI, 97 atapi_scsipi_cmd, 98 atapi_interpret_sense, 99 atapi_print_addr, 100 ahci_atapi_kill_pending, 101 }; 102 #endif /* NATAPIBUS */ 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 const struct ata_bustype ahci_ata_bustype = { 107 SCSIPI_BUSTYPE_ATA, 108 ahci_ata_bio, 109 ahci_reset_drive, 110 ahci_reset_channel, 111 ahci_exec_command, 112 ata_get_params, 113 ahci_ata_addref, 114 ahci_ata_delref, 115 ahci_killpending 116 }; 117 118 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 119 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 int 123 ahci_reset(struct ahci_softc *sc) 124 { 125 int i; 126 127 /* reset controller */ 128 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 129 /* wait up to 1s for reset to complete */ 130 for (i = 0; i < 1000; i++) { 131 delay(1000); 132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 133 break; 134 } 135 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 136 aprint_error("%s: reset failed\n", AHCINAME(sc)); 137 return -1; 138 } 139 /* enable ahci mode */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 141 return 0; 142 } 143 144 void 145 ahci_setup_ports(struct ahci_softc *sc) 146 { 147 u_int32_t ahci_ports; 148 int i, port; 149 150 ahci_ports = AHCI_READ(sc, AHCI_PI); 151 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 152 if ((ahci_ports & (1 << i)) == 0) 153 continue; 154 if (port >= sc->sc_atac.atac_nchannels) { 155 aprint_error("%s: more ports than announced\n", 156 AHCINAME(sc)); 157 break; 158 } 159 ahci_setup_port(sc, i); 160 } 161 } 162 163 void 164 ahci_reprobe_drives(struct ahci_softc *sc) 165 { 166 u_int32_t ahci_ports; 167 int i, port; 168 struct ahci_channel *achp; 169 struct ata_channel *chp; 170 171 ahci_ports = AHCI_READ(sc, AHCI_PI); 172 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 173 if ((ahci_ports & (1 << i)) == 0) 174 continue; 175 if (port >= sc->sc_atac.atac_nchannels) { 176 aprint_error("%s: more ports than announced\n", 177 AHCINAME(sc)); 178 break; 179 } 180 achp = &sc->sc_channels[i]; 181 chp = &achp->ata_channel; 182 183 ahci_probe_drive(chp); 184 } 185 } 186 187 static void 188 ahci_setup_port(struct ahci_softc *sc, int i) 189 { 190 struct ahci_channel *achp; 191 192 achp = &sc->sc_channels[i]; 193 194 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 195 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 196 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 197 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 198 } 199 200 void 201 ahci_enable_intrs(struct ahci_softc *sc) 202 { 203 204 /* clear interrupts */ 205 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 206 /* enable interrupts */ 207 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 208 } 209 210 void 211 ahci_attach(struct ahci_softc *sc) 212 { 213 u_int32_t ahci_cap, ahci_rev, ahci_ports; 214 int i, j, port; 215 struct ahci_channel *achp; 216 struct ata_channel *chp; 217 int error; 218 bus_dma_segment_t seg; 219 int rseg; 220 int dmasize; 221 void *cmdhp; 222 void *cmdtblp; 223 224 if (ahci_reset(sc) != 0) 225 return; 226 227 ahci_cap = AHCI_READ(sc, AHCI_CAP); 228 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 229 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 230 ahci_rev = AHCI_READ(sc, AHCI_VS); 231 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 232 switch(ahci_rev) { 233 case AHCI_VS_10: 234 aprint_normal("1.0"); 235 break; 236 case AHCI_VS_11: 237 aprint_normal("1.1"); 238 break; 239 case AHCI_VS_12: 240 aprint_normal("1.2"); 241 break; 242 default: 243 aprint_normal("0x%x", ahci_rev); 244 break; 245 } 246 247 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 248 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 249 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 250 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 251 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 252 sc->sc_atac.atac_pio_cap = 4; 253 sc->sc_atac.atac_dma_cap = 2; 254 sc->sc_atac.atac_udma_cap = 6; 255 sc->sc_atac.atac_channels = sc->sc_chanarray; 256 sc->sc_atac.atac_probe = ahci_probe_drive; 257 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 258 sc->sc_atac.atac_set_modes = ahci_setup_channel; 259 #if NATAPIBUS > 0 260 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 261 #endif 262 263 dmasize = 264 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 265 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 266 &seg, 1, &rseg, BUS_DMA_NOWAIT); 267 if (error) { 268 aprint_error("%s: unable to allocate command header memory" 269 ", error=%d\n", AHCINAME(sc), error); 270 return; 271 } 272 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 273 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 274 if (error) { 275 aprint_error("%s: unable to map command header memory" 276 ", error=%d\n", AHCINAME(sc), error); 277 return; 278 } 279 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 280 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 281 if (error) { 282 aprint_error("%s: unable to create command header map" 283 ", error=%d\n", AHCINAME(sc), error); 284 return; 285 } 286 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 287 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 288 if (error) { 289 aprint_error("%s: unable to load command header map" 290 ", error=%d\n", AHCINAME(sc), error); 291 return; 292 } 293 sc->sc_cmd_hdr = cmdhp; 294 295 ahci_enable_intrs(sc); 296 297 ahci_ports = AHCI_READ(sc, AHCI_PI); 298 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 299 if ((ahci_ports & (1 << i)) == 0) 300 continue; 301 if (port >= sc->sc_atac.atac_nchannels) { 302 aprint_error("%s: more ports than announced\n", 303 AHCINAME(sc)); 304 break; 305 } 306 achp = &sc->sc_channels[i]; 307 chp = (struct ata_channel *)achp; 308 sc->sc_chanarray[i] = chp; 309 chp->ch_channel = i; 310 chp->ch_atac = &sc->sc_atac; 311 chp->ch_queue = malloc(sizeof(struct ata_queue), 312 M_DEVBUF, M_NOWAIT); 313 if (chp->ch_queue == NULL) { 314 aprint_error("%s port %d: can't allocate memory for " 315 "command queue", AHCINAME(sc), i); 316 break; 317 } 318 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 319 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 320 &seg, 1, &rseg, BUS_DMA_NOWAIT); 321 if (error) { 322 aprint_error("%s: unable to allocate command table " 323 "memory, error=%d\n", AHCINAME(sc), error); 324 break; 325 } 326 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 327 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 328 if (error) { 329 aprint_error("%s: unable to map command table memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 break; 332 } 333 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 334 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 335 if (error) { 336 aprint_error("%s: unable to create command table map" 337 ", error=%d\n", AHCINAME(sc), error); 338 break; 339 } 340 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 341 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 342 if (error) { 343 aprint_error("%s: unable to load command table map" 344 ", error=%d\n", AHCINAME(sc), error); 345 break; 346 } 347 achp->ahcic_cmdh = (struct ahci_cmd_header *) 348 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 349 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 350 AHCI_CMDH_SIZE * port; 351 achp->ahcic_rfis = (struct ahci_r_fis *) 352 ((char *)cmdhp + 353 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 354 AHCI_RFIS_SIZE * port); 355 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 356 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 357 AHCI_RFIS_SIZE * port; 358 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 359 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 360 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 361 DEBUG_PROBE); 362 363 for (j = 0; j < sc->sc_ncmds; j++) { 364 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 365 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 366 achp->ahcic_bus_cmd_tbl[j] = 367 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 368 AHCI_CMDTBL_SIZE * j; 369 achp->ahcic_cmdh[j].cmdh_cmdtba = 370 htole32(achp->ahcic_bus_cmd_tbl[j]); 371 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 372 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 373 achp->ahcic_cmd_tbl[j], 374 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 375 /* The xfer DMA map */ 376 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 377 AHCI_NPRD, 0x400000 /* 4MB */, 0, 378 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 379 &achp->ahcic_datad[j]); 380 if (error) { 381 aprint_error("%s: couldn't alloc xfer DMA map, " 382 "error=%d\n", AHCINAME(sc), error); 383 goto end; 384 } 385 } 386 ahci_setup_port(sc, i); 387 chp->ch_ndrive = 1; 388 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 389 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 390 aprint_error("%s: couldn't map channel %d " 391 "sata_status regs\n", AHCINAME(sc), i); 392 break; 393 } 394 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 395 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 396 aprint_error("%s: couldn't map channel %d " 397 "sata_control regs\n", AHCINAME(sc), i); 398 break; 399 } 400 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 401 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 402 aprint_error("%s: couldn't map channel %d " 403 "sata_error regs\n", AHCINAME(sc), i); 404 break; 405 } 406 ata_channel_attach(chp); 407 port++; 408 end: 409 continue; 410 } 411 } 412 413 int 414 ahci_intr(void *v) 415 { 416 struct ahci_softc *sc = v; 417 u_int32_t is; 418 int i, r = 0; 419 420 while ((is = AHCI_READ(sc, AHCI_IS))) { 421 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 422 DEBUG_INTR); 423 r = 1; 424 AHCI_WRITE(sc, AHCI_IS, is); 425 for (i = 0; i < AHCI_MAX_PORTS; i++) 426 if (is & (1 << i)) 427 ahci_intr_port(sc, &sc->sc_channels[i]); 428 } 429 return r; 430 } 431 432 void 433 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 434 { 435 u_int32_t is, tfd; 436 struct ata_channel *chp = &achp->ata_channel; 437 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 438 int slot; 439 440 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 441 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 442 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 443 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 444 DEBUG_INTR); 445 446 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 447 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 448 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 449 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 450 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 451 return; 452 /* stop channel */ 453 ahci_channel_stop(sc, chp, 0); 454 if (slot != 0) { 455 printf("ahci_intr_port: slot %d\n", slot); 456 panic("ahci_intr_port"); 457 } 458 if (is & AHCI_P_IX_TFES) { 459 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 460 chp->ch_error = 461 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 462 chp->ch_status = (tfd & 0xff); 463 } else { 464 /* emulate a CRC error */ 465 chp->ch_error = WDCE_CRC; 466 chp->ch_status = WDCS_ERR; 467 } 468 xfer->c_intr(chp, xfer, is); 469 /* if channel has not been restarted, do it now */ 470 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 471 == 0) 472 ahci_channel_start(sc, chp); 473 } else { 474 slot = 0; /* XXX */ 475 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 476 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 477 chp->ch_channel, is, achp->ahcic_cmds_active, 478 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 479 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 480 return; 481 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 482 == 0) { 483 xfer->c_intr(chp, xfer, 0); 484 } 485 } 486 } 487 488 void 489 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 490 { 491 struct ata_channel *chp = drvp->chnl_softc; 492 ata_reset_channel(chp, flags); 493 return; 494 } 495 496 void 497 ahci_reset_channel(struct ata_channel *chp, int flags) 498 { 499 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 500 struct ahci_channel *achp = (struct ahci_channel *)chp; 501 502 ahci_channel_stop(sc, chp, flags); 503 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 504 achp->ahcic_sstatus) != SStatus_DET_DEV) { 505 printf("%s: port reset failed\n", AHCINAME(sc)); 506 /* XXX and then ? */ 507 } 508 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 509 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 510 if (chp->ch_queue->active_xfer) { 511 chp->ch_queue->active_xfer->c_kill_xfer(chp, 512 chp->ch_queue->active_xfer, KILL_RESET); 513 } 514 ahci_channel_start(sc, chp); 515 #if 0 516 /* Wait 15s for device to host FIS to arrive. */ 517 for (i = 0; i <1500; i++) { 518 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) & AHCI_P_IX_DHRS) 519 break; 520 if (flags & AT_WAIT) 521 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 522 else 523 delay (10000); 524 } 525 if (i == 1500) 526 aprint_error("%s port %d: D2H FIS never arrived\n", AHCINAME(sc)); 527 #endif 528 /* clear port interrupt register */ 529 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 530 531 return; 532 } 533 534 int 535 ahci_ata_addref(struct ata_drive_datas *drvp) 536 { 537 return 0; 538 } 539 540 void 541 ahci_ata_delref(struct ata_drive_datas *drvp) 542 { 543 return; 544 } 545 546 void 547 ahci_killpending(struct ata_drive_datas *drvp) 548 { 549 return; 550 } 551 552 void 553 ahci_probe_drive(struct ata_channel *chp) 554 { 555 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 556 struct ahci_channel *achp = (struct ahci_channel *)chp; 557 int i, s; 558 u_int32_t sig; 559 560 /* XXX This should be done by other code. */ 561 for (i = 0; i < chp->ch_ndrive; i++) { 562 chp->ch_drive[i].chnl_softc = chp; 563 chp->ch_drive[i].drive = i; 564 } 565 566 /* bring interface up, power up and spin up device */ 567 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 568 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 569 /* reset the PHY and bring online */ 570 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 571 achp->ahcic_sstatus)) { 572 case SStatus_DET_DEV: 573 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 574 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 575 #if 0 576 /* wait 15s for d2h FIS */ 577 for (i = 0; i <1500; i++) { 578 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) 579 & AHCI_P_IX_DHRS) 580 break; 581 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 582 } 583 if (i == 1500) 584 aprint_error("%s: D2H FIS never arrived\n", 585 AHCINAME(sc)); 586 #endif 587 588 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 589 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 590 AHCINAME(sc), chp->ch_channel, sig, 591 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 592 /* 593 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 594 * cases we get wrong values here, so ignore it. 595 */ 596 s = splbio(); 597 if ((sig & 0xffff0000) == 0xeb140000) { 598 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 599 } else 600 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 601 splx(s); 602 /* enable interrupts */ 603 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 604 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 605 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 606 AHCI_P_IX_DHRS); 607 /* and start operations */ 608 ahci_channel_start(sc, chp); 609 /* wait 500ms before actually starting operations */ 610 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 611 break; 612 613 default: 614 break; 615 } 616 } 617 618 void 619 ahci_setup_channel(struct ata_channel *chp) 620 { 621 return; 622 } 623 624 int 625 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 626 { 627 struct ata_channel *chp = drvp->chnl_softc; 628 struct ata_xfer *xfer; 629 int ret; 630 int s; 631 632 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 633 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 634 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 635 DEBUG_XFERS); 636 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 637 ATAXF_NOSLEEP); 638 if (xfer == NULL) { 639 return ATACMD_TRY_AGAIN; 640 } 641 if (ata_c->flags & AT_POLL) 642 xfer->c_flags |= C_POLL; 643 if (ata_c->flags & AT_WAIT) 644 xfer->c_flags |= C_WAIT; 645 xfer->c_drive = drvp->drive; 646 xfer->c_databuf = ata_c->data; 647 xfer->c_bcount = ata_c->bcount; 648 xfer->c_cmd = ata_c; 649 xfer->c_start = ahci_cmd_start; 650 xfer->c_intr = ahci_cmd_complete; 651 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 652 s = splbio(); 653 ata_exec_xfer(chp, xfer); 654 #ifdef DIAGNOSTIC 655 if ((ata_c->flags & AT_POLL) != 0 && 656 (ata_c->flags & AT_DONE) == 0) 657 panic("ahci_exec_command: polled command not done"); 658 #endif 659 if (ata_c->flags & AT_DONE) { 660 ret = ATACMD_COMPLETE; 661 } else { 662 if (ata_c->flags & AT_WAIT) { 663 while ((ata_c->flags & AT_DONE) == 0) { 664 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 665 } 666 ret = ATACMD_COMPLETE; 667 } else { 668 ret = ATACMD_QUEUED; 669 } 670 } 671 splx(s); 672 return ret; 673 } 674 675 void 676 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 677 { 678 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 679 struct ahci_channel *achp = (struct ahci_channel *)chp; 680 struct ata_command *ata_c = xfer->c_cmd; 681 int slot = 0 /* XXX slot */; 682 struct ahci_cmd_tbl *cmd_tbl; 683 struct ahci_cmd_header *cmd_h; 684 u_int8_t *fis; 685 int i; 686 int channel = chp->ch_channel; 687 688 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 689 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 690 691 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 692 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 693 cmd_tbl), DEBUG_XFERS); 694 fis = cmd_tbl->cmdt_cfis; 695 696 fis[0] = 0x27; /* host to device */ 697 fis[1] = 0x80; /* command FIS */ 698 fis[2] = ata_c->r_command; 699 fis[3] = ata_c->r_features; 700 fis[4] = ata_c->r_sector; 701 fis[5] = ata_c->r_cyl & 0xff; 702 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 703 fis[7] = ata_c->r_head & 0x0f; 704 fis[8] = 0; 705 fis[9] = 0; 706 fis[10] = 0; 707 fis[11] = 0; 708 fis[12] = ata_c->r_count; 709 fis[13] = 0; 710 fis[14] = 0; 711 fis[15] = WDCTL_4BIT; 712 fis[16] = 0; 713 fis[17] = 0; 714 fis[18] = 0; 715 fis[19] = 0; 716 717 cmd_h = &achp->ahcic_cmdh[slot]; 718 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 719 chp->ch_channel, cmd_h), DEBUG_XFERS); 720 if (ahci_dma_setup(chp, slot, 721 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 722 ata_c->bcount, 723 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 724 ata_c->flags |= AT_DF; 725 ahci_cmd_complete(chp, xfer, slot); 726 return; 727 } 728 cmd_h->cmdh_flags = htole16( 729 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 730 20 /* fis lenght */ / 4); 731 cmd_h->cmdh_prdbc = 0; 732 AHCI_CMDH_SYNC(sc, achp, slot, 733 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 734 735 if (ata_c->flags & AT_POLL) { 736 /* polled command, disable interrupts */ 737 AHCI_WRITE(sc, AHCI_GHC, 738 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 739 } 740 chp->ch_flags |= ATACH_IRQ_WAIT; 741 chp->ch_status = 0; 742 /* start command */ 743 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 744 /* and says we started this command */ 745 achp->ahcic_cmds_active |= 1 << slot; 746 747 if ((ata_c->flags & AT_POLL) == 0) { 748 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 749 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 750 ahci_timeout, chp); 751 return; 752 } 753 /* 754 * Polled command. 755 */ 756 for (i = 0; i < ata_c->timeout / 10; i++) { 757 if (ata_c->flags & AT_DONE) 758 break; 759 ahci_intr_port(sc, achp); 760 if (ata_c->flags & AT_WAIT) 761 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 762 else 763 delay(10000); 764 } 765 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 766 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 767 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 768 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 769 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 770 DEBUG_XFERS); 771 if ((ata_c->flags & AT_DONE) == 0) { 772 ata_c->flags |= AT_TIMEOU; 773 ahci_cmd_complete(chp, xfer, slot); 774 } 775 /* reenable interrupts */ 776 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 777 } 778 779 void 780 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 781 { 782 struct ata_command *ata_c = xfer->c_cmd; 783 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 784 DEBUG_FUNCS); 785 786 switch (reason) { 787 case KILL_GONE: 788 ata_c->flags |= AT_GONE; 789 break; 790 case KILL_RESET: 791 ata_c->flags |= AT_RESET; 792 break; 793 default: 794 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 795 panic("ahci_cmd_kill_xfer"); 796 } 797 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 798 } 799 800 int 801 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 802 { 803 int slot = 0; /* XXX slot */ 804 struct ata_command *ata_c = xfer->c_cmd; 805 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 806 807 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 808 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 809 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 810 DEBUG_FUNCS); 811 chp->ch_flags &= ~ATACH_IRQ_WAIT; 812 if (xfer->c_flags & C_TIMEOU) { 813 ata_c->flags |= AT_TIMEOU; 814 } else 815 callout_stop(&chp->ch_callout); 816 817 chp->ch_queue->active_xfer = NULL; 818 819 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 820 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 821 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 822 wakeup(&chp->ch_queue->active_xfer); 823 return 0; 824 } 825 if (is) { 826 ata_c->r_head = 0; 827 ata_c->r_count = 0; 828 ata_c->r_sector = 0; 829 ata_c->r_cyl = 0; 830 if (chp->ch_status & WDCS_BSY) { 831 ata_c->flags |= AT_TIMEOU; 832 } else if (chp->ch_status & WDCS_ERR) { 833 ata_c->r_error = chp->ch_error; 834 ata_c->flags |= AT_ERROR; 835 } 836 } 837 ahci_cmd_done(chp, xfer, slot); 838 return 0; 839 } 840 841 void 842 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 843 { 844 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 845 struct ahci_channel *achp = (struct ahci_channel *)chp; 846 struct ata_command *ata_c = xfer->c_cmd; 847 848 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 849 DEBUG_FUNCS); 850 851 /* this comamnd is not active any more */ 852 achp->ahcic_cmds_active &= ~(1 << slot); 853 854 if (ata_c->flags & (AT_READ|AT_WRITE)) { 855 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 856 achp->ahcic_datad[slot]->dm_mapsize, 857 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 858 BUS_DMASYNC_POSTWRITE); 859 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 860 } 861 862 AHCI_CMDH_SYNC(sc, achp, slot, 863 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 864 865 ata_c->flags |= AT_DONE; 866 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 867 ata_c->flags |= AT_XFDONE; 868 869 ata_free_xfer(chp, xfer); 870 if (ata_c->flags & AT_WAIT) 871 wakeup(ata_c); 872 else if (ata_c->callback) 873 ata_c->callback(ata_c->callback_arg); 874 atastart(chp); 875 return; 876 } 877 878 int 879 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 880 { 881 struct ata_channel *chp = drvp->chnl_softc; 882 struct ata_xfer *xfer; 883 884 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 885 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 886 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 887 DEBUG_XFERS); 888 xfer = ata_get_xfer(ATAXF_NOSLEEP); 889 if (xfer == NULL) { 890 return ATACMD_TRY_AGAIN; 891 } 892 if (ata_bio->flags & ATA_POLL) 893 xfer->c_flags |= C_POLL; 894 xfer->c_drive = drvp->drive; 895 xfer->c_cmd = ata_bio; 896 xfer->c_databuf = ata_bio->databuf; 897 xfer->c_bcount = ata_bio->bcount; 898 xfer->c_start = ahci_bio_start; 899 xfer->c_intr = ahci_bio_complete; 900 xfer->c_kill_xfer = ahci_bio_kill_xfer; 901 ata_exec_xfer(chp, xfer); 902 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 903 } 904 905 void 906 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 907 { 908 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 909 struct ahci_channel *achp = (struct ahci_channel *)chp; 910 struct ata_bio *ata_bio = xfer->c_cmd; 911 int slot = 0 /* XXX slot */; 912 struct ahci_cmd_tbl *cmd_tbl; 913 struct ahci_cmd_header *cmd_h; 914 u_int8_t *fis; 915 int i, nblks; 916 int channel = chp->ch_channel; 917 918 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 919 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 920 921 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 922 923 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 924 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 925 cmd_tbl), DEBUG_XFERS); 926 fis = cmd_tbl->cmdt_cfis; 927 928 fis[0] = 0x27; /* host to device */ 929 fis[1] = 0x80; /* command FIS */ 930 if (ata_bio->flags & ATA_LBA48) { 931 fis[2] = (ata_bio->flags & ATA_READ) ? 932 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 933 } else { 934 fis[2] = 935 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 936 } 937 fis[3] = 0; /* features */ 938 fis[4] = ata_bio->blkno & 0xff; 939 fis[5] = (ata_bio->blkno >> 8) & 0xff; 940 fis[6] = (ata_bio->blkno >> 16) & 0xff; 941 if (ata_bio->flags & ATA_LBA48) { 942 fis[7] = WDSD_LBA; 943 fis[8] = (ata_bio->blkno >> 24) & 0xff; 944 fis[9] = (ata_bio->blkno >> 32) & 0xff; 945 fis[10] = (ata_bio->blkno >> 40) & 0xff; 946 } else { 947 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 948 fis[8] = 0; 949 fis[9] = 0; 950 fis[10] = 0; 951 } 952 fis[11] = 0; /* ext features */ 953 fis[12] = nblks & 0xff; 954 fis[13] = (ata_bio->flags & ATA_LBA48) ? 955 ((nblks >> 8) & 0xff) : 0; 956 fis[14] = 0; 957 fis[15] = WDCTL_4BIT; 958 fis[16] = 0; 959 fis[17] = 0; 960 fis[18] = 0; 961 fis[19] = 0; 962 963 cmd_h = &achp->ahcic_cmdh[slot]; 964 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 965 chp->ch_channel, cmd_h), DEBUG_XFERS); 966 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 967 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 968 ata_bio->error = ERR_DMA; 969 ata_bio->r_error = 0; 970 ahci_bio_complete(chp, xfer, slot); 971 return; 972 } 973 cmd_h->cmdh_flags = htole16( 974 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 975 20 /* fis lenght */ / 4); 976 cmd_h->cmdh_prdbc = 0; 977 AHCI_CMDH_SYNC(sc, achp, slot, 978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 979 980 if (xfer->c_flags & C_POLL) { 981 /* polled command, disable interrupts */ 982 AHCI_WRITE(sc, AHCI_GHC, 983 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 984 } 985 chp->ch_flags |= ATACH_IRQ_WAIT; 986 chp->ch_status = 0; 987 /* start command */ 988 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 989 /* and says we started this command */ 990 achp->ahcic_cmds_active |= 1 << slot; 991 992 if ((xfer->c_flags & C_POLL) == 0) { 993 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 994 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 995 ahci_timeout, chp); 996 return; 997 } 998 /* 999 * Polled command. 1000 */ 1001 for (i = 0; i < ATA_DELAY / 10; i++) { 1002 if (ata_bio->flags & ATA_ITSDONE) 1003 break; 1004 ahci_intr_port(sc, achp); 1005 if (ata_bio->flags & ATA_NOSLEEP) 1006 delay(10000); 1007 else 1008 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1009 } 1010 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1011 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1012 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1013 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1014 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1015 DEBUG_XFERS); 1016 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1017 ata_bio->error = TIMEOUT; 1018 ahci_bio_complete(chp, xfer, slot); 1019 } 1020 /* reenable interrupts */ 1021 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1022 } 1023 1024 void 1025 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1026 { 1027 int slot = 0; /* XXX slot */ 1028 int drive = xfer->c_drive; 1029 struct ata_bio *ata_bio = xfer->c_cmd; 1030 struct ahci_channel *achp = (struct ahci_channel *)chp; 1031 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1032 DEBUG_FUNCS); 1033 1034 achp->ahcic_cmds_active &= ~(1 << slot); 1035 ata_free_xfer(chp, xfer); 1036 ata_bio->flags |= ATA_ITSDONE; 1037 switch (reason) { 1038 case KILL_GONE: 1039 ata_bio->error = ERR_NODEV; 1040 break; 1041 case KILL_RESET: 1042 ata_bio->error = ERR_RESET; 1043 break; 1044 default: 1045 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1046 panic("ahci_bio_kill_xfer"); 1047 } 1048 ata_bio->r_error = WDCE_ABRT; 1049 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1050 } 1051 1052 int 1053 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1054 { 1055 int slot = 0; /* XXX slot */ 1056 struct ata_bio *ata_bio = xfer->c_cmd; 1057 int drive = xfer->c_drive; 1058 struct ahci_channel *achp = (struct ahci_channel *)chp; 1059 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1060 1061 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1062 DEBUG_FUNCS); 1063 1064 achp->ahcic_cmds_active &= ~(1 << slot); 1065 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1066 if (xfer->c_flags & C_TIMEOU) { 1067 ata_bio->error = TIMEOUT; 1068 } else { 1069 callout_stop(&chp->ch_callout); 1070 ata_bio->error = 0; 1071 } 1072 1073 chp->ch_queue->active_xfer = NULL; 1074 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1075 achp->ahcic_datad[slot]->dm_mapsize, 1076 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1077 BUS_DMASYNC_POSTWRITE); 1078 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1079 1080 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1081 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1082 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1083 wakeup(&chp->ch_queue->active_xfer); 1084 return 0; 1085 } 1086 ata_free_xfer(chp, xfer); 1087 ata_bio->flags |= ATA_ITSDONE; 1088 if (chp->ch_status & WDCS_DWF) { 1089 ata_bio->error = ERR_DF; 1090 } else if (chp->ch_status & WDCS_ERR) { 1091 ata_bio->error = ERROR; 1092 ata_bio->r_error = chp->ch_error; 1093 } else if (chp->ch_status & WDCS_CORR) 1094 ata_bio->flags |= ATA_CORR; 1095 1096 AHCI_CMDH_SYNC(sc, achp, slot, 1097 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1098 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1099 ata_bio->bcount), DEBUG_XFERS); 1100 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1101 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1102 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1103 atastart(chp); 1104 return 0; 1105 } 1106 1107 void 1108 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1109 { 1110 int i; 1111 /* stop channel */ 1112 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1113 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1114 /* wait 1s for channel to stop */ 1115 for (i = 0; i <100; i++) { 1116 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1117 == 0) 1118 break; 1119 if (flags & AT_WAIT) 1120 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1121 else 1122 delay(10000); 1123 } 1124 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1125 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1126 /* XXX controller reset ? */ 1127 return; 1128 } 1129 } 1130 1131 void 1132 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1133 { 1134 /* clear error */ 1135 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1136 1137 /* and start controller */ 1138 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1139 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1140 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1141 } 1142 1143 void 1144 ahci_timeout(void *v) 1145 { 1146 struct ata_channel *chp = (struct ata_channel *)v; 1147 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1148 int s = splbio(); 1149 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1150 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1151 xfer->c_flags |= C_TIMEOU; 1152 xfer->c_intr(chp, xfer, 0); 1153 } 1154 splx(s); 1155 } 1156 1157 int 1158 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1159 size_t count, int op) 1160 { 1161 int error, seg; 1162 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1163 struct ahci_channel *achp = (struct ahci_channel *)chp; 1164 struct ahci_cmd_tbl *cmd_tbl; 1165 struct ahci_cmd_header *cmd_h; 1166 1167 cmd_h = &achp->ahcic_cmdh[slot]; 1168 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1169 1170 if (data == NULL) { 1171 cmd_h->cmdh_prdtl = 0; 1172 goto end; 1173 } 1174 1175 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1176 data, count, NULL, 1177 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1178 if (error) { 1179 printf("%s port %d: failed to load xfer: %d\n", 1180 AHCINAME(sc), chp->ch_channel, error); 1181 return error; 1182 } 1183 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1184 achp->ahcic_datad[slot]->dm_mapsize, 1185 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1186 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1187 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1188 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1189 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1190 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1191 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1192 } 1193 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1194 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1195 end: 1196 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1197 return 0; 1198 } 1199 1200 #if NATAPIBUS > 0 1201 void 1202 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1203 { 1204 struct ata_channel *chp = ata_sc->sc_chan; 1205 struct atac_softc *atac = chp->ch_atac; 1206 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1207 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1208 /* 1209 * Fill in the scsipi_adapter. 1210 */ 1211 adapt->adapt_dev = atac->atac_dev; 1212 adapt->adapt_nchannels = atac->atac_nchannels; 1213 adapt->adapt_request = ahci_atapi_scsipi_request; 1214 adapt->adapt_minphys = ahci_atapi_minphys; 1215 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1216 1217 /* 1218 * Fill in the scsipi_channel. 1219 */ 1220 memset(chan, 0, sizeof(*chan)); 1221 chan->chan_adapter = adapt; 1222 chan->chan_bustype = &ahci_atapi_bustype; 1223 chan->chan_channel = chp->ch_channel; 1224 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1225 chan->chan_openings = 1; 1226 chan->chan_max_periph = 1; 1227 chan->chan_ntargets = 1; 1228 chan->chan_nluns = 1; 1229 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1230 atapiprint); 1231 } 1232 1233 void 1234 ahci_atapi_minphys(struct buf *bp) 1235 { 1236 if (bp->b_bcount > MAXPHYS) 1237 bp->b_bcount = MAXPHYS; 1238 minphys(bp); 1239 } 1240 1241 /* 1242 * Kill off all pending xfers for a periph. 1243 * 1244 * Must be called at splbio(). 1245 */ 1246 void 1247 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1248 { 1249 struct atac_softc *atac = 1250 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1251 struct ata_channel *chp = 1252 atac->atac_channels[periph->periph_channel->chan_channel]; 1253 1254 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1255 } 1256 1257 void 1258 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1259 scsipi_adapter_req_t req, void *arg) 1260 { 1261 struct scsipi_adapter *adapt = chan->chan_adapter; 1262 struct scsipi_periph *periph; 1263 struct scsipi_xfer *sc_xfer; 1264 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1265 struct atac_softc *atac = &sc->sc_atac; 1266 struct ata_xfer *xfer; 1267 int channel = chan->chan_channel; 1268 int drive, s; 1269 1270 switch (req) { 1271 case ADAPTER_REQ_RUN_XFER: 1272 sc_xfer = arg; 1273 periph = sc_xfer->xs_periph; 1274 drive = periph->periph_target; 1275 if (!device_is_active(atac->atac_dev)) { 1276 sc_xfer->error = XS_DRIVER_STUFFUP; 1277 scsipi_done(sc_xfer); 1278 return; 1279 } 1280 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1281 if (xfer == NULL) { 1282 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1283 scsipi_done(sc_xfer); 1284 return; 1285 } 1286 1287 if (sc_xfer->xs_control & XS_CTL_POLL) 1288 xfer->c_flags |= C_POLL; 1289 xfer->c_drive = drive; 1290 xfer->c_flags |= C_ATAPI; 1291 xfer->c_cmd = sc_xfer; 1292 xfer->c_databuf = sc_xfer->data; 1293 xfer->c_bcount = sc_xfer->datalen; 1294 xfer->c_start = ahci_atapi_start; 1295 xfer->c_intr = ahci_atapi_complete; 1296 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1297 xfer->c_dscpoll = 0; 1298 s = splbio(); 1299 ata_exec_xfer(atac->atac_channels[channel], xfer); 1300 #ifdef DIAGNOSTIC 1301 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1302 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1303 panic("ahci_atapi_scsipi_request: polled command " 1304 "not done"); 1305 #endif 1306 splx(s); 1307 return; 1308 default: 1309 /* Not supported, nothing to do. */ 1310 ; 1311 } 1312 } 1313 1314 void 1315 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1316 { 1317 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1318 struct ahci_channel *achp = (struct ahci_channel *)chp; 1319 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1320 int slot = 0 /* XXX slot */; 1321 struct ahci_cmd_tbl *cmd_tbl; 1322 struct ahci_cmd_header *cmd_h; 1323 u_int8_t *fis; 1324 int i; 1325 int channel = chp->ch_channel; 1326 1327 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1328 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1329 1330 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1331 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1332 cmd_tbl), DEBUG_XFERS); 1333 fis = cmd_tbl->cmdt_cfis; 1334 1335 fis[0] = 0x27; /* host to device */ 1336 fis[1] = 0x80; /* command FIS */ 1337 fis[2] = ATAPI_PKT_CMD; 1338 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1339 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1340 fis[3] = (sc_xfer->datalen ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1341 fis[4] = 0; 1342 fis[5] = 0; 1343 fis[6] = 0; 1344 fis[7] = WDSD_LBA; 1345 fis[8] = 0; 1346 fis[9] = 0; 1347 fis[10] = 0; 1348 fis[11] = 0; /* ext features */ 1349 fis[12] = 0; 1350 fis[13] = 0; 1351 fis[14] = 0; 1352 fis[15] = WDCTL_4BIT; 1353 fis[16] = 0; 1354 fis[17] = 0; 1355 fis[18] = 0; 1356 fis[19] = 0; 1357 1358 cmd_h = &achp->ahcic_cmdh[slot]; 1359 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1360 chp->ch_channel, cmd_h), DEBUG_XFERS); 1361 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1362 sc_xfer->datalen, 1363 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1364 BUS_DMA_READ : BUS_DMA_WRITE)) { 1365 sc_xfer->error = XS_DRIVER_STUFFUP; 1366 ahci_atapi_complete(chp, xfer, slot); 1367 return; 1368 } 1369 cmd_h->cmdh_flags = htole16( 1370 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1371 20 /* fis lenght */ / 4 | AHCI_CMDH_F_A); 1372 cmd_h->cmdh_prdbc = 0; 1373 AHCI_CMDH_SYNC(sc, achp, slot, 1374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1375 1376 if (xfer->c_flags & C_POLL) { 1377 /* polled command, disable interrupts */ 1378 AHCI_WRITE(sc, AHCI_GHC, 1379 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1380 } 1381 chp->ch_flags |= ATACH_IRQ_WAIT; 1382 chp->ch_status = 0; 1383 /* start command */ 1384 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1385 /* and says we started this command */ 1386 achp->ahcic_cmds_active |= 1 << slot; 1387 1388 if ((xfer->c_flags & C_POLL) == 0) { 1389 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1390 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1391 ahci_timeout, chp); 1392 return; 1393 } 1394 /* 1395 * Polled command. 1396 */ 1397 for (i = 0; i < ATA_DELAY / 10; i++) { 1398 if (sc_xfer->xs_status & XS_STS_DONE) 1399 break; 1400 ahci_intr_port(sc, achp); 1401 delay(10000); 1402 } 1403 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1404 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1405 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1406 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1407 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1408 DEBUG_XFERS); 1409 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1410 sc_xfer->error = XS_TIMEOUT; 1411 ahci_atapi_complete(chp, xfer, slot); 1412 } 1413 /* reenable interrupts */ 1414 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1415 } 1416 1417 int 1418 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1419 { 1420 int slot = 0; /* XXX slot */ 1421 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1422 int drive = xfer->c_drive; 1423 struct ahci_channel *achp = (struct ahci_channel *)chp; 1424 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1425 1426 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1427 DEBUG_FUNCS); 1428 1429 achp->ahcic_cmds_active &= ~(1 << slot); 1430 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1431 if (xfer->c_flags & C_TIMEOU) { 1432 sc_xfer->error = XS_TIMEOUT; 1433 } else { 1434 callout_stop(&chp->ch_callout); 1435 sc_xfer->error = 0; 1436 } 1437 1438 chp->ch_queue->active_xfer = NULL; 1439 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1440 achp->ahcic_datad[slot]->dm_mapsize, 1441 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1442 BUS_DMASYNC_POSTWRITE); 1443 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1444 1445 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1446 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1447 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1448 wakeup(&chp->ch_queue->active_xfer); 1449 return 0; 1450 } 1451 ata_free_xfer(chp, xfer); 1452 1453 AHCI_CMDH_SYNC(sc, achp, slot, 1454 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1455 sc_xfer->resid = sc_xfer->datalen; 1456 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1457 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1458 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1459 if (chp->ch_status & WDCS_ERR && 1460 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1461 sc_xfer->resid == sc_xfer->datalen)) { 1462 sc_xfer->error = XS_SHORTSENSE; 1463 sc_xfer->sense.atapi_sense = chp->ch_error; 1464 if ((sc_xfer->xs_periph->periph_quirks & 1465 PQUIRK_NOSENSE) == 0) { 1466 /* ask scsipi to send a REQUEST_SENSE */ 1467 sc_xfer->error = XS_BUSY; 1468 sc_xfer->status = SCSI_CHECK; 1469 } 1470 } 1471 scsipi_done(sc_xfer); 1472 atastart(chp); 1473 return 0; 1474 } 1475 1476 void 1477 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1478 { 1479 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1480 struct ahci_channel *achp = (struct ahci_channel *)chp; 1481 int slot = 0; /* XXX slot */ 1482 1483 achp->ahcic_cmds_active &= ~(1 << slot); 1484 1485 /* remove this command from xfer queue */ 1486 switch (reason) { 1487 case KILL_GONE: 1488 sc_xfer->error = XS_DRIVER_STUFFUP; 1489 break; 1490 case KILL_RESET: 1491 sc_xfer->error = XS_RESET; 1492 break; 1493 default: 1494 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1495 panic("ahci_ata_atapi_kill_xfer"); 1496 } 1497 ata_free_xfer(chp, xfer); 1498 scsipi_done(sc_xfer); 1499 } 1500 1501 void 1502 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1503 { 1504 struct scsipi_channel *chan = sc->sc_channel; 1505 struct scsipi_periph *periph; 1506 struct ataparams ids; 1507 struct ataparams *id = &ids; 1508 struct ahci_softc *ahcic = 1509 device_private(chan->chan_adapter->adapt_dev); 1510 struct atac_softc *atac = &ahcic->sc_atac; 1511 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1512 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1513 struct scsipibus_attach_args sa; 1514 char serial_number[21], model[41], firmware_revision[9]; 1515 int s; 1516 1517 /* skip if already attached */ 1518 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1519 return; 1520 1521 /* if no ATAPI device detected at attach time, skip */ 1522 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1523 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1524 "not present\n", target), DEBUG_PROBE); 1525 return; 1526 } 1527 1528 /* Some ATAPI devices need a bit more time after software reset. */ 1529 delay(5000); 1530 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1531 #ifdef ATAPI_DEBUG_PROBE 1532 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1533 AHCINAME(ahcic), target, 1534 id->atap_config & ATAPI_CFG_CMD_MASK, 1535 id->atap_config & ATAPI_CFG_DRQ_MASK); 1536 #endif 1537 periph = scsipi_alloc_periph(M_NOWAIT); 1538 if (periph == NULL) { 1539 aprint_error_dev(sc->sc_dev, 1540 "unable to allocate periph for drive %d\n", 1541 target); 1542 return; 1543 } 1544 periph->periph_dev = NULL; 1545 periph->periph_channel = chan; 1546 periph->periph_switch = &atapi_probe_periphsw; 1547 periph->periph_target = target; 1548 periph->periph_lun = 0; 1549 periph->periph_quirks = PQUIRK_ONLYBIG; 1550 1551 #ifdef SCSIPI_DEBUG 1552 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1553 SCSIPI_DEBUG_TARGET == target) 1554 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1555 #endif 1556 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1557 if (id->atap_config & ATAPI_CFG_REMOV) 1558 periph->periph_flags |= PERIPH_REMOVABLE; 1559 if (periph->periph_type == T_SEQUENTIAL) { 1560 s = splbio(); 1561 drvp->drive_flags |= DRIVE_ATAPIST; 1562 splx(s); 1563 } 1564 1565 sa.sa_periph = periph; 1566 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1567 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1568 T_REMOV : T_FIXED; 1569 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1570 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1571 20); 1572 scsipi_strvis((u_char *)firmware_revision, 8, 1573 id->atap_revision, 8); 1574 sa.sa_inqbuf.vendor = model; 1575 sa.sa_inqbuf.product = serial_number; 1576 sa.sa_inqbuf.revision = firmware_revision; 1577 1578 /* 1579 * Determine the operating mode capabilities of the device. 1580 */ 1581 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1582 periph->periph_cap |= PERIPH_CAP_CMD16; 1583 /* XXX This is gross. */ 1584 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1585 1586 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1587 1588 if (drvp->drv_softc) 1589 ata_probe_caps(drvp); 1590 else { 1591 s = splbio(); 1592 drvp->drive_flags &= ~DRIVE_ATAPI; 1593 splx(s); 1594 } 1595 } else { 1596 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1597 "failed for drive %s:%d:%d: error 0x%x\n", 1598 AHCINAME(ahcic), chp->ch_channel, target, 1599 chp->ch_error), DEBUG_PROBE); 1600 s = splbio(); 1601 drvp->drive_flags &= ~DRIVE_ATAPI; 1602 splx(s); 1603 } 1604 } 1605 #endif /* NATAPIBUS */ 1606
Indexes created Wed Sep 24 05:09:52 GMT 2025