ahcisata_core.c revision 1.18.2.1
1 /* $NetBSD: ahcisata_core.c,v 1.18.2.1 2009/03/03 18:30:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.18.2.1 2009/03/03 18:30:45 skrll Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 #include <sys/buf.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/ic/wdcreg.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/satavar.h> 50 #include <dev/ata/satareg.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 54 55 #include "atapibus.h" 56 57 #ifdef AHCI_DEBUG 58 int ahcidebug_mask = 0x0; 59 #endif 60 61 void ahci_probe_drive(struct ata_channel *); 62 void ahci_setup_channel(struct ata_channel *); 63 64 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 65 void ahci_reset_drive(struct ata_drive_datas *, int); 66 void ahci_reset_channel(struct ata_channel *, int); 67 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 68 int ahci_ata_addref(struct ata_drive_datas *); 69 void ahci_ata_delref(struct ata_drive_datas *); 70 void ahci_killpending(struct ata_drive_datas *); 71 72 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 73 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 74 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 75 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 77 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 78 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 79 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 80 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 81 void ahci_timeout(void *); 82 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 83 84 #if NATAPIBUS > 0 85 void ahci_atapibus_attach(struct atabus_softc *); 86 void ahci_atapi_kill_pending(struct scsipi_periph *); 87 void ahci_atapi_minphys(struct buf *); 88 void ahci_atapi_scsipi_request(struct scsipi_channel *, 89 scsipi_adapter_req_t, void *); 90 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 91 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 92 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 93 void ahci_atapi_probe_device(struct atapibus_softc *, int); 94 95 static const struct scsipi_bustype ahci_atapi_bustype = { 96 SCSIPI_BUSTYPE_ATAPI, 97 atapi_scsipi_cmd, 98 atapi_interpret_sense, 99 atapi_print_addr, 100 ahci_atapi_kill_pending, 101 }; 102 #endif /* NATAPIBUS */ 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 const struct ata_bustype ahci_ata_bustype = { 107 SCSIPI_BUSTYPE_ATA, 108 ahci_ata_bio, 109 ahci_reset_drive, 110 ahci_reset_channel, 111 ahci_exec_command, 112 ata_get_params, 113 ahci_ata_addref, 114 ahci_ata_delref, 115 ahci_killpending 116 }; 117 118 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 119 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 int 123 ahci_reset(struct ahci_softc *sc) 124 { 125 int i; 126 127 /* reset controller */ 128 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 129 /* wait up to 1s for reset to complete */ 130 for (i = 0; i < 1000; i++) { 131 delay(1000); 132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 133 break; 134 } 135 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 136 aprint_error("%s: reset failed\n", AHCINAME(sc)); 137 return -1; 138 } 139 /* enable ahci mode */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 141 return 0; 142 } 143 144 void 145 ahci_setup_ports(struct ahci_softc *sc) 146 { 147 u_int32_t ahci_ports; 148 int i, port; 149 150 ahci_ports = AHCI_READ(sc, AHCI_PI); 151 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 152 if ((ahci_ports & (1 << i)) == 0) 153 continue; 154 if (port >= sc->sc_atac.atac_nchannels) { 155 aprint_error("%s: more ports than announced\n", 156 AHCINAME(sc)); 157 break; 158 } 159 ahci_setup_port(sc, i); 160 } 161 } 162 163 void 164 ahci_reprobe_drives(struct ahci_softc *sc) 165 { 166 u_int32_t ahci_ports; 167 int i, port; 168 struct ahci_channel *achp; 169 struct ata_channel *chp; 170 171 ahci_ports = AHCI_READ(sc, AHCI_PI); 172 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 173 if ((ahci_ports & (1 << i)) == 0) 174 continue; 175 if (port >= sc->sc_atac.atac_nchannels) { 176 aprint_error("%s: more ports than announced\n", 177 AHCINAME(sc)); 178 break; 179 } 180 achp = &sc->sc_channels[i]; 181 chp = &achp->ata_channel; 182 183 ahci_probe_drive(chp); 184 } 185 } 186 187 static void 188 ahci_setup_port(struct ahci_softc *sc, int i) 189 { 190 struct ahci_channel *achp; 191 192 achp = &sc->sc_channels[i]; 193 194 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 195 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 196 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 197 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 198 } 199 200 void 201 ahci_enable_intrs(struct ahci_softc *sc) 202 { 203 204 /* clear interrupts */ 205 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 206 /* enable interrupts */ 207 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 208 } 209 210 void 211 ahci_attach(struct ahci_softc *sc) 212 { 213 u_int32_t ahci_cap, ahci_rev, ahci_ports; 214 int i, j, port; 215 struct ahci_channel *achp; 216 struct ata_channel *chp; 217 int error; 218 bus_dma_segment_t seg; 219 int rseg; 220 int dmasize; 221 void *cmdhp; 222 void *cmdtblp; 223 224 if (ahci_reset(sc) != 0) 225 return; 226 227 ahci_cap = AHCI_READ(sc, AHCI_CAP); 228 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 229 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 230 ahci_rev = AHCI_READ(sc, AHCI_VS); 231 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 232 switch(ahci_rev) { 233 case AHCI_VS_10: 234 aprint_normal("1.0"); 235 break; 236 case AHCI_VS_11: 237 aprint_normal("1.1"); 238 break; 239 case AHCI_VS_12: 240 aprint_normal("1.2"); 241 break; 242 default: 243 aprint_normal("0x%x", ahci_rev); 244 break; 245 } 246 247 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 248 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 249 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 250 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 251 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 252 sc->sc_atac.atac_pio_cap = 4; 253 sc->sc_atac.atac_dma_cap = 2; 254 sc->sc_atac.atac_udma_cap = 6; 255 sc->sc_atac.atac_channels = sc->sc_chanarray; 256 sc->sc_atac.atac_probe = ahci_probe_drive; 257 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 258 sc->sc_atac.atac_set_modes = ahci_setup_channel; 259 #if NATAPIBUS > 0 260 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 261 #endif 262 263 dmasize = 264 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 265 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 266 &seg, 1, &rseg, BUS_DMA_NOWAIT); 267 if (error) { 268 aprint_error("%s: unable to allocate command header memory" 269 ", error=%d\n", AHCINAME(sc), error); 270 return; 271 } 272 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 273 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 274 if (error) { 275 aprint_error("%s: unable to map command header memory" 276 ", error=%d\n", AHCINAME(sc), error); 277 return; 278 } 279 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 280 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 281 if (error) { 282 aprint_error("%s: unable to create command header map" 283 ", error=%d\n", AHCINAME(sc), error); 284 return; 285 } 286 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 287 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 288 if (error) { 289 aprint_error("%s: unable to load command header map" 290 ", error=%d\n", AHCINAME(sc), error); 291 return; 292 } 293 sc->sc_cmd_hdr = cmdhp; 294 295 ahci_enable_intrs(sc); 296 297 ahci_ports = AHCI_READ(sc, AHCI_PI); 298 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 299 if ((ahci_ports & (1 << i)) == 0) 300 continue; 301 if (port >= sc->sc_atac.atac_nchannels) { 302 aprint_error("%s: more ports than announced\n", 303 AHCINAME(sc)); 304 break; 305 } 306 achp = &sc->sc_channels[i]; 307 chp = (struct ata_channel *)achp; 308 sc->sc_chanarray[i] = chp; 309 chp->ch_channel = i; 310 chp->ch_atac = &sc->sc_atac; 311 chp->ch_queue = malloc(sizeof(struct ata_queue), 312 M_DEVBUF, M_NOWAIT); 313 if (chp->ch_queue == NULL) { 314 aprint_error("%s port %d: can't allocate memory for " 315 "command queue", AHCINAME(sc), i); 316 break; 317 } 318 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 319 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 320 &seg, 1, &rseg, BUS_DMA_NOWAIT); 321 if (error) { 322 aprint_error("%s: unable to allocate command table " 323 "memory, error=%d\n", AHCINAME(sc), error); 324 break; 325 } 326 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 327 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 328 if (error) { 329 aprint_error("%s: unable to map command table memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 break; 332 } 333 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 334 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 335 if (error) { 336 aprint_error("%s: unable to create command table map" 337 ", error=%d\n", AHCINAME(sc), error); 338 break; 339 } 340 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 341 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 342 if (error) { 343 aprint_error("%s: unable to load command table map" 344 ", error=%d\n", AHCINAME(sc), error); 345 break; 346 } 347 achp->ahcic_cmdh = (struct ahci_cmd_header *) 348 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 349 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 350 AHCI_CMDH_SIZE * port; 351 achp->ahcic_rfis = (struct ahci_r_fis *) 352 ((char *)cmdhp + 353 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 354 AHCI_RFIS_SIZE * port); 355 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 356 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 357 AHCI_RFIS_SIZE * port; 358 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 359 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 360 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 361 DEBUG_PROBE); 362 363 for (j = 0; j < sc->sc_ncmds; j++) { 364 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 365 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 366 achp->ahcic_bus_cmd_tbl[j] = 367 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 368 AHCI_CMDTBL_SIZE * j; 369 achp->ahcic_cmdh[j].cmdh_cmdtba = 370 htole32(achp->ahcic_bus_cmd_tbl[j]); 371 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 372 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 373 achp->ahcic_cmd_tbl[j], 374 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 375 /* The xfer DMA map */ 376 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 377 AHCI_NPRD, 0x400000 /* 4MB */, 0, 378 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 379 &achp->ahcic_datad[j]); 380 if (error) { 381 aprint_error("%s: couldn't alloc xfer DMA map, " 382 "error=%d\n", AHCINAME(sc), error); 383 goto end; 384 } 385 } 386 ahci_setup_port(sc, i); 387 chp->ch_ndrive = 1; 388 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 389 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 390 aprint_error("%s: couldn't map channel %d " 391 "sata_status regs\n", AHCINAME(sc), i); 392 break; 393 } 394 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 395 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 396 aprint_error("%s: couldn't map channel %d " 397 "sata_control regs\n", AHCINAME(sc), i); 398 break; 399 } 400 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 401 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 402 aprint_error("%s: couldn't map channel %d " 403 "sata_error regs\n", AHCINAME(sc), i); 404 break; 405 } 406 ata_channel_attach(chp); 407 port++; 408 end: 409 continue; 410 } 411 } 412 413 int 414 ahci_intr(void *v) 415 { 416 struct ahci_softc *sc = v; 417 u_int32_t is; 418 int i, r = 0; 419 420 while ((is = AHCI_READ(sc, AHCI_IS))) { 421 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 422 DEBUG_INTR); 423 r = 1; 424 AHCI_WRITE(sc, AHCI_IS, is); 425 for (i = 0; i < AHCI_MAX_PORTS; i++) 426 if (is & (1 << i)) 427 ahci_intr_port(sc, &sc->sc_channels[i]); 428 } 429 return r; 430 } 431 432 void 433 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 434 { 435 u_int32_t is, tfd; 436 struct ata_channel *chp = &achp->ata_channel; 437 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 438 int slot; 439 440 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 441 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 442 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 443 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 444 DEBUG_INTR); 445 446 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 447 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 448 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 449 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 450 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 451 return; 452 /* stop channel */ 453 ahci_channel_stop(sc, chp, 0); 454 if (slot != 0) { 455 printf("ahci_intr_port: slot %d\n", slot); 456 panic("ahci_intr_port"); 457 } 458 if (is & AHCI_P_IX_TFES) { 459 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 460 chp->ch_error = 461 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 462 chp->ch_status = (tfd & 0xff); 463 } else { 464 /* emulate a CRC error */ 465 chp->ch_error = WDCE_CRC; 466 chp->ch_status = WDCS_ERR; 467 } 468 xfer->c_intr(chp, xfer, is); 469 /* if channel has not been restarted, do it now */ 470 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 471 == 0) 472 ahci_channel_start(sc, chp); 473 } else { 474 slot = 0; /* XXX */ 475 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 476 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 477 chp->ch_channel, is, achp->ahcic_cmds_active, 478 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 479 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 480 return; 481 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 482 == 0) { 483 xfer->c_intr(chp, xfer, 0); 484 } 485 } 486 } 487 488 void 489 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 490 { 491 struct ata_channel *chp = drvp->chnl_softc; 492 ata_reset_channel(chp, flags); 493 return; 494 } 495 496 void 497 ahci_reset_channel(struct ata_channel *chp, int flags) 498 { 499 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 500 struct ahci_channel *achp = (struct ahci_channel *)chp; 501 int i, tfd; 502 503 ahci_channel_stop(sc, chp, flags); 504 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 505 achp->ahcic_sstatus) != SStatus_DET_DEV) { 506 printf("%s: port reset failed\n", AHCINAME(sc)); 507 /* XXX and then ? */ 508 } 509 if (chp->ch_queue->active_xfer) { 510 chp->ch_queue->active_xfer->c_kill_xfer(chp, 511 chp->ch_queue->active_xfer, KILL_RESET); 512 } 513 ahci_channel_start(sc, chp); 514 /* wait 31s for BSY to clear */ 515 for (i = 0; i <3100; i++) { 516 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 517 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 518 & WDCS_BSY) == 0) 519 break; 520 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 521 } 522 if (i == 1500) 523 aprint_error("%s: BSY never cleared, TD 0x%x\n", 524 AHCINAME(sc), tfd); 525 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 526 DEBUG_PROBE); 527 /* clear port interrupt register */ 528 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 529 530 return; 531 } 532 533 int 534 ahci_ata_addref(struct ata_drive_datas *drvp) 535 { 536 return 0; 537 } 538 539 void 540 ahci_ata_delref(struct ata_drive_datas *drvp) 541 { 542 return; 543 } 544 545 void 546 ahci_killpending(struct ata_drive_datas *drvp) 547 { 548 return; 549 } 550 551 void 552 ahci_probe_drive(struct ata_channel *chp) 553 { 554 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 555 struct ahci_channel *achp = (struct ahci_channel *)chp; 556 int i, s; 557 u_int32_t sig; 558 559 /* XXX This should be done by other code. */ 560 for (i = 0; i < chp->ch_ndrive; i++) { 561 chp->ch_drive[i].chnl_softc = chp; 562 chp->ch_drive[i].drive = i; 563 } 564 565 /* bring interface up, accept FISs, power up and spin up device */ 566 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 567 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 568 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 569 /* reset the PHY and bring online */ 570 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 571 achp->ahcic_sstatus)) { 572 case SStatus_DET_DEV: 573 /* clear SErrors and start operations */ 574 ahci_channel_start(sc, chp); 575 /* wait 31s for BSY to clear */ 576 for (i = 0; i <3100; i++) { 577 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 578 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 579 & WDCS_BSY) == 0) 580 break; 581 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 582 } 583 if (i == 1500) 584 aprint_error("%s: BSY never cleared, TD 0x%x\n", 585 AHCINAME(sc), sig); 586 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 587 DEBUG_PROBE); 588 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 589 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 590 AHCINAME(sc), chp->ch_channel, sig, 591 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 592 /* 593 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 594 * cases we get wrong values here, so ignore it. 595 */ 596 s = splbio(); 597 if ((sig & 0xffff0000) == 0xeb140000) { 598 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 599 } else 600 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 601 splx(s); 602 /* enable interrupts */ 603 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 604 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 605 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 606 AHCI_P_IX_DHRS); 607 /* wait 500ms before actually starting operations */ 608 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 609 break; 610 611 default: 612 break; 613 } 614 } 615 616 void 617 ahci_setup_channel(struct ata_channel *chp) 618 { 619 return; 620 } 621 622 int 623 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 624 { 625 struct ata_channel *chp = drvp->chnl_softc; 626 struct ata_xfer *xfer; 627 int ret; 628 int s; 629 630 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 631 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 632 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 633 DEBUG_XFERS); 634 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 635 ATAXF_NOSLEEP); 636 if (xfer == NULL) { 637 return ATACMD_TRY_AGAIN; 638 } 639 if (ata_c->flags & AT_POLL) 640 xfer->c_flags |= C_POLL; 641 if (ata_c->flags & AT_WAIT) 642 xfer->c_flags |= C_WAIT; 643 xfer->c_drive = drvp->drive; 644 xfer->c_databuf = ata_c->data; 645 xfer->c_bcount = ata_c->bcount; 646 xfer->c_cmd = ata_c; 647 xfer->c_start = ahci_cmd_start; 648 xfer->c_intr = ahci_cmd_complete; 649 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 650 s = splbio(); 651 ata_exec_xfer(chp, xfer); 652 #ifdef DIAGNOSTIC 653 if ((ata_c->flags & AT_POLL) != 0 && 654 (ata_c->flags & AT_DONE) == 0) 655 panic("ahci_exec_command: polled command not done"); 656 #endif 657 if (ata_c->flags & AT_DONE) { 658 ret = ATACMD_COMPLETE; 659 } else { 660 if (ata_c->flags & AT_WAIT) { 661 while ((ata_c->flags & AT_DONE) == 0) { 662 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 663 } 664 ret = ATACMD_COMPLETE; 665 } else { 666 ret = ATACMD_QUEUED; 667 } 668 } 669 splx(s); 670 return ret; 671 } 672 673 void 674 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 675 { 676 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 677 struct ahci_channel *achp = (struct ahci_channel *)chp; 678 struct ata_command *ata_c = xfer->c_cmd; 679 int slot = 0 /* XXX slot */; 680 struct ahci_cmd_tbl *cmd_tbl; 681 struct ahci_cmd_header *cmd_h; 682 u_int8_t *fis; 683 int i; 684 int channel = chp->ch_channel; 685 686 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 687 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 688 689 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 690 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 691 cmd_tbl), DEBUG_XFERS); 692 fis = cmd_tbl->cmdt_cfis; 693 694 fis[0] = 0x27; /* host to device */ 695 fis[1] = 0x80; /* command FIS */ 696 fis[2] = ata_c->r_command; 697 fis[3] = ata_c->r_features; 698 fis[4] = ata_c->r_sector; 699 fis[5] = ata_c->r_cyl & 0xff; 700 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 701 fis[7] = ata_c->r_head & 0x0f; 702 fis[8] = 0; 703 fis[9] = 0; 704 fis[10] = 0; 705 fis[11] = 0; 706 fis[12] = ata_c->r_count; 707 fis[13] = 0; 708 fis[14] = 0; 709 fis[15] = WDCTL_4BIT; 710 fis[16] = 0; 711 fis[17] = 0; 712 fis[18] = 0; 713 fis[19] = 0; 714 715 cmd_h = &achp->ahcic_cmdh[slot]; 716 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 717 chp->ch_channel, cmd_h), DEBUG_XFERS); 718 if (ahci_dma_setup(chp, slot, 719 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 720 ata_c->bcount, 721 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 722 ata_c->flags |= AT_DF; 723 ahci_cmd_complete(chp, xfer, slot); 724 return; 725 } 726 cmd_h->cmdh_flags = htole16( 727 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 728 20 /* fis lenght */ / 4); 729 cmd_h->cmdh_prdbc = 0; 730 AHCI_CMDH_SYNC(sc, achp, slot, 731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 732 733 if (ata_c->flags & AT_POLL) { 734 /* polled command, disable interrupts */ 735 AHCI_WRITE(sc, AHCI_GHC, 736 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 737 } 738 chp->ch_flags |= ATACH_IRQ_WAIT; 739 chp->ch_status = 0; 740 /* start command */ 741 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 742 /* and says we started this command */ 743 achp->ahcic_cmds_active |= 1 << slot; 744 745 if ((ata_c->flags & AT_POLL) == 0) { 746 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 747 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 748 ahci_timeout, chp); 749 return; 750 } 751 /* 752 * Polled command. 753 */ 754 for (i = 0; i < ata_c->timeout / 10; i++) { 755 if (ata_c->flags & AT_DONE) 756 break; 757 ahci_intr_port(sc, achp); 758 if (ata_c->flags & AT_WAIT) 759 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 760 else 761 delay(10000); 762 } 763 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 764 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 765 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 766 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 767 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 768 DEBUG_XFERS); 769 if ((ata_c->flags & AT_DONE) == 0) { 770 ata_c->flags |= AT_TIMEOU; 771 ahci_cmd_complete(chp, xfer, slot); 772 } 773 /* reenable interrupts */ 774 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 775 } 776 777 void 778 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 779 { 780 struct ata_command *ata_c = xfer->c_cmd; 781 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 782 DEBUG_FUNCS); 783 784 switch (reason) { 785 case KILL_GONE: 786 ata_c->flags |= AT_GONE; 787 break; 788 case KILL_RESET: 789 ata_c->flags |= AT_RESET; 790 break; 791 default: 792 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 793 panic("ahci_cmd_kill_xfer"); 794 } 795 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 796 } 797 798 int 799 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 800 { 801 int slot = 0; /* XXX slot */ 802 struct ata_command *ata_c = xfer->c_cmd; 803 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 804 805 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 806 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 807 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 808 DEBUG_FUNCS); 809 chp->ch_flags &= ~ATACH_IRQ_WAIT; 810 if (xfer->c_flags & C_TIMEOU) { 811 ata_c->flags |= AT_TIMEOU; 812 } else 813 callout_stop(&chp->ch_callout); 814 815 chp->ch_queue->active_xfer = NULL; 816 817 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 818 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 819 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 820 wakeup(&chp->ch_queue->active_xfer); 821 return 0; 822 } 823 if (is) { 824 ata_c->r_head = 0; 825 ata_c->r_count = 0; 826 ata_c->r_sector = 0; 827 ata_c->r_cyl = 0; 828 if (chp->ch_status & WDCS_BSY) { 829 ata_c->flags |= AT_TIMEOU; 830 } else if (chp->ch_status & WDCS_ERR) { 831 ata_c->r_error = chp->ch_error; 832 ata_c->flags |= AT_ERROR; 833 } 834 } 835 ahci_cmd_done(chp, xfer, slot); 836 return 0; 837 } 838 839 void 840 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 841 { 842 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 843 struct ahci_channel *achp = (struct ahci_channel *)chp; 844 struct ata_command *ata_c = xfer->c_cmd; 845 846 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 847 DEBUG_FUNCS); 848 849 /* this comamnd is not active any more */ 850 achp->ahcic_cmds_active &= ~(1 << slot); 851 852 if (ata_c->flags & (AT_READ|AT_WRITE)) { 853 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 854 achp->ahcic_datad[slot]->dm_mapsize, 855 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 856 BUS_DMASYNC_POSTWRITE); 857 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 858 } 859 860 AHCI_CMDH_SYNC(sc, achp, slot, 861 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 862 863 ata_c->flags |= AT_DONE; 864 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 865 ata_c->flags |= AT_XFDONE; 866 867 ata_free_xfer(chp, xfer); 868 if (ata_c->flags & AT_WAIT) 869 wakeup(ata_c); 870 else if (ata_c->callback) 871 ata_c->callback(ata_c->callback_arg); 872 atastart(chp); 873 return; 874 } 875 876 int 877 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 878 { 879 struct ata_channel *chp = drvp->chnl_softc; 880 struct ata_xfer *xfer; 881 882 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 883 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 884 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 885 DEBUG_XFERS); 886 xfer = ata_get_xfer(ATAXF_NOSLEEP); 887 if (xfer == NULL) { 888 return ATACMD_TRY_AGAIN; 889 } 890 if (ata_bio->flags & ATA_POLL) 891 xfer->c_flags |= C_POLL; 892 xfer->c_drive = drvp->drive; 893 xfer->c_cmd = ata_bio; 894 xfer->c_databuf = ata_bio->databuf; 895 xfer->c_bcount = ata_bio->bcount; 896 xfer->c_start = ahci_bio_start; 897 xfer->c_intr = ahci_bio_complete; 898 xfer->c_kill_xfer = ahci_bio_kill_xfer; 899 ata_exec_xfer(chp, xfer); 900 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 901 } 902 903 void 904 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 905 { 906 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 907 struct ahci_channel *achp = (struct ahci_channel *)chp; 908 struct ata_bio *ata_bio = xfer->c_cmd; 909 int slot = 0 /* XXX slot */; 910 struct ahci_cmd_tbl *cmd_tbl; 911 struct ahci_cmd_header *cmd_h; 912 u_int8_t *fis; 913 int i, nblks; 914 int channel = chp->ch_channel; 915 916 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 917 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 918 919 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 920 921 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 922 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 923 cmd_tbl), DEBUG_XFERS); 924 fis = cmd_tbl->cmdt_cfis; 925 926 fis[0] = 0x27; /* host to device */ 927 fis[1] = 0x80; /* command FIS */ 928 if (ata_bio->flags & ATA_LBA48) { 929 fis[2] = (ata_bio->flags & ATA_READ) ? 930 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 931 } else { 932 fis[2] = 933 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 934 } 935 fis[3] = 0; /* features */ 936 fis[4] = ata_bio->blkno & 0xff; 937 fis[5] = (ata_bio->blkno >> 8) & 0xff; 938 fis[6] = (ata_bio->blkno >> 16) & 0xff; 939 if (ata_bio->flags & ATA_LBA48) { 940 fis[7] = WDSD_LBA; 941 fis[8] = (ata_bio->blkno >> 24) & 0xff; 942 fis[9] = (ata_bio->blkno >> 32) & 0xff; 943 fis[10] = (ata_bio->blkno >> 40) & 0xff; 944 } else { 945 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 946 fis[8] = 0; 947 fis[9] = 0; 948 fis[10] = 0; 949 } 950 fis[11] = 0; /* ext features */ 951 fis[12] = nblks & 0xff; 952 fis[13] = (ata_bio->flags & ATA_LBA48) ? 953 ((nblks >> 8) & 0xff) : 0; 954 fis[14] = 0; 955 fis[15] = WDCTL_4BIT; 956 fis[16] = 0; 957 fis[17] = 0; 958 fis[18] = 0; 959 fis[19] = 0; 960 961 cmd_h = &achp->ahcic_cmdh[slot]; 962 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 963 chp->ch_channel, cmd_h), DEBUG_XFERS); 964 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 965 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 966 ata_bio->error = ERR_DMA; 967 ata_bio->r_error = 0; 968 ahci_bio_complete(chp, xfer, slot); 969 return; 970 } 971 cmd_h->cmdh_flags = htole16( 972 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 973 20 /* fis lenght */ / 4); 974 cmd_h->cmdh_prdbc = 0; 975 AHCI_CMDH_SYNC(sc, achp, slot, 976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 977 978 if (xfer->c_flags & C_POLL) { 979 /* polled command, disable interrupts */ 980 AHCI_WRITE(sc, AHCI_GHC, 981 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 982 } 983 chp->ch_flags |= ATACH_IRQ_WAIT; 984 chp->ch_status = 0; 985 /* start command */ 986 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 987 /* and says we started this command */ 988 achp->ahcic_cmds_active |= 1 << slot; 989 990 if ((xfer->c_flags & C_POLL) == 0) { 991 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 992 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 993 ahci_timeout, chp); 994 return; 995 } 996 /* 997 * Polled command. 998 */ 999 for (i = 0; i < ATA_DELAY / 10; i++) { 1000 if (ata_bio->flags & ATA_ITSDONE) 1001 break; 1002 ahci_intr_port(sc, achp); 1003 if (ata_bio->flags & ATA_NOSLEEP) 1004 delay(10000); 1005 else 1006 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1007 } 1008 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1009 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1010 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1011 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1012 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1013 DEBUG_XFERS); 1014 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1015 ata_bio->error = TIMEOUT; 1016 ahci_bio_complete(chp, xfer, slot); 1017 } 1018 /* reenable interrupts */ 1019 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1020 } 1021 1022 void 1023 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1024 { 1025 int slot = 0; /* XXX slot */ 1026 int drive = xfer->c_drive; 1027 struct ata_bio *ata_bio = xfer->c_cmd; 1028 struct ahci_channel *achp = (struct ahci_channel *)chp; 1029 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1030 DEBUG_FUNCS); 1031 1032 achp->ahcic_cmds_active &= ~(1 << slot); 1033 ata_free_xfer(chp, xfer); 1034 ata_bio->flags |= ATA_ITSDONE; 1035 switch (reason) { 1036 case KILL_GONE: 1037 ata_bio->error = ERR_NODEV; 1038 break; 1039 case KILL_RESET: 1040 ata_bio->error = ERR_RESET; 1041 break; 1042 default: 1043 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1044 panic("ahci_bio_kill_xfer"); 1045 } 1046 ata_bio->r_error = WDCE_ABRT; 1047 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1048 } 1049 1050 int 1051 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1052 { 1053 int slot = 0; /* XXX slot */ 1054 struct ata_bio *ata_bio = xfer->c_cmd; 1055 int drive = xfer->c_drive; 1056 struct ahci_channel *achp = (struct ahci_channel *)chp; 1057 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1058 1059 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1060 DEBUG_FUNCS); 1061 1062 achp->ahcic_cmds_active &= ~(1 << slot); 1063 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1064 if (xfer->c_flags & C_TIMEOU) { 1065 ata_bio->error = TIMEOUT; 1066 } else { 1067 callout_stop(&chp->ch_callout); 1068 ata_bio->error = NOERROR; 1069 } 1070 1071 chp->ch_queue->active_xfer = NULL; 1072 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1073 achp->ahcic_datad[slot]->dm_mapsize, 1074 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1075 BUS_DMASYNC_POSTWRITE); 1076 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1077 1078 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1079 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1080 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1081 wakeup(&chp->ch_queue->active_xfer); 1082 return 0; 1083 } 1084 ata_free_xfer(chp, xfer); 1085 ata_bio->flags |= ATA_ITSDONE; 1086 if (chp->ch_status & WDCS_DWF) { 1087 ata_bio->error = ERR_DF; 1088 } else if (chp->ch_status & WDCS_ERR) { 1089 ata_bio->error = ERROR; 1090 ata_bio->r_error = chp->ch_error; 1091 } else if (chp->ch_status & WDCS_CORR) 1092 ata_bio->flags |= ATA_CORR; 1093 1094 AHCI_CMDH_SYNC(sc, achp, slot, 1095 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1096 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1097 ata_bio->bcount), DEBUG_XFERS); 1098 /* 1099 * if it was a write, complete data buffer may have been transfered 1100 * before error detection; in this case don't use cmdh_prdbc 1101 * as it won't reflect what was written to media. Assume nothing 1102 * was transfered and leave bcount as-is. 1103 */ 1104 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1105 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1106 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1107 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1108 atastart(chp); 1109 return 0; 1110 } 1111 1112 void 1113 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1114 { 1115 int i; 1116 /* stop channel */ 1117 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1118 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1119 /* wait 1s for channel to stop */ 1120 for (i = 0; i <100; i++) { 1121 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1122 == 0) 1123 break; 1124 if (flags & AT_WAIT) 1125 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1126 else 1127 delay(10000); 1128 } 1129 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1130 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1131 /* XXX controller reset ? */ 1132 return; 1133 } 1134 } 1135 1136 void 1137 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1138 { 1139 /* clear error */ 1140 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1141 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1142 1143 /* and start controller */ 1144 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1145 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1146 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1147 } 1148 1149 void 1150 ahci_timeout(void *v) 1151 { 1152 struct ata_channel *chp = (struct ata_channel *)v; 1153 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1154 int s = splbio(); 1155 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1156 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1157 xfer->c_flags |= C_TIMEOU; 1158 xfer->c_intr(chp, xfer, 0); 1159 } 1160 splx(s); 1161 } 1162 1163 int 1164 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1165 size_t count, int op) 1166 { 1167 int error, seg; 1168 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1169 struct ahci_channel *achp = (struct ahci_channel *)chp; 1170 struct ahci_cmd_tbl *cmd_tbl; 1171 struct ahci_cmd_header *cmd_h; 1172 1173 cmd_h = &achp->ahcic_cmdh[slot]; 1174 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1175 1176 if (data == NULL) { 1177 cmd_h->cmdh_prdtl = 0; 1178 goto end; 1179 } 1180 1181 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1182 data, count, NULL, 1183 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1184 if (error) { 1185 printf("%s port %d: failed to load xfer: %d\n", 1186 AHCINAME(sc), chp->ch_channel, error); 1187 return error; 1188 } 1189 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1190 achp->ahcic_datad[slot]->dm_mapsize, 1191 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1192 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1193 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1194 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1195 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1196 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1197 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1198 } 1199 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1200 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1201 end: 1202 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1203 return 0; 1204 } 1205 1206 #if NATAPIBUS > 0 1207 void 1208 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1209 { 1210 struct ata_channel *chp = ata_sc->sc_chan; 1211 struct atac_softc *atac = chp->ch_atac; 1212 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1213 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1214 /* 1215 * Fill in the scsipi_adapter. 1216 */ 1217 adapt->adapt_dev = atac->atac_dev; 1218 adapt->adapt_nchannels = atac->atac_nchannels; 1219 adapt->adapt_request = ahci_atapi_scsipi_request; 1220 adapt->adapt_minphys = ahci_atapi_minphys; 1221 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1222 1223 /* 1224 * Fill in the scsipi_channel. 1225 */ 1226 memset(chan, 0, sizeof(*chan)); 1227 chan->chan_adapter = adapt; 1228 chan->chan_bustype = &ahci_atapi_bustype; 1229 chan->chan_channel = chp->ch_channel; 1230 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1231 chan->chan_openings = 1; 1232 chan->chan_max_periph = 1; 1233 chan->chan_ntargets = 1; 1234 chan->chan_nluns = 1; 1235 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1236 atapiprint); 1237 } 1238 1239 void 1240 ahci_atapi_minphys(struct buf *bp) 1241 { 1242 if (bp->b_bcount > MAXPHYS) 1243 bp->b_bcount = MAXPHYS; 1244 minphys(bp); 1245 } 1246 1247 /* 1248 * Kill off all pending xfers for a periph. 1249 * 1250 * Must be called at splbio(). 1251 */ 1252 void 1253 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1254 { 1255 struct atac_softc *atac = 1256 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1257 struct ata_channel *chp = 1258 atac->atac_channels[periph->periph_channel->chan_channel]; 1259 1260 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1261 } 1262 1263 void 1264 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1265 scsipi_adapter_req_t req, void *arg) 1266 { 1267 struct scsipi_adapter *adapt = chan->chan_adapter; 1268 struct scsipi_periph *periph; 1269 struct scsipi_xfer *sc_xfer; 1270 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1271 struct atac_softc *atac = &sc->sc_atac; 1272 struct ata_xfer *xfer; 1273 int channel = chan->chan_channel; 1274 int drive, s; 1275 1276 switch (req) { 1277 case ADAPTER_REQ_RUN_XFER: 1278 sc_xfer = arg; 1279 periph = sc_xfer->xs_periph; 1280 drive = periph->periph_target; 1281 if (!device_is_active(atac->atac_dev)) { 1282 sc_xfer->error = XS_DRIVER_STUFFUP; 1283 scsipi_done(sc_xfer); 1284 return; 1285 } 1286 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1287 if (xfer == NULL) { 1288 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1289 scsipi_done(sc_xfer); 1290 return; 1291 } 1292 1293 if (sc_xfer->xs_control & XS_CTL_POLL) 1294 xfer->c_flags |= C_POLL; 1295 xfer->c_drive = drive; 1296 xfer->c_flags |= C_ATAPI; 1297 xfer->c_cmd = sc_xfer; 1298 xfer->c_databuf = sc_xfer->data; 1299 xfer->c_bcount = sc_xfer->datalen; 1300 xfer->c_start = ahci_atapi_start; 1301 xfer->c_intr = ahci_atapi_complete; 1302 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1303 xfer->c_dscpoll = 0; 1304 s = splbio(); 1305 ata_exec_xfer(atac->atac_channels[channel], xfer); 1306 #ifdef DIAGNOSTIC 1307 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1308 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1309 panic("ahci_atapi_scsipi_request: polled command " 1310 "not done"); 1311 #endif 1312 splx(s); 1313 return; 1314 default: 1315 /* Not supported, nothing to do. */ 1316 ; 1317 } 1318 } 1319 1320 void 1321 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1322 { 1323 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1324 struct ahci_channel *achp = (struct ahci_channel *)chp; 1325 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1326 int slot = 0 /* XXX slot */; 1327 struct ahci_cmd_tbl *cmd_tbl; 1328 struct ahci_cmd_header *cmd_h; 1329 u_int8_t *fis; 1330 int i; 1331 int channel = chp->ch_channel; 1332 1333 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1334 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1335 1336 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1337 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1338 cmd_tbl), DEBUG_XFERS); 1339 fis = cmd_tbl->cmdt_cfis; 1340 1341 fis[0] = 0x27; /* host to device */ 1342 fis[1] = 0x80; /* command FIS */ 1343 fis[2] = ATAPI_PKT_CMD; 1344 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1345 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1346 fis[3] = (sc_xfer->datalen ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1347 fis[4] = 0; 1348 fis[5] = 0; 1349 fis[6] = 0; 1350 fis[7] = WDSD_LBA; 1351 fis[8] = 0; 1352 fis[9] = 0; 1353 fis[10] = 0; 1354 fis[11] = 0; /* ext features */ 1355 fis[12] = 0; 1356 fis[13] = 0; 1357 fis[14] = 0; 1358 fis[15] = WDCTL_4BIT; 1359 fis[16] = 0; 1360 fis[17] = 0; 1361 fis[18] = 0; 1362 fis[19] = 0; 1363 1364 cmd_h = &achp->ahcic_cmdh[slot]; 1365 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1366 chp->ch_channel, cmd_h), DEBUG_XFERS); 1367 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1368 sc_xfer->datalen, 1369 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1370 BUS_DMA_READ : BUS_DMA_WRITE)) { 1371 sc_xfer->error = XS_DRIVER_STUFFUP; 1372 ahci_atapi_complete(chp, xfer, slot); 1373 return; 1374 } 1375 cmd_h->cmdh_flags = htole16( 1376 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1377 20 /* fis lenght */ / 4 | AHCI_CMDH_F_A); 1378 cmd_h->cmdh_prdbc = 0; 1379 AHCI_CMDH_SYNC(sc, achp, slot, 1380 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1381 1382 if (xfer->c_flags & C_POLL) { 1383 /* polled command, disable interrupts */ 1384 AHCI_WRITE(sc, AHCI_GHC, 1385 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1386 } 1387 chp->ch_flags |= ATACH_IRQ_WAIT; 1388 chp->ch_status = 0; 1389 /* start command */ 1390 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1391 /* and says we started this command */ 1392 achp->ahcic_cmds_active |= 1 << slot; 1393 1394 if ((xfer->c_flags & C_POLL) == 0) { 1395 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1396 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1397 ahci_timeout, chp); 1398 return; 1399 } 1400 /* 1401 * Polled command. 1402 */ 1403 for (i = 0; i < ATA_DELAY / 10; i++) { 1404 if (sc_xfer->xs_status & XS_STS_DONE) 1405 break; 1406 ahci_intr_port(sc, achp); 1407 delay(10000); 1408 } 1409 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1410 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1411 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1412 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1413 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1414 DEBUG_XFERS); 1415 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1416 sc_xfer->error = XS_TIMEOUT; 1417 ahci_atapi_complete(chp, xfer, slot); 1418 } 1419 /* reenable interrupts */ 1420 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1421 } 1422 1423 int 1424 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1425 { 1426 int slot = 0; /* XXX slot */ 1427 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1428 int drive = xfer->c_drive; 1429 struct ahci_channel *achp = (struct ahci_channel *)chp; 1430 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1431 1432 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1433 DEBUG_FUNCS); 1434 1435 achp->ahcic_cmds_active &= ~(1 << slot); 1436 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1437 if (xfer->c_flags & C_TIMEOU) { 1438 sc_xfer->error = XS_TIMEOUT; 1439 } else { 1440 callout_stop(&chp->ch_callout); 1441 sc_xfer->error = 0; 1442 } 1443 1444 chp->ch_queue->active_xfer = NULL; 1445 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1446 achp->ahcic_datad[slot]->dm_mapsize, 1447 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1448 BUS_DMASYNC_POSTWRITE); 1449 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1450 1451 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1452 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1453 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1454 wakeup(&chp->ch_queue->active_xfer); 1455 return 0; 1456 } 1457 ata_free_xfer(chp, xfer); 1458 1459 AHCI_CMDH_SYNC(sc, achp, slot, 1460 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1461 sc_xfer->resid = sc_xfer->datalen; 1462 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1463 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1464 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1465 if (chp->ch_status & WDCS_ERR && 1466 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1467 sc_xfer->resid == sc_xfer->datalen)) { 1468 sc_xfer->error = XS_SHORTSENSE; 1469 sc_xfer->sense.atapi_sense = chp->ch_error; 1470 if ((sc_xfer->xs_periph->periph_quirks & 1471 PQUIRK_NOSENSE) == 0) { 1472 /* ask scsipi to send a REQUEST_SENSE */ 1473 sc_xfer->error = XS_BUSY; 1474 sc_xfer->status = SCSI_CHECK; 1475 } 1476 } 1477 scsipi_done(sc_xfer); 1478 atastart(chp); 1479 return 0; 1480 } 1481 1482 void 1483 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1484 { 1485 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1486 struct ahci_channel *achp = (struct ahci_channel *)chp; 1487 int slot = 0; /* XXX slot */ 1488 1489 achp->ahcic_cmds_active &= ~(1 << slot); 1490 1491 /* remove this command from xfer queue */ 1492 switch (reason) { 1493 case KILL_GONE: 1494 sc_xfer->error = XS_DRIVER_STUFFUP; 1495 break; 1496 case KILL_RESET: 1497 sc_xfer->error = XS_RESET; 1498 break; 1499 default: 1500 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1501 panic("ahci_ata_atapi_kill_xfer"); 1502 } 1503 ata_free_xfer(chp, xfer); 1504 scsipi_done(sc_xfer); 1505 } 1506 1507 void 1508 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1509 { 1510 struct scsipi_channel *chan = sc->sc_channel; 1511 struct scsipi_periph *periph; 1512 struct ataparams ids; 1513 struct ataparams *id = &ids; 1514 struct ahci_softc *ahcic = 1515 device_private(chan->chan_adapter->adapt_dev); 1516 struct atac_softc *atac = &ahcic->sc_atac; 1517 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1518 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1519 struct scsipibus_attach_args sa; 1520 char serial_number[21], model[41], firmware_revision[9]; 1521 int s; 1522 1523 /* skip if already attached */ 1524 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1525 return; 1526 1527 /* if no ATAPI device detected at attach time, skip */ 1528 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1529 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1530 "not present\n", target), DEBUG_PROBE); 1531 return; 1532 } 1533 1534 /* Some ATAPI devices need a bit more time after software reset. */ 1535 delay(5000); 1536 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1537 #ifdef ATAPI_DEBUG_PROBE 1538 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1539 AHCINAME(ahcic), target, 1540 id->atap_config & ATAPI_CFG_CMD_MASK, 1541 id->atap_config & ATAPI_CFG_DRQ_MASK); 1542 #endif 1543 periph = scsipi_alloc_periph(M_NOWAIT); 1544 if (periph == NULL) { 1545 aprint_error_dev(sc->sc_dev, 1546 "unable to allocate periph for drive %d\n", 1547 target); 1548 return; 1549 } 1550 periph->periph_dev = NULL; 1551 periph->periph_channel = chan; 1552 periph->periph_switch = &atapi_probe_periphsw; 1553 periph->periph_target = target; 1554 periph->periph_lun = 0; 1555 periph->periph_quirks = PQUIRK_ONLYBIG; 1556 1557 #ifdef SCSIPI_DEBUG 1558 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1559 SCSIPI_DEBUG_TARGET == target) 1560 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1561 #endif 1562 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1563 if (id->atap_config & ATAPI_CFG_REMOV) 1564 periph->periph_flags |= PERIPH_REMOVABLE; 1565 if (periph->periph_type == T_SEQUENTIAL) { 1566 s = splbio(); 1567 drvp->drive_flags |= DRIVE_ATAPIST; 1568 splx(s); 1569 } 1570 1571 sa.sa_periph = periph; 1572 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1573 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1574 T_REMOV : T_FIXED; 1575 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1576 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1577 20); 1578 scsipi_strvis((u_char *)firmware_revision, 8, 1579 id->atap_revision, 8); 1580 sa.sa_inqbuf.vendor = model; 1581 sa.sa_inqbuf.product = serial_number; 1582 sa.sa_inqbuf.revision = firmware_revision; 1583 1584 /* 1585 * Determine the operating mode capabilities of the device. 1586 */ 1587 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1588 periph->periph_cap |= PERIPH_CAP_CMD16; 1589 /* XXX This is gross. */ 1590 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1591 1592 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1593 1594 if (drvp->drv_softc) 1595 ata_probe_caps(drvp); 1596 else { 1597 s = splbio(); 1598 drvp->drive_flags &= ~DRIVE_ATAPI; 1599 splx(s); 1600 } 1601 } else { 1602 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1603 "failed for drive %s:%d:%d: error 0x%x\n", 1604 AHCINAME(ahcic), chp->ch_channel, target, 1605 chp->ch_error), DEBUG_PROBE); 1606 s = splbio(); 1607 drvp->drive_flags &= ~DRIVE_ATAPI; 1608 splx(s); 1609 } 1610 } 1611 #endif /* NATAPIBUS */ 1612
Indexes created Fri Oct 17 00:09:41 GMT 2025