ahcisata_core.c revision 1.18.4.2
1 /* $NetBSD: ahcisata_core.c,v 1.18.4.2 2010/03/06 22:10:46 sborrill Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.18.4.2 2010/03/06 22:10:46 sborrill Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 #include <sys/buf.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/ic/wdcreg.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/satavar.h> 50 #include <dev/ata/satareg.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 54 55 #include "atapibus.h" 56 57 #ifdef AHCI_DEBUG 58 int ahcidebug_mask = 0x0; 59 #endif 60 61 void ahci_probe_drive(struct ata_channel *); 62 void ahci_setup_channel(struct ata_channel *); 63 64 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 65 void ahci_reset_drive(struct ata_drive_datas *, int); 66 void ahci_reset_channel(struct ata_channel *, int); 67 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 68 int ahci_ata_addref(struct ata_drive_datas *); 69 void ahci_ata_delref(struct ata_drive_datas *); 70 void ahci_killpending(struct ata_drive_datas *); 71 72 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 73 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 74 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 75 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 77 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 78 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 79 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 80 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 81 void ahci_timeout(void *); 82 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 83 84 #if NATAPIBUS > 0 85 void ahci_atapibus_attach(struct atabus_softc *); 86 void ahci_atapi_kill_pending(struct scsipi_periph *); 87 void ahci_atapi_minphys(struct buf *); 88 void ahci_atapi_scsipi_request(struct scsipi_channel *, 89 scsipi_adapter_req_t, void *); 90 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 91 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 92 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 93 void ahci_atapi_probe_device(struct atapibus_softc *, int); 94 95 static const struct scsipi_bustype ahci_atapi_bustype = { 96 SCSIPI_BUSTYPE_ATAPI, 97 atapi_scsipi_cmd, 98 atapi_interpret_sense, 99 atapi_print_addr, 100 ahci_atapi_kill_pending, 101 }; 102 #endif /* NATAPIBUS */ 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 const struct ata_bustype ahci_ata_bustype = { 107 SCSIPI_BUSTYPE_ATA, 108 ahci_ata_bio, 109 ahci_reset_drive, 110 ahci_reset_channel, 111 ahci_exec_command, 112 ata_get_params, 113 ahci_ata_addref, 114 ahci_ata_delref, 115 ahci_killpending 116 }; 117 118 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 119 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 int 123 ahci_reset(struct ahci_softc *sc) 124 { 125 int i; 126 127 /* reset controller */ 128 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 129 /* wait up to 1s for reset to complete */ 130 for (i = 0; i < 1000; i++) { 131 delay(1000); 132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 133 break; 134 } 135 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 136 aprint_error("%s: reset failed\n", AHCINAME(sc)); 137 return -1; 138 } 139 /* enable ahci mode */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 141 return 0; 142 } 143 144 void 145 ahci_setup_ports(struct ahci_softc *sc) 146 { 147 u_int32_t ahci_ports; 148 int i, port; 149 150 ahci_ports = AHCI_READ(sc, AHCI_PI); 151 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 152 if ((ahci_ports & (1 << i)) == 0) 153 continue; 154 if (port >= sc->sc_atac.atac_nchannels) { 155 aprint_error("%s: more ports than announced\n", 156 AHCINAME(sc)); 157 break; 158 } 159 ahci_setup_port(sc, i); 160 } 161 } 162 163 void 164 ahci_reprobe_drives(struct ahci_softc *sc) 165 { 166 u_int32_t ahci_ports; 167 int i, port; 168 struct ahci_channel *achp; 169 struct ata_channel *chp; 170 171 ahci_ports = AHCI_READ(sc, AHCI_PI); 172 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 173 if ((ahci_ports & (1 << i)) == 0) 174 continue; 175 if (port >= sc->sc_atac.atac_nchannels) { 176 aprint_error("%s: more ports than announced\n", 177 AHCINAME(sc)); 178 break; 179 } 180 achp = &sc->sc_channels[i]; 181 chp = &achp->ata_channel; 182 183 ahci_probe_drive(chp); 184 } 185 } 186 187 static void 188 ahci_setup_port(struct ahci_softc *sc, int i) 189 { 190 struct ahci_channel *achp; 191 192 achp = &sc->sc_channels[i]; 193 194 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 195 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 196 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 197 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 198 } 199 200 void 201 ahci_enable_intrs(struct ahci_softc *sc) 202 { 203 204 /* clear interrupts */ 205 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 206 /* enable interrupts */ 207 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 208 } 209 210 void 211 ahci_attach(struct ahci_softc *sc) 212 { 213 u_int32_t ahci_cap, ahci_rev, ahci_ports; 214 int i, j, port; 215 struct ahci_channel *achp; 216 struct ata_channel *chp; 217 int error; 218 bus_dma_segment_t seg; 219 int rseg; 220 int dmasize; 221 void *cmdhp; 222 void *cmdtblp; 223 224 if (ahci_reset(sc) != 0) 225 return; 226 227 ahci_cap = AHCI_READ(sc, AHCI_CAP); 228 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 229 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 230 ahci_rev = AHCI_READ(sc, AHCI_VS); 231 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 232 switch(ahci_rev) { 233 case AHCI_VS_10: 234 aprint_normal("1.0"); 235 break; 236 case AHCI_VS_11: 237 aprint_normal("1.1"); 238 break; 239 case AHCI_VS_12: 240 aprint_normal("1.2"); 241 break; 242 default: 243 aprint_normal("0x%x", ahci_rev); 244 break; 245 } 246 247 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 248 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 249 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 250 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 251 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 252 sc->sc_atac.atac_pio_cap = 4; 253 sc->sc_atac.atac_dma_cap = 2; 254 sc->sc_atac.atac_udma_cap = 6; 255 sc->sc_atac.atac_channels = sc->sc_chanarray; 256 sc->sc_atac.atac_probe = ahci_probe_drive; 257 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 258 sc->sc_atac.atac_set_modes = ahci_setup_channel; 259 #if NATAPIBUS > 0 260 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 261 #endif 262 263 dmasize = 264 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 265 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 266 &seg, 1, &rseg, BUS_DMA_NOWAIT); 267 if (error) { 268 aprint_error("%s: unable to allocate command header memory" 269 ", error=%d\n", AHCINAME(sc), error); 270 return; 271 } 272 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 273 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 274 if (error) { 275 aprint_error("%s: unable to map command header memory" 276 ", error=%d\n", AHCINAME(sc), error); 277 return; 278 } 279 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 280 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 281 if (error) { 282 aprint_error("%s: unable to create command header map" 283 ", error=%d\n", AHCINAME(sc), error); 284 return; 285 } 286 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 287 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 288 if (error) { 289 aprint_error("%s: unable to load command header map" 290 ", error=%d\n", AHCINAME(sc), error); 291 return; 292 } 293 sc->sc_cmd_hdr = cmdhp; 294 295 ahci_enable_intrs(sc); 296 297 ahci_ports = AHCI_READ(sc, AHCI_PI); 298 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 299 if ((ahci_ports & (1 << i)) == 0) 300 continue; 301 if (port >= sc->sc_atac.atac_nchannels) { 302 aprint_error("%s: more ports than announced\n", 303 AHCINAME(sc)); 304 break; 305 } 306 achp = &sc->sc_channels[i]; 307 chp = (struct ata_channel *)achp; 308 sc->sc_chanarray[i] = chp; 309 chp->ch_channel = i; 310 chp->ch_atac = &sc->sc_atac; 311 chp->ch_queue = malloc(sizeof(struct ata_queue), 312 M_DEVBUF, M_NOWAIT); 313 if (chp->ch_queue == NULL) { 314 aprint_error("%s port %d: can't allocate memory for " 315 "command queue", AHCINAME(sc), i); 316 break; 317 } 318 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 319 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 320 &seg, 1, &rseg, BUS_DMA_NOWAIT); 321 if (error) { 322 aprint_error("%s: unable to allocate command table " 323 "memory, error=%d\n", AHCINAME(sc), error); 324 break; 325 } 326 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 327 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 328 if (error) { 329 aprint_error("%s: unable to map command table memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 break; 332 } 333 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 334 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 335 if (error) { 336 aprint_error("%s: unable to create command table map" 337 ", error=%d\n", AHCINAME(sc), error); 338 break; 339 } 340 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 341 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 342 if (error) { 343 aprint_error("%s: unable to load command table map" 344 ", error=%d\n", AHCINAME(sc), error); 345 break; 346 } 347 achp->ahcic_cmdh = (struct ahci_cmd_header *) 348 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 349 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 350 AHCI_CMDH_SIZE * port; 351 achp->ahcic_rfis = (struct ahci_r_fis *) 352 ((char *)cmdhp + 353 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 354 AHCI_RFIS_SIZE * port); 355 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 356 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 357 AHCI_RFIS_SIZE * port; 358 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 359 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 360 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 361 DEBUG_PROBE); 362 363 for (j = 0; j < sc->sc_ncmds; j++) { 364 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 365 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 366 achp->ahcic_bus_cmd_tbl[j] = 367 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 368 AHCI_CMDTBL_SIZE * j; 369 achp->ahcic_cmdh[j].cmdh_cmdtba = 370 htole32(achp->ahcic_bus_cmd_tbl[j]); 371 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 372 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 373 achp->ahcic_cmd_tbl[j], 374 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 375 /* The xfer DMA map */ 376 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 377 AHCI_NPRD, 0x400000 /* 4MB */, 0, 378 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 379 &achp->ahcic_datad[j]); 380 if (error) { 381 aprint_error("%s: couldn't alloc xfer DMA map, " 382 "error=%d\n", AHCINAME(sc), error); 383 goto end; 384 } 385 } 386 ahci_setup_port(sc, i); 387 chp->ch_ndrive = 1; 388 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 389 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 390 aprint_error("%s: couldn't map channel %d " 391 "sata_status regs\n", AHCINAME(sc), i); 392 break; 393 } 394 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 395 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 396 aprint_error("%s: couldn't map channel %d " 397 "sata_control regs\n", AHCINAME(sc), i); 398 break; 399 } 400 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 401 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 402 aprint_error("%s: couldn't map channel %d " 403 "sata_error regs\n", AHCINAME(sc), i); 404 break; 405 } 406 ata_channel_attach(chp); 407 port++; 408 end: 409 continue; 410 } 411 } 412 413 int 414 ahci_intr(void *v) 415 { 416 struct ahci_softc *sc = v; 417 u_int32_t is; 418 int i, r = 0; 419 420 while ((is = AHCI_READ(sc, AHCI_IS))) { 421 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 422 DEBUG_INTR); 423 r = 1; 424 AHCI_WRITE(sc, AHCI_IS, is); 425 for (i = 0; i < AHCI_MAX_PORTS; i++) 426 if (is & (1 << i)) 427 ahci_intr_port(sc, &sc->sc_channels[i]); 428 } 429 return r; 430 } 431 432 void 433 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 434 { 435 u_int32_t is, tfd; 436 struct ata_channel *chp = &achp->ata_channel; 437 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 438 int slot; 439 440 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 441 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 442 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 443 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 444 DEBUG_INTR); 445 446 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 447 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 448 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 449 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 450 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 451 return; 452 /* stop channel */ 453 ahci_channel_stop(sc, chp, 0); 454 if (slot != 0) { 455 printf("ahci_intr_port: slot %d\n", slot); 456 panic("ahci_intr_port"); 457 } 458 if (is & AHCI_P_IX_TFES) { 459 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 460 chp->ch_error = 461 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 462 chp->ch_status = (tfd & 0xff); 463 } else { 464 /* emulate a CRC error */ 465 chp->ch_error = WDCE_CRC; 466 chp->ch_status = WDCS_ERR; 467 } 468 xfer->c_intr(chp, xfer, is); 469 /* if channel has not been restarted, do it now */ 470 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 471 == 0) 472 ahci_channel_start(sc, chp); 473 } else { 474 slot = 0; /* XXX */ 475 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 476 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 477 chp->ch_channel, is, achp->ahcic_cmds_active, 478 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 479 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 480 return; 481 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 482 == 0) { 483 xfer->c_intr(chp, xfer, 0); 484 } 485 } 486 } 487 488 void 489 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 490 { 491 struct ata_channel *chp = drvp->chnl_softc; 492 ata_reset_channel(chp, flags); 493 return; 494 } 495 496 void 497 ahci_reset_channel(struct ata_channel *chp, int flags) 498 { 499 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 500 struct ahci_channel *achp = (struct ahci_channel *)chp; 501 int i, tfd; 502 503 ahci_channel_stop(sc, chp, flags); 504 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 505 achp->ahcic_sstatus) != SStatus_DET_DEV) { 506 printf("%s: port reset failed\n", AHCINAME(sc)); 507 /* XXX and then ? */ 508 } 509 if (chp->ch_queue->active_xfer) { 510 chp->ch_queue->active_xfer->c_kill_xfer(chp, 511 chp->ch_queue->active_xfer, KILL_RESET); 512 } 513 /* wait 31s for BSY to clear */ 514 for (i = 0; i <3100; i++) { 515 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 516 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 517 & WDCS_BSY) == 0) 518 break; 519 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 520 } 521 if (i == 1500) 522 aprint_error("%s: BSY never cleared, TD 0x%x\n", 523 AHCINAME(sc), tfd); 524 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 525 DEBUG_PROBE); 526 /* clear port interrupt register */ 527 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 528 /* and start channel */ 529 ahci_channel_start(sc, chp); 530 531 return; 532 } 533 534 int 535 ahci_ata_addref(struct ata_drive_datas *drvp) 536 { 537 return 0; 538 } 539 540 void 541 ahci_ata_delref(struct ata_drive_datas *drvp) 542 { 543 return; 544 } 545 546 void 547 ahci_killpending(struct ata_drive_datas *drvp) 548 { 549 return; 550 } 551 552 void 553 ahci_probe_drive(struct ata_channel *chp) 554 { 555 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 556 struct ahci_channel *achp = (struct ahci_channel *)chp; 557 int i, s; 558 u_int32_t sig; 559 560 /* XXX This should be done by other code. */ 561 for (i = 0; i < chp->ch_ndrive; i++) { 562 chp->ch_drive[i].chnl_softc = chp; 563 chp->ch_drive[i].drive = i; 564 } 565 566 /* bring interface up, accept FISs, power up and spin up device */ 567 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 568 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 569 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 570 /* reset the PHY and bring online */ 571 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 572 achp->ahcic_sstatus)) { 573 case SStatus_DET_DEV: 574 /* wait 31s for BSY to clear */ 575 for (i = 0; i <3100; i++) { 576 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 577 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 578 & WDCS_BSY) == 0) 579 break; 580 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 581 } 582 if (i == 1500) { 583 aprint_error("%s: BSY never cleared, TD 0x%x\n", 584 AHCINAME(sc), sig); 585 return; 586 } 587 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 588 DEBUG_PROBE); 589 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 590 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 591 AHCINAME(sc), chp->ch_channel, sig, 592 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 593 /* 594 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 595 * cases we get wrong values here, so ignore it. 596 */ 597 s = splbio(); 598 if ((sig & 0xffff0000) == 0xeb140000) { 599 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 600 } else 601 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 602 splx(s); 603 /* clear port interrupt register */ 604 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 605 /* start channel */ 606 ahci_channel_start(sc, chp); 607 /* and enable interrupts */ 608 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 609 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 610 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 611 AHCI_P_IX_DHRS); 612 /* wait 500ms before actually starting operations */ 613 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 614 break; 615 616 default: 617 break; 618 } 619 } 620 621 void 622 ahci_setup_channel(struct ata_channel *chp) 623 { 624 return; 625 } 626 627 int 628 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 629 { 630 struct ata_channel *chp = drvp->chnl_softc; 631 struct ata_xfer *xfer; 632 int ret; 633 int s; 634 635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 636 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 637 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 638 DEBUG_XFERS); 639 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 640 ATAXF_NOSLEEP); 641 if (xfer == NULL) { 642 return ATACMD_TRY_AGAIN; 643 } 644 if (ata_c->flags & AT_POLL) 645 xfer->c_flags |= C_POLL; 646 if (ata_c->flags & AT_WAIT) 647 xfer->c_flags |= C_WAIT; 648 xfer->c_drive = drvp->drive; 649 xfer->c_databuf = ata_c->data; 650 xfer->c_bcount = ata_c->bcount; 651 xfer->c_cmd = ata_c; 652 xfer->c_start = ahci_cmd_start; 653 xfer->c_intr = ahci_cmd_complete; 654 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 655 s = splbio(); 656 ata_exec_xfer(chp, xfer); 657 #ifdef DIAGNOSTIC 658 if ((ata_c->flags & AT_POLL) != 0 && 659 (ata_c->flags & AT_DONE) == 0) 660 panic("ahci_exec_command: polled command not done"); 661 #endif 662 if (ata_c->flags & AT_DONE) { 663 ret = ATACMD_COMPLETE; 664 } else { 665 if (ata_c->flags & AT_WAIT) { 666 while ((ata_c->flags & AT_DONE) == 0) { 667 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 668 } 669 ret = ATACMD_COMPLETE; 670 } else { 671 ret = ATACMD_QUEUED; 672 } 673 } 674 splx(s); 675 return ret; 676 } 677 678 void 679 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 680 { 681 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 682 struct ahci_channel *achp = (struct ahci_channel *)chp; 683 struct ata_command *ata_c = xfer->c_cmd; 684 int slot = 0 /* XXX slot */; 685 struct ahci_cmd_tbl *cmd_tbl; 686 struct ahci_cmd_header *cmd_h; 687 u_int8_t *fis; 688 int i; 689 int channel = chp->ch_channel; 690 691 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 692 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 693 694 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 695 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 696 cmd_tbl), DEBUG_XFERS); 697 fis = cmd_tbl->cmdt_cfis; 698 699 fis[0] = 0x27; /* host to device */ 700 fis[1] = 0x80; /* command FIS */ 701 fis[2] = ata_c->r_command; 702 fis[3] = ata_c->r_features; 703 fis[4] = ata_c->r_sector; 704 fis[5] = ata_c->r_cyl & 0xff; 705 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 706 fis[7] = ata_c->r_head & 0x0f; 707 fis[8] = 0; 708 fis[9] = 0; 709 fis[10] = 0; 710 fis[11] = 0; 711 fis[12] = ata_c->r_count; 712 fis[13] = 0; 713 fis[14] = 0; 714 fis[15] = WDCTL_4BIT; 715 fis[16] = 0; 716 fis[17] = 0; 717 fis[18] = 0; 718 fis[19] = 0; 719 720 cmd_h = &achp->ahcic_cmdh[slot]; 721 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 722 chp->ch_channel, cmd_h), DEBUG_XFERS); 723 if (ahci_dma_setup(chp, slot, 724 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 725 ata_c->bcount, 726 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 727 ata_c->flags |= AT_DF; 728 ahci_cmd_complete(chp, xfer, slot); 729 return; 730 } 731 cmd_h->cmdh_flags = htole16( 732 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 733 20 /* fis lenght */ / 4); 734 cmd_h->cmdh_prdbc = 0; 735 AHCI_CMDH_SYNC(sc, achp, slot, 736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 737 738 if (ata_c->flags & AT_POLL) { 739 /* polled command, disable interrupts */ 740 AHCI_WRITE(sc, AHCI_GHC, 741 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 742 } 743 chp->ch_flags |= ATACH_IRQ_WAIT; 744 chp->ch_status = 0; 745 /* start command */ 746 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 747 /* and says we started this command */ 748 achp->ahcic_cmds_active |= 1 << slot; 749 750 if ((ata_c->flags & AT_POLL) == 0) { 751 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 752 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 753 ahci_timeout, chp); 754 return; 755 } 756 /* 757 * Polled command. 758 */ 759 for (i = 0; i < ata_c->timeout / 10; i++) { 760 if (ata_c->flags & AT_DONE) 761 break; 762 ahci_intr_port(sc, achp); 763 if (ata_c->flags & AT_WAIT) 764 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 765 else 766 delay(10000); 767 } 768 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 769 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 770 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 771 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 772 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 773 DEBUG_XFERS); 774 if ((ata_c->flags & AT_DONE) == 0) { 775 ata_c->flags |= AT_TIMEOU; 776 ahci_cmd_complete(chp, xfer, slot); 777 } 778 /* reenable interrupts */ 779 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 780 } 781 782 void 783 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 784 { 785 struct ata_command *ata_c = xfer->c_cmd; 786 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 787 DEBUG_FUNCS); 788 789 switch (reason) { 790 case KILL_GONE: 791 ata_c->flags |= AT_GONE; 792 break; 793 case KILL_RESET: 794 ata_c->flags |= AT_RESET; 795 break; 796 default: 797 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 798 panic("ahci_cmd_kill_xfer"); 799 } 800 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 801 } 802 803 int 804 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 805 { 806 int slot = 0; /* XXX slot */ 807 struct ata_command *ata_c = xfer->c_cmd; 808 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 809 810 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 811 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 812 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 813 DEBUG_FUNCS); 814 chp->ch_flags &= ~ATACH_IRQ_WAIT; 815 if (xfer->c_flags & C_TIMEOU) { 816 ata_c->flags |= AT_TIMEOU; 817 } else 818 callout_stop(&chp->ch_callout); 819 820 chp->ch_queue->active_xfer = NULL; 821 822 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 823 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 824 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 825 wakeup(&chp->ch_queue->active_xfer); 826 return 0; 827 } 828 if (is) { 829 ata_c->r_head = 0; 830 ata_c->r_count = 0; 831 ata_c->r_sector = 0; 832 ata_c->r_cyl = 0; 833 if (chp->ch_status & WDCS_BSY) { 834 ata_c->flags |= AT_TIMEOU; 835 } else if (chp->ch_status & WDCS_ERR) { 836 ata_c->r_error = chp->ch_error; 837 ata_c->flags |= AT_ERROR; 838 } 839 } 840 ahci_cmd_done(chp, xfer, slot); 841 return 0; 842 } 843 844 void 845 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 846 { 847 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 848 struct ahci_channel *achp = (struct ahci_channel *)chp; 849 struct ata_command *ata_c = xfer->c_cmd; 850 851 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 852 DEBUG_FUNCS); 853 854 /* this comamnd is not active any more */ 855 achp->ahcic_cmds_active &= ~(1 << slot); 856 857 if (ata_c->flags & (AT_READ|AT_WRITE)) { 858 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 859 achp->ahcic_datad[slot]->dm_mapsize, 860 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 861 BUS_DMASYNC_POSTWRITE); 862 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 863 } 864 865 AHCI_CMDH_SYNC(sc, achp, slot, 866 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 867 868 ata_c->flags |= AT_DONE; 869 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 870 ata_c->flags |= AT_XFDONE; 871 872 ata_free_xfer(chp, xfer); 873 if (ata_c->flags & AT_WAIT) 874 wakeup(ata_c); 875 else if (ata_c->callback) 876 ata_c->callback(ata_c->callback_arg); 877 atastart(chp); 878 return; 879 } 880 881 int 882 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 883 { 884 struct ata_channel *chp = drvp->chnl_softc; 885 struct ata_xfer *xfer; 886 887 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 888 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 889 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 890 DEBUG_XFERS); 891 xfer = ata_get_xfer(ATAXF_NOSLEEP); 892 if (xfer == NULL) { 893 return ATACMD_TRY_AGAIN; 894 } 895 if (ata_bio->flags & ATA_POLL) 896 xfer->c_flags |= C_POLL; 897 xfer->c_drive = drvp->drive; 898 xfer->c_cmd = ata_bio; 899 xfer->c_databuf = ata_bio->databuf; 900 xfer->c_bcount = ata_bio->bcount; 901 xfer->c_start = ahci_bio_start; 902 xfer->c_intr = ahci_bio_complete; 903 xfer->c_kill_xfer = ahci_bio_kill_xfer; 904 ata_exec_xfer(chp, xfer); 905 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 906 } 907 908 void 909 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 910 { 911 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 912 struct ahci_channel *achp = (struct ahci_channel *)chp; 913 struct ata_bio *ata_bio = xfer->c_cmd; 914 int slot = 0 /* XXX slot */; 915 struct ahci_cmd_tbl *cmd_tbl; 916 struct ahci_cmd_header *cmd_h; 917 u_int8_t *fis; 918 int i, nblks; 919 int channel = chp->ch_channel; 920 921 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 922 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 923 924 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 925 926 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 927 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 928 cmd_tbl), DEBUG_XFERS); 929 fis = cmd_tbl->cmdt_cfis; 930 931 fis[0] = 0x27; /* host to device */ 932 fis[1] = 0x80; /* command FIS */ 933 if (ata_bio->flags & ATA_LBA48) { 934 fis[2] = (ata_bio->flags & ATA_READ) ? 935 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 936 } else { 937 fis[2] = 938 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 939 } 940 fis[3] = 0; /* features */ 941 fis[4] = ata_bio->blkno & 0xff; 942 fis[5] = (ata_bio->blkno >> 8) & 0xff; 943 fis[6] = (ata_bio->blkno >> 16) & 0xff; 944 if (ata_bio->flags & ATA_LBA48) { 945 fis[7] = WDSD_LBA; 946 fis[8] = (ata_bio->blkno >> 24) & 0xff; 947 fis[9] = (ata_bio->blkno >> 32) & 0xff; 948 fis[10] = (ata_bio->blkno >> 40) & 0xff; 949 } else { 950 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 951 fis[8] = 0; 952 fis[9] = 0; 953 fis[10] = 0; 954 } 955 fis[11] = 0; /* ext features */ 956 fis[12] = nblks & 0xff; 957 fis[13] = (ata_bio->flags & ATA_LBA48) ? 958 ((nblks >> 8) & 0xff) : 0; 959 fis[14] = 0; 960 fis[15] = WDCTL_4BIT; 961 fis[16] = 0; 962 fis[17] = 0; 963 fis[18] = 0; 964 fis[19] = 0; 965 966 cmd_h = &achp->ahcic_cmdh[slot]; 967 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 968 chp->ch_channel, cmd_h), DEBUG_XFERS); 969 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 970 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 971 ata_bio->error = ERR_DMA; 972 ata_bio->r_error = 0; 973 ahci_bio_complete(chp, xfer, slot); 974 return; 975 } 976 cmd_h->cmdh_flags = htole16( 977 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 978 20 /* fis lenght */ / 4); 979 cmd_h->cmdh_prdbc = 0; 980 AHCI_CMDH_SYNC(sc, achp, slot, 981 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 982 983 if (xfer->c_flags & C_POLL) { 984 /* polled command, disable interrupts */ 985 AHCI_WRITE(sc, AHCI_GHC, 986 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 987 } 988 chp->ch_flags |= ATACH_IRQ_WAIT; 989 chp->ch_status = 0; 990 /* start command */ 991 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 992 /* and says we started this command */ 993 achp->ahcic_cmds_active |= 1 << slot; 994 995 if ((xfer->c_flags & C_POLL) == 0) { 996 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 997 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 998 ahci_timeout, chp); 999 return; 1000 } 1001 /* 1002 * Polled command. 1003 */ 1004 for (i = 0; i < ATA_DELAY / 10; i++) { 1005 if (ata_bio->flags & ATA_ITSDONE) 1006 break; 1007 ahci_intr_port(sc, achp); 1008 if (ata_bio->flags & ATA_NOSLEEP) 1009 delay(10000); 1010 else 1011 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1012 } 1013 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1014 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1015 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1016 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1017 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1018 DEBUG_XFERS); 1019 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1020 ata_bio->error = TIMEOUT; 1021 ahci_bio_complete(chp, xfer, slot); 1022 } 1023 /* reenable interrupts */ 1024 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1025 } 1026 1027 void 1028 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1029 { 1030 int slot = 0; /* XXX slot */ 1031 int drive = xfer->c_drive; 1032 struct ata_bio *ata_bio = xfer->c_cmd; 1033 struct ahci_channel *achp = (struct ahci_channel *)chp; 1034 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1035 DEBUG_FUNCS); 1036 1037 achp->ahcic_cmds_active &= ~(1 << slot); 1038 ata_free_xfer(chp, xfer); 1039 ata_bio->flags |= ATA_ITSDONE; 1040 switch (reason) { 1041 case KILL_GONE: 1042 ata_bio->error = ERR_NODEV; 1043 break; 1044 case KILL_RESET: 1045 ata_bio->error = ERR_RESET; 1046 break; 1047 default: 1048 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1049 panic("ahci_bio_kill_xfer"); 1050 } 1051 ata_bio->r_error = WDCE_ABRT; 1052 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1053 } 1054 1055 int 1056 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1057 { 1058 int slot = 0; /* XXX slot */ 1059 struct ata_bio *ata_bio = xfer->c_cmd; 1060 int drive = xfer->c_drive; 1061 struct ahci_channel *achp = (struct ahci_channel *)chp; 1062 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1063 1064 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1065 DEBUG_FUNCS); 1066 1067 achp->ahcic_cmds_active &= ~(1 << slot); 1068 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1069 if (xfer->c_flags & C_TIMEOU) { 1070 ata_bio->error = TIMEOUT; 1071 } else { 1072 callout_stop(&chp->ch_callout); 1073 ata_bio->error = NOERROR; 1074 } 1075 1076 chp->ch_queue->active_xfer = NULL; 1077 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1078 achp->ahcic_datad[slot]->dm_mapsize, 1079 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1080 BUS_DMASYNC_POSTWRITE); 1081 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1082 1083 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1084 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1085 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1086 wakeup(&chp->ch_queue->active_xfer); 1087 return 0; 1088 } 1089 ata_free_xfer(chp, xfer); 1090 ata_bio->flags |= ATA_ITSDONE; 1091 if (chp->ch_status & WDCS_DWF) { 1092 ata_bio->error = ERR_DF; 1093 } else if (chp->ch_status & WDCS_ERR) { 1094 ata_bio->error = ERROR; 1095 ata_bio->r_error = chp->ch_error; 1096 } else if (chp->ch_status & WDCS_CORR) 1097 ata_bio->flags |= ATA_CORR; 1098 1099 AHCI_CMDH_SYNC(sc, achp, slot, 1100 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1101 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1102 ata_bio->bcount), DEBUG_XFERS); 1103 /* 1104 * if it was a write, complete data buffer may have been transfered 1105 * before error detection; in this case don't use cmdh_prdbc 1106 * as it won't reflect what was written to media. Assume nothing 1107 * was transfered and leave bcount as-is. 1108 */ 1109 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1110 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1111 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1112 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1113 atastart(chp); 1114 return 0; 1115 } 1116 1117 void 1118 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1119 { 1120 int i; 1121 /* stop channel */ 1122 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1123 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1124 /* wait 1s for channel to stop */ 1125 for (i = 0; i <100; i++) { 1126 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1127 == 0) 1128 break; 1129 if (flags & AT_WAIT) 1130 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1131 else 1132 delay(10000); 1133 } 1134 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1135 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1136 /* XXX controller reset ? */ 1137 return; 1138 } 1139 } 1140 1141 void 1142 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1143 { 1144 /* clear error */ 1145 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1146 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1147 1148 /* and start controller */ 1149 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1150 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1151 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1152 } 1153 1154 void 1155 ahci_timeout(void *v) 1156 { 1157 struct ata_channel *chp = (struct ata_channel *)v; 1158 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1159 int s = splbio(); 1160 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1161 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1162 xfer->c_flags |= C_TIMEOU; 1163 xfer->c_intr(chp, xfer, 0); 1164 } 1165 splx(s); 1166 } 1167 1168 int 1169 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1170 size_t count, int op) 1171 { 1172 int error, seg; 1173 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1174 struct ahci_channel *achp = (struct ahci_channel *)chp; 1175 struct ahci_cmd_tbl *cmd_tbl; 1176 struct ahci_cmd_header *cmd_h; 1177 1178 cmd_h = &achp->ahcic_cmdh[slot]; 1179 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1180 1181 if (data == NULL) { 1182 cmd_h->cmdh_prdtl = 0; 1183 goto end; 1184 } 1185 1186 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1187 data, count, NULL, 1188 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1189 if (error) { 1190 printf("%s port %d: failed to load xfer: %d\n", 1191 AHCINAME(sc), chp->ch_channel, error); 1192 return error; 1193 } 1194 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1195 achp->ahcic_datad[slot]->dm_mapsize, 1196 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1197 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1198 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1199 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1200 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1201 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1202 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1203 } 1204 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1205 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1206 end: 1207 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1208 return 0; 1209 } 1210 1211 #if NATAPIBUS > 0 1212 void 1213 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1214 { 1215 struct ata_channel *chp = ata_sc->sc_chan; 1216 struct atac_softc *atac = chp->ch_atac; 1217 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1218 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1219 /* 1220 * Fill in the scsipi_adapter. 1221 */ 1222 adapt->adapt_dev = atac->atac_dev; 1223 adapt->adapt_nchannels = atac->atac_nchannels; 1224 adapt->adapt_request = ahci_atapi_scsipi_request; 1225 adapt->adapt_minphys = ahci_atapi_minphys; 1226 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1227 1228 /* 1229 * Fill in the scsipi_channel. 1230 */ 1231 memset(chan, 0, sizeof(*chan)); 1232 chan->chan_adapter = adapt; 1233 chan->chan_bustype = &ahci_atapi_bustype; 1234 chan->chan_channel = chp->ch_channel; 1235 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1236 chan->chan_openings = 1; 1237 chan->chan_max_periph = 1; 1238 chan->chan_ntargets = 1; 1239 chan->chan_nluns = 1; 1240 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1241 atapiprint); 1242 } 1243 1244 void 1245 ahci_atapi_minphys(struct buf *bp) 1246 { 1247 if (bp->b_bcount > MAXPHYS) 1248 bp->b_bcount = MAXPHYS; 1249 minphys(bp); 1250 } 1251 1252 /* 1253 * Kill off all pending xfers for a periph. 1254 * 1255 * Must be called at splbio(). 1256 */ 1257 void 1258 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1259 { 1260 struct atac_softc *atac = 1261 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1262 struct ata_channel *chp = 1263 atac->atac_channels[periph->periph_channel->chan_channel]; 1264 1265 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1266 } 1267 1268 void 1269 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1270 scsipi_adapter_req_t req, void *arg) 1271 { 1272 struct scsipi_adapter *adapt = chan->chan_adapter; 1273 struct scsipi_periph *periph; 1274 struct scsipi_xfer *sc_xfer; 1275 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1276 struct atac_softc *atac = &sc->sc_atac; 1277 struct ata_xfer *xfer; 1278 int channel = chan->chan_channel; 1279 int drive, s; 1280 1281 switch (req) { 1282 case ADAPTER_REQ_RUN_XFER: 1283 sc_xfer = arg; 1284 periph = sc_xfer->xs_periph; 1285 drive = periph->periph_target; 1286 if (!device_is_active(atac->atac_dev)) { 1287 sc_xfer->error = XS_DRIVER_STUFFUP; 1288 scsipi_done(sc_xfer); 1289 return; 1290 } 1291 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1292 if (xfer == NULL) { 1293 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1294 scsipi_done(sc_xfer); 1295 return; 1296 } 1297 1298 if (sc_xfer->xs_control & XS_CTL_POLL) 1299 xfer->c_flags |= C_POLL; 1300 xfer->c_drive = drive; 1301 xfer->c_flags |= C_ATAPI; 1302 xfer->c_cmd = sc_xfer; 1303 xfer->c_databuf = sc_xfer->data; 1304 xfer->c_bcount = sc_xfer->datalen; 1305 xfer->c_start = ahci_atapi_start; 1306 xfer->c_intr = ahci_atapi_complete; 1307 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1308 xfer->c_dscpoll = 0; 1309 s = splbio(); 1310 ata_exec_xfer(atac->atac_channels[channel], xfer); 1311 #ifdef DIAGNOSTIC 1312 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1313 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1314 panic("ahci_atapi_scsipi_request: polled command " 1315 "not done"); 1316 #endif 1317 splx(s); 1318 return; 1319 default: 1320 /* Not supported, nothing to do. */ 1321 ; 1322 } 1323 } 1324 1325 void 1326 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1327 { 1328 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1329 struct ahci_channel *achp = (struct ahci_channel *)chp; 1330 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1331 int slot = 0 /* XXX slot */; 1332 struct ahci_cmd_tbl *cmd_tbl; 1333 struct ahci_cmd_header *cmd_h; 1334 u_int8_t *fis; 1335 int i; 1336 int channel = chp->ch_channel; 1337 1338 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1339 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1340 1341 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1342 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1343 cmd_tbl), DEBUG_XFERS); 1344 fis = cmd_tbl->cmdt_cfis; 1345 1346 fis[0] = 0x27; /* host to device */ 1347 fis[1] = 0x80; /* command FIS */ 1348 fis[2] = ATAPI_PKT_CMD; 1349 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1350 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1351 fis[3] = (sc_xfer->datalen ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1352 fis[4] = 0; 1353 fis[5] = 0; 1354 fis[6] = 0; 1355 fis[7] = WDSD_LBA; 1356 fis[8] = 0; 1357 fis[9] = 0; 1358 fis[10] = 0; 1359 fis[11] = 0; /* ext features */ 1360 fis[12] = 0; 1361 fis[13] = 0; 1362 fis[14] = 0; 1363 fis[15] = WDCTL_4BIT; 1364 fis[16] = 0; 1365 fis[17] = 0; 1366 fis[18] = 0; 1367 fis[19] = 0; 1368 1369 cmd_h = &achp->ahcic_cmdh[slot]; 1370 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1371 chp->ch_channel, cmd_h), DEBUG_XFERS); 1372 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1373 sc_xfer->datalen, 1374 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1375 BUS_DMA_READ : BUS_DMA_WRITE)) { 1376 sc_xfer->error = XS_DRIVER_STUFFUP; 1377 ahci_atapi_complete(chp, xfer, slot); 1378 return; 1379 } 1380 cmd_h->cmdh_flags = htole16( 1381 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1382 20 /* fis lenght */ / 4 | AHCI_CMDH_F_A); 1383 cmd_h->cmdh_prdbc = 0; 1384 AHCI_CMDH_SYNC(sc, achp, slot, 1385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1386 1387 if (xfer->c_flags & C_POLL) { 1388 /* polled command, disable interrupts */ 1389 AHCI_WRITE(sc, AHCI_GHC, 1390 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1391 } 1392 chp->ch_flags |= ATACH_IRQ_WAIT; 1393 chp->ch_status = 0; 1394 /* start command */ 1395 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1396 /* and says we started this command */ 1397 achp->ahcic_cmds_active |= 1 << slot; 1398 1399 if ((xfer->c_flags & C_POLL) == 0) { 1400 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1401 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1402 ahci_timeout, chp); 1403 return; 1404 } 1405 /* 1406 * Polled command. 1407 */ 1408 for (i = 0; i < ATA_DELAY / 10; i++) { 1409 if (sc_xfer->xs_status & XS_STS_DONE) 1410 break; 1411 ahci_intr_port(sc, achp); 1412 delay(10000); 1413 } 1414 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1415 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1416 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1417 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1418 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1419 DEBUG_XFERS); 1420 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1421 sc_xfer->error = XS_TIMEOUT; 1422 ahci_atapi_complete(chp, xfer, slot); 1423 } 1424 /* reenable interrupts */ 1425 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1426 } 1427 1428 int 1429 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1430 { 1431 int slot = 0; /* XXX slot */ 1432 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1433 int drive = xfer->c_drive; 1434 struct ahci_channel *achp = (struct ahci_channel *)chp; 1435 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1436 1437 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1438 DEBUG_FUNCS); 1439 1440 achp->ahcic_cmds_active &= ~(1 << slot); 1441 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1442 if (xfer->c_flags & C_TIMEOU) { 1443 sc_xfer->error = XS_TIMEOUT; 1444 } else { 1445 callout_stop(&chp->ch_callout); 1446 sc_xfer->error = 0; 1447 } 1448 1449 chp->ch_queue->active_xfer = NULL; 1450 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1451 achp->ahcic_datad[slot]->dm_mapsize, 1452 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1453 BUS_DMASYNC_POSTWRITE); 1454 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1455 1456 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1457 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1458 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1459 wakeup(&chp->ch_queue->active_xfer); 1460 return 0; 1461 } 1462 ata_free_xfer(chp, xfer); 1463 1464 AHCI_CMDH_SYNC(sc, achp, slot, 1465 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1466 sc_xfer->resid = sc_xfer->datalen; 1467 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1468 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1469 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1470 if (chp->ch_status & WDCS_ERR && 1471 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1472 sc_xfer->resid == sc_xfer->datalen)) { 1473 sc_xfer->error = XS_SHORTSENSE; 1474 sc_xfer->sense.atapi_sense = chp->ch_error; 1475 if ((sc_xfer->xs_periph->periph_quirks & 1476 PQUIRK_NOSENSE) == 0) { 1477 /* ask scsipi to send a REQUEST_SENSE */ 1478 sc_xfer->error = XS_BUSY; 1479 sc_xfer->status = SCSI_CHECK; 1480 } 1481 } 1482 scsipi_done(sc_xfer); 1483 atastart(chp); 1484 return 0; 1485 } 1486 1487 void 1488 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1489 { 1490 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1491 struct ahci_channel *achp = (struct ahci_channel *)chp; 1492 int slot = 0; /* XXX slot */ 1493 1494 achp->ahcic_cmds_active &= ~(1 << slot); 1495 1496 /* remove this command from xfer queue */ 1497 switch (reason) { 1498 case KILL_GONE: 1499 sc_xfer->error = XS_DRIVER_STUFFUP; 1500 break; 1501 case KILL_RESET: 1502 sc_xfer->error = XS_RESET; 1503 break; 1504 default: 1505 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1506 panic("ahci_ata_atapi_kill_xfer"); 1507 } 1508 ata_free_xfer(chp, xfer); 1509 scsipi_done(sc_xfer); 1510 } 1511 1512 void 1513 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1514 { 1515 struct scsipi_channel *chan = sc->sc_channel; 1516 struct scsipi_periph *periph; 1517 struct ataparams ids; 1518 struct ataparams *id = &ids; 1519 struct ahci_softc *ahcic = 1520 device_private(chan->chan_adapter->adapt_dev); 1521 struct atac_softc *atac = &ahcic->sc_atac; 1522 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1523 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1524 struct scsipibus_attach_args sa; 1525 char serial_number[21], model[41], firmware_revision[9]; 1526 int s; 1527 1528 /* skip if already attached */ 1529 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1530 return; 1531 1532 /* if no ATAPI device detected at attach time, skip */ 1533 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1534 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1535 "not present\n", target), DEBUG_PROBE); 1536 return; 1537 } 1538 1539 /* Some ATAPI devices need a bit more time after software reset. */ 1540 delay(5000); 1541 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1542 #ifdef ATAPI_DEBUG_PROBE 1543 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1544 AHCINAME(ahcic), target, 1545 id->atap_config & ATAPI_CFG_CMD_MASK, 1546 id->atap_config & ATAPI_CFG_DRQ_MASK); 1547 #endif 1548 periph = scsipi_alloc_periph(M_NOWAIT); 1549 if (periph == NULL) { 1550 aprint_error_dev(sc->sc_dev, 1551 "unable to allocate periph for drive %d\n", 1552 target); 1553 return; 1554 } 1555 periph->periph_dev = NULL; 1556 periph->periph_channel = chan; 1557 periph->periph_switch = &atapi_probe_periphsw; 1558 periph->periph_target = target; 1559 periph->periph_lun = 0; 1560 periph->periph_quirks = PQUIRK_ONLYBIG; 1561 1562 #ifdef SCSIPI_DEBUG 1563 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1564 SCSIPI_DEBUG_TARGET == target) 1565 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1566 #endif 1567 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1568 if (id->atap_config & ATAPI_CFG_REMOV) 1569 periph->periph_flags |= PERIPH_REMOVABLE; 1570 if (periph->periph_type == T_SEQUENTIAL) { 1571 s = splbio(); 1572 drvp->drive_flags |= DRIVE_ATAPIST; 1573 splx(s); 1574 } 1575 1576 sa.sa_periph = periph; 1577 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1578 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1579 T_REMOV : T_FIXED; 1580 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1581 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1582 20); 1583 scsipi_strvis((u_char *)firmware_revision, 8, 1584 id->atap_revision, 8); 1585 sa.sa_inqbuf.vendor = model; 1586 sa.sa_inqbuf.product = serial_number; 1587 sa.sa_inqbuf.revision = firmware_revision; 1588 1589 /* 1590 * Determine the operating mode capabilities of the device. 1591 */ 1592 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1593 periph->periph_cap |= PERIPH_CAP_CMD16; 1594 /* XXX This is gross. */ 1595 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1596 1597 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1598 1599 if (drvp->drv_softc) 1600 ata_probe_caps(drvp); 1601 else { 1602 s = splbio(); 1603 drvp->drive_flags &= ~DRIVE_ATAPI; 1604 splx(s); 1605 } 1606 } else { 1607 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1608 "failed for drive %s:%d:%d: error 0x%x\n", 1609 AHCINAME(ahcic), chp->ch_channel, target, 1610 chp->ch_error), DEBUG_PROBE); 1611 s = splbio(); 1612 drvp->drive_flags &= ~DRIVE_ATAPI; 1613 splx(s); 1614 } 1615 } 1616 #endif /* NATAPIBUS */ 1617
Indexes created Fri Oct 17 00:09:41 GMT 2025