ahcisata_core.c revision 1.28
1 /* $NetBSD: ahcisata_core.c,v 1.28 2010/07/20 19:24:11 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.28 2010/07/20 19:24:11 jakllsch Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/ata/atareg.h> 43 #include <dev/ata/satavar.h> 44 #include <dev/ata/satareg.h> 45 #include <dev/ata/satafisvar.h> 46 #include <dev/ata/satafisreg.h> 47 #include <dev/ic/ahcisatavar.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0x0; 55 #endif 56 57 void ahci_probe_drive(struct ata_channel *); 58 void ahci_setup_channel(struct ata_channel *); 59 60 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 void ahci_reset_drive(struct ata_drive_datas *, int); 62 void ahci_reset_channel(struct ata_channel *, int); 63 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 64 int ahci_ata_addref(struct ata_drive_datas *); 65 void ahci_ata_delref(struct ata_drive_datas *); 66 void ahci_killpending(struct ata_drive_datas *); 67 68 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 69 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 70 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 71 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 72 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 73 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 74 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 75 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 76 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 77 void ahci_timeout(void *); 78 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 79 80 #if NATAPIBUS > 0 81 void ahci_atapibus_attach(struct atabus_softc *); 82 void ahci_atapi_kill_pending(struct scsipi_periph *); 83 void ahci_atapi_minphys(struct buf *); 84 void ahci_atapi_scsipi_request(struct scsipi_channel *, 85 scsipi_adapter_req_t, void *); 86 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 87 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 88 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 89 void ahci_atapi_probe_device(struct atapibus_softc *, int); 90 91 static const struct scsipi_bustype ahci_atapi_bustype = { 92 SCSIPI_BUSTYPE_ATAPI, 93 atapi_scsipi_cmd, 94 atapi_interpret_sense, 95 atapi_print_addr, 96 ahci_atapi_kill_pending, 97 }; 98 #endif /* NATAPIBUS */ 99 100 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 101 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 102 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 103 104 const struct ata_bustype ahci_ata_bustype = { 105 SCSIPI_BUSTYPE_ATA, 106 ahci_ata_bio, 107 ahci_reset_drive, 108 ahci_reset_channel, 109 ahci_exec_command, 110 ata_get_params, 111 ahci_ata_addref, 112 ahci_ata_delref, 113 ahci_killpending 114 }; 115 116 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 117 118 static void ahci_setup_port(struct ahci_softc *sc, int i); 119 120 int 121 ahci_reset(struct ahci_softc *sc) 122 { 123 int i; 124 125 /* reset controller */ 126 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 127 /* wait up to 1s for reset to complete */ 128 for (i = 0; i < 1000; i++) { 129 delay(1000); 130 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 131 break; 132 } 133 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 134 aprint_error("%s: reset failed\n", AHCINAME(sc)); 135 return -1; 136 } 137 /* enable ahci mode */ 138 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 139 return 0; 140 } 141 142 void 143 ahci_setup_ports(struct ahci_softc *sc) 144 { 145 uint32_t ahci_ports; 146 int i, port; 147 148 ahci_ports = AHCI_READ(sc, AHCI_PI); 149 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 150 if ((ahci_ports & (1 << i)) == 0) 151 continue; 152 if (port >= sc->sc_atac.atac_nchannels) { 153 aprint_error("%s: more ports than announced\n", 154 AHCINAME(sc)); 155 break; 156 } 157 ahci_setup_port(sc, i); 158 } 159 } 160 161 void 162 ahci_reprobe_drives(struct ahci_softc *sc) 163 { 164 uint32_t ahci_ports; 165 int i, port; 166 struct ahci_channel *achp; 167 struct ata_channel *chp; 168 169 ahci_ports = AHCI_READ(sc, AHCI_PI); 170 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 171 if ((ahci_ports & (1 << i)) == 0) 172 continue; 173 if (port >= sc->sc_atac.atac_nchannels) { 174 aprint_error("%s: more ports than announced\n", 175 AHCINAME(sc)); 176 break; 177 } 178 achp = &sc->sc_channels[i]; 179 chp = &achp->ata_channel; 180 181 ahci_probe_drive(chp); 182 } 183 } 184 185 static void 186 ahci_setup_port(struct ahci_softc *sc, int i) 187 { 188 struct ahci_channel *achp; 189 190 achp = &sc->sc_channels[i]; 191 192 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 193 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 194 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 195 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 196 } 197 198 void 199 ahci_enable_intrs(struct ahci_softc *sc) 200 { 201 202 /* clear interrupts */ 203 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 204 /* enable interrupts */ 205 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 206 } 207 208 void 209 ahci_attach(struct ahci_softc *sc) 210 { 211 uint32_t ahci_cap, ahci_rev, ahci_ports; 212 int i, j, port; 213 struct ahci_channel *achp; 214 struct ata_channel *chp; 215 int error; 216 bus_dma_segment_t seg; 217 int rseg; 218 int dmasize; 219 void *cmdhp; 220 void *cmdtblp; 221 222 if (ahci_reset(sc) != 0) 223 return; 224 225 ahci_cap = AHCI_READ(sc, AHCI_CAP); 226 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 227 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 228 ahci_rev = AHCI_READ(sc, AHCI_VS); 229 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 230 switch(ahci_rev) { 231 case AHCI_VS_10: 232 aprint_normal("1.0"); 233 break; 234 case AHCI_VS_11: 235 aprint_normal("1.1"); 236 break; 237 case AHCI_VS_12: 238 aprint_normal("1.2"); 239 break; 240 default: 241 aprint_normal("0x%x", ahci_rev); 242 break; 243 } 244 245 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 246 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 247 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 248 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 249 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 250 sc->sc_atac.atac_pio_cap = 4; 251 sc->sc_atac.atac_dma_cap = 2; 252 sc->sc_atac.atac_udma_cap = 6; 253 sc->sc_atac.atac_channels = sc->sc_chanarray; 254 sc->sc_atac.atac_probe = ahci_probe_drive; 255 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 256 sc->sc_atac.atac_set_modes = ahci_setup_channel; 257 #if NATAPIBUS > 0 258 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 259 #endif 260 261 dmasize = 262 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 263 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 264 &seg, 1, &rseg, BUS_DMA_NOWAIT); 265 if (error) { 266 aprint_error("%s: unable to allocate command header memory" 267 ", error=%d\n", AHCINAME(sc), error); 268 return; 269 } 270 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 271 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 272 if (error) { 273 aprint_error("%s: unable to map command header memory" 274 ", error=%d\n", AHCINAME(sc), error); 275 return; 276 } 277 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 278 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 279 if (error) { 280 aprint_error("%s: unable to create command header map" 281 ", error=%d\n", AHCINAME(sc), error); 282 return; 283 } 284 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 285 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 286 if (error) { 287 aprint_error("%s: unable to load command header map" 288 ", error=%d\n", AHCINAME(sc), error); 289 return; 290 } 291 sc->sc_cmd_hdr = cmdhp; 292 293 ahci_enable_intrs(sc); 294 295 ahci_ports = AHCI_READ(sc, AHCI_PI); 296 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 297 if ((ahci_ports & (1 << i)) == 0) 298 continue; 299 if (port >= sc->sc_atac.atac_nchannels) { 300 aprint_error("%s: more ports than announced\n", 301 AHCINAME(sc)); 302 break; 303 } 304 achp = &sc->sc_channels[i]; 305 chp = (struct ata_channel *)achp; 306 sc->sc_chanarray[i] = chp; 307 chp->ch_channel = i; 308 chp->ch_atac = &sc->sc_atac; 309 chp->ch_queue = malloc(sizeof(struct ata_queue), 310 M_DEVBUF, M_NOWAIT); 311 if (chp->ch_queue == NULL) { 312 aprint_error("%s port %d: can't allocate memory for " 313 "command queue", AHCINAME(sc), i); 314 break; 315 } 316 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 318 &seg, 1, &rseg, BUS_DMA_NOWAIT); 319 if (error) { 320 aprint_error("%s: unable to allocate command table " 321 "memory, error=%d\n", AHCINAME(sc), error); 322 break; 323 } 324 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 325 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 326 if (error) { 327 aprint_error("%s: unable to map command table memory" 328 ", error=%d\n", AHCINAME(sc), error); 329 break; 330 } 331 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 332 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 333 if (error) { 334 aprint_error("%s: unable to create command table map" 335 ", error=%d\n", AHCINAME(sc), error); 336 break; 337 } 338 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 339 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error("%s: unable to load command table map" 342 ", error=%d\n", AHCINAME(sc), error); 343 break; 344 } 345 achp->ahcic_cmdh = (struct ahci_cmd_header *) 346 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 347 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 348 AHCI_CMDH_SIZE * port; 349 achp->ahcic_rfis = (struct ahci_r_fis *) 350 ((char *)cmdhp + 351 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 352 AHCI_RFIS_SIZE * port); 353 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 354 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 355 AHCI_RFIS_SIZE * port; 356 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 357 "rfis %p (0x%" PRIx64 ")\n", i, 358 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 359 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 360 DEBUG_PROBE); 361 362 for (j = 0; j < sc->sc_ncmds; j++) { 363 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 364 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 365 achp->ahcic_bus_cmd_tbl[j] = 366 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 367 AHCI_CMDTBL_SIZE * j; 368 achp->ahcic_cmdh[j].cmdh_cmdtba = 369 htole64(achp->ahcic_bus_cmd_tbl[j]); 370 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 371 achp->ahcic_cmd_tbl[j], 372 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 373 /* The xfer DMA map */ 374 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 375 AHCI_NPRD, 0x400000 /* 4MB */, 0, 376 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 377 &achp->ahcic_datad[j]); 378 if (error) { 379 aprint_error("%s: couldn't alloc xfer DMA map, " 380 "error=%d\n", AHCINAME(sc), error); 381 goto end; 382 } 383 } 384 ahci_setup_port(sc, i); 385 chp->ch_ndrive = 1; 386 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 387 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 388 aprint_error("%s: couldn't map channel %d " 389 "sata_status regs\n", AHCINAME(sc), i); 390 break; 391 } 392 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 393 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 394 aprint_error("%s: couldn't map channel %d " 395 "sata_control regs\n", AHCINAME(sc), i); 396 break; 397 } 398 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 399 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 400 aprint_error("%s: couldn't map channel %d " 401 "sata_error regs\n", AHCINAME(sc), i); 402 break; 403 } 404 ata_channel_attach(chp); 405 port++; 406 end: 407 continue; 408 } 409 } 410 411 int 412 ahci_intr(void *v) 413 { 414 struct ahci_softc *sc = v; 415 uint32_t is; 416 int i, r = 0; 417 418 while ((is = AHCI_READ(sc, AHCI_IS))) { 419 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 420 DEBUG_INTR); 421 r = 1; 422 AHCI_WRITE(sc, AHCI_IS, is); 423 for (i = 0; i < AHCI_MAX_PORTS; i++) 424 if (is & (1 << i)) 425 ahci_intr_port(sc, &sc->sc_channels[i]); 426 } 427 return r; 428 } 429 430 void 431 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 432 { 433 uint32_t is, tfd; 434 struct ata_channel *chp = &achp->ata_channel; 435 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 436 int slot; 437 438 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 439 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 440 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 441 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 442 DEBUG_INTR); 443 444 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 445 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 446 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 447 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 448 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 449 return; 450 /* stop channel */ 451 ahci_channel_stop(sc, chp, 0); 452 if (slot != 0) { 453 printf("ahci_intr_port: slot %d\n", slot); 454 panic("ahci_intr_port"); 455 } 456 if (is & AHCI_P_IX_TFES) { 457 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 458 chp->ch_error = 459 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 460 chp->ch_status = (tfd & 0xff); 461 } else { 462 /* emulate a CRC error */ 463 chp->ch_error = WDCE_CRC; 464 chp->ch_status = WDCS_ERR; 465 } 466 xfer->c_intr(chp, xfer, is); 467 /* if channel has not been restarted, do it now */ 468 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 469 == 0) 470 ahci_channel_start(sc, chp); 471 } else { 472 slot = 0; /* XXX */ 473 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 474 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 475 chp->ch_channel, is, achp->ahcic_cmds_active, 476 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 477 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 478 return; 479 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 480 == 0) { 481 xfer->c_intr(chp, xfer, 0); 482 } 483 } 484 } 485 486 void 487 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 488 { 489 struct ata_channel *chp = drvp->chnl_softc; 490 ata_reset_channel(chp, flags); 491 return; 492 } 493 494 void 495 ahci_reset_channel(struct ata_channel *chp, int flags) 496 { 497 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 498 struct ahci_channel *achp = (struct ahci_channel *)chp; 499 int i, tfd; 500 501 ahci_channel_stop(sc, chp, flags); 502 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 503 achp->ahcic_sstatus) != SStatus_DET_DEV) { 504 printf("%s: port reset failed\n", AHCINAME(sc)); 505 /* XXX and then ? */ 506 } 507 if (chp->ch_queue->active_xfer) { 508 chp->ch_queue->active_xfer->c_kill_xfer(chp, 509 chp->ch_queue->active_xfer, KILL_RESET); 510 } 511 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 512 /* clear port interrupt register */ 513 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 514 /* clear SErrors and start operations */ 515 ahci_channel_start(sc, chp); 516 /* wait 31s for BSY to clear */ 517 for (i = 0; i <AHCI_RST_WAIT; i++) { 518 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 519 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 520 & WDCS_BSY) == 0) 521 break; 522 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 523 } 524 if (i == AHCI_RST_WAIT) 525 aprint_error("%s: BSY never cleared, TD 0x%x\n", 526 AHCINAME(sc), tfd); 527 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 528 DEBUG_PROBE); 529 /* clear port interrupt register */ 530 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 531 532 return; 533 } 534 535 int 536 ahci_ata_addref(struct ata_drive_datas *drvp) 537 { 538 return 0; 539 } 540 541 void 542 ahci_ata_delref(struct ata_drive_datas *drvp) 543 { 544 return; 545 } 546 547 void 548 ahci_killpending(struct ata_drive_datas *drvp) 549 { 550 return; 551 } 552 553 void 554 ahci_probe_drive(struct ata_channel *chp) 555 { 556 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 557 struct ahci_channel *achp = (struct ahci_channel *)chp; 558 int i, s; 559 uint32_t sig; 560 561 /* XXX This should be done by other code. */ 562 for (i = 0; i < chp->ch_ndrive; i++) { 563 chp->ch_drive[i].chnl_softc = chp; 564 chp->ch_drive[i].drive = i; 565 } 566 567 /* bring interface up, accept FISs, power up and spin up device */ 568 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 569 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 570 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 571 /* reset the PHY and bring online */ 572 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 573 achp->ahcic_sstatus)) { 574 case SStatus_DET_DEV: 575 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 576 /* clear port interrupt register */ 577 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 578 /* clear SErrors and start operations */ 579 ahci_channel_start(sc, chp); 580 /* wait 31s for BSY to clear */ 581 for (i = 0; i <AHCI_RST_WAIT; i++) { 582 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 583 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 584 & WDCS_BSY) == 0) 585 break; 586 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 587 } 588 if (i == AHCI_RST_WAIT) { 589 aprint_error("%s: BSY never cleared, TD 0x%x\n", 590 AHCINAME(sc), sig); 591 return; 592 } 593 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 594 DEBUG_PROBE); 595 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 596 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 597 AHCINAME(sc), chp->ch_channel, sig, 598 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 599 /* 600 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 601 * cases we get wrong values here, so ignore it. 602 */ 603 s = splbio(); 604 if ((sig & 0xffff0000) == 0xeb140000) { 605 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 606 } else 607 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 608 splx(s); 609 /* clear port interrupt register */ 610 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 611 /* and enable interrupts */ 612 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 613 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 614 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 615 AHCI_P_IX_DHRS); 616 /* wait 500ms before actually starting operations */ 617 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 618 break; 619 620 default: 621 break; 622 } 623 } 624 625 void 626 ahci_setup_channel(struct ata_channel *chp) 627 { 628 return; 629 } 630 631 int 632 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 633 { 634 struct ata_channel *chp = drvp->chnl_softc; 635 struct ata_xfer *xfer; 636 int ret; 637 int s; 638 639 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 640 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 641 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 642 DEBUG_XFERS); 643 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 644 ATAXF_NOSLEEP); 645 if (xfer == NULL) { 646 return ATACMD_TRY_AGAIN; 647 } 648 if (ata_c->flags & AT_POLL) 649 xfer->c_flags |= C_POLL; 650 if (ata_c->flags & AT_WAIT) 651 xfer->c_flags |= C_WAIT; 652 xfer->c_drive = drvp->drive; 653 xfer->c_databuf = ata_c->data; 654 xfer->c_bcount = ata_c->bcount; 655 xfer->c_cmd = ata_c; 656 xfer->c_start = ahci_cmd_start; 657 xfer->c_intr = ahci_cmd_complete; 658 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 659 s = splbio(); 660 ata_exec_xfer(chp, xfer); 661 #ifdef DIAGNOSTIC 662 if ((ata_c->flags & AT_POLL) != 0 && 663 (ata_c->flags & AT_DONE) == 0) 664 panic("ahci_exec_command: polled command not done"); 665 #endif 666 if (ata_c->flags & AT_DONE) { 667 ret = ATACMD_COMPLETE; 668 } else { 669 if (ata_c->flags & AT_WAIT) { 670 while ((ata_c->flags & AT_DONE) == 0) { 671 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 672 } 673 ret = ATACMD_COMPLETE; 674 } else { 675 ret = ATACMD_QUEUED; 676 } 677 } 678 splx(s); 679 return ret; 680 } 681 682 void 683 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 684 { 685 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 686 struct ahci_channel *achp = (struct ahci_channel *)chp; 687 struct ata_command *ata_c = xfer->c_cmd; 688 int slot = 0 /* XXX slot */; 689 struct ahci_cmd_tbl *cmd_tbl; 690 struct ahci_cmd_header *cmd_h; 691 int i; 692 int channel = chp->ch_channel; 693 694 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 695 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 696 697 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 698 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 699 cmd_tbl), DEBUG_XFERS); 700 701 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 702 703 cmd_h = &achp->ahcic_cmdh[slot]; 704 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 705 chp->ch_channel, cmd_h), DEBUG_XFERS); 706 if (ahci_dma_setup(chp, slot, 707 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 708 ata_c->bcount, 709 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 710 ata_c->flags |= AT_DF; 711 ahci_cmd_complete(chp, xfer, slot); 712 return; 713 } 714 cmd_h->cmdh_flags = htole16( 715 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 716 RHD_FISLEN / 4); 717 cmd_h->cmdh_prdbc = 0; 718 AHCI_CMDH_SYNC(sc, achp, slot, 719 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 720 721 if (ata_c->flags & AT_POLL) { 722 /* polled command, disable interrupts */ 723 AHCI_WRITE(sc, AHCI_GHC, 724 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 725 } 726 chp->ch_flags |= ATACH_IRQ_WAIT; 727 chp->ch_status = 0; 728 /* start command */ 729 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 730 /* and says we started this command */ 731 achp->ahcic_cmds_active |= 1 << slot; 732 733 if ((ata_c->flags & AT_POLL) == 0) { 734 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 735 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 736 ahci_timeout, chp); 737 return; 738 } 739 /* 740 * Polled command. 741 */ 742 for (i = 0; i < ata_c->timeout / 10; i++) { 743 if (ata_c->flags & AT_DONE) 744 break; 745 ahci_intr_port(sc, achp); 746 if (ata_c->flags & AT_WAIT) 747 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 748 else 749 delay(10000); 750 } 751 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 752 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 753 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 754 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 755 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 756 DEBUG_XFERS); 757 if ((ata_c->flags & AT_DONE) == 0) { 758 ata_c->flags |= AT_TIMEOU; 759 ahci_cmd_complete(chp, xfer, slot); 760 } 761 /* reenable interrupts */ 762 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 763 } 764 765 void 766 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 767 { 768 struct ata_command *ata_c = xfer->c_cmd; 769 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 770 DEBUG_FUNCS); 771 772 switch (reason) { 773 case KILL_GONE: 774 ata_c->flags |= AT_GONE; 775 break; 776 case KILL_RESET: 777 ata_c->flags |= AT_RESET; 778 break; 779 default: 780 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 781 panic("ahci_cmd_kill_xfer"); 782 } 783 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 784 } 785 786 int 787 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 788 { 789 int slot = 0; /* XXX slot */ 790 struct ata_command *ata_c = xfer->c_cmd; 791 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 792 struct ahci_channel *achp = (struct ahci_channel *)chp; 793 794 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 795 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 796 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 797 DEBUG_FUNCS); 798 chp->ch_flags &= ~ATACH_IRQ_WAIT; 799 if (xfer->c_flags & C_TIMEOU) { 800 ata_c->flags |= AT_TIMEOU; 801 } else 802 callout_stop(&chp->ch_callout); 803 804 chp->ch_queue->active_xfer = NULL; 805 806 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 807 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 808 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 809 wakeup(&chp->ch_queue->active_xfer); 810 return 0; 811 } 812 813 if (chp->ch_status & WDCS_BSY) { 814 ata_c->flags |= AT_TIMEOU; 815 } else if (chp->ch_status & WDCS_ERR) { 816 ata_c->r_error = chp->ch_error; 817 ata_c->flags |= AT_ERROR; 818 } 819 820 if (ata_c->flags & AT_READREG) 821 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 822 823 ahci_cmd_done(chp, xfer, slot); 824 return 0; 825 } 826 827 void 828 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 829 { 830 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 831 struct ahci_channel *achp = (struct ahci_channel *)chp; 832 struct ata_command *ata_c = xfer->c_cmd; 833 uint16_t *idwordbuf; 834 int i; 835 836 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 837 DEBUG_FUNCS); 838 839 /* this comamnd is not active any more */ 840 achp->ahcic_cmds_active &= ~(1 << slot); 841 842 if (ata_c->flags & (AT_READ|AT_WRITE)) { 843 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 844 achp->ahcic_datad[slot]->dm_mapsize, 845 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 846 BUS_DMASYNC_POSTWRITE); 847 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 848 } 849 850 AHCI_CMDH_SYNC(sc, achp, slot, 851 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 852 853 /* ata(4) expects IDENTIFY data to be in host endianess */ 854 if (ata_c->r_command == WDCC_IDENTIFY || 855 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 856 idwordbuf = xfer->c_databuf; 857 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 858 idwordbuf[i] = le16toh(idwordbuf[i]); 859 } 860 } 861 862 ata_c->flags |= AT_DONE; 863 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 864 ata_c->flags |= AT_XFDONE; 865 866 ata_free_xfer(chp, xfer); 867 if (ata_c->flags & AT_WAIT) 868 wakeup(ata_c); 869 else if (ata_c->callback) 870 ata_c->callback(ata_c->callback_arg); 871 atastart(chp); 872 return; 873 } 874 875 int 876 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 877 { 878 struct ata_channel *chp = drvp->chnl_softc; 879 struct ata_xfer *xfer; 880 881 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 882 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 883 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 884 DEBUG_XFERS); 885 xfer = ata_get_xfer(ATAXF_NOSLEEP); 886 if (xfer == NULL) { 887 return ATACMD_TRY_AGAIN; 888 } 889 if (ata_bio->flags & ATA_POLL) 890 xfer->c_flags |= C_POLL; 891 xfer->c_drive = drvp->drive; 892 xfer->c_cmd = ata_bio; 893 xfer->c_databuf = ata_bio->databuf; 894 xfer->c_bcount = ata_bio->bcount; 895 xfer->c_start = ahci_bio_start; 896 xfer->c_intr = ahci_bio_complete; 897 xfer->c_kill_xfer = ahci_bio_kill_xfer; 898 ata_exec_xfer(chp, xfer); 899 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 900 } 901 902 void 903 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 904 { 905 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 906 struct ahci_channel *achp = (struct ahci_channel *)chp; 907 struct ata_bio *ata_bio = xfer->c_cmd; 908 int slot = 0 /* XXX slot */; 909 struct ahci_cmd_tbl *cmd_tbl; 910 struct ahci_cmd_header *cmd_h; 911 int i; 912 int channel = chp->ch_channel; 913 914 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 915 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 916 917 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 918 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 919 cmd_tbl), DEBUG_XFERS); 920 921 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 922 923 cmd_h = &achp->ahcic_cmdh[slot]; 924 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 925 chp->ch_channel, cmd_h), DEBUG_XFERS); 926 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 927 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 928 ata_bio->error = ERR_DMA; 929 ata_bio->r_error = 0; 930 ahci_bio_complete(chp, xfer, slot); 931 return; 932 } 933 cmd_h->cmdh_flags = htole16( 934 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 935 RHD_FISLEN / 4); 936 cmd_h->cmdh_prdbc = 0; 937 AHCI_CMDH_SYNC(sc, achp, slot, 938 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 939 940 if (xfer->c_flags & C_POLL) { 941 /* polled command, disable interrupts */ 942 AHCI_WRITE(sc, AHCI_GHC, 943 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 944 } 945 chp->ch_flags |= ATACH_IRQ_WAIT; 946 chp->ch_status = 0; 947 /* start command */ 948 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 949 /* and says we started this command */ 950 achp->ahcic_cmds_active |= 1 << slot; 951 952 if ((xfer->c_flags & C_POLL) == 0) { 953 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 954 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 955 ahci_timeout, chp); 956 return; 957 } 958 /* 959 * Polled command. 960 */ 961 for (i = 0; i < ATA_DELAY / 10; i++) { 962 if (ata_bio->flags & ATA_ITSDONE) 963 break; 964 ahci_intr_port(sc, achp); 965 if (ata_bio->flags & ATA_NOSLEEP) 966 delay(10000); 967 else 968 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 969 } 970 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 971 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 972 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 973 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 974 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 975 DEBUG_XFERS); 976 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 977 ata_bio->error = TIMEOUT; 978 ahci_bio_complete(chp, xfer, slot); 979 } 980 /* reenable interrupts */ 981 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 982 } 983 984 void 985 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 986 { 987 int slot = 0; /* XXX slot */ 988 int drive = xfer->c_drive; 989 struct ata_bio *ata_bio = xfer->c_cmd; 990 struct ahci_channel *achp = (struct ahci_channel *)chp; 991 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 992 DEBUG_FUNCS); 993 994 achp->ahcic_cmds_active &= ~(1 << slot); 995 ata_free_xfer(chp, xfer); 996 ata_bio->flags |= ATA_ITSDONE; 997 switch (reason) { 998 case KILL_GONE: 999 ata_bio->error = ERR_NODEV; 1000 break; 1001 case KILL_RESET: 1002 ata_bio->error = ERR_RESET; 1003 break; 1004 default: 1005 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1006 panic("ahci_bio_kill_xfer"); 1007 } 1008 ata_bio->r_error = WDCE_ABRT; 1009 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1010 } 1011 1012 int 1013 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1014 { 1015 int slot = 0; /* XXX slot */ 1016 struct ata_bio *ata_bio = xfer->c_cmd; 1017 int drive = xfer->c_drive; 1018 struct ahci_channel *achp = (struct ahci_channel *)chp; 1019 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1020 1021 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1022 DEBUG_FUNCS); 1023 1024 achp->ahcic_cmds_active &= ~(1 << slot); 1025 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1026 if (xfer->c_flags & C_TIMEOU) { 1027 ata_bio->error = TIMEOUT; 1028 } else { 1029 callout_stop(&chp->ch_callout); 1030 ata_bio->error = NOERROR; 1031 } 1032 1033 chp->ch_queue->active_xfer = NULL; 1034 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1035 achp->ahcic_datad[slot]->dm_mapsize, 1036 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1037 BUS_DMASYNC_POSTWRITE); 1038 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1039 1040 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1041 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1042 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1043 wakeup(&chp->ch_queue->active_xfer); 1044 return 0; 1045 } 1046 ata_free_xfer(chp, xfer); 1047 ata_bio->flags |= ATA_ITSDONE; 1048 if (chp->ch_status & WDCS_DWF) { 1049 ata_bio->error = ERR_DF; 1050 } else if (chp->ch_status & WDCS_ERR) { 1051 ata_bio->error = ERROR; 1052 ata_bio->r_error = chp->ch_error; 1053 } else if (chp->ch_status & WDCS_CORR) 1054 ata_bio->flags |= ATA_CORR; 1055 1056 AHCI_CMDH_SYNC(sc, achp, slot, 1057 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1058 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1059 ata_bio->bcount), DEBUG_XFERS); 1060 /* 1061 * if it was a write, complete data buffer may have been transfered 1062 * before error detection; in this case don't use cmdh_prdbc 1063 * as it won't reflect what was written to media. Assume nothing 1064 * was transfered and leave bcount as-is. 1065 */ 1066 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1067 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1068 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1069 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1070 atastart(chp); 1071 return 0; 1072 } 1073 1074 void 1075 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1076 { 1077 int i; 1078 /* stop channel */ 1079 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1080 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1081 /* wait 1s for channel to stop */ 1082 for (i = 0; i <100; i++) { 1083 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1084 == 0) 1085 break; 1086 if (flags & AT_WAIT) 1087 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1088 else 1089 delay(10000); 1090 } 1091 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1092 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1093 /* XXX controller reset ? */ 1094 return; 1095 } 1096 } 1097 1098 void 1099 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1100 { 1101 /* clear error */ 1102 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1103 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1104 1105 /* and start controller */ 1106 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1107 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1108 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1109 } 1110 1111 void 1112 ahci_timeout(void *v) 1113 { 1114 struct ata_channel *chp = (struct ata_channel *)v; 1115 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1116 int s = splbio(); 1117 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1118 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1119 xfer->c_flags |= C_TIMEOU; 1120 xfer->c_intr(chp, xfer, 0); 1121 } 1122 splx(s); 1123 } 1124 1125 int 1126 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1127 size_t count, int op) 1128 { 1129 int error, seg; 1130 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1131 struct ahci_channel *achp = (struct ahci_channel *)chp; 1132 struct ahci_cmd_tbl *cmd_tbl; 1133 struct ahci_cmd_header *cmd_h; 1134 1135 cmd_h = &achp->ahcic_cmdh[slot]; 1136 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1137 1138 if (data == NULL) { 1139 cmd_h->cmdh_prdtl = 0; 1140 goto end; 1141 } 1142 1143 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1144 data, count, NULL, 1145 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1146 if (error) { 1147 printf("%s port %d: failed to load xfer: %d\n", 1148 AHCINAME(sc), chp->ch_channel, error); 1149 return error; 1150 } 1151 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1152 achp->ahcic_datad[slot]->dm_mapsize, 1153 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1154 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1155 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1156 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1157 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1158 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1159 } 1160 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1161 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1162 end: 1163 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1164 return 0; 1165 } 1166 1167 #if NATAPIBUS > 0 1168 void 1169 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1170 { 1171 struct ata_channel *chp = ata_sc->sc_chan; 1172 struct atac_softc *atac = chp->ch_atac; 1173 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1174 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1175 /* 1176 * Fill in the scsipi_adapter. 1177 */ 1178 adapt->adapt_dev = atac->atac_dev; 1179 adapt->adapt_nchannels = atac->atac_nchannels; 1180 adapt->adapt_request = ahci_atapi_scsipi_request; 1181 adapt->adapt_minphys = ahci_atapi_minphys; 1182 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1183 1184 /* 1185 * Fill in the scsipi_channel. 1186 */ 1187 memset(chan, 0, sizeof(*chan)); 1188 chan->chan_adapter = adapt; 1189 chan->chan_bustype = &ahci_atapi_bustype; 1190 chan->chan_channel = chp->ch_channel; 1191 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1192 chan->chan_openings = 1; 1193 chan->chan_max_periph = 1; 1194 chan->chan_ntargets = 1; 1195 chan->chan_nluns = 1; 1196 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1197 atapiprint); 1198 } 1199 1200 void 1201 ahci_atapi_minphys(struct buf *bp) 1202 { 1203 if (bp->b_bcount > MAXPHYS) 1204 bp->b_bcount = MAXPHYS; 1205 minphys(bp); 1206 } 1207 1208 /* 1209 * Kill off all pending xfers for a periph. 1210 * 1211 * Must be called at splbio(). 1212 */ 1213 void 1214 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1215 { 1216 struct atac_softc *atac = 1217 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1218 struct ata_channel *chp = 1219 atac->atac_channels[periph->periph_channel->chan_channel]; 1220 1221 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1222 } 1223 1224 void 1225 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1226 scsipi_adapter_req_t req, void *arg) 1227 { 1228 struct scsipi_adapter *adapt = chan->chan_adapter; 1229 struct scsipi_periph *periph; 1230 struct scsipi_xfer *sc_xfer; 1231 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1232 struct atac_softc *atac = &sc->sc_atac; 1233 struct ata_xfer *xfer; 1234 int channel = chan->chan_channel; 1235 int drive, s; 1236 1237 switch (req) { 1238 case ADAPTER_REQ_RUN_XFER: 1239 sc_xfer = arg; 1240 periph = sc_xfer->xs_periph; 1241 drive = periph->periph_target; 1242 if (!device_is_active(atac->atac_dev)) { 1243 sc_xfer->error = XS_DRIVER_STUFFUP; 1244 scsipi_done(sc_xfer); 1245 return; 1246 } 1247 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1248 if (xfer == NULL) { 1249 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1250 scsipi_done(sc_xfer); 1251 return; 1252 } 1253 1254 if (sc_xfer->xs_control & XS_CTL_POLL) 1255 xfer->c_flags |= C_POLL; 1256 xfer->c_drive = drive; 1257 xfer->c_flags |= C_ATAPI; 1258 xfer->c_cmd = sc_xfer; 1259 xfer->c_databuf = sc_xfer->data; 1260 xfer->c_bcount = sc_xfer->datalen; 1261 xfer->c_start = ahci_atapi_start; 1262 xfer->c_intr = ahci_atapi_complete; 1263 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1264 xfer->c_dscpoll = 0; 1265 s = splbio(); 1266 ata_exec_xfer(atac->atac_channels[channel], xfer); 1267 #ifdef DIAGNOSTIC 1268 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1269 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1270 panic("ahci_atapi_scsipi_request: polled command " 1271 "not done"); 1272 #endif 1273 splx(s); 1274 return; 1275 default: 1276 /* Not supported, nothing to do. */ 1277 ; 1278 } 1279 } 1280 1281 void 1282 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1283 { 1284 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1285 struct ahci_channel *achp = (struct ahci_channel *)chp; 1286 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1287 int slot = 0 /* XXX slot */; 1288 struct ahci_cmd_tbl *cmd_tbl; 1289 struct ahci_cmd_header *cmd_h; 1290 int i; 1291 int channel = chp->ch_channel; 1292 1293 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1294 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1295 1296 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1297 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1298 cmd_tbl), DEBUG_XFERS); 1299 1300 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1301 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1302 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1303 1304 cmd_h = &achp->ahcic_cmdh[slot]; 1305 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1306 chp->ch_channel, cmd_h), DEBUG_XFERS); 1307 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1308 sc_xfer->datalen, 1309 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1310 BUS_DMA_READ : BUS_DMA_WRITE)) { 1311 sc_xfer->error = XS_DRIVER_STUFFUP; 1312 ahci_atapi_complete(chp, xfer, slot); 1313 return; 1314 } 1315 cmd_h->cmdh_flags = htole16( 1316 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1317 RHD_FISLEN / 4 | AHCI_CMDH_F_A); 1318 cmd_h->cmdh_prdbc = 0; 1319 AHCI_CMDH_SYNC(sc, achp, slot, 1320 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1321 1322 if (xfer->c_flags & C_POLL) { 1323 /* polled command, disable interrupts */ 1324 AHCI_WRITE(sc, AHCI_GHC, 1325 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1326 } 1327 chp->ch_flags |= ATACH_IRQ_WAIT; 1328 chp->ch_status = 0; 1329 /* start command */ 1330 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1331 /* and says we started this command */ 1332 achp->ahcic_cmds_active |= 1 << slot; 1333 1334 if ((xfer->c_flags & C_POLL) == 0) { 1335 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1336 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1337 ahci_timeout, chp); 1338 return; 1339 } 1340 /* 1341 * Polled command. 1342 */ 1343 for (i = 0; i < ATA_DELAY / 10; i++) { 1344 if (sc_xfer->xs_status & XS_STS_DONE) 1345 break; 1346 ahci_intr_port(sc, achp); 1347 delay(10000); 1348 } 1349 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1350 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1351 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1352 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1353 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1354 DEBUG_XFERS); 1355 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1356 sc_xfer->error = XS_TIMEOUT; 1357 ahci_atapi_complete(chp, xfer, slot); 1358 } 1359 /* reenable interrupts */ 1360 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1361 } 1362 1363 int 1364 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1365 { 1366 int slot = 0; /* XXX slot */ 1367 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1368 int drive = xfer->c_drive; 1369 struct ahci_channel *achp = (struct ahci_channel *)chp; 1370 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1371 1372 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1373 DEBUG_FUNCS); 1374 1375 achp->ahcic_cmds_active &= ~(1 << slot); 1376 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1377 if (xfer->c_flags & C_TIMEOU) { 1378 sc_xfer->error = XS_TIMEOUT; 1379 } else { 1380 callout_stop(&chp->ch_callout); 1381 sc_xfer->error = 0; 1382 } 1383 1384 chp->ch_queue->active_xfer = NULL; 1385 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1386 achp->ahcic_datad[slot]->dm_mapsize, 1387 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1388 BUS_DMASYNC_POSTWRITE); 1389 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1390 1391 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1392 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1393 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1394 wakeup(&chp->ch_queue->active_xfer); 1395 return 0; 1396 } 1397 ata_free_xfer(chp, xfer); 1398 1399 AHCI_CMDH_SYNC(sc, achp, slot, 1400 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1401 sc_xfer->resid = sc_xfer->datalen; 1402 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1403 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1404 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1405 if (chp->ch_status & WDCS_ERR && 1406 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1407 sc_xfer->resid == sc_xfer->datalen)) { 1408 sc_xfer->error = XS_SHORTSENSE; 1409 sc_xfer->sense.atapi_sense = chp->ch_error; 1410 if ((sc_xfer->xs_periph->periph_quirks & 1411 PQUIRK_NOSENSE) == 0) { 1412 /* ask scsipi to send a REQUEST_SENSE */ 1413 sc_xfer->error = XS_BUSY; 1414 sc_xfer->status = SCSI_CHECK; 1415 } 1416 } 1417 scsipi_done(sc_xfer); 1418 atastart(chp); 1419 return 0; 1420 } 1421 1422 void 1423 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1424 { 1425 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1426 struct ahci_channel *achp = (struct ahci_channel *)chp; 1427 int slot = 0; /* XXX slot */ 1428 1429 achp->ahcic_cmds_active &= ~(1 << slot); 1430 1431 /* remove this command from xfer queue */ 1432 switch (reason) { 1433 case KILL_GONE: 1434 sc_xfer->error = XS_DRIVER_STUFFUP; 1435 break; 1436 case KILL_RESET: 1437 sc_xfer->error = XS_RESET; 1438 break; 1439 default: 1440 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1441 panic("ahci_ata_atapi_kill_xfer"); 1442 } 1443 ata_free_xfer(chp, xfer); 1444 scsipi_done(sc_xfer); 1445 } 1446 1447 void 1448 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1449 { 1450 struct scsipi_channel *chan = sc->sc_channel; 1451 struct scsipi_periph *periph; 1452 struct ataparams ids; 1453 struct ataparams *id = &ids; 1454 struct ahci_softc *ahcic = 1455 device_private(chan->chan_adapter->adapt_dev); 1456 struct atac_softc *atac = &ahcic->sc_atac; 1457 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1458 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1459 struct scsipibus_attach_args sa; 1460 char serial_number[21], model[41], firmware_revision[9]; 1461 int s; 1462 1463 /* skip if already attached */ 1464 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1465 return; 1466 1467 /* if no ATAPI device detected at attach time, skip */ 1468 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1469 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1470 "not present\n", target), DEBUG_PROBE); 1471 return; 1472 } 1473 1474 /* Some ATAPI devices need a bit more time after software reset. */ 1475 delay(5000); 1476 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1477 #ifdef ATAPI_DEBUG_PROBE 1478 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1479 AHCINAME(ahcic), target, 1480 id->atap_config & ATAPI_CFG_CMD_MASK, 1481 id->atap_config & ATAPI_CFG_DRQ_MASK); 1482 #endif 1483 periph = scsipi_alloc_periph(M_NOWAIT); 1484 if (periph == NULL) { 1485 aprint_error_dev(sc->sc_dev, 1486 "unable to allocate periph for drive %d\n", 1487 target); 1488 return; 1489 } 1490 periph->periph_dev = NULL; 1491 periph->periph_channel = chan; 1492 periph->periph_switch = &atapi_probe_periphsw; 1493 periph->periph_target = target; 1494 periph->periph_lun = 0; 1495 periph->periph_quirks = PQUIRK_ONLYBIG; 1496 1497 #ifdef SCSIPI_DEBUG 1498 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1499 SCSIPI_DEBUG_TARGET == target) 1500 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1501 #endif 1502 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1503 if (id->atap_config & ATAPI_CFG_REMOV) 1504 periph->periph_flags |= PERIPH_REMOVABLE; 1505 if (periph->periph_type == T_SEQUENTIAL) { 1506 s = splbio(); 1507 drvp->drive_flags |= DRIVE_ATAPIST; 1508 splx(s); 1509 } 1510 1511 sa.sa_periph = periph; 1512 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1513 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1514 T_REMOV : T_FIXED; 1515 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1516 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1517 20); 1518 scsipi_strvis((u_char *)firmware_revision, 8, 1519 id->atap_revision, 8); 1520 sa.sa_inqbuf.vendor = model; 1521 sa.sa_inqbuf.product = serial_number; 1522 sa.sa_inqbuf.revision = firmware_revision; 1523 1524 /* 1525 * Determine the operating mode capabilities of the device. 1526 */ 1527 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1528 periph->periph_cap |= PERIPH_CAP_CMD16; 1529 /* XXX This is gross. */ 1530 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1531 1532 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1533 1534 if (drvp->drv_softc) 1535 ata_probe_caps(drvp); 1536 else { 1537 s = splbio(); 1538 drvp->drive_flags &= ~DRIVE_ATAPI; 1539 splx(s); 1540 } 1541 } else { 1542 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1543 "failed for drive %s:%d:%d: error 0x%x\n", 1544 AHCINAME(ahcic), chp->ch_channel, target, 1545 chp->ch_error), DEBUG_PROBE); 1546 s = splbio(); 1547 drvp->drive_flags &= ~DRIVE_ATAPI; 1548 splx(s); 1549 } 1550 } 1551 #endif /* NATAPIBUS */ 1552
Indexes created Sat Sep 27 22:09:54 GMT 2025