ahcisata_core.c revision 1.32
1 /* $NetBSD: ahcisata_core.c,v 1.32 2011/08/20 16:03:48 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.32 2011/08/20 16:03:48 jakllsch Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ic/ahcisatavar.h> 46 47 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 48 49 #include "atapibus.h" 50 51 #ifdef AHCI_DEBUG 52 int ahcidebug_mask = 0x0; 53 #endif 54 55 static void ahci_probe_drive(struct ata_channel *); 56 static void ahci_setup_channel(struct ata_channel *); 57 58 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 59 static void ahci_reset_drive(struct ata_drive_datas *, int); 60 static void ahci_reset_channel(struct ata_channel *, int); 61 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 62 static int ahci_ata_addref(struct ata_drive_datas *); 63 static void ahci_ata_delref(struct ata_drive_datas *); 64 static void ahci_killpending(struct ata_drive_datas *); 65 66 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 67 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 68 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 69 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 70 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 74 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 75 static void ahci_timeout(void *); 76 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 77 78 #if NATAPIBUS > 0 79 static void ahci_atapibus_attach(struct atabus_softc *); 80 static void ahci_atapi_kill_pending(struct scsipi_periph *); 81 static void ahci_atapi_minphys(struct buf *); 82 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 83 scsipi_adapter_req_t, void *); 84 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 85 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 86 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 87 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 88 89 static const struct scsipi_bustype ahci_atapi_bustype = { 90 SCSIPI_BUSTYPE_ATAPI, 91 atapi_scsipi_cmd, 92 atapi_interpret_sense, 93 atapi_print_addr, 94 ahci_atapi_kill_pending, 95 }; 96 #endif /* NATAPIBUS */ 97 98 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 99 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 100 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 101 102 const struct ata_bustype ahci_ata_bustype = { 103 SCSIPI_BUSTYPE_ATA, 104 ahci_ata_bio, 105 ahci_reset_drive, 106 ahci_reset_channel, 107 ahci_exec_command, 108 ata_get_params, 109 ahci_ata_addref, 110 ahci_ata_delref, 111 ahci_killpending 112 }; 113 114 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 115 static void ahci_setup_port(struct ahci_softc *sc, int i); 116 117 static int 118 ahci_reset(struct ahci_softc *sc) 119 { 120 int i; 121 122 /* reset controller */ 123 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 124 /* wait up to 1s for reset to complete */ 125 for (i = 0; i < 1000; i++) { 126 delay(1000); 127 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 128 break; 129 } 130 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 131 aprint_error("%s: reset failed\n", AHCINAME(sc)); 132 return -1; 133 } 134 /* enable ahci mode */ 135 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 136 return 0; 137 } 138 139 static void 140 ahci_setup_ports(struct ahci_softc *sc) 141 { 142 uint32_t ahci_ports; 143 int i, port; 144 145 ahci_ports = AHCI_READ(sc, AHCI_PI); 146 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 147 if ((ahci_ports & (1 << i)) == 0) 148 continue; 149 if (port >= sc->sc_atac.atac_nchannels) { 150 aprint_error("%s: more ports than announced\n", 151 AHCINAME(sc)); 152 break; 153 } 154 ahci_setup_port(sc, i); 155 } 156 } 157 158 static void 159 ahci_reprobe_drives(struct ahci_softc *sc) 160 { 161 uint32_t ahci_ports; 162 int i, port; 163 struct ahci_channel *achp; 164 struct ata_channel *chp; 165 166 ahci_ports = AHCI_READ(sc, AHCI_PI); 167 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 168 if ((ahci_ports & (1 << i)) == 0) 169 continue; 170 if (port >= sc->sc_atac.atac_nchannels) { 171 aprint_error("%s: more ports than announced\n", 172 AHCINAME(sc)); 173 break; 174 } 175 achp = &sc->sc_channels[i]; 176 chp = &achp->ata_channel; 177 178 ahci_probe_drive(chp); 179 } 180 } 181 182 static void 183 ahci_setup_port(struct ahci_softc *sc, int i) 184 { 185 struct ahci_channel *achp; 186 187 achp = &sc->sc_channels[i]; 188 189 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 190 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 191 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 192 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 193 } 194 195 static void 196 ahci_enable_intrs(struct ahci_softc *sc) 197 { 198 199 /* clear interrupts */ 200 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 201 /* enable interrupts */ 202 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 203 } 204 205 void 206 ahci_attach(struct ahci_softc *sc) 207 { 208 uint32_t ahci_cap, ahci_rev, ahci_ports; 209 int i, j, port; 210 struct ahci_channel *achp; 211 struct ata_channel *chp; 212 int error; 213 int dmasize; 214 char buf[128]; 215 void *cmdhp; 216 void *cmdtblp; 217 218 if (ahci_reset(sc) != 0) 219 return; 220 221 ahci_cap = AHCI_READ(sc, AHCI_CAP); 222 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 223 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 224 ahci_rev = AHCI_READ(sc, AHCI_VS); 225 snprintb(buf, sizeof(buf), "\177\020" 226 /* "f\000\005NP\0" */ 227 "b\005SXS\0" 228 "b\006EMS\0" 229 "b\007CCCS\0" 230 /* "f\010\005NCS\0" */ 231 "b\015PSC\0" 232 "b\016SSC\0" 233 "b\017PMD\0" 234 "b\020FBSS\0" 235 "b\021SPM\0" 236 "b\022SAM\0" 237 "b\023SNZO\0" 238 "f\024\003ISS\0" 239 "=\001Gen1\0" 240 "=\002Gen2\0" 241 "=\003Gen3\0" 242 "b\030SCLO\0" 243 "b\031SAL\0" 244 "b\032SALP\0" 245 "b\033SSS\0" 246 "b\034SMPS\0" 247 "b\035SSNTF\0" 248 "b\036SNCQ\0" 249 "b\037S64A\0" 250 "\0", ahci_cap); 251 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 252 ", %d ports, %d slots, CAP %s\n", 253 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 254 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 255 256 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 257 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 258 sc->sc_atac.atac_pio_cap = 4; 259 sc->sc_atac.atac_dma_cap = 2; 260 sc->sc_atac.atac_udma_cap = 6; 261 sc->sc_atac.atac_channels = sc->sc_chanarray; 262 sc->sc_atac.atac_probe = ahci_probe_drive; 263 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 264 sc->sc_atac.atac_set_modes = ahci_setup_channel; 265 #if NATAPIBUS > 0 266 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 267 #endif 268 269 dmasize = 270 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 271 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 272 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 273 if (error) { 274 aprint_error("%s: unable to allocate command header memory" 275 ", error=%d\n", AHCINAME(sc), error); 276 return; 277 } 278 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 279 sc->sc_cmd_hdr_nseg, dmasize, 280 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 281 if (error) { 282 aprint_error("%s: unable to map command header memory" 283 ", error=%d\n", AHCINAME(sc), error); 284 return; 285 } 286 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 287 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 288 if (error) { 289 aprint_error("%s: unable to create command header map" 290 ", error=%d\n", AHCINAME(sc), error); 291 return; 292 } 293 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 294 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 295 if (error) { 296 aprint_error("%s: unable to load command header map" 297 ", error=%d\n", AHCINAME(sc), error); 298 return; 299 } 300 sc->sc_cmd_hdr = cmdhp; 301 302 ahci_enable_intrs(sc); 303 304 ahci_ports = AHCI_READ(sc, AHCI_PI); 305 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 306 if ((ahci_ports & (1 << i)) == 0) 307 continue; 308 if (port >= sc->sc_atac.atac_nchannels) { 309 aprint_error("%s: more ports than announced\n", 310 AHCINAME(sc)); 311 break; 312 } 313 achp = &sc->sc_channels[i]; 314 chp = &achp->ata_channel; 315 sc->sc_chanarray[i] = chp; 316 chp->ch_channel = i; 317 chp->ch_atac = &sc->sc_atac; 318 chp->ch_queue = malloc(sizeof(struct ata_queue), 319 M_DEVBUF, M_NOWAIT); 320 if (chp->ch_queue == NULL) { 321 aprint_error("%s port %d: can't allocate memory for " 322 "command queue", AHCINAME(sc), i); 323 break; 324 } 325 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 326 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 327 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 328 BUS_DMA_NOWAIT); 329 if (error) { 330 aprint_error("%s: unable to allocate command table " 331 "memory, error=%d\n", AHCINAME(sc), error); 332 break; 333 } 334 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 335 achp->ahcic_cmd_tbl_nseg, dmasize, 336 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 337 if (error) { 338 aprint_error("%s: unable to map command table memory" 339 ", error=%d\n", AHCINAME(sc), error); 340 break; 341 } 342 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 343 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 344 if (error) { 345 aprint_error("%s: unable to create command table map" 346 ", error=%d\n", AHCINAME(sc), error); 347 break; 348 } 349 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 350 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 351 if (error) { 352 aprint_error("%s: unable to load command table map" 353 ", error=%d\n", AHCINAME(sc), error); 354 break; 355 } 356 achp->ahcic_cmdh = (struct ahci_cmd_header *) 357 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 358 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 359 AHCI_CMDH_SIZE * port; 360 achp->ahcic_rfis = (struct ahci_r_fis *) 361 ((char *)cmdhp + 362 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 363 AHCI_RFIS_SIZE * port); 364 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 365 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 366 AHCI_RFIS_SIZE * port; 367 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 368 "rfis %p (0x%" PRIx64 ")\n", i, 369 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 370 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 371 DEBUG_PROBE); 372 373 for (j = 0; j < sc->sc_ncmds; j++) { 374 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 375 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 376 achp->ahcic_bus_cmd_tbl[j] = 377 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 378 AHCI_CMDTBL_SIZE * j; 379 achp->ahcic_cmdh[j].cmdh_cmdtba = 380 htole64(achp->ahcic_bus_cmd_tbl[j]); 381 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 382 achp->ahcic_cmd_tbl[j], 383 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 384 /* The xfer DMA map */ 385 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 386 AHCI_NPRD, 0x400000 /* 4MB */, 0, 387 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 388 &achp->ahcic_datad[j]); 389 if (error) { 390 aprint_error("%s: couldn't alloc xfer DMA map, " 391 "error=%d\n", AHCINAME(sc), error); 392 goto end; 393 } 394 } 395 ahci_setup_port(sc, i); 396 chp->ch_ndrive = 1; 397 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 398 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 399 aprint_error("%s: couldn't map channel %d " 400 "sata_status regs\n", AHCINAME(sc), i); 401 break; 402 } 403 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 404 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 405 aprint_error("%s: couldn't map channel %d " 406 "sata_control regs\n", AHCINAME(sc), i); 407 break; 408 } 409 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 410 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 411 aprint_error("%s: couldn't map channel %d " 412 "sata_error regs\n", AHCINAME(sc), i); 413 break; 414 } 415 ata_channel_attach(chp); 416 port++; 417 end: 418 continue; 419 } 420 } 421 422 int 423 ahci_detach(struct ahci_softc *sc, int flags) 424 { 425 struct atac_softc *atac; 426 struct ahci_channel *achp; 427 struct ata_channel *chp; 428 struct scsipi_adapter *adapt; 429 uint32_t ahci_ports; 430 int i, j; 431 int error; 432 433 atac = &sc->sc_atac; 434 adapt = &atac->atac_atapi_adapter._generic; 435 436 ahci_ports = AHCI_READ(sc, AHCI_PI); 437 for (i = 0; i < AHCI_MAX_PORTS; i++) { 438 achp = &sc->sc_channels[i]; 439 chp = &achp->ata_channel; 440 441 if ((ahci_ports & (1 << i)) == 0) 442 continue; 443 if (i >= sc->sc_atac.atac_nchannels) { 444 aprint_error("%s: more ports than announced\n", 445 AHCINAME(sc)); 446 break; 447 } 448 449 if (chp->atabus == NULL) 450 continue; 451 if ((error = config_detach(chp->atabus, flags)) != 0) 452 return error; 453 454 for (j = 0; j < sc->sc_ncmds; j++) 455 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 456 457 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 458 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 459 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 460 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 461 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 462 achp->ahcic_cmd_tbl_nseg); 463 464 free(chp->ch_queue, M_DEVBUF); 465 chp->atabus = NULL; 466 } 467 468 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 469 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 470 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 471 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 472 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 473 474 if (adapt->adapt_refcnt != 0) 475 return EBUSY; 476 477 return 0; 478 } 479 480 void 481 ahci_resume(struct ahci_softc *sc) 482 { 483 ahci_reset(sc); 484 ahci_setup_ports(sc); 485 ahci_reprobe_drives(sc); 486 ahci_enable_intrs(sc); 487 } 488 489 int 490 ahci_intr(void *v) 491 { 492 struct ahci_softc *sc = v; 493 uint32_t is; 494 int i, r = 0; 495 496 while ((is = AHCI_READ(sc, AHCI_IS))) { 497 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 498 DEBUG_INTR); 499 r = 1; 500 AHCI_WRITE(sc, AHCI_IS, is); 501 for (i = 0; i < AHCI_MAX_PORTS; i++) 502 if (is & (1 << i)) 503 ahci_intr_port(sc, &sc->sc_channels[i]); 504 } 505 return r; 506 } 507 508 static void 509 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 510 { 511 uint32_t is, tfd; 512 struct ata_channel *chp = &achp->ata_channel; 513 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 514 int slot; 515 516 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 517 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 518 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 519 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 520 DEBUG_INTR); 521 522 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 523 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 524 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 525 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 526 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 527 return; 528 /* stop channel */ 529 ahci_channel_stop(sc, chp, 0); 530 if (slot != 0) { 531 printf("ahci_intr_port: slot %d\n", slot); 532 panic("ahci_intr_port"); 533 } 534 if (is & AHCI_P_IX_TFES) { 535 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 536 chp->ch_error = 537 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 538 chp->ch_status = (tfd & 0xff); 539 } else { 540 /* emulate a CRC error */ 541 chp->ch_error = WDCE_CRC; 542 chp->ch_status = WDCS_ERR; 543 } 544 xfer->c_intr(chp, xfer, is); 545 /* if channel has not been restarted, do it now */ 546 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 547 == 0) 548 ahci_channel_start(sc, chp); 549 } else { 550 slot = 0; /* XXX */ 551 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 552 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 553 chp->ch_channel, is, achp->ahcic_cmds_active, 554 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 555 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 556 return; 557 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 558 == 0) { 559 xfer->c_intr(chp, xfer, 0); 560 } 561 } 562 } 563 564 static void 565 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 566 { 567 struct ata_channel *chp = drvp->chnl_softc; 568 ata_reset_channel(chp, flags); 569 return; 570 } 571 572 static void 573 ahci_reset_channel(struct ata_channel *chp, int flags) 574 { 575 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 576 struct ahci_channel *achp = (struct ahci_channel *)chp; 577 int i, tfd; 578 579 ahci_channel_stop(sc, chp, flags); 580 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 581 achp->ahcic_sstatus) != SStatus_DET_DEV) { 582 printf("%s: port reset failed\n", AHCINAME(sc)); 583 /* XXX and then ? */ 584 } 585 if (chp->ch_queue->active_xfer) { 586 chp->ch_queue->active_xfer->c_kill_xfer(chp, 587 chp->ch_queue->active_xfer, KILL_RESET); 588 } 589 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 590 /* clear port interrupt register */ 591 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 592 /* clear SErrors and start operations */ 593 ahci_channel_start(sc, chp); 594 /* wait 31s for BSY to clear */ 595 for (i = 0; i <AHCI_RST_WAIT; i++) { 596 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 597 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 598 & WDCS_BSY) == 0) 599 break; 600 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 601 } 602 if (i == AHCI_RST_WAIT) 603 aprint_error("%s: BSY never cleared, TD 0x%x\n", 604 AHCINAME(sc), tfd); 605 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 606 DEBUG_PROBE); 607 /* clear port interrupt register */ 608 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 609 610 return; 611 } 612 613 static int 614 ahci_ata_addref(struct ata_drive_datas *drvp) 615 { 616 return 0; 617 } 618 619 static void 620 ahci_ata_delref(struct ata_drive_datas *drvp) 621 { 622 return; 623 } 624 625 static void 626 ahci_killpending(struct ata_drive_datas *drvp) 627 { 628 return; 629 } 630 631 static void 632 ahci_probe_drive(struct ata_channel *chp) 633 { 634 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 635 struct ahci_channel *achp = (struct ahci_channel *)chp; 636 int i, s; 637 uint32_t sig; 638 639 /* XXX This should be done by other code. */ 640 for (i = 0; i < chp->ch_ndrive; i++) { 641 chp->ch_drive[i].chnl_softc = chp; 642 chp->ch_drive[i].drive = i; 643 } 644 645 /* bring interface up, accept FISs, power up and spin up device */ 646 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 647 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 648 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 649 /* reset the PHY and bring online */ 650 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 651 achp->ahcic_sstatus)) { 652 case SStatus_DET_DEV: 653 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 654 /* clear port interrupt register */ 655 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 656 /* clear SErrors and start operations */ 657 ahci_channel_start(sc, chp); 658 /* wait 31s for BSY to clear */ 659 for (i = 0; i <AHCI_RST_WAIT; i++) { 660 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 661 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 662 & WDCS_BSY) == 0) 663 break; 664 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 665 } 666 if (i == AHCI_RST_WAIT) { 667 aprint_error("%s: BSY never cleared, TD 0x%x\n", 668 AHCINAME(sc), sig); 669 return; 670 } 671 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 672 DEBUG_PROBE); 673 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 674 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 675 AHCINAME(sc), chp->ch_channel, sig, 676 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 677 /* 678 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 679 * cases we get wrong values here, so ignore it. 680 */ 681 s = splbio(); 682 if ((sig & 0xffff0000) == 0xeb140000) { 683 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 684 } else 685 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 686 splx(s); 687 /* clear port interrupt register */ 688 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 689 /* and enable interrupts */ 690 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 691 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 692 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 693 AHCI_P_IX_DHRS); 694 /* wait 500ms before actually starting operations */ 695 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 696 break; 697 698 default: 699 break; 700 } 701 } 702 703 static void 704 ahci_setup_channel(struct ata_channel *chp) 705 { 706 return; 707 } 708 709 static int 710 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 711 { 712 struct ata_channel *chp = drvp->chnl_softc; 713 struct ata_xfer *xfer; 714 int ret; 715 int s; 716 717 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 718 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 719 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 720 DEBUG_XFERS); 721 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 722 ATAXF_NOSLEEP); 723 if (xfer == NULL) { 724 return ATACMD_TRY_AGAIN; 725 } 726 if (ata_c->flags & AT_POLL) 727 xfer->c_flags |= C_POLL; 728 if (ata_c->flags & AT_WAIT) 729 xfer->c_flags |= C_WAIT; 730 xfer->c_drive = drvp->drive; 731 xfer->c_databuf = ata_c->data; 732 xfer->c_bcount = ata_c->bcount; 733 xfer->c_cmd = ata_c; 734 xfer->c_start = ahci_cmd_start; 735 xfer->c_intr = ahci_cmd_complete; 736 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 737 s = splbio(); 738 ata_exec_xfer(chp, xfer); 739 #ifdef DIAGNOSTIC 740 if ((ata_c->flags & AT_POLL) != 0 && 741 (ata_c->flags & AT_DONE) == 0) 742 panic("ahci_exec_command: polled command not done"); 743 #endif 744 if (ata_c->flags & AT_DONE) { 745 ret = ATACMD_COMPLETE; 746 } else { 747 if (ata_c->flags & AT_WAIT) { 748 while ((ata_c->flags & AT_DONE) == 0) { 749 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 750 } 751 ret = ATACMD_COMPLETE; 752 } else { 753 ret = ATACMD_QUEUED; 754 } 755 } 756 splx(s); 757 return ret; 758 } 759 760 static void 761 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 762 { 763 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 764 struct ahci_channel *achp = (struct ahci_channel *)chp; 765 struct ata_command *ata_c = xfer->c_cmd; 766 int slot = 0 /* XXX slot */; 767 struct ahci_cmd_tbl *cmd_tbl; 768 struct ahci_cmd_header *cmd_h; 769 int i; 770 int channel = chp->ch_channel; 771 772 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 773 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 774 775 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 776 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 777 cmd_tbl), DEBUG_XFERS); 778 779 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 780 781 cmd_h = &achp->ahcic_cmdh[slot]; 782 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 783 chp->ch_channel, cmd_h), DEBUG_XFERS); 784 if (ahci_dma_setup(chp, slot, 785 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 786 ata_c->data : NULL, 787 ata_c->bcount, 788 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 789 ata_c->flags |= AT_DF; 790 ahci_cmd_complete(chp, xfer, slot); 791 return; 792 } 793 cmd_h->cmdh_flags = htole16( 794 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 795 RHD_FISLEN / 4); 796 cmd_h->cmdh_prdbc = 0; 797 AHCI_CMDH_SYNC(sc, achp, slot, 798 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 799 800 if (ata_c->flags & AT_POLL) { 801 /* polled command, disable interrupts */ 802 AHCI_WRITE(sc, AHCI_GHC, 803 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 804 } 805 chp->ch_flags |= ATACH_IRQ_WAIT; 806 chp->ch_status = 0; 807 /* start command */ 808 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 809 /* and says we started this command */ 810 achp->ahcic_cmds_active |= 1 << slot; 811 812 if ((ata_c->flags & AT_POLL) == 0) { 813 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 814 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 815 ahci_timeout, chp); 816 return; 817 } 818 /* 819 * Polled command. 820 */ 821 for (i = 0; i < ata_c->timeout / 10; i++) { 822 if (ata_c->flags & AT_DONE) 823 break; 824 ahci_intr_port(sc, achp); 825 if (ata_c->flags & AT_WAIT) 826 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 827 else 828 delay(10000); 829 } 830 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 831 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 832 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 833 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 834 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 835 DEBUG_XFERS); 836 if ((ata_c->flags & AT_DONE) == 0) { 837 ata_c->flags |= AT_TIMEOU; 838 ahci_cmd_complete(chp, xfer, slot); 839 } 840 /* reenable interrupts */ 841 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 842 } 843 844 static void 845 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 846 { 847 struct ata_command *ata_c = xfer->c_cmd; 848 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 849 DEBUG_FUNCS); 850 851 switch (reason) { 852 case KILL_GONE: 853 ata_c->flags |= AT_GONE; 854 break; 855 case KILL_RESET: 856 ata_c->flags |= AT_RESET; 857 break; 858 default: 859 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 860 panic("ahci_cmd_kill_xfer"); 861 } 862 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 863 } 864 865 static int 866 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 867 { 868 int slot = 0; /* XXX slot */ 869 struct ata_command *ata_c = xfer->c_cmd; 870 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 871 struct ahci_channel *achp = (struct ahci_channel *)chp; 872 873 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 874 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 875 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 876 DEBUG_FUNCS); 877 chp->ch_flags &= ~ATACH_IRQ_WAIT; 878 if (xfer->c_flags & C_TIMEOU) { 879 ata_c->flags |= AT_TIMEOU; 880 } else 881 callout_stop(&chp->ch_callout); 882 883 chp->ch_queue->active_xfer = NULL; 884 885 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 886 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 887 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 888 wakeup(&chp->ch_queue->active_xfer); 889 return 0; 890 } 891 892 if (chp->ch_status & WDCS_BSY) { 893 ata_c->flags |= AT_TIMEOU; 894 } else if (chp->ch_status & WDCS_ERR) { 895 ata_c->r_error = chp->ch_error; 896 ata_c->flags |= AT_ERROR; 897 } 898 899 if (ata_c->flags & AT_READREG) 900 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 901 902 ahci_cmd_done(chp, xfer, slot); 903 return 0; 904 } 905 906 static void 907 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 908 { 909 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 910 struct ahci_channel *achp = (struct ahci_channel *)chp; 911 struct ata_command *ata_c = xfer->c_cmd; 912 uint16_t *idwordbuf; 913 int i; 914 915 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 916 DEBUG_FUNCS); 917 918 /* this comamnd is not active any more */ 919 achp->ahcic_cmds_active &= ~(1 << slot); 920 921 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 922 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 923 achp->ahcic_datad[slot]->dm_mapsize, 924 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 925 BUS_DMASYNC_POSTWRITE); 926 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 927 } 928 929 AHCI_CMDH_SYNC(sc, achp, slot, 930 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 931 932 /* ata(4) expects IDENTIFY data to be in host endianess */ 933 if (ata_c->r_command == WDCC_IDENTIFY || 934 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 935 idwordbuf = xfer->c_databuf; 936 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 937 idwordbuf[i] = le16toh(idwordbuf[i]); 938 } 939 } 940 941 ata_c->flags |= AT_DONE; 942 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 943 ata_c->flags |= AT_XFDONE; 944 945 ata_free_xfer(chp, xfer); 946 if (ata_c->flags & AT_WAIT) 947 wakeup(ata_c); 948 else if (ata_c->callback) 949 ata_c->callback(ata_c->callback_arg); 950 atastart(chp); 951 return; 952 } 953 954 static int 955 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 956 { 957 struct ata_channel *chp = drvp->chnl_softc; 958 struct ata_xfer *xfer; 959 960 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 961 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 962 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 963 DEBUG_XFERS); 964 xfer = ata_get_xfer(ATAXF_NOSLEEP); 965 if (xfer == NULL) { 966 return ATACMD_TRY_AGAIN; 967 } 968 if (ata_bio->flags & ATA_POLL) 969 xfer->c_flags |= C_POLL; 970 xfer->c_drive = drvp->drive; 971 xfer->c_cmd = ata_bio; 972 xfer->c_databuf = ata_bio->databuf; 973 xfer->c_bcount = ata_bio->bcount; 974 xfer->c_start = ahci_bio_start; 975 xfer->c_intr = ahci_bio_complete; 976 xfer->c_kill_xfer = ahci_bio_kill_xfer; 977 ata_exec_xfer(chp, xfer); 978 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 979 } 980 981 static void 982 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 983 { 984 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 985 struct ahci_channel *achp = (struct ahci_channel *)chp; 986 struct ata_bio *ata_bio = xfer->c_cmd; 987 int slot = 0 /* XXX slot */; 988 struct ahci_cmd_tbl *cmd_tbl; 989 struct ahci_cmd_header *cmd_h; 990 int i; 991 int channel = chp->ch_channel; 992 993 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 994 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 995 996 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 997 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 998 cmd_tbl), DEBUG_XFERS); 999 1000 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1001 1002 cmd_h = &achp->ahcic_cmdh[slot]; 1003 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1004 chp->ch_channel, cmd_h), DEBUG_XFERS); 1005 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1006 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1007 ata_bio->error = ERR_DMA; 1008 ata_bio->r_error = 0; 1009 ahci_bio_complete(chp, xfer, slot); 1010 return; 1011 } 1012 cmd_h->cmdh_flags = htole16( 1013 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1014 RHD_FISLEN / 4); 1015 cmd_h->cmdh_prdbc = 0; 1016 AHCI_CMDH_SYNC(sc, achp, slot, 1017 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1018 1019 if (xfer->c_flags & C_POLL) { 1020 /* polled command, disable interrupts */ 1021 AHCI_WRITE(sc, AHCI_GHC, 1022 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1023 } 1024 chp->ch_flags |= ATACH_IRQ_WAIT; 1025 chp->ch_status = 0; 1026 /* start command */ 1027 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1028 /* and says we started this command */ 1029 achp->ahcic_cmds_active |= 1 << slot; 1030 1031 if ((xfer->c_flags & C_POLL) == 0) { 1032 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1033 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1034 ahci_timeout, chp); 1035 return; 1036 } 1037 /* 1038 * Polled command. 1039 */ 1040 for (i = 0; i < ATA_DELAY / 10; i++) { 1041 if (ata_bio->flags & ATA_ITSDONE) 1042 break; 1043 ahci_intr_port(sc, achp); 1044 if (ata_bio->flags & ATA_NOSLEEP) 1045 delay(10000); 1046 else 1047 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1048 } 1049 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1050 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1051 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1052 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1053 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1054 DEBUG_XFERS); 1055 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1056 ata_bio->error = TIMEOUT; 1057 ahci_bio_complete(chp, xfer, slot); 1058 } 1059 /* reenable interrupts */ 1060 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1061 } 1062 1063 static void 1064 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1065 { 1066 int slot = 0; /* XXX slot */ 1067 int drive = xfer->c_drive; 1068 struct ata_bio *ata_bio = xfer->c_cmd; 1069 struct ahci_channel *achp = (struct ahci_channel *)chp; 1070 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1071 DEBUG_FUNCS); 1072 1073 achp->ahcic_cmds_active &= ~(1 << slot); 1074 ata_free_xfer(chp, xfer); 1075 ata_bio->flags |= ATA_ITSDONE; 1076 switch (reason) { 1077 case KILL_GONE: 1078 ata_bio->error = ERR_NODEV; 1079 break; 1080 case KILL_RESET: 1081 ata_bio->error = ERR_RESET; 1082 break; 1083 default: 1084 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1085 panic("ahci_bio_kill_xfer"); 1086 } 1087 ata_bio->r_error = WDCE_ABRT; 1088 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1089 } 1090 1091 static int 1092 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1093 { 1094 int slot = 0; /* XXX slot */ 1095 struct ata_bio *ata_bio = xfer->c_cmd; 1096 int drive = xfer->c_drive; 1097 struct ahci_channel *achp = (struct ahci_channel *)chp; 1098 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1099 1100 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1101 DEBUG_FUNCS); 1102 1103 achp->ahcic_cmds_active &= ~(1 << slot); 1104 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1105 if (xfer->c_flags & C_TIMEOU) { 1106 ata_bio->error = TIMEOUT; 1107 } else { 1108 callout_stop(&chp->ch_callout); 1109 ata_bio->error = NOERROR; 1110 } 1111 1112 chp->ch_queue->active_xfer = NULL; 1113 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1114 achp->ahcic_datad[slot]->dm_mapsize, 1115 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1116 BUS_DMASYNC_POSTWRITE); 1117 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1118 1119 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1120 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1121 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1122 wakeup(&chp->ch_queue->active_xfer); 1123 return 0; 1124 } 1125 ata_free_xfer(chp, xfer); 1126 ata_bio->flags |= ATA_ITSDONE; 1127 if (chp->ch_status & WDCS_DWF) { 1128 ata_bio->error = ERR_DF; 1129 } else if (chp->ch_status & WDCS_ERR) { 1130 ata_bio->error = ERROR; 1131 ata_bio->r_error = chp->ch_error; 1132 } else if (chp->ch_status & WDCS_CORR) 1133 ata_bio->flags |= ATA_CORR; 1134 1135 AHCI_CMDH_SYNC(sc, achp, slot, 1136 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1137 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1138 ata_bio->bcount), DEBUG_XFERS); 1139 /* 1140 * if it was a write, complete data buffer may have been transfered 1141 * before error detection; in this case don't use cmdh_prdbc 1142 * as it won't reflect what was written to media. Assume nothing 1143 * was transfered and leave bcount as-is. 1144 */ 1145 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1146 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1147 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1148 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1149 atastart(chp); 1150 return 0; 1151 } 1152 1153 static void 1154 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1155 { 1156 int i; 1157 /* stop channel */ 1158 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1159 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1160 /* wait 1s for channel to stop */ 1161 for (i = 0; i <100; i++) { 1162 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1163 == 0) 1164 break; 1165 if (flags & AT_WAIT) 1166 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1167 else 1168 delay(10000); 1169 } 1170 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1171 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1172 /* XXX controller reset ? */ 1173 return; 1174 } 1175 } 1176 1177 static void 1178 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1179 { 1180 /* clear error */ 1181 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1182 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1183 1184 /* and start controller */ 1185 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1186 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1187 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1188 } 1189 1190 static void 1191 ahci_timeout(void *v) 1192 { 1193 struct ata_channel *chp = (struct ata_channel *)v; 1194 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1195 int s = splbio(); 1196 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1197 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1198 xfer->c_flags |= C_TIMEOU; 1199 xfer->c_intr(chp, xfer, 0); 1200 } 1201 splx(s); 1202 } 1203 1204 static int 1205 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1206 size_t count, int op) 1207 { 1208 int error, seg; 1209 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1210 struct ahci_channel *achp = (struct ahci_channel *)chp; 1211 struct ahci_cmd_tbl *cmd_tbl; 1212 struct ahci_cmd_header *cmd_h; 1213 1214 cmd_h = &achp->ahcic_cmdh[slot]; 1215 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1216 1217 if (data == NULL) { 1218 cmd_h->cmdh_prdtl = 0; 1219 goto end; 1220 } 1221 1222 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1223 data, count, NULL, 1224 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1225 if (error) { 1226 printf("%s port %d: failed to load xfer: %d\n", 1227 AHCINAME(sc), chp->ch_channel, error); 1228 return error; 1229 } 1230 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1231 achp->ahcic_datad[slot]->dm_mapsize, 1232 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1233 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1234 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1235 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1236 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1237 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1238 } 1239 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1240 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1241 end: 1242 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1243 return 0; 1244 } 1245 1246 #if NATAPIBUS > 0 1247 static void 1248 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1249 { 1250 struct ata_channel *chp = ata_sc->sc_chan; 1251 struct atac_softc *atac = chp->ch_atac; 1252 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1253 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1254 /* 1255 * Fill in the scsipi_adapter. 1256 */ 1257 adapt->adapt_dev = atac->atac_dev; 1258 adapt->adapt_nchannels = atac->atac_nchannels; 1259 adapt->adapt_request = ahci_atapi_scsipi_request; 1260 adapt->adapt_minphys = ahci_atapi_minphys; 1261 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1262 1263 /* 1264 * Fill in the scsipi_channel. 1265 */ 1266 memset(chan, 0, sizeof(*chan)); 1267 chan->chan_adapter = adapt; 1268 chan->chan_bustype = &ahci_atapi_bustype; 1269 chan->chan_channel = chp->ch_channel; 1270 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1271 chan->chan_openings = 1; 1272 chan->chan_max_periph = 1; 1273 chan->chan_ntargets = 1; 1274 chan->chan_nluns = 1; 1275 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1276 atapiprint); 1277 } 1278 1279 static void 1280 ahci_atapi_minphys(struct buf *bp) 1281 { 1282 if (bp->b_bcount > MAXPHYS) 1283 bp->b_bcount = MAXPHYS; 1284 minphys(bp); 1285 } 1286 1287 /* 1288 * Kill off all pending xfers for a periph. 1289 * 1290 * Must be called at splbio(). 1291 */ 1292 static void 1293 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1294 { 1295 struct atac_softc *atac = 1296 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1297 struct ata_channel *chp = 1298 atac->atac_channels[periph->periph_channel->chan_channel]; 1299 1300 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1301 } 1302 1303 static void 1304 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1305 scsipi_adapter_req_t req, void *arg) 1306 { 1307 struct scsipi_adapter *adapt = chan->chan_adapter; 1308 struct scsipi_periph *periph; 1309 struct scsipi_xfer *sc_xfer; 1310 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1311 struct atac_softc *atac = &sc->sc_atac; 1312 struct ata_xfer *xfer; 1313 int channel = chan->chan_channel; 1314 int drive, s; 1315 1316 switch (req) { 1317 case ADAPTER_REQ_RUN_XFER: 1318 sc_xfer = arg; 1319 periph = sc_xfer->xs_periph; 1320 drive = periph->periph_target; 1321 if (!device_is_active(atac->atac_dev)) { 1322 sc_xfer->error = XS_DRIVER_STUFFUP; 1323 scsipi_done(sc_xfer); 1324 return; 1325 } 1326 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1327 if (xfer == NULL) { 1328 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1329 scsipi_done(sc_xfer); 1330 return; 1331 } 1332 1333 if (sc_xfer->xs_control & XS_CTL_POLL) 1334 xfer->c_flags |= C_POLL; 1335 xfer->c_drive = drive; 1336 xfer->c_flags |= C_ATAPI; 1337 xfer->c_cmd = sc_xfer; 1338 xfer->c_databuf = sc_xfer->data; 1339 xfer->c_bcount = sc_xfer->datalen; 1340 xfer->c_start = ahci_atapi_start; 1341 xfer->c_intr = ahci_atapi_complete; 1342 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1343 xfer->c_dscpoll = 0; 1344 s = splbio(); 1345 ata_exec_xfer(atac->atac_channels[channel], xfer); 1346 #ifdef DIAGNOSTIC 1347 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1348 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1349 panic("ahci_atapi_scsipi_request: polled command " 1350 "not done"); 1351 #endif 1352 splx(s); 1353 return; 1354 default: 1355 /* Not supported, nothing to do. */ 1356 ; 1357 } 1358 } 1359 1360 static void 1361 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1362 { 1363 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1364 struct ahci_channel *achp = (struct ahci_channel *)chp; 1365 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1366 int slot = 0 /* XXX slot */; 1367 struct ahci_cmd_tbl *cmd_tbl; 1368 struct ahci_cmd_header *cmd_h; 1369 int i; 1370 int channel = chp->ch_channel; 1371 1372 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1373 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1374 1375 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1376 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1377 cmd_tbl), DEBUG_XFERS); 1378 1379 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1380 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1381 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1382 1383 cmd_h = &achp->ahcic_cmdh[slot]; 1384 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1385 chp->ch_channel, cmd_h), DEBUG_XFERS); 1386 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1387 sc_xfer->datalen, 1388 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1389 BUS_DMA_READ : BUS_DMA_WRITE)) { 1390 sc_xfer->error = XS_DRIVER_STUFFUP; 1391 ahci_atapi_complete(chp, xfer, slot); 1392 return; 1393 } 1394 cmd_h->cmdh_flags = htole16( 1395 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1396 RHD_FISLEN / 4 | AHCI_CMDH_F_A); 1397 cmd_h->cmdh_prdbc = 0; 1398 AHCI_CMDH_SYNC(sc, achp, slot, 1399 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1400 1401 if (xfer->c_flags & C_POLL) { 1402 /* polled command, disable interrupts */ 1403 AHCI_WRITE(sc, AHCI_GHC, 1404 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1405 } 1406 chp->ch_flags |= ATACH_IRQ_WAIT; 1407 chp->ch_status = 0; 1408 /* start command */ 1409 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1410 /* and says we started this command */ 1411 achp->ahcic_cmds_active |= 1 << slot; 1412 1413 if ((xfer->c_flags & C_POLL) == 0) { 1414 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1415 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1416 ahci_timeout, chp); 1417 return; 1418 } 1419 /* 1420 * Polled command. 1421 */ 1422 for (i = 0; i < ATA_DELAY / 10; i++) { 1423 if (sc_xfer->xs_status & XS_STS_DONE) 1424 break; 1425 ahci_intr_port(sc, achp); 1426 delay(10000); 1427 } 1428 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1429 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1430 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1431 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1432 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1433 DEBUG_XFERS); 1434 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1435 sc_xfer->error = XS_TIMEOUT; 1436 ahci_atapi_complete(chp, xfer, slot); 1437 } 1438 /* reenable interrupts */ 1439 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1440 } 1441 1442 static int 1443 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1444 { 1445 int slot = 0; /* XXX slot */ 1446 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1447 int drive = xfer->c_drive; 1448 struct ahci_channel *achp = (struct ahci_channel *)chp; 1449 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1450 1451 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1452 DEBUG_FUNCS); 1453 1454 achp->ahcic_cmds_active &= ~(1 << slot); 1455 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1456 if (xfer->c_flags & C_TIMEOU) { 1457 sc_xfer->error = XS_TIMEOUT; 1458 } else { 1459 callout_stop(&chp->ch_callout); 1460 sc_xfer->error = 0; 1461 } 1462 1463 chp->ch_queue->active_xfer = NULL; 1464 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1465 achp->ahcic_datad[slot]->dm_mapsize, 1466 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1467 BUS_DMASYNC_POSTWRITE); 1468 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1469 1470 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1471 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1472 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1473 wakeup(&chp->ch_queue->active_xfer); 1474 return 0; 1475 } 1476 ata_free_xfer(chp, xfer); 1477 1478 AHCI_CMDH_SYNC(sc, achp, slot, 1479 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1480 sc_xfer->resid = sc_xfer->datalen; 1481 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1482 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1483 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1484 if (chp->ch_status & WDCS_ERR && 1485 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1486 sc_xfer->resid == sc_xfer->datalen)) { 1487 sc_xfer->error = XS_SHORTSENSE; 1488 sc_xfer->sense.atapi_sense = chp->ch_error; 1489 if ((sc_xfer->xs_periph->periph_quirks & 1490 PQUIRK_NOSENSE) == 0) { 1491 /* ask scsipi to send a REQUEST_SENSE */ 1492 sc_xfer->error = XS_BUSY; 1493 sc_xfer->status = SCSI_CHECK; 1494 } 1495 } 1496 scsipi_done(sc_xfer); 1497 atastart(chp); 1498 return 0; 1499 } 1500 1501 static void 1502 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1503 { 1504 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1505 struct ahci_channel *achp = (struct ahci_channel *)chp; 1506 int slot = 0; /* XXX slot */ 1507 1508 achp->ahcic_cmds_active &= ~(1 << slot); 1509 1510 /* remove this command from xfer queue */ 1511 switch (reason) { 1512 case KILL_GONE: 1513 sc_xfer->error = XS_DRIVER_STUFFUP; 1514 break; 1515 case KILL_RESET: 1516 sc_xfer->error = XS_RESET; 1517 break; 1518 default: 1519 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1520 panic("ahci_ata_atapi_kill_xfer"); 1521 } 1522 ata_free_xfer(chp, xfer); 1523 scsipi_done(sc_xfer); 1524 } 1525 1526 static void 1527 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1528 { 1529 struct scsipi_channel *chan = sc->sc_channel; 1530 struct scsipi_periph *periph; 1531 struct ataparams ids; 1532 struct ataparams *id = &ids; 1533 struct ahci_softc *ahcic = 1534 device_private(chan->chan_adapter->adapt_dev); 1535 struct atac_softc *atac = &ahcic->sc_atac; 1536 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1537 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1538 struct scsipibus_attach_args sa; 1539 char serial_number[21], model[41], firmware_revision[9]; 1540 int s; 1541 1542 /* skip if already attached */ 1543 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1544 return; 1545 1546 /* if no ATAPI device detected at attach time, skip */ 1547 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1548 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1549 "not present\n", target), DEBUG_PROBE); 1550 return; 1551 } 1552 1553 /* Some ATAPI devices need a bit more time after software reset. */ 1554 delay(5000); 1555 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1556 #ifdef ATAPI_DEBUG_PROBE 1557 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1558 AHCINAME(ahcic), target, 1559 id->atap_config & ATAPI_CFG_CMD_MASK, 1560 id->atap_config & ATAPI_CFG_DRQ_MASK); 1561 #endif 1562 periph = scsipi_alloc_periph(M_NOWAIT); 1563 if (periph == NULL) { 1564 aprint_error_dev(sc->sc_dev, 1565 "unable to allocate periph for drive %d\n", 1566 target); 1567 return; 1568 } 1569 periph->periph_dev = NULL; 1570 periph->periph_channel = chan; 1571 periph->periph_switch = &atapi_probe_periphsw; 1572 periph->periph_target = target; 1573 periph->periph_lun = 0; 1574 periph->periph_quirks = PQUIRK_ONLYBIG; 1575 1576 #ifdef SCSIPI_DEBUG 1577 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1578 SCSIPI_DEBUG_TARGET == target) 1579 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1580 #endif 1581 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1582 if (id->atap_config & ATAPI_CFG_REMOV) 1583 periph->periph_flags |= PERIPH_REMOVABLE; 1584 if (periph->periph_type == T_SEQUENTIAL) { 1585 s = splbio(); 1586 drvp->drive_flags |= DRIVE_ATAPIST; 1587 splx(s); 1588 } 1589 1590 sa.sa_periph = periph; 1591 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1592 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1593 T_REMOV : T_FIXED; 1594 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1595 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1596 20); 1597 scsipi_strvis((u_char *)firmware_revision, 8, 1598 id->atap_revision, 8); 1599 sa.sa_inqbuf.vendor = model; 1600 sa.sa_inqbuf.product = serial_number; 1601 sa.sa_inqbuf.revision = firmware_revision; 1602 1603 /* 1604 * Determine the operating mode capabilities of the device. 1605 */ 1606 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1607 periph->periph_cap |= PERIPH_CAP_CMD16; 1608 /* XXX This is gross. */ 1609 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1610 1611 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1612 1613 if (drvp->drv_softc) 1614 ata_probe_caps(drvp); 1615 else { 1616 s = splbio(); 1617 drvp->drive_flags &= ~DRIVE_ATAPI; 1618 splx(s); 1619 } 1620 } else { 1621 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1622 "failed for drive %s:%d:%d: error 0x%x\n", 1623 AHCINAME(ahcic), chp->ch_channel, target, 1624 chp->ch_error), DEBUG_PROBE); 1625 s = splbio(); 1626 drvp->drive_flags &= ~DRIVE_ATAPI; 1627 splx(s); 1628 } 1629 } 1630 #endif /* NATAPIBUS */ 1631
Indexes created Fri Sep 26 08:10:20 GMT 2025