ahcisata_core.c revision 1.32.2.3
1 /* $NetBSD: ahcisata_core.c,v 1.32.2.3 2012/10/30 17:21:00 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.32.2.3 2012/10/30 17:21:00 yamt Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 62 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 63 static void ahci_reset_channel(struct ata_channel *, int); 64 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 65 static int ahci_ata_addref(struct ata_drive_datas *); 66 static void ahci_ata_delref(struct ata_drive_datas *); 67 static void ahci_killpending(struct ata_drive_datas *); 68 69 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 70 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 74 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 75 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 77 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 78 int, int); 79 static void ahci_timeout(void *); 80 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 static void ahci_atapibus_attach(struct atabus_softc *); 84 static void ahci_atapi_kill_pending(struct scsipi_periph *); 85 static void ahci_atapi_minphys(struct buf *); 86 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 NULL, 100 }; 101 #endif /* NATAPIBUS */ 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 105 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 106 107 const struct ata_bustype ahci_ata_bustype = { 108 SCSIPI_BUSTYPE_ATA, 109 ahci_ata_bio, 110 ahci_reset_drive, 111 ahci_reset_channel, 112 ahci_exec_command, 113 ata_get_params, 114 ahci_ata_addref, 115 ahci_ata_delref, 116 ahci_killpending 117 }; 118 119 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 static int 123 ahci_reset(struct ahci_softc *sc) 124 { 125 int i; 126 127 /* reset controller */ 128 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 129 /* wait up to 1s for reset to complete */ 130 for (i = 0; i < 1000; i++) { 131 delay(1000); 132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 133 break; 134 } 135 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 136 aprint_error("%s: reset failed\n", AHCINAME(sc)); 137 return -1; 138 } 139 /* enable ahci mode */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 141 return 0; 142 } 143 144 static void 145 ahci_setup_ports(struct ahci_softc *sc) 146 { 147 uint32_t ahci_ports; 148 int i, port; 149 150 ahci_ports = AHCI_READ(sc, AHCI_PI); 151 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 152 if ((ahci_ports & (1 << i)) == 0) 153 continue; 154 if (port >= sc->sc_atac.atac_nchannels) { 155 aprint_error("%s: more ports than announced\n", 156 AHCINAME(sc)); 157 break; 158 } 159 ahci_setup_port(sc, i); 160 } 161 } 162 163 static void 164 ahci_reprobe_drives(struct ahci_softc *sc) 165 { 166 uint32_t ahci_ports; 167 int i, port; 168 struct ahci_channel *achp; 169 struct ata_channel *chp; 170 171 ahci_ports = AHCI_READ(sc, AHCI_PI); 172 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 173 if ((ahci_ports & (1 << i)) == 0) 174 continue; 175 if (port >= sc->sc_atac.atac_nchannels) { 176 aprint_error("%s: more ports than announced\n", 177 AHCINAME(sc)); 178 break; 179 } 180 achp = &sc->sc_channels[i]; 181 chp = &achp->ata_channel; 182 183 ahci_probe_drive(chp); 184 } 185 } 186 187 static void 188 ahci_setup_port(struct ahci_softc *sc, int i) 189 { 190 struct ahci_channel *achp; 191 192 achp = &sc->sc_channels[i]; 193 194 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 195 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 196 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 197 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 198 } 199 200 static void 201 ahci_enable_intrs(struct ahci_softc *sc) 202 { 203 204 /* clear interrupts */ 205 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 206 /* enable interrupts */ 207 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 208 } 209 210 void 211 ahci_attach(struct ahci_softc *sc) 212 { 213 uint32_t ahci_rev, ahci_ports; 214 int i, j, port; 215 struct ahci_channel *achp; 216 struct ata_channel *chp; 217 int error; 218 int dmasize; 219 char buf[128]; 220 void *cmdhp; 221 void *cmdtblp; 222 223 if (ahci_reset(sc) != 0) 224 return; 225 226 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 227 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 228 aprint_verbose_dev(sc->sc_atac.atac_dev, 229 "ignoring broken port multiplier support\n"); 230 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 231 } 232 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 233 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 234 ahci_rev = AHCI_READ(sc, AHCI_VS); 235 snprintb(buf, sizeof(buf), "\177\020" 236 /* "f\000\005NP\0" */ 237 "b\005SXS\0" 238 "b\006EMS\0" 239 "b\007CCCS\0" 240 /* "f\010\005NCS\0" */ 241 "b\015PSC\0" 242 "b\016SSC\0" 243 "b\017PMD\0" 244 "b\020FBSS\0" 245 "b\021SPM\0" 246 "b\022SAM\0" 247 "b\023SNZO\0" 248 "f\024\003ISS\0" 249 "=\001Gen1\0" 250 "=\002Gen2\0" 251 "=\003Gen3\0" 252 "b\030SCLO\0" 253 "b\031SAL\0" 254 "b\032SALP\0" 255 "b\033SSS\0" 256 "b\034SMPS\0" 257 "b\035SSNTF\0" 258 "b\036SNCQ\0" 259 "b\037S64A\0" 260 "\0", sc->sc_ahci_cap); 261 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 262 ", %d ports, %d slots, CAP %s\n", 263 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 264 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 265 266 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 267 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 268 sc->sc_atac.atac_pio_cap = 4; 269 sc->sc_atac.atac_dma_cap = 2; 270 sc->sc_atac.atac_udma_cap = 6; 271 sc->sc_atac.atac_channels = sc->sc_chanarray; 272 sc->sc_atac.atac_probe = ahci_probe_drive; 273 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 274 sc->sc_atac.atac_set_modes = ahci_setup_channel; 275 #if NATAPIBUS > 0 276 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 277 #endif 278 279 dmasize = 280 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 281 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 282 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 283 if (error) { 284 aprint_error("%s: unable to allocate command header memory" 285 ", error=%d\n", AHCINAME(sc), error); 286 return; 287 } 288 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 289 sc->sc_cmd_hdr_nseg, dmasize, 290 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 291 if (error) { 292 aprint_error("%s: unable to map command header memory" 293 ", error=%d\n", AHCINAME(sc), error); 294 return; 295 } 296 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 297 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 298 if (error) { 299 aprint_error("%s: unable to create command header map" 300 ", error=%d\n", AHCINAME(sc), error); 301 return; 302 } 303 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 304 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 305 if (error) { 306 aprint_error("%s: unable to load command header map" 307 ", error=%d\n", AHCINAME(sc), error); 308 return; 309 } 310 sc->sc_cmd_hdr = cmdhp; 311 312 ahci_enable_intrs(sc); 313 314 ahci_ports = AHCI_READ(sc, AHCI_PI); 315 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 316 if ((ahci_ports & (1 << i)) == 0) 317 continue; 318 if (port >= sc->sc_atac.atac_nchannels) { 319 aprint_error("%s: more ports than announced\n", 320 AHCINAME(sc)); 321 break; 322 } 323 achp = &sc->sc_channels[i]; 324 chp = &achp->ata_channel; 325 sc->sc_chanarray[i] = chp; 326 chp->ch_channel = i; 327 chp->ch_atac = &sc->sc_atac; 328 chp->ch_queue = malloc(sizeof(struct ata_queue), 329 M_DEVBUF, M_NOWAIT); 330 if (chp->ch_queue == NULL) { 331 aprint_error("%s port %d: can't allocate memory for " 332 "command queue", AHCINAME(sc), i); 333 break; 334 } 335 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 338 BUS_DMA_NOWAIT); 339 if (error) { 340 aprint_error("%s: unable to allocate command table " 341 "memory, error=%d\n", AHCINAME(sc), error); 342 break; 343 } 344 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 345 achp->ahcic_cmd_tbl_nseg, dmasize, 346 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 347 if (error) { 348 aprint_error("%s: unable to map command table memory" 349 ", error=%d\n", AHCINAME(sc), error); 350 break; 351 } 352 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 353 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 354 if (error) { 355 aprint_error("%s: unable to create command table map" 356 ", error=%d\n", AHCINAME(sc), error); 357 break; 358 } 359 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 360 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 361 if (error) { 362 aprint_error("%s: unable to load command table map" 363 ", error=%d\n", AHCINAME(sc), error); 364 break; 365 } 366 achp->ahcic_cmdh = (struct ahci_cmd_header *) 367 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 368 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 369 AHCI_CMDH_SIZE * port; 370 achp->ahcic_rfis = (struct ahci_r_fis *) 371 ((char *)cmdhp + 372 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 373 AHCI_RFIS_SIZE * port); 374 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 375 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 376 AHCI_RFIS_SIZE * port; 377 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 378 "rfis %p (0x%" PRIx64 ")\n", i, 379 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 380 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 381 DEBUG_PROBE); 382 383 for (j = 0; j < sc->sc_ncmds; j++) { 384 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 385 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 386 achp->ahcic_bus_cmd_tbl[j] = 387 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 388 AHCI_CMDTBL_SIZE * j; 389 achp->ahcic_cmdh[j].cmdh_cmdtba = 390 htole64(achp->ahcic_bus_cmd_tbl[j]); 391 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 392 achp->ahcic_cmd_tbl[j], 393 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 394 /* The xfer DMA map */ 395 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 396 AHCI_NPRD, 0x400000 /* 4MB */, 0, 397 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 398 &achp->ahcic_datad[j]); 399 if (error) { 400 aprint_error("%s: couldn't alloc xfer DMA map, " 401 "error=%d\n", AHCINAME(sc), error); 402 goto end; 403 } 404 } 405 ahci_setup_port(sc, i); 406 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 407 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 408 aprint_error("%s: couldn't map channel %d " 409 "sata_status regs\n", AHCINAME(sc), i); 410 break; 411 } 412 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 413 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 414 aprint_error("%s: couldn't map channel %d " 415 "sata_control regs\n", AHCINAME(sc), i); 416 break; 417 } 418 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 419 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 420 aprint_error("%s: couldn't map channel %d " 421 "sata_error regs\n", AHCINAME(sc), i); 422 break; 423 } 424 ata_channel_attach(chp); 425 port++; 426 end: 427 continue; 428 } 429 } 430 431 int 432 ahci_detach(struct ahci_softc *sc, int flags) 433 { 434 struct atac_softc *atac; 435 struct ahci_channel *achp; 436 struct ata_channel *chp; 437 struct scsipi_adapter *adapt; 438 uint32_t ahci_ports; 439 int i, j; 440 int error; 441 442 atac = &sc->sc_atac; 443 adapt = &atac->atac_atapi_adapter._generic; 444 445 ahci_ports = AHCI_READ(sc, AHCI_PI); 446 for (i = 0; i < AHCI_MAX_PORTS; i++) { 447 achp = &sc->sc_channels[i]; 448 chp = &achp->ata_channel; 449 450 if ((ahci_ports & (1 << i)) == 0) 451 continue; 452 if (i >= sc->sc_atac.atac_nchannels) { 453 aprint_error("%s: more ports than announced\n", 454 AHCINAME(sc)); 455 break; 456 } 457 458 if (chp->atabus == NULL) 459 continue; 460 if ((error = config_detach(chp->atabus, flags)) != 0) 461 return error; 462 463 for (j = 0; j < sc->sc_ncmds; j++) 464 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 465 466 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 467 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 468 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 469 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 470 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 471 achp->ahcic_cmd_tbl_nseg); 472 473 free(chp->ch_queue, M_DEVBUF); 474 chp->atabus = NULL; 475 } 476 477 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 478 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 479 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 480 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 481 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 482 483 if (adapt->adapt_refcnt != 0) 484 return EBUSY; 485 486 return 0; 487 } 488 489 void 490 ahci_resume(struct ahci_softc *sc) 491 { 492 ahci_reset(sc); 493 ahci_setup_ports(sc); 494 ahci_reprobe_drives(sc); 495 ahci_enable_intrs(sc); 496 } 497 498 int 499 ahci_intr(void *v) 500 { 501 struct ahci_softc *sc = v; 502 uint32_t is; 503 int i, r = 0; 504 505 while ((is = AHCI_READ(sc, AHCI_IS))) { 506 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 507 DEBUG_INTR); 508 r = 1; 509 AHCI_WRITE(sc, AHCI_IS, is); 510 for (i = 0; i < AHCI_MAX_PORTS; i++) 511 if (is & (1 << i)) 512 ahci_intr_port(sc, &sc->sc_channels[i]); 513 } 514 return r; 515 } 516 517 static void 518 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 519 { 520 uint32_t is, tfd; 521 struct ata_channel *chp = &achp->ata_channel; 522 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 523 int slot; 524 525 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 526 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 527 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 528 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 529 DEBUG_INTR); 530 531 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 532 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 533 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 534 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 535 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 536 return; 537 /* stop channel */ 538 ahci_channel_stop(sc, chp, 0); 539 if (slot != 0) { 540 printf("ahci_intr_port: slot %d\n", slot); 541 panic("ahci_intr_port"); 542 } 543 if (is & AHCI_P_IX_TFES) { 544 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 545 chp->ch_error = 546 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 547 chp->ch_status = (tfd & 0xff); 548 } else { 549 /* emulate a CRC error */ 550 chp->ch_error = WDCE_CRC; 551 chp->ch_status = WDCS_ERR; 552 } 553 if (is & AHCI_P_IX_IFS) { 554 aprint_error("%s port %d: SERR 0x%x\n", 555 AHCINAME(sc), chp->ch_channel, 556 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 557 } 558 xfer->c_intr(chp, xfer, is); 559 /* if channel has not been restarted, do it now */ 560 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 561 == 0) 562 ahci_channel_start(sc, chp, 0, 0); 563 } else { 564 slot = 0; /* XXX */ 565 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 566 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 567 chp->ch_channel, is, achp->ahcic_cmds_active, 568 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 569 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 570 return; 571 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 572 == 0) { 573 xfer->c_intr(chp, xfer, 0); 574 } 575 } 576 } 577 578 static void 579 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 580 { 581 struct ata_channel *chp = drvp->chnl_softc; 582 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 583 AHCI_WRITE(sc, AHCI_GHC, 584 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 585 ahci_channel_stop(sc, chp, flags); 586 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 587 ata_reset_channel(chp, flags); 588 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 589 return; 590 } 591 592 /* return error code from ata_bio */ 593 static int 594 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 595 { 596 struct ahci_channel *achp = (struct ahci_channel *)chp; 597 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 598 int i; 599 uint32_t is; 600 601 timeout = timeout * 10; /* wait is 10ms */ 602 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 603 /* start command */ 604 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 605 for (i = 0; i < timeout; i++) { 606 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 607 return 0; 608 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 609 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 610 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 611 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 612 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 613 /* 614 * we got the D2H FIS anyway, 615 * assume sig is valid. 616 * channel is restarted later 617 */ 618 return ERROR; 619 } 620 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 621 AHCINAME(sc), chp->ch_channel, is); 622 return ERR_DF; 623 } 624 if (flags & AT_WAIT) 625 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 626 else 627 delay(10000); 628 } 629 aprint_debug("%s channel %d: timeout sending FIS\n", 630 AHCINAME(sc), chp->ch_channel); 631 return TIMEOUT; 632 } 633 634 static int 635 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 636 uint32_t *sigp) 637 { 638 struct ahci_channel *achp = (struct ahci_channel *)chp; 639 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 640 struct ahci_cmd_tbl *cmd_tbl; 641 struct ahci_cmd_header *cmd_h; 642 int i; 643 uint32_t sig; 644 645 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 646 again: 647 /* clear port interrupt register */ 648 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 649 /* clear SErrors and start operations */ 650 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 651 /* 652 * issue a command list override to clear BSY. 653 * This is needed if there's a PMP with no drive 654 * on port 0 655 */ 656 ahci_channel_start(sc, chp, flags, 1); 657 } else { 658 ahci_channel_start(sc, chp, flags, 0); 659 } 660 if (drive > 0) { 661 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 662 } 663 /* polled command, assume interrupts are disabled */ 664 /* use slot 0 to send reset, the channel is idle */ 665 cmd_h = &achp->ahcic_cmdh[0]; 666 cmd_tbl = achp->ahcic_cmd_tbl[0]; 667 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 668 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 669 cmd_h->cmdh_prdbc = 0; 670 memset(cmd_tbl->cmdt_cfis, 0, 64); 671 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 672 cmd_tbl->cmdt_cfis[rhd_c] = drive; 673 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 674 switch(ahci_exec_fis(chp, 1, flags)) { 675 case ERR_DF: 676 case TIMEOUT: 677 aprint_error("%s channel %d: setting WDCTL_RST failed " 678 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 679 if (sigp) 680 *sigp = 0xffffffff; 681 goto end; 682 default: 683 break; 684 } 685 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 686 (drive << AHCI_CMDH_F_PMP_SHIFT)); 687 cmd_h->cmdh_prdbc = 0; 688 memset(cmd_tbl->cmdt_cfis, 0, 64); 689 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 690 cmd_tbl->cmdt_cfis[rhd_c] = drive; 691 cmd_tbl->cmdt_cfis[rhd_control] = 0; 692 switch(ahci_exec_fis(chp, 31, flags)) { 693 case ERR_DF: 694 case TIMEOUT: 695 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 696 drive == PMP_PORT_CTL) { 697 /* 698 * some controllers fails to reset when 699 * targeting a PMP but a single drive is attached. 700 * try again with port 0 701 */ 702 drive = 0; 703 ahci_channel_stop(sc, chp, flags); 704 goto again; 705 } 706 aprint_error("%s channel %d: clearing WDCTL_RST failed " 707 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 708 if (sigp) 709 *sigp = 0xffffffff; 710 goto end; 711 default: 712 break; 713 } 714 /* 715 * wait 31s for BSY to clear 716 * This should not be needed, but some controllers clear the 717 * command slot before receiving the D2H FIS ... 718 */ 719 for (i = 0; i <AHCI_RST_WAIT; i++) { 720 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 721 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 722 & WDCS_BSY) == 0) 723 break; 724 if (flags & AT_WAIT) 725 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 726 else 727 delay(10000); 728 } 729 if (i == AHCI_RST_WAIT) { 730 aprint_error("%s: BSY never cleared, TD 0x%x\n", 731 AHCINAME(sc), sig); 732 if (sigp) 733 *sigp = 0xffffffff; 734 goto end; 735 } 736 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 737 DEBUG_PROBE); 738 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 739 if (sigp) 740 *sigp = sig; 741 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 742 AHCINAME(sc), chp->ch_channel, sig, 743 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 744 end: 745 ahci_channel_stop(sc, chp, flags); 746 if (flags & AT_WAIT) 747 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 748 else 749 delay(500000); 750 /* clear port interrupt register */ 751 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 752 ahci_channel_start(sc, chp, AT_WAIT, 753 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 754 return 0; 755 } 756 757 static void 758 ahci_reset_channel(struct ata_channel *chp, int flags) 759 { 760 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 761 struct ahci_channel *achp = (struct ahci_channel *)chp; 762 int i, tfd; 763 764 ahci_channel_stop(sc, chp, flags); 765 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 766 achp->ahcic_sstatus) != SStatus_DET_DEV) { 767 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 768 /* XXX and then ? */ 769 } 770 if (chp->ch_queue->active_xfer) { 771 chp->ch_queue->active_xfer->c_kill_xfer(chp, 772 chp->ch_queue->active_xfer, KILL_RESET); 773 } 774 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 775 /* clear port interrupt register */ 776 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 777 /* clear SErrors and start operations */ 778 ahci_channel_start(sc, chp, flags, 1); 779 /* wait 31s for BSY to clear */ 780 for (i = 0; i <AHCI_RST_WAIT; i++) { 781 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 782 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 783 & WDCS_BSY) == 0) 784 break; 785 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 786 } 787 if (i == AHCI_RST_WAIT) 788 aprint_error("%s: BSY never cleared, TD 0x%x\n", 789 AHCINAME(sc), tfd); 790 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 791 DEBUG_PROBE); 792 /* clear port interrupt register */ 793 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 794 795 return; 796 } 797 798 static int 799 ahci_ata_addref(struct ata_drive_datas *drvp) 800 { 801 return 0; 802 } 803 804 static void 805 ahci_ata_delref(struct ata_drive_datas *drvp) 806 { 807 return; 808 } 809 810 static void 811 ahci_killpending(struct ata_drive_datas *drvp) 812 { 813 return; 814 } 815 816 static void 817 ahci_probe_drive(struct ata_channel *chp) 818 { 819 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 820 struct ahci_channel *achp = (struct ahci_channel *)chp; 821 uint32_t sig; 822 823 /* bring interface up, accept FISs, power up and spin up device */ 824 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 825 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 826 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 827 /* reset the PHY and bring online */ 828 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 829 achp->ahcic_sstatus)) { 830 case SStatus_DET_DEV: 831 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 832 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 833 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 834 } else { 835 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 836 } 837 sata_interpret_sig(chp, 0, sig); 838 /* if we have a PMP attached, inform the controller */ 839 if (chp->ch_ndrives > PMP_PORT_CTL && 840 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 841 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 842 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 843 AHCI_P_CMD_PMA); 844 } 845 /* clear port interrupt register */ 846 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 847 848 /* and enable interrupts */ 849 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 850 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 851 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 852 AHCI_P_IX_PSS | AHCI_P_IX_DHRS); 853 /* wait 500ms before actually starting operations */ 854 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 855 break; 856 857 default: 858 break; 859 } 860 } 861 862 static void 863 ahci_setup_channel(struct ata_channel *chp) 864 { 865 return; 866 } 867 868 static int 869 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 870 { 871 struct ata_channel *chp = drvp->chnl_softc; 872 struct ata_xfer *xfer; 873 int ret; 874 int s; 875 876 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 877 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 878 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 879 DEBUG_XFERS); 880 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 881 ATAXF_NOSLEEP); 882 if (xfer == NULL) { 883 return ATACMD_TRY_AGAIN; 884 } 885 if (ata_c->flags & AT_POLL) 886 xfer->c_flags |= C_POLL; 887 if (ata_c->flags & AT_WAIT) 888 xfer->c_flags |= C_WAIT; 889 xfer->c_drive = drvp->drive; 890 xfer->c_databuf = ata_c->data; 891 xfer->c_bcount = ata_c->bcount; 892 xfer->c_cmd = ata_c; 893 xfer->c_start = ahci_cmd_start; 894 xfer->c_intr = ahci_cmd_complete; 895 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 896 s = splbio(); 897 ata_exec_xfer(chp, xfer); 898 #ifdef DIAGNOSTIC 899 if ((ata_c->flags & AT_POLL) != 0 && 900 (ata_c->flags & AT_DONE) == 0) 901 panic("ahci_exec_command: polled command not done"); 902 #endif 903 if (ata_c->flags & AT_DONE) { 904 ret = ATACMD_COMPLETE; 905 } else { 906 if (ata_c->flags & AT_WAIT) { 907 while ((ata_c->flags & AT_DONE) == 0) { 908 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 909 } 910 ret = ATACMD_COMPLETE; 911 } else { 912 ret = ATACMD_QUEUED; 913 } 914 } 915 splx(s); 916 return ret; 917 } 918 919 static void 920 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 921 { 922 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 923 struct ahci_channel *achp = (struct ahci_channel *)chp; 924 struct ata_command *ata_c = xfer->c_cmd; 925 int slot = 0 /* XXX slot */; 926 struct ahci_cmd_tbl *cmd_tbl; 927 struct ahci_cmd_header *cmd_h; 928 int i; 929 int channel = chp->ch_channel; 930 931 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n", 932 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout), 933 DEBUG_XFERS); 934 935 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 936 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 937 cmd_tbl), DEBUG_XFERS); 938 939 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 940 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 941 942 cmd_h = &achp->ahcic_cmdh[slot]; 943 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 944 chp->ch_channel, cmd_h), DEBUG_XFERS); 945 if (ahci_dma_setup(chp, slot, 946 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 947 ata_c->data : NULL, 948 ata_c->bcount, 949 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 950 ata_c->flags |= AT_DF; 951 ahci_cmd_complete(chp, xfer, slot); 952 return; 953 } 954 cmd_h->cmdh_flags = htole16( 955 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 956 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 957 cmd_h->cmdh_prdbc = 0; 958 AHCI_CMDH_SYNC(sc, achp, slot, 959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 960 961 if (ata_c->flags & AT_POLL) { 962 /* polled command, disable interrupts */ 963 AHCI_WRITE(sc, AHCI_GHC, 964 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 965 } 966 chp->ch_flags |= ATACH_IRQ_WAIT; 967 chp->ch_status = 0; 968 /* start command */ 969 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 970 /* and says we started this command */ 971 achp->ahcic_cmds_active |= 1 << slot; 972 973 if ((ata_c->flags & AT_POLL) == 0) { 974 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 975 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 976 ahci_timeout, chp); 977 return; 978 } 979 /* 980 * Polled command. 981 */ 982 for (i = 0; i < ata_c->timeout / 10; i++) { 983 if (ata_c->flags & AT_DONE) 984 break; 985 ahci_intr_port(sc, achp); 986 if (ata_c->flags & AT_WAIT) 987 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 988 else 989 delay(10000); 990 } 991 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 992 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 993 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 994 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 995 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 996 DEBUG_XFERS); 997 if ((ata_c->flags & AT_DONE) == 0) { 998 ata_c->flags |= AT_TIMEOU; 999 ahci_cmd_complete(chp, xfer, slot); 1000 } 1001 /* reenable interrupts */ 1002 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1003 } 1004 1005 static void 1006 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1007 { 1008 struct ata_command *ata_c = xfer->c_cmd; 1009 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1010 DEBUG_FUNCS); 1011 1012 switch (reason) { 1013 case KILL_GONE: 1014 ata_c->flags |= AT_GONE; 1015 break; 1016 case KILL_RESET: 1017 ata_c->flags |= AT_RESET; 1018 break; 1019 default: 1020 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1021 panic("ahci_cmd_kill_xfer"); 1022 } 1023 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1024 } 1025 1026 static int 1027 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1028 { 1029 int slot = 0; /* XXX slot */ 1030 struct ata_command *ata_c = xfer->c_cmd; 1031 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1032 struct ahci_channel *achp = (struct ahci_channel *)chp; 1033 1034 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1035 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1036 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1037 DEBUG_FUNCS); 1038 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1039 if (xfer->c_flags & C_TIMEOU) { 1040 ata_c->flags |= AT_TIMEOU; 1041 } else 1042 callout_stop(&chp->ch_callout); 1043 1044 chp->ch_queue->active_xfer = NULL; 1045 1046 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1047 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1048 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1049 wakeup(&chp->ch_queue->active_xfer); 1050 return 0; 1051 } 1052 1053 if (chp->ch_status & WDCS_BSY) { 1054 ata_c->flags |= AT_TIMEOU; 1055 } else if (chp->ch_status & WDCS_ERR) { 1056 ata_c->r_error = chp->ch_error; 1057 ata_c->flags |= AT_ERROR; 1058 } 1059 1060 if (ata_c->flags & AT_READREG) 1061 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1062 1063 ahci_cmd_done(chp, xfer, slot); 1064 return 0; 1065 } 1066 1067 static void 1068 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1069 { 1070 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1071 struct ahci_channel *achp = (struct ahci_channel *)chp; 1072 struct ata_command *ata_c = xfer->c_cmd; 1073 uint16_t *idwordbuf; 1074 int i; 1075 1076 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n", 1077 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1078 1079 /* this comamnd is not active any more */ 1080 achp->ahcic_cmds_active &= ~(1 << slot); 1081 1082 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1083 bus_dmamap_t map = achp->ahcic_datad[slot]; 1084 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1085 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1086 BUS_DMASYNC_POSTWRITE); 1087 bus_dmamap_unload(sc->sc_dmat, map); 1088 } 1089 1090 AHCI_CMDH_SYNC(sc, achp, slot, 1091 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1092 1093 /* ata(4) expects IDENTIFY data to be in host endianess */ 1094 if (ata_c->r_command == WDCC_IDENTIFY || 1095 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1096 idwordbuf = xfer->c_databuf; 1097 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1098 idwordbuf[i] = le16toh(idwordbuf[i]); 1099 } 1100 } 1101 1102 ata_c->flags |= AT_DONE; 1103 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1104 ata_c->flags |= AT_XFDONE; 1105 1106 ata_free_xfer(chp, xfer); 1107 if (ata_c->flags & AT_WAIT) 1108 wakeup(ata_c); 1109 else if (ata_c->callback) 1110 ata_c->callback(ata_c->callback_arg); 1111 atastart(chp); 1112 return; 1113 } 1114 1115 static int 1116 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1117 { 1118 struct ata_channel *chp = drvp->chnl_softc; 1119 struct ata_xfer *xfer; 1120 1121 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1122 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1123 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1124 DEBUG_XFERS); 1125 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1126 if (xfer == NULL) { 1127 return ATACMD_TRY_AGAIN; 1128 } 1129 if (ata_bio->flags & ATA_POLL) 1130 xfer->c_flags |= C_POLL; 1131 xfer->c_drive = drvp->drive; 1132 xfer->c_cmd = ata_bio; 1133 xfer->c_databuf = ata_bio->databuf; 1134 xfer->c_bcount = ata_bio->bcount; 1135 xfer->c_start = ahci_bio_start; 1136 xfer->c_intr = ahci_bio_complete; 1137 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1138 ata_exec_xfer(chp, xfer); 1139 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1140 } 1141 1142 static void 1143 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1144 { 1145 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1146 struct ahci_channel *achp = (struct ahci_channel *)chp; 1147 struct ata_bio *ata_bio = xfer->c_cmd; 1148 int slot = 0 /* XXX slot */; 1149 struct ahci_cmd_tbl *cmd_tbl; 1150 struct ahci_cmd_header *cmd_h; 1151 int i; 1152 int channel = chp->ch_channel; 1153 1154 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1155 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1156 1157 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1158 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1159 cmd_tbl), DEBUG_XFERS); 1160 1161 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1162 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1163 1164 cmd_h = &achp->ahcic_cmdh[slot]; 1165 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1166 chp->ch_channel, cmd_h), DEBUG_XFERS); 1167 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1168 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1169 ata_bio->error = ERR_DMA; 1170 ata_bio->r_error = 0; 1171 ahci_bio_complete(chp, xfer, slot); 1172 return; 1173 } 1174 cmd_h->cmdh_flags = htole16( 1175 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1176 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1177 cmd_h->cmdh_prdbc = 0; 1178 AHCI_CMDH_SYNC(sc, achp, slot, 1179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1180 1181 if (xfer->c_flags & C_POLL) { 1182 /* polled command, disable interrupts */ 1183 AHCI_WRITE(sc, AHCI_GHC, 1184 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1185 } 1186 chp->ch_flags |= ATACH_IRQ_WAIT; 1187 chp->ch_status = 0; 1188 /* start command */ 1189 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1190 /* and says we started this command */ 1191 achp->ahcic_cmds_active |= 1 << slot; 1192 1193 if ((xfer->c_flags & C_POLL) == 0) { 1194 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1195 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1196 ahci_timeout, chp); 1197 return; 1198 } 1199 /* 1200 * Polled command. 1201 */ 1202 for (i = 0; i < ATA_DELAY / 10; i++) { 1203 if (ata_bio->flags & ATA_ITSDONE) 1204 break; 1205 ahci_intr_port(sc, achp); 1206 if (ata_bio->flags & ATA_NOSLEEP) 1207 delay(10000); 1208 else 1209 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1210 } 1211 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1212 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1213 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1214 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1215 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1216 DEBUG_XFERS); 1217 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1218 ata_bio->error = TIMEOUT; 1219 ahci_bio_complete(chp, xfer, slot); 1220 } 1221 /* reenable interrupts */ 1222 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1223 } 1224 1225 static void 1226 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1227 { 1228 int slot = 0; /* XXX slot */ 1229 int drive = xfer->c_drive; 1230 struct ata_bio *ata_bio = xfer->c_cmd; 1231 struct ahci_channel *achp = (struct ahci_channel *)chp; 1232 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1233 DEBUG_FUNCS); 1234 1235 achp->ahcic_cmds_active &= ~(1 << slot); 1236 ata_free_xfer(chp, xfer); 1237 ata_bio->flags |= ATA_ITSDONE; 1238 switch (reason) { 1239 case KILL_GONE: 1240 ata_bio->error = ERR_NODEV; 1241 break; 1242 case KILL_RESET: 1243 ata_bio->error = ERR_RESET; 1244 break; 1245 default: 1246 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1247 panic("ahci_bio_kill_xfer"); 1248 } 1249 ata_bio->r_error = WDCE_ABRT; 1250 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1251 } 1252 1253 static int 1254 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1255 { 1256 int slot = 0; /* XXX slot */ 1257 struct ata_bio *ata_bio = xfer->c_cmd; 1258 int drive = xfer->c_drive; 1259 struct ahci_channel *achp = (struct ahci_channel *)chp; 1260 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1261 1262 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1263 DEBUG_FUNCS); 1264 1265 achp->ahcic_cmds_active &= ~(1 << slot); 1266 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1267 if (xfer->c_flags & C_TIMEOU) { 1268 ata_bio->error = TIMEOUT; 1269 } else { 1270 callout_stop(&chp->ch_callout); 1271 ata_bio->error = NOERROR; 1272 } 1273 1274 chp->ch_queue->active_xfer = NULL; 1275 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1276 achp->ahcic_datad[slot]->dm_mapsize, 1277 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1278 BUS_DMASYNC_POSTWRITE); 1279 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1280 1281 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1282 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1283 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1284 wakeup(&chp->ch_queue->active_xfer); 1285 return 0; 1286 } 1287 ata_free_xfer(chp, xfer); 1288 ata_bio->flags |= ATA_ITSDONE; 1289 if (chp->ch_status & WDCS_DWF) { 1290 ata_bio->error = ERR_DF; 1291 } else if (chp->ch_status & WDCS_ERR) { 1292 ata_bio->error = ERROR; 1293 ata_bio->r_error = chp->ch_error; 1294 } else if (chp->ch_status & WDCS_CORR) 1295 ata_bio->flags |= ATA_CORR; 1296 1297 AHCI_CMDH_SYNC(sc, achp, slot, 1298 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1299 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1300 ata_bio->bcount), DEBUG_XFERS); 1301 /* 1302 * if it was a write, complete data buffer may have been transfered 1303 * before error detection; in this case don't use cmdh_prdbc 1304 * as it won't reflect what was written to media. Assume nothing 1305 * was transfered and leave bcount as-is. 1306 */ 1307 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1308 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1309 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1310 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1311 atastart(chp); 1312 return 0; 1313 } 1314 1315 static void 1316 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1317 { 1318 int i; 1319 /* stop channel */ 1320 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1321 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1322 /* wait 1s for channel to stop */ 1323 for (i = 0; i <100; i++) { 1324 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1325 == 0) 1326 break; 1327 if (flags & AT_WAIT) 1328 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1329 else 1330 delay(10000); 1331 } 1332 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1333 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1334 /* XXX controller reset ? */ 1335 return; 1336 } 1337 } 1338 1339 static void 1340 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1341 int flags, int clo) 1342 { 1343 int i; 1344 uint32_t p_cmd; 1345 /* clear error */ 1346 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1347 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1348 1349 if (clo) { 1350 /* issue command list override */ 1351 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1352 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1353 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1354 /* wait 1s for AHCI_CAP_CLO to clear */ 1355 for (i = 0; i <100; i++) { 1356 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1357 AHCI_P_CMD_CLO) == 0) 1358 break; 1359 if (flags & AT_WAIT) 1360 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1361 else 1362 delay(10000); 1363 } 1364 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1365 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1366 /* XXX controller reset ? */ 1367 return; 1368 } 1369 } 1370 /* and start controller */ 1371 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1372 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1373 if (chp->ch_ndrives > PMP_PORT_CTL && 1374 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1375 p_cmd |= AHCI_P_CMD_PMA; 1376 } 1377 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1378 } 1379 1380 static void 1381 ahci_timeout(void *v) 1382 { 1383 struct ata_channel *chp = (struct ata_channel *)v; 1384 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1385 #ifdef AHCI_DEBUG 1386 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1387 #endif 1388 int s = splbio(); 1389 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel))), DEBUG_INTR); 1390 1391 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1392 xfer->c_flags |= C_TIMEOU; 1393 xfer->c_intr(chp, xfer, 0); 1394 } 1395 splx(s); 1396 } 1397 1398 static int 1399 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1400 size_t count, int op) 1401 { 1402 int error, seg; 1403 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1404 struct ahci_channel *achp = (struct ahci_channel *)chp; 1405 struct ahci_cmd_tbl *cmd_tbl; 1406 struct ahci_cmd_header *cmd_h; 1407 1408 cmd_h = &achp->ahcic_cmdh[slot]; 1409 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1410 1411 if (data == NULL) { 1412 cmd_h->cmdh_prdtl = 0; 1413 goto end; 1414 } 1415 1416 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1417 data, count, NULL, 1418 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1419 if (error) { 1420 printf("%s port %d: failed to load xfer: %d\n", 1421 AHCINAME(sc), chp->ch_channel, error); 1422 return error; 1423 } 1424 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1425 achp->ahcic_datad[slot]->dm_mapsize, 1426 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1427 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1428 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1429 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1430 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1431 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1432 } 1433 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1434 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1435 end: 1436 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1437 return 0; 1438 } 1439 1440 #if NATAPIBUS > 0 1441 static void 1442 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1443 { 1444 struct ata_channel *chp = ata_sc->sc_chan; 1445 struct atac_softc *atac = chp->ch_atac; 1446 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1447 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1448 /* 1449 * Fill in the scsipi_adapter. 1450 */ 1451 adapt->adapt_dev = atac->atac_dev; 1452 adapt->adapt_nchannels = atac->atac_nchannels; 1453 adapt->adapt_request = ahci_atapi_scsipi_request; 1454 adapt->adapt_minphys = ahci_atapi_minphys; 1455 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1456 1457 /* 1458 * Fill in the scsipi_channel. 1459 */ 1460 memset(chan, 0, sizeof(*chan)); 1461 chan->chan_adapter = adapt; 1462 chan->chan_bustype = &ahci_atapi_bustype; 1463 chan->chan_channel = chp->ch_channel; 1464 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1465 chan->chan_openings = 1; 1466 chan->chan_max_periph = 1; 1467 chan->chan_ntargets = 1; 1468 chan->chan_nluns = 1; 1469 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1470 atapiprint); 1471 } 1472 1473 static void 1474 ahci_atapi_minphys(struct buf *bp) 1475 { 1476 if (bp->b_bcount > MAXPHYS) 1477 bp->b_bcount = MAXPHYS; 1478 minphys(bp); 1479 } 1480 1481 /* 1482 * Kill off all pending xfers for a periph. 1483 * 1484 * Must be called at splbio(). 1485 */ 1486 static void 1487 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1488 { 1489 struct atac_softc *atac = 1490 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1491 struct ata_channel *chp = 1492 atac->atac_channels[periph->periph_channel->chan_channel]; 1493 1494 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1495 } 1496 1497 static void 1498 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1499 scsipi_adapter_req_t req, void *arg) 1500 { 1501 struct scsipi_adapter *adapt = chan->chan_adapter; 1502 struct scsipi_periph *periph; 1503 struct scsipi_xfer *sc_xfer; 1504 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1505 struct atac_softc *atac = &sc->sc_atac; 1506 struct ata_xfer *xfer; 1507 int channel = chan->chan_channel; 1508 int drive, s; 1509 1510 switch (req) { 1511 case ADAPTER_REQ_RUN_XFER: 1512 sc_xfer = arg; 1513 periph = sc_xfer->xs_periph; 1514 drive = periph->periph_target; 1515 if (!device_is_active(atac->atac_dev)) { 1516 sc_xfer->error = XS_DRIVER_STUFFUP; 1517 scsipi_done(sc_xfer); 1518 return; 1519 } 1520 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1521 if (xfer == NULL) { 1522 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1523 scsipi_done(sc_xfer); 1524 return; 1525 } 1526 1527 if (sc_xfer->xs_control & XS_CTL_POLL) 1528 xfer->c_flags |= C_POLL; 1529 xfer->c_drive = drive; 1530 xfer->c_flags |= C_ATAPI; 1531 xfer->c_cmd = sc_xfer; 1532 xfer->c_databuf = sc_xfer->data; 1533 xfer->c_bcount = sc_xfer->datalen; 1534 xfer->c_start = ahci_atapi_start; 1535 xfer->c_intr = ahci_atapi_complete; 1536 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1537 xfer->c_dscpoll = 0; 1538 s = splbio(); 1539 ata_exec_xfer(atac->atac_channels[channel], xfer); 1540 #ifdef DIAGNOSTIC 1541 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1542 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1543 panic("ahci_atapi_scsipi_request: polled command " 1544 "not done"); 1545 #endif 1546 splx(s); 1547 return; 1548 default: 1549 /* Not supported, nothing to do. */ 1550 ; 1551 } 1552 } 1553 1554 static void 1555 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1556 { 1557 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1558 struct ahci_channel *achp = (struct ahci_channel *)chp; 1559 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1560 int slot = 0 /* XXX slot */; 1561 struct ahci_cmd_tbl *cmd_tbl; 1562 struct ahci_cmd_header *cmd_h; 1563 int i; 1564 int channel = chp->ch_channel; 1565 1566 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1567 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1568 1569 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1570 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1571 cmd_tbl), DEBUG_XFERS); 1572 1573 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1574 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1575 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1576 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1577 1578 cmd_h = &achp->ahcic_cmdh[slot]; 1579 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1580 chp->ch_channel, cmd_h), DEBUG_XFERS); 1581 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1582 sc_xfer->datalen, 1583 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1584 BUS_DMA_READ : BUS_DMA_WRITE)) { 1585 sc_xfer->error = XS_DRIVER_STUFFUP; 1586 ahci_atapi_complete(chp, xfer, slot); 1587 return; 1588 } 1589 cmd_h->cmdh_flags = htole16( 1590 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1591 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1592 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1593 cmd_h->cmdh_prdbc = 0; 1594 AHCI_CMDH_SYNC(sc, achp, slot, 1595 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1596 1597 if (xfer->c_flags & C_POLL) { 1598 /* polled command, disable interrupts */ 1599 AHCI_WRITE(sc, AHCI_GHC, 1600 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1601 } 1602 chp->ch_flags |= ATACH_IRQ_WAIT; 1603 chp->ch_status = 0; 1604 /* start command */ 1605 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1606 /* and says we started this command */ 1607 achp->ahcic_cmds_active |= 1 << slot; 1608 1609 if ((xfer->c_flags & C_POLL) == 0) { 1610 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1611 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1612 ahci_timeout, chp); 1613 return; 1614 } 1615 /* 1616 * Polled command. 1617 */ 1618 for (i = 0; i < ATA_DELAY / 10; i++) { 1619 if (sc_xfer->xs_status & XS_STS_DONE) 1620 break; 1621 ahci_intr_port(sc, achp); 1622 delay(10000); 1623 } 1624 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1625 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1626 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1627 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1628 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1629 DEBUG_XFERS); 1630 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1631 sc_xfer->error = XS_TIMEOUT; 1632 ahci_atapi_complete(chp, xfer, slot); 1633 } 1634 /* reenable interrupts */ 1635 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1636 } 1637 1638 static int 1639 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1640 { 1641 int slot = 0; /* XXX slot */ 1642 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1643 int drive = xfer->c_drive; 1644 struct ahci_channel *achp = (struct ahci_channel *)chp; 1645 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1646 1647 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1648 DEBUG_FUNCS); 1649 1650 achp->ahcic_cmds_active &= ~(1 << slot); 1651 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1652 if (xfer->c_flags & C_TIMEOU) { 1653 sc_xfer->error = XS_TIMEOUT; 1654 } else { 1655 callout_stop(&chp->ch_callout); 1656 sc_xfer->error = 0; 1657 } 1658 1659 chp->ch_queue->active_xfer = NULL; 1660 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1661 achp->ahcic_datad[slot]->dm_mapsize, 1662 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1663 BUS_DMASYNC_POSTWRITE); 1664 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1665 1666 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1667 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1668 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1669 wakeup(&chp->ch_queue->active_xfer); 1670 return 0; 1671 } 1672 ata_free_xfer(chp, xfer); 1673 1674 AHCI_CMDH_SYNC(sc, achp, slot, 1675 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1676 sc_xfer->resid = sc_xfer->datalen; 1677 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1678 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1679 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1680 if (chp->ch_status & WDCS_ERR && 1681 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1682 sc_xfer->resid == sc_xfer->datalen)) { 1683 sc_xfer->error = XS_SHORTSENSE; 1684 sc_xfer->sense.atapi_sense = chp->ch_error; 1685 if ((sc_xfer->xs_periph->periph_quirks & 1686 PQUIRK_NOSENSE) == 0) { 1687 /* ask scsipi to send a REQUEST_SENSE */ 1688 sc_xfer->error = XS_BUSY; 1689 sc_xfer->status = SCSI_CHECK; 1690 } 1691 } 1692 scsipi_done(sc_xfer); 1693 atastart(chp); 1694 return 0; 1695 } 1696 1697 static void 1698 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1699 { 1700 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1701 struct ahci_channel *achp = (struct ahci_channel *)chp; 1702 int slot = 0; /* XXX slot */ 1703 1704 achp->ahcic_cmds_active &= ~(1 << slot); 1705 1706 /* remove this command from xfer queue */ 1707 switch (reason) { 1708 case KILL_GONE: 1709 sc_xfer->error = XS_DRIVER_STUFFUP; 1710 break; 1711 case KILL_RESET: 1712 sc_xfer->error = XS_RESET; 1713 break; 1714 default: 1715 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1716 panic("ahci_ata_atapi_kill_xfer"); 1717 } 1718 ata_free_xfer(chp, xfer); 1719 scsipi_done(sc_xfer); 1720 } 1721 1722 static void 1723 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1724 { 1725 struct scsipi_channel *chan = sc->sc_channel; 1726 struct scsipi_periph *periph; 1727 struct ataparams ids; 1728 struct ataparams *id = &ids; 1729 struct ahci_softc *ahcic = 1730 device_private(chan->chan_adapter->adapt_dev); 1731 struct atac_softc *atac = &ahcic->sc_atac; 1732 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1733 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1734 struct scsipibus_attach_args sa; 1735 char serial_number[21], model[41], firmware_revision[9]; 1736 int s; 1737 1738 /* skip if already attached */ 1739 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1740 return; 1741 1742 /* if no ATAPI device detected at attach time, skip */ 1743 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1744 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1745 "not present\n", target), DEBUG_PROBE); 1746 return; 1747 } 1748 1749 /* Some ATAPI devices need a bit more time after software reset. */ 1750 delay(5000); 1751 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1752 #ifdef ATAPI_DEBUG_PROBE 1753 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1754 AHCINAME(ahcic), target, 1755 id->atap_config & ATAPI_CFG_CMD_MASK, 1756 id->atap_config & ATAPI_CFG_DRQ_MASK); 1757 #endif 1758 periph = scsipi_alloc_periph(M_NOWAIT); 1759 if (periph == NULL) { 1760 aprint_error_dev(sc->sc_dev, 1761 "unable to allocate periph for drive %d\n", 1762 target); 1763 return; 1764 } 1765 periph->periph_dev = NULL; 1766 periph->periph_channel = chan; 1767 periph->periph_switch = &atapi_probe_periphsw; 1768 periph->periph_target = target; 1769 periph->periph_lun = 0; 1770 periph->periph_quirks = PQUIRK_ONLYBIG; 1771 1772 #ifdef SCSIPI_DEBUG 1773 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1774 SCSIPI_DEBUG_TARGET == target) 1775 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1776 #endif 1777 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1778 if (id->atap_config & ATAPI_CFG_REMOV) 1779 periph->periph_flags |= PERIPH_REMOVABLE; 1780 if (periph->periph_type == T_SEQUENTIAL) { 1781 s = splbio(); 1782 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1783 splx(s); 1784 } 1785 1786 sa.sa_periph = periph; 1787 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1788 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1789 T_REMOV : T_FIXED; 1790 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1791 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1792 20); 1793 scsipi_strvis((u_char *)firmware_revision, 8, 1794 id->atap_revision, 8); 1795 sa.sa_inqbuf.vendor = model; 1796 sa.sa_inqbuf.product = serial_number; 1797 sa.sa_inqbuf.revision = firmware_revision; 1798 1799 /* 1800 * Determine the operating mode capabilities of the device. 1801 */ 1802 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1803 periph->periph_cap |= PERIPH_CAP_CMD16; 1804 /* XXX This is gross. */ 1805 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1806 1807 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1808 1809 if (drvp->drv_softc) 1810 ata_probe_caps(drvp); 1811 else { 1812 s = splbio(); 1813 drvp->drive_type = ATA_DRIVET_NONE; 1814 splx(s); 1815 } 1816 } else { 1817 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1818 "failed for drive %s:%d:%d: error 0x%x\n", 1819 AHCINAME(ahcic), chp->ch_channel, target, 1820 chp->ch_error), DEBUG_PROBE); 1821 s = splbio(); 1822 drvp->drive_type = ATA_DRIVET_NONE; 1823 splx(s); 1824 } 1825 } 1826 #endif /* NATAPIBUS */ 1827
Indexes created Fri Oct 17 00:09:41 GMT 2025