ahcisata_core.c revision 1.32.2.4
1 /* $NetBSD: ahcisata_core.c,v 1.32.2.4 2014/05/22 11:40:21 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.32.2.4 2014/05/22 11:40:21 yamt Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 62 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 63 static void ahci_reset_channel(struct ata_channel *, int); 64 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 65 static int ahci_ata_addref(struct ata_drive_datas *); 66 static void ahci_ata_delref(struct ata_drive_datas *); 67 static void ahci_killpending(struct ata_drive_datas *); 68 69 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 70 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 74 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 75 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 77 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 78 int, int); 79 static void ahci_timeout(void *); 80 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 static void ahci_atapibus_attach(struct atabus_softc *); 84 static void ahci_atapi_kill_pending(struct scsipi_periph *); 85 static void ahci_atapi_minphys(struct buf *); 86 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 NULL, 100 }; 101 #endif /* NATAPIBUS */ 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 105 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 106 107 const struct ata_bustype ahci_ata_bustype = { 108 SCSIPI_BUSTYPE_ATA, 109 ahci_ata_bio, 110 ahci_reset_drive, 111 ahci_reset_channel, 112 ahci_exec_command, 113 ata_get_params, 114 ahci_ata_addref, 115 ahci_ata_delref, 116 ahci_killpending 117 }; 118 119 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 static void 123 ahci_enable(struct ahci_softc *sc) 124 { 125 uint32_t ghc; 126 127 ghc = AHCI_READ(sc, AHCI_GHC); 128 if (!(ghc & AHCI_GHC_AE)) { 129 ghc |= AHCI_GHC_AE; 130 AHCI_WRITE(sc, AHCI_GHC, ghc); 131 } 132 } 133 134 static int 135 ahci_reset(struct ahci_softc *sc) 136 { 137 int i; 138 139 /* reset controller */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 141 /* wait up to 1s for reset to complete */ 142 for (i = 0; i < 1000; i++) { 143 delay(1000); 144 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 145 break; 146 } 147 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 148 aprint_error("%s: reset failed\n", AHCINAME(sc)); 149 return -1; 150 } 151 /* enable ahci mode */ 152 ahci_enable(sc); 153 154 if (sc->sc_save_init_data) { 155 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 156 if (sc->sc_init_data.cap2) 157 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 158 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 159 } 160 161 return 0; 162 } 163 164 static void 165 ahci_setup_ports(struct ahci_softc *sc) 166 { 167 int i, port; 168 169 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 170 if ((sc->sc_ahci_ports & (1 << i)) == 0) 171 continue; 172 if (port >= sc->sc_atac.atac_nchannels) { 173 aprint_error("%s: more ports than announced\n", 174 AHCINAME(sc)); 175 break; 176 } 177 ahci_setup_port(sc, i); 178 } 179 } 180 181 static void 182 ahci_reprobe_drives(struct ahci_softc *sc) 183 { 184 int i, port; 185 struct ahci_channel *achp; 186 struct ata_channel *chp; 187 188 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 189 if ((sc->sc_ahci_ports & (1 << i)) == 0) 190 continue; 191 if (port >= sc->sc_atac.atac_nchannels) { 192 aprint_error("%s: more ports than announced\n", 193 AHCINAME(sc)); 194 break; 195 } 196 achp = &sc->sc_channels[i]; 197 chp = &achp->ata_channel; 198 199 ahci_probe_drive(chp); 200 } 201 } 202 203 static void 204 ahci_setup_port(struct ahci_softc *sc, int i) 205 { 206 struct ahci_channel *achp; 207 208 achp = &sc->sc_channels[i]; 209 210 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 211 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 212 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 213 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 214 } 215 216 static void 217 ahci_enable_intrs(struct ahci_softc *sc) 218 { 219 220 /* clear interrupts */ 221 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 222 /* enable interrupts */ 223 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 224 } 225 226 void 227 ahci_attach(struct ahci_softc *sc) 228 { 229 uint32_t ahci_rev; 230 int i, j, port; 231 struct ahci_channel *achp; 232 struct ata_channel *chp; 233 int error; 234 int dmasize; 235 char buf[128]; 236 void *cmdhp; 237 void *cmdtblp; 238 239 if (sc->sc_save_init_data) { 240 ahci_enable(sc); 241 242 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 243 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 244 245 ahci_rev = AHCI_READ(sc, AHCI_VS); 246 if (AHCI_VS_MJR(ahci_rev) > 1 || 247 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 248 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 249 } else { 250 sc->sc_init_data.cap2 = 0; 251 } 252 if (sc->sc_init_data.ports == 0) { 253 sc->sc_init_data.ports = sc->sc_ahci_ports; 254 } 255 } 256 257 if (ahci_reset(sc) != 0) 258 return; 259 260 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 261 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 262 aprint_verbose_dev(sc->sc_atac.atac_dev, 263 "ignoring broken port multiplier support\n"); 264 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 265 } 266 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 267 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 268 ahci_rev = AHCI_READ(sc, AHCI_VS); 269 snprintb(buf, sizeof(buf), "\177\020" 270 /* "f\000\005NP\0" */ 271 "b\005SXS\0" 272 "b\006EMS\0" 273 "b\007CCCS\0" 274 /* "f\010\005NCS\0" */ 275 "b\015PSC\0" 276 "b\016SSC\0" 277 "b\017PMD\0" 278 "b\020FBSS\0" 279 "b\021SPM\0" 280 "b\022SAM\0" 281 "b\023SNZO\0" 282 "f\024\003ISS\0" 283 "=\001Gen1\0" 284 "=\002Gen2\0" 285 "=\003Gen3\0" 286 "b\030SCLO\0" 287 "b\031SAL\0" 288 "b\032SALP\0" 289 "b\033SSS\0" 290 "b\034SMPS\0" 291 "b\035SSNTF\0" 292 "b\036SNCQ\0" 293 "b\037S64A\0" 294 "\0", sc->sc_ahci_cap); 295 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 296 ", %d port%s, %d slot%s, CAP %s\n", 297 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 298 sc->sc_atac.atac_nchannels, 299 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 300 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 301 302 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 303 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 304 sc->sc_atac.atac_pio_cap = 4; 305 sc->sc_atac.atac_dma_cap = 2; 306 sc->sc_atac.atac_udma_cap = 6; 307 sc->sc_atac.atac_channels = sc->sc_chanarray; 308 sc->sc_atac.atac_probe = ahci_probe_drive; 309 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 310 sc->sc_atac.atac_set_modes = ahci_setup_channel; 311 #if NATAPIBUS > 0 312 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 313 #endif 314 315 dmasize = 316 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 318 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 319 if (error) { 320 aprint_error("%s: unable to allocate command header memory" 321 ", error=%d\n", AHCINAME(sc), error); 322 return; 323 } 324 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 325 sc->sc_cmd_hdr_nseg, dmasize, 326 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 327 if (error) { 328 aprint_error("%s: unable to map command header memory" 329 ", error=%d\n", AHCINAME(sc), error); 330 return; 331 } 332 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 333 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 334 if (error) { 335 aprint_error("%s: unable to create command header map" 336 ", error=%d\n", AHCINAME(sc), error); 337 return; 338 } 339 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 340 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error("%s: unable to load command header map" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 sc->sc_cmd_hdr = cmdhp; 347 348 ahci_enable_intrs(sc); 349 350 if (sc->sc_ahci_ports == 0) { 351 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 352 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 353 DEBUG_PROBE); 354 } 355 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 356 if ((sc->sc_ahci_ports & (1 << i)) == 0) 357 continue; 358 if (port >= sc->sc_atac.atac_nchannels) { 359 aprint_error("%s: more ports than announced\n", 360 AHCINAME(sc)); 361 break; 362 } 363 achp = &sc->sc_channels[i]; 364 chp = &achp->ata_channel; 365 sc->sc_chanarray[i] = chp; 366 chp->ch_channel = i; 367 chp->ch_atac = &sc->sc_atac; 368 chp->ch_queue = malloc(sizeof(struct ata_queue), 369 M_DEVBUF, M_NOWAIT|M_ZERO); 370 if (chp->ch_queue == NULL) { 371 aprint_error("%s port %d: can't allocate memory for " 372 "command queue", AHCINAME(sc), i); 373 break; 374 } 375 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 376 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 377 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 378 BUS_DMA_NOWAIT); 379 if (error) { 380 aprint_error("%s: unable to allocate command table " 381 "memory, error=%d\n", AHCINAME(sc), error); 382 break; 383 } 384 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 385 achp->ahcic_cmd_tbl_nseg, dmasize, 386 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 387 if (error) { 388 aprint_error("%s: unable to map command table memory" 389 ", error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 393 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 394 if (error) { 395 aprint_error("%s: unable to create command table map" 396 ", error=%d\n", AHCINAME(sc), error); 397 break; 398 } 399 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 400 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 401 if (error) { 402 aprint_error("%s: unable to load command table map" 403 ", error=%d\n", AHCINAME(sc), error); 404 break; 405 } 406 achp->ahcic_cmdh = (struct ahci_cmd_header *) 407 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 408 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 409 AHCI_CMDH_SIZE * port; 410 achp->ahcic_rfis = (struct ahci_r_fis *) 411 ((char *)cmdhp + 412 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 413 AHCI_RFIS_SIZE * port); 414 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 415 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 416 AHCI_RFIS_SIZE * port; 417 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 418 "rfis %p (0x%" PRIx64 ")\n", i, 419 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 420 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 421 DEBUG_PROBE); 422 423 for (j = 0; j < sc->sc_ncmds; j++) { 424 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 425 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 426 achp->ahcic_bus_cmd_tbl[j] = 427 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 428 AHCI_CMDTBL_SIZE * j; 429 achp->ahcic_cmdh[j].cmdh_cmdtba = 430 htole64(achp->ahcic_bus_cmd_tbl[j]); 431 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 432 achp->ahcic_cmd_tbl[j], 433 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 434 /* The xfer DMA map */ 435 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 436 AHCI_NPRD, 0x400000 /* 4MB */, 0, 437 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 438 &achp->ahcic_datad[j]); 439 if (error) { 440 aprint_error("%s: couldn't alloc xfer DMA map, " 441 "error=%d\n", AHCINAME(sc), error); 442 goto end; 443 } 444 } 445 ahci_setup_port(sc, i); 446 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 447 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 448 aprint_error("%s: couldn't map channel %d " 449 "sata_status regs\n", AHCINAME(sc), i); 450 break; 451 } 452 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 453 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 454 aprint_error("%s: couldn't map channel %d " 455 "sata_control regs\n", AHCINAME(sc), i); 456 break; 457 } 458 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 459 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 460 aprint_error("%s: couldn't map channel %d " 461 "sata_error regs\n", AHCINAME(sc), i); 462 break; 463 } 464 ata_channel_attach(chp); 465 port++; 466 end: 467 continue; 468 } 469 } 470 471 int 472 ahci_detach(struct ahci_softc *sc, int flags) 473 { 474 struct atac_softc *atac; 475 struct ahci_channel *achp; 476 struct ata_channel *chp; 477 struct scsipi_adapter *adapt; 478 int i, j; 479 int error; 480 481 atac = &sc->sc_atac; 482 adapt = &atac->atac_atapi_adapter._generic; 483 484 for (i = 0; i < AHCI_MAX_PORTS; i++) { 485 achp = &sc->sc_channels[i]; 486 chp = &achp->ata_channel; 487 488 if ((sc->sc_ahci_ports & (1 << i)) == 0) 489 continue; 490 if (i >= sc->sc_atac.atac_nchannels) { 491 aprint_error("%s: more ports than announced\n", 492 AHCINAME(sc)); 493 break; 494 } 495 496 if (chp->atabus == NULL) 497 continue; 498 if ((error = config_detach(chp->atabus, flags)) != 0) 499 return error; 500 501 for (j = 0; j < sc->sc_ncmds; j++) 502 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 503 504 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 505 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 506 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 507 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 508 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 509 achp->ahcic_cmd_tbl_nseg); 510 511 free(chp->ch_queue, M_DEVBUF); 512 chp->atabus = NULL; 513 } 514 515 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 516 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 517 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 518 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 519 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 520 521 if (adapt->adapt_refcnt != 0) 522 return EBUSY; 523 524 return 0; 525 } 526 527 void 528 ahci_resume(struct ahci_softc *sc) 529 { 530 ahci_reset(sc); 531 ahci_setup_ports(sc); 532 ahci_reprobe_drives(sc); 533 ahci_enable_intrs(sc); 534 } 535 536 int 537 ahci_intr(void *v) 538 { 539 struct ahci_softc *sc = v; 540 uint32_t is; 541 int i, r = 0; 542 543 while ((is = AHCI_READ(sc, AHCI_IS))) { 544 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 545 DEBUG_INTR); 546 r = 1; 547 AHCI_WRITE(sc, AHCI_IS, is); 548 for (i = 0; i < AHCI_MAX_PORTS; i++) 549 if (is & (1 << i)) 550 ahci_intr_port(sc, &sc->sc_channels[i]); 551 } 552 return r; 553 } 554 555 static void 556 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 557 { 558 uint32_t is, tfd; 559 struct ata_channel *chp = &achp->ata_channel; 560 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 561 int slot; 562 563 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 564 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 565 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 566 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 567 DEBUG_INTR); 568 569 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 570 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 571 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 572 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 573 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 574 return; 575 /* stop channel */ 576 ahci_channel_stop(sc, chp, 0); 577 if (slot != 0) { 578 printf("ahci_intr_port: slot %d\n", slot); 579 panic("ahci_intr_port"); 580 } 581 if (is & AHCI_P_IX_TFES) { 582 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 583 chp->ch_error = 584 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 585 chp->ch_status = (tfd & 0xff); 586 } else { 587 /* emulate a CRC error */ 588 chp->ch_error = WDCE_CRC; 589 chp->ch_status = WDCS_ERR; 590 } 591 if (is & AHCI_P_IX_IFS) { 592 aprint_error("%s port %d: SERR 0x%x\n", 593 AHCINAME(sc), chp->ch_channel, 594 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 595 } 596 xfer->c_intr(chp, xfer, is); 597 /* if channel has not been restarted, do it now */ 598 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 599 == 0) 600 ahci_channel_start(sc, chp, 0, 0); 601 } else { 602 slot = 0; /* XXX */ 603 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 604 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 605 chp->ch_channel, is, achp->ahcic_cmds_active, 606 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 607 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 608 return; 609 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 610 == 0) { 611 xfer->c_intr(chp, xfer, 0); 612 } 613 } 614 } 615 616 static void 617 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 618 { 619 struct ata_channel *chp = drvp->chnl_softc; 620 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 621 AHCI_WRITE(sc, AHCI_GHC, 622 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 623 ahci_channel_stop(sc, chp, flags); 624 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 625 ata_reset_channel(chp, flags); 626 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 627 return; 628 } 629 630 /* return error code from ata_bio */ 631 static int 632 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 633 { 634 struct ahci_channel *achp = (struct ahci_channel *)chp; 635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 636 int i; 637 uint32_t is; 638 639 timeout = timeout * 10; /* wait is 10ms */ 640 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 641 /* start command */ 642 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 643 for (i = 0; i < timeout; i++) { 644 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 645 return 0; 646 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 647 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 648 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 649 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 650 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 651 /* 652 * we got the D2H FIS anyway, 653 * assume sig is valid. 654 * channel is restarted later 655 */ 656 return ERROR; 657 } 658 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 659 AHCINAME(sc), chp->ch_channel, is); 660 return ERR_DF; 661 } 662 if (flags & AT_WAIT) 663 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 664 else 665 delay(10000); 666 } 667 aprint_debug("%s channel %d: timeout sending FIS\n", 668 AHCINAME(sc), chp->ch_channel); 669 return TIMEOUT; 670 } 671 672 static int 673 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 674 uint32_t *sigp) 675 { 676 struct ahci_channel *achp = (struct ahci_channel *)chp; 677 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 678 struct ahci_cmd_tbl *cmd_tbl; 679 struct ahci_cmd_header *cmd_h; 680 int i; 681 uint32_t sig; 682 683 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 684 again: 685 /* clear port interrupt register */ 686 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 687 /* clear SErrors and start operations */ 688 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 689 /* 690 * issue a command list override to clear BSY. 691 * This is needed if there's a PMP with no drive 692 * on port 0 693 */ 694 ahci_channel_start(sc, chp, flags, 1); 695 } else { 696 ahci_channel_start(sc, chp, flags, 0); 697 } 698 if (drive > 0) { 699 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 700 } 701 /* polled command, assume interrupts are disabled */ 702 /* use slot 0 to send reset, the channel is idle */ 703 cmd_h = &achp->ahcic_cmdh[0]; 704 cmd_tbl = achp->ahcic_cmd_tbl[0]; 705 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 706 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 707 cmd_h->cmdh_prdbc = 0; 708 memset(cmd_tbl->cmdt_cfis, 0, 64); 709 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 710 cmd_tbl->cmdt_cfis[rhd_c] = drive; 711 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 712 switch(ahci_exec_fis(chp, 1, flags)) { 713 case ERR_DF: 714 case TIMEOUT: 715 aprint_error("%s channel %d: setting WDCTL_RST failed " 716 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 717 if (sigp) 718 *sigp = 0xffffffff; 719 goto end; 720 default: 721 break; 722 } 723 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 724 (drive << AHCI_CMDH_F_PMP_SHIFT)); 725 cmd_h->cmdh_prdbc = 0; 726 memset(cmd_tbl->cmdt_cfis, 0, 64); 727 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 728 cmd_tbl->cmdt_cfis[rhd_c] = drive; 729 cmd_tbl->cmdt_cfis[rhd_control] = 0; 730 switch(ahci_exec_fis(chp, 31, flags)) { 731 case ERR_DF: 732 case TIMEOUT: 733 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 734 drive == PMP_PORT_CTL) { 735 /* 736 * some controllers fails to reset when 737 * targeting a PMP but a single drive is attached. 738 * try again with port 0 739 */ 740 drive = 0; 741 ahci_channel_stop(sc, chp, flags); 742 goto again; 743 } 744 aprint_error("%s channel %d: clearing WDCTL_RST failed " 745 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 746 if (sigp) 747 *sigp = 0xffffffff; 748 goto end; 749 default: 750 break; 751 } 752 /* 753 * wait 31s for BSY to clear 754 * This should not be needed, but some controllers clear the 755 * command slot before receiving the D2H FIS ... 756 */ 757 for (i = 0; i < AHCI_RST_WAIT; i++) { 758 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 759 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 760 break; 761 if (flags & AT_WAIT) 762 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 763 else 764 delay(10000); 765 } 766 if (i == AHCI_RST_WAIT) { 767 aprint_error("%s: BSY never cleared, TD 0x%x\n", 768 AHCINAME(sc), sig); 769 if (sigp) 770 *sigp = 0xffffffff; 771 goto end; 772 } 773 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 774 DEBUG_PROBE); 775 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 776 if (sigp) 777 *sigp = sig; 778 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 779 AHCINAME(sc), chp->ch_channel, sig, 780 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 781 end: 782 ahci_channel_stop(sc, chp, flags); 783 if (flags & AT_WAIT) 784 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 785 else 786 delay(500000); 787 /* clear port interrupt register */ 788 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 789 ahci_channel_start(sc, chp, flags, 790 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 791 return 0; 792 } 793 794 static void 795 ahci_reset_channel(struct ata_channel *chp, int flags) 796 { 797 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 798 struct ahci_channel *achp = (struct ahci_channel *)chp; 799 int i, tfd; 800 801 ahci_channel_stop(sc, chp, flags); 802 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 803 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 804 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 805 /* XXX and then ? */ 806 } 807 if (chp->ch_queue->active_xfer) { 808 chp->ch_queue->active_xfer->c_kill_xfer(chp, 809 chp->ch_queue->active_xfer, KILL_RESET); 810 } 811 ata_delay(500, "ahcirst", flags); 812 /* clear port interrupt register */ 813 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 814 /* clear SErrors and start operations */ 815 ahci_channel_start(sc, chp, flags, 1); 816 /* wait 31s for BSY to clear */ 817 for (i = 0; i <AHCI_RST_WAIT; i++) { 818 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 819 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 820 & WDCS_BSY) == 0) 821 break; 822 ata_delay(10, "ahcid2h", flags); 823 } 824 if (i == AHCI_RST_WAIT) 825 aprint_error("%s: BSY never cleared, TD 0x%x\n", 826 AHCINAME(sc), tfd); 827 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 828 DEBUG_PROBE); 829 /* clear port interrupt register */ 830 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 831 832 return; 833 } 834 835 static int 836 ahci_ata_addref(struct ata_drive_datas *drvp) 837 { 838 return 0; 839 } 840 841 static void 842 ahci_ata_delref(struct ata_drive_datas *drvp) 843 { 844 return; 845 } 846 847 static void 848 ahci_killpending(struct ata_drive_datas *drvp) 849 { 850 return; 851 } 852 853 static void 854 ahci_probe_drive(struct ata_channel *chp) 855 { 856 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 857 struct ahci_channel *achp = (struct ahci_channel *)chp; 858 uint32_t sig; 859 860 /* bring interface up, accept FISs, power up and spin up device */ 861 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 862 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 863 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 864 /* reset the PHY and bring online */ 865 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 866 achp->ahcic_sstatus, AT_WAIT)) { 867 case SStatus_DET_DEV: 868 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 869 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 870 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 871 } else { 872 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 873 } 874 sata_interpret_sig(chp, 0, sig); 875 /* if we have a PMP attached, inform the controller */ 876 if (chp->ch_ndrives > PMP_PORT_CTL && 877 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 878 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 879 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 880 AHCI_P_CMD_PMA); 881 } 882 /* clear port interrupt register */ 883 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 884 885 /* and enable interrupts */ 886 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 887 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 888 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 889 AHCI_P_IX_PSS | AHCI_P_IX_DHRS); 890 /* wait 500ms before actually starting operations */ 891 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 892 break; 893 894 default: 895 break; 896 } 897 } 898 899 static void 900 ahci_setup_channel(struct ata_channel *chp) 901 { 902 return; 903 } 904 905 static int 906 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 907 { 908 struct ata_channel *chp = drvp->chnl_softc; 909 struct ata_xfer *xfer; 910 int ret; 911 int s; 912 913 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 914 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 915 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 916 DEBUG_XFERS); 917 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 918 ATAXF_NOSLEEP); 919 if (xfer == NULL) { 920 return ATACMD_TRY_AGAIN; 921 } 922 if (ata_c->flags & AT_POLL) 923 xfer->c_flags |= C_POLL; 924 if (ata_c->flags & AT_WAIT) 925 xfer->c_flags |= C_WAIT; 926 xfer->c_drive = drvp->drive; 927 xfer->c_databuf = ata_c->data; 928 xfer->c_bcount = ata_c->bcount; 929 xfer->c_cmd = ata_c; 930 xfer->c_start = ahci_cmd_start; 931 xfer->c_intr = ahci_cmd_complete; 932 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 933 s = splbio(); 934 ata_exec_xfer(chp, xfer); 935 #ifdef DIAGNOSTIC 936 if ((ata_c->flags & AT_POLL) != 0 && 937 (ata_c->flags & AT_DONE) == 0) 938 panic("ahci_exec_command: polled command not done"); 939 #endif 940 if (ata_c->flags & AT_DONE) { 941 ret = ATACMD_COMPLETE; 942 } else { 943 if (ata_c->flags & AT_WAIT) { 944 while ((ata_c->flags & AT_DONE) == 0) { 945 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 946 } 947 ret = ATACMD_COMPLETE; 948 } else { 949 ret = ATACMD_QUEUED; 950 } 951 } 952 splx(s); 953 return ret; 954 } 955 956 static void 957 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 958 { 959 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 960 struct ahci_channel *achp = (struct ahci_channel *)chp; 961 struct ata_command *ata_c = xfer->c_cmd; 962 int slot = 0 /* XXX slot */; 963 struct ahci_cmd_tbl *cmd_tbl; 964 struct ahci_cmd_header *cmd_h; 965 int i; 966 int channel = chp->ch_channel; 967 968 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n", 969 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout), 970 DEBUG_XFERS); 971 972 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 973 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 974 cmd_tbl), DEBUG_XFERS); 975 976 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 977 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 978 979 cmd_h = &achp->ahcic_cmdh[slot]; 980 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 981 chp->ch_channel, cmd_h), DEBUG_XFERS); 982 if (ahci_dma_setup(chp, slot, 983 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 984 ata_c->data : NULL, 985 ata_c->bcount, 986 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 987 ata_c->flags |= AT_DF; 988 ahci_cmd_complete(chp, xfer, slot); 989 return; 990 } 991 cmd_h->cmdh_flags = htole16( 992 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 993 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 994 cmd_h->cmdh_prdbc = 0; 995 AHCI_CMDH_SYNC(sc, achp, slot, 996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 997 998 if (ata_c->flags & AT_POLL) { 999 /* polled command, disable interrupts */ 1000 AHCI_WRITE(sc, AHCI_GHC, 1001 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1002 } 1003 chp->ch_flags |= ATACH_IRQ_WAIT; 1004 chp->ch_status = 0; 1005 /* start command */ 1006 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1007 /* and says we started this command */ 1008 achp->ahcic_cmds_active |= 1 << slot; 1009 1010 if ((ata_c->flags & AT_POLL) == 0) { 1011 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1012 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 1013 ahci_timeout, chp); 1014 return; 1015 } 1016 /* 1017 * Polled command. 1018 */ 1019 for (i = 0; i < ata_c->timeout / 10; i++) { 1020 if (ata_c->flags & AT_DONE) 1021 break; 1022 ahci_intr_port(sc, achp); 1023 if (ata_c->flags & AT_WAIT) 1024 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1025 else 1026 delay(10000); 1027 } 1028 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1029 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1030 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1031 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1032 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1033 DEBUG_XFERS); 1034 if ((ata_c->flags & AT_DONE) == 0) { 1035 ata_c->flags |= AT_TIMEOU; 1036 ahci_cmd_complete(chp, xfer, slot); 1037 } 1038 /* reenable interrupts */ 1039 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1040 } 1041 1042 static void 1043 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1044 { 1045 struct ata_command *ata_c = xfer->c_cmd; 1046 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1047 DEBUG_FUNCS); 1048 1049 switch (reason) { 1050 case KILL_GONE: 1051 ata_c->flags |= AT_GONE; 1052 break; 1053 case KILL_RESET: 1054 ata_c->flags |= AT_RESET; 1055 break; 1056 default: 1057 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1058 panic("ahci_cmd_kill_xfer"); 1059 } 1060 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1061 } 1062 1063 static int 1064 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1065 { 1066 int slot = 0; /* XXX slot */ 1067 struct ata_command *ata_c = xfer->c_cmd; 1068 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1069 struct ahci_channel *achp = (struct ahci_channel *)chp; 1070 1071 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1072 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1073 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1074 DEBUG_FUNCS); 1075 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1076 if (xfer->c_flags & C_TIMEOU) { 1077 ata_c->flags |= AT_TIMEOU; 1078 } else 1079 callout_stop(&chp->ch_callout); 1080 1081 chp->ch_queue->active_xfer = NULL; 1082 1083 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1084 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1085 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1086 wakeup(&chp->ch_queue->active_xfer); 1087 return 0; 1088 } 1089 1090 if (chp->ch_status & WDCS_BSY) { 1091 ata_c->flags |= AT_TIMEOU; 1092 } else if (chp->ch_status & WDCS_ERR) { 1093 ata_c->r_error = chp->ch_error; 1094 ata_c->flags |= AT_ERROR; 1095 } 1096 1097 if (ata_c->flags & AT_READREG) 1098 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1099 1100 ahci_cmd_done(chp, xfer, slot); 1101 return 0; 1102 } 1103 1104 static void 1105 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1106 { 1107 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1108 struct ahci_channel *achp = (struct ahci_channel *)chp; 1109 struct ata_command *ata_c = xfer->c_cmd; 1110 uint16_t *idwordbuf; 1111 int i; 1112 1113 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n", 1114 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1115 1116 /* this comamnd is not active any more */ 1117 achp->ahcic_cmds_active &= ~(1 << slot); 1118 1119 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1120 bus_dmamap_t map = achp->ahcic_datad[slot]; 1121 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1122 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1123 BUS_DMASYNC_POSTWRITE); 1124 bus_dmamap_unload(sc->sc_dmat, map); 1125 } 1126 1127 AHCI_CMDH_SYNC(sc, achp, slot, 1128 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1129 1130 /* ata(4) expects IDENTIFY data to be in host endianess */ 1131 if (ata_c->r_command == WDCC_IDENTIFY || 1132 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1133 idwordbuf = xfer->c_databuf; 1134 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1135 idwordbuf[i] = le16toh(idwordbuf[i]); 1136 } 1137 } 1138 1139 ata_c->flags |= AT_DONE; 1140 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1141 ata_c->flags |= AT_XFDONE; 1142 1143 ata_free_xfer(chp, xfer); 1144 if (ata_c->flags & AT_WAIT) 1145 wakeup(ata_c); 1146 else if (ata_c->callback) 1147 ata_c->callback(ata_c->callback_arg); 1148 atastart(chp); 1149 return; 1150 } 1151 1152 static int 1153 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1154 { 1155 struct ata_channel *chp = drvp->chnl_softc; 1156 struct ata_xfer *xfer; 1157 1158 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1159 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1160 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1161 DEBUG_XFERS); 1162 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1163 if (xfer == NULL) { 1164 return ATACMD_TRY_AGAIN; 1165 } 1166 if (ata_bio->flags & ATA_POLL) 1167 xfer->c_flags |= C_POLL; 1168 xfer->c_drive = drvp->drive; 1169 xfer->c_cmd = ata_bio; 1170 xfer->c_databuf = ata_bio->databuf; 1171 xfer->c_bcount = ata_bio->bcount; 1172 xfer->c_start = ahci_bio_start; 1173 xfer->c_intr = ahci_bio_complete; 1174 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1175 ata_exec_xfer(chp, xfer); 1176 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1177 } 1178 1179 static void 1180 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1181 { 1182 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1183 struct ahci_channel *achp = (struct ahci_channel *)chp; 1184 struct ata_bio *ata_bio = xfer->c_cmd; 1185 int slot = 0 /* XXX slot */; 1186 struct ahci_cmd_tbl *cmd_tbl; 1187 struct ahci_cmd_header *cmd_h; 1188 int i; 1189 int channel = chp->ch_channel; 1190 1191 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1192 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1193 1194 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1195 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1196 cmd_tbl), DEBUG_XFERS); 1197 1198 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1199 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1200 1201 cmd_h = &achp->ahcic_cmdh[slot]; 1202 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1203 chp->ch_channel, cmd_h), DEBUG_XFERS); 1204 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1205 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1206 ata_bio->error = ERR_DMA; 1207 ata_bio->r_error = 0; 1208 ahci_bio_complete(chp, xfer, slot); 1209 return; 1210 } 1211 cmd_h->cmdh_flags = htole16( 1212 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1213 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1214 cmd_h->cmdh_prdbc = 0; 1215 AHCI_CMDH_SYNC(sc, achp, slot, 1216 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1217 1218 if (xfer->c_flags & C_POLL) { 1219 /* polled command, disable interrupts */ 1220 AHCI_WRITE(sc, AHCI_GHC, 1221 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1222 } 1223 chp->ch_flags |= ATACH_IRQ_WAIT; 1224 chp->ch_status = 0; 1225 /* start command */ 1226 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1227 /* and says we started this command */ 1228 achp->ahcic_cmds_active |= 1 << slot; 1229 1230 if ((xfer->c_flags & C_POLL) == 0) { 1231 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1232 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1233 ahci_timeout, chp); 1234 return; 1235 } 1236 /* 1237 * Polled command. 1238 */ 1239 for (i = 0; i < ATA_DELAY * 10; i++) { 1240 if (ata_bio->flags & ATA_ITSDONE) 1241 break; 1242 ahci_intr_port(sc, achp); 1243 delay(100); 1244 } 1245 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1246 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1247 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1248 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1249 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1250 DEBUG_XFERS); 1251 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1252 ata_bio->error = TIMEOUT; 1253 ahci_bio_complete(chp, xfer, slot); 1254 } 1255 /* reenable interrupts */ 1256 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1257 } 1258 1259 static void 1260 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1261 { 1262 int slot = 0; /* XXX slot */ 1263 int drive = xfer->c_drive; 1264 struct ata_bio *ata_bio = xfer->c_cmd; 1265 struct ahci_channel *achp = (struct ahci_channel *)chp; 1266 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1267 DEBUG_FUNCS); 1268 1269 achp->ahcic_cmds_active &= ~(1 << slot); 1270 ata_free_xfer(chp, xfer); 1271 ata_bio->flags |= ATA_ITSDONE; 1272 switch (reason) { 1273 case KILL_GONE: 1274 ata_bio->error = ERR_NODEV; 1275 break; 1276 case KILL_RESET: 1277 ata_bio->error = ERR_RESET; 1278 break; 1279 default: 1280 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1281 panic("ahci_bio_kill_xfer"); 1282 } 1283 ata_bio->r_error = WDCE_ABRT; 1284 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1285 } 1286 1287 static int 1288 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1289 { 1290 int slot = 0; /* XXX slot */ 1291 struct ata_bio *ata_bio = xfer->c_cmd; 1292 int drive = xfer->c_drive; 1293 struct ahci_channel *achp = (struct ahci_channel *)chp; 1294 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1295 1296 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1297 DEBUG_FUNCS); 1298 1299 achp->ahcic_cmds_active &= ~(1 << slot); 1300 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1301 if (xfer->c_flags & C_TIMEOU) { 1302 ata_bio->error = TIMEOUT; 1303 } else { 1304 callout_stop(&chp->ch_callout); 1305 ata_bio->error = NOERROR; 1306 } 1307 1308 chp->ch_queue->active_xfer = NULL; 1309 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1310 achp->ahcic_datad[slot]->dm_mapsize, 1311 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1312 BUS_DMASYNC_POSTWRITE); 1313 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1314 1315 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1316 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1317 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1318 wakeup(&chp->ch_queue->active_xfer); 1319 return 0; 1320 } 1321 ata_free_xfer(chp, xfer); 1322 ata_bio->flags |= ATA_ITSDONE; 1323 if (chp->ch_status & WDCS_DWF) { 1324 ata_bio->error = ERR_DF; 1325 } else if (chp->ch_status & WDCS_ERR) { 1326 ata_bio->error = ERROR; 1327 ata_bio->r_error = chp->ch_error; 1328 } else if (chp->ch_status & WDCS_CORR) 1329 ata_bio->flags |= ATA_CORR; 1330 1331 AHCI_CMDH_SYNC(sc, achp, slot, 1332 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1333 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1334 ata_bio->bcount), DEBUG_XFERS); 1335 /* 1336 * if it was a write, complete data buffer may have been transfered 1337 * before error detection; in this case don't use cmdh_prdbc 1338 * as it won't reflect what was written to media. Assume nothing 1339 * was transfered and leave bcount as-is. 1340 */ 1341 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1342 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1343 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1344 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1345 atastart(chp); 1346 return 0; 1347 } 1348 1349 static void 1350 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1351 { 1352 int i; 1353 /* stop channel */ 1354 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1355 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1356 /* wait 1s for channel to stop */ 1357 for (i = 0; i <100; i++) { 1358 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1359 == 0) 1360 break; 1361 if (flags & AT_WAIT) 1362 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1363 else 1364 delay(10000); 1365 } 1366 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1367 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1368 /* XXX controller reset ? */ 1369 return; 1370 } 1371 1372 if (sc->sc_channel_stop) 1373 sc->sc_channel_stop(sc, chp); 1374 } 1375 1376 static void 1377 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1378 int flags, int clo) 1379 { 1380 int i; 1381 uint32_t p_cmd; 1382 /* clear error */ 1383 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1384 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1385 1386 if (clo) { 1387 /* issue command list override */ 1388 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1389 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1390 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1391 /* wait 1s for AHCI_CAP_CLO to clear */ 1392 for (i = 0; i <100; i++) { 1393 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1394 AHCI_P_CMD_CLO) == 0) 1395 break; 1396 if (flags & AT_WAIT) 1397 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1398 else 1399 delay(10000); 1400 } 1401 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1402 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1403 /* XXX controller reset ? */ 1404 return; 1405 } 1406 } 1407 1408 if (sc->sc_channel_start) 1409 sc->sc_channel_start(sc, chp); 1410 1411 /* and start controller */ 1412 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1413 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1414 if (chp->ch_ndrives > PMP_PORT_CTL && 1415 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1416 p_cmd |= AHCI_P_CMD_PMA; 1417 } 1418 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1419 } 1420 1421 static void 1422 ahci_timeout(void *v) 1423 { 1424 struct ata_channel *chp = (struct ata_channel *)v; 1425 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1426 #ifdef AHCI_DEBUG 1427 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1428 #endif 1429 int s = splbio(); 1430 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x ghc %08x is %08x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)), AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS)), DEBUG_INTR); 1431 1432 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1433 xfer->c_flags |= C_TIMEOU; 1434 xfer->c_intr(chp, xfer, 0); 1435 } 1436 splx(s); 1437 } 1438 1439 static int 1440 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1441 size_t count, int op) 1442 { 1443 int error, seg; 1444 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1445 struct ahci_channel *achp = (struct ahci_channel *)chp; 1446 struct ahci_cmd_tbl *cmd_tbl; 1447 struct ahci_cmd_header *cmd_h; 1448 1449 cmd_h = &achp->ahcic_cmdh[slot]; 1450 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1451 1452 if (data == NULL) { 1453 cmd_h->cmdh_prdtl = 0; 1454 goto end; 1455 } 1456 1457 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1458 data, count, NULL, 1459 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1460 if (error) { 1461 printf("%s port %d: failed to load xfer: %d\n", 1462 AHCINAME(sc), chp->ch_channel, error); 1463 return error; 1464 } 1465 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1466 achp->ahcic_datad[slot]->dm_mapsize, 1467 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1468 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1469 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1470 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1471 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1472 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1473 } 1474 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1475 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1476 end: 1477 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1478 return 0; 1479 } 1480 1481 #if NATAPIBUS > 0 1482 static void 1483 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1484 { 1485 struct ata_channel *chp = ata_sc->sc_chan; 1486 struct atac_softc *atac = chp->ch_atac; 1487 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1488 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1489 /* 1490 * Fill in the scsipi_adapter. 1491 */ 1492 adapt->adapt_dev = atac->atac_dev; 1493 adapt->adapt_nchannels = atac->atac_nchannels; 1494 adapt->adapt_request = ahci_atapi_scsipi_request; 1495 adapt->adapt_minphys = ahci_atapi_minphys; 1496 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1497 1498 /* 1499 * Fill in the scsipi_channel. 1500 */ 1501 memset(chan, 0, sizeof(*chan)); 1502 chan->chan_adapter = adapt; 1503 chan->chan_bustype = &ahci_atapi_bustype; 1504 chan->chan_channel = chp->ch_channel; 1505 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1506 chan->chan_openings = 1; 1507 chan->chan_max_periph = 1; 1508 chan->chan_ntargets = 1; 1509 chan->chan_nluns = 1; 1510 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1511 atapiprint); 1512 } 1513 1514 static void 1515 ahci_atapi_minphys(struct buf *bp) 1516 { 1517 if (bp->b_bcount > MAXPHYS) 1518 bp->b_bcount = MAXPHYS; 1519 minphys(bp); 1520 } 1521 1522 /* 1523 * Kill off all pending xfers for a periph. 1524 * 1525 * Must be called at splbio(). 1526 */ 1527 static void 1528 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1529 { 1530 struct atac_softc *atac = 1531 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1532 struct ata_channel *chp = 1533 atac->atac_channels[periph->periph_channel->chan_channel]; 1534 1535 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1536 } 1537 1538 static void 1539 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1540 scsipi_adapter_req_t req, void *arg) 1541 { 1542 struct scsipi_adapter *adapt = chan->chan_adapter; 1543 struct scsipi_periph *periph; 1544 struct scsipi_xfer *sc_xfer; 1545 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1546 struct atac_softc *atac = &sc->sc_atac; 1547 struct ata_xfer *xfer; 1548 int channel = chan->chan_channel; 1549 int drive, s; 1550 1551 switch (req) { 1552 case ADAPTER_REQ_RUN_XFER: 1553 sc_xfer = arg; 1554 periph = sc_xfer->xs_periph; 1555 drive = periph->periph_target; 1556 if (!device_is_active(atac->atac_dev)) { 1557 sc_xfer->error = XS_DRIVER_STUFFUP; 1558 scsipi_done(sc_xfer); 1559 return; 1560 } 1561 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1562 if (xfer == NULL) { 1563 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1564 scsipi_done(sc_xfer); 1565 return; 1566 } 1567 1568 if (sc_xfer->xs_control & XS_CTL_POLL) 1569 xfer->c_flags |= C_POLL; 1570 xfer->c_drive = drive; 1571 xfer->c_flags |= C_ATAPI; 1572 xfer->c_cmd = sc_xfer; 1573 xfer->c_databuf = sc_xfer->data; 1574 xfer->c_bcount = sc_xfer->datalen; 1575 xfer->c_start = ahci_atapi_start; 1576 xfer->c_intr = ahci_atapi_complete; 1577 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1578 xfer->c_dscpoll = 0; 1579 s = splbio(); 1580 ata_exec_xfer(atac->atac_channels[channel], xfer); 1581 #ifdef DIAGNOSTIC 1582 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1583 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1584 panic("ahci_atapi_scsipi_request: polled command " 1585 "not done"); 1586 #endif 1587 splx(s); 1588 return; 1589 default: 1590 /* Not supported, nothing to do. */ 1591 ; 1592 } 1593 } 1594 1595 static void 1596 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1597 { 1598 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1599 struct ahci_channel *achp = (struct ahci_channel *)chp; 1600 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1601 int slot = 0 /* XXX slot */; 1602 struct ahci_cmd_tbl *cmd_tbl; 1603 struct ahci_cmd_header *cmd_h; 1604 int i; 1605 int channel = chp->ch_channel; 1606 1607 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1608 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1609 1610 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1611 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1612 cmd_tbl), DEBUG_XFERS); 1613 1614 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1615 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1616 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1617 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1618 1619 cmd_h = &achp->ahcic_cmdh[slot]; 1620 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1621 chp->ch_channel, cmd_h), DEBUG_XFERS); 1622 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1623 sc_xfer->datalen, 1624 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1625 BUS_DMA_READ : BUS_DMA_WRITE)) { 1626 sc_xfer->error = XS_DRIVER_STUFFUP; 1627 ahci_atapi_complete(chp, xfer, slot); 1628 return; 1629 } 1630 cmd_h->cmdh_flags = htole16( 1631 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1632 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1633 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1634 cmd_h->cmdh_prdbc = 0; 1635 AHCI_CMDH_SYNC(sc, achp, slot, 1636 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1637 1638 if (xfer->c_flags & C_POLL) { 1639 /* polled command, disable interrupts */ 1640 AHCI_WRITE(sc, AHCI_GHC, 1641 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1642 } 1643 chp->ch_flags |= ATACH_IRQ_WAIT; 1644 chp->ch_status = 0; 1645 /* start command */ 1646 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1647 /* and says we started this command */ 1648 achp->ahcic_cmds_active |= 1 << slot; 1649 1650 if ((xfer->c_flags & C_POLL) == 0) { 1651 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1652 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1653 ahci_timeout, chp); 1654 return; 1655 } 1656 /* 1657 * Polled command. 1658 */ 1659 for (i = 0; i < ATA_DELAY / 10; i++) { 1660 if (sc_xfer->xs_status & XS_STS_DONE) 1661 break; 1662 ahci_intr_port(sc, achp); 1663 delay(10000); 1664 } 1665 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1666 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1667 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1668 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1669 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1670 DEBUG_XFERS); 1671 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1672 sc_xfer->error = XS_TIMEOUT; 1673 ahci_atapi_complete(chp, xfer, slot); 1674 } 1675 /* reenable interrupts */ 1676 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1677 } 1678 1679 static int 1680 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1681 { 1682 int slot = 0; /* XXX slot */ 1683 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1684 int drive = xfer->c_drive; 1685 struct ahci_channel *achp = (struct ahci_channel *)chp; 1686 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1687 1688 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1689 DEBUG_FUNCS); 1690 1691 achp->ahcic_cmds_active &= ~(1 << slot); 1692 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1693 if (xfer->c_flags & C_TIMEOU) { 1694 sc_xfer->error = XS_TIMEOUT; 1695 } else { 1696 callout_stop(&chp->ch_callout); 1697 sc_xfer->error = 0; 1698 } 1699 1700 chp->ch_queue->active_xfer = NULL; 1701 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1702 achp->ahcic_datad[slot]->dm_mapsize, 1703 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1704 BUS_DMASYNC_POSTWRITE); 1705 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1706 1707 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1708 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1709 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1710 wakeup(&chp->ch_queue->active_xfer); 1711 return 0; 1712 } 1713 ata_free_xfer(chp, xfer); 1714 1715 AHCI_CMDH_SYNC(sc, achp, slot, 1716 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1717 sc_xfer->resid = sc_xfer->datalen; 1718 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1719 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1720 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1721 if (chp->ch_status & WDCS_ERR && 1722 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1723 sc_xfer->resid == sc_xfer->datalen)) { 1724 sc_xfer->error = XS_SHORTSENSE; 1725 sc_xfer->sense.atapi_sense = chp->ch_error; 1726 if ((sc_xfer->xs_periph->periph_quirks & 1727 PQUIRK_NOSENSE) == 0) { 1728 /* ask scsipi to send a REQUEST_SENSE */ 1729 sc_xfer->error = XS_BUSY; 1730 sc_xfer->status = SCSI_CHECK; 1731 } 1732 } 1733 scsipi_done(sc_xfer); 1734 atastart(chp); 1735 return 0; 1736 } 1737 1738 static void 1739 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1740 { 1741 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1742 struct ahci_channel *achp = (struct ahci_channel *)chp; 1743 int slot = 0; /* XXX slot */ 1744 1745 achp->ahcic_cmds_active &= ~(1 << slot); 1746 1747 /* remove this command from xfer queue */ 1748 switch (reason) { 1749 case KILL_GONE: 1750 sc_xfer->error = XS_DRIVER_STUFFUP; 1751 break; 1752 case KILL_RESET: 1753 sc_xfer->error = XS_RESET; 1754 break; 1755 default: 1756 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1757 panic("ahci_ata_atapi_kill_xfer"); 1758 } 1759 ata_free_xfer(chp, xfer); 1760 scsipi_done(sc_xfer); 1761 } 1762 1763 static void 1764 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1765 { 1766 struct scsipi_channel *chan = sc->sc_channel; 1767 struct scsipi_periph *periph; 1768 struct ataparams ids; 1769 struct ataparams *id = &ids; 1770 struct ahci_softc *ahcic = 1771 device_private(chan->chan_adapter->adapt_dev); 1772 struct atac_softc *atac = &ahcic->sc_atac; 1773 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1774 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1775 struct scsipibus_attach_args sa; 1776 char serial_number[21], model[41], firmware_revision[9]; 1777 int s; 1778 1779 /* skip if already attached */ 1780 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1781 return; 1782 1783 /* if no ATAPI device detected at attach time, skip */ 1784 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1785 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1786 "not present\n", target), DEBUG_PROBE); 1787 return; 1788 } 1789 1790 /* Some ATAPI devices need a bit more time after software reset. */ 1791 delay(5000); 1792 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1793 #ifdef ATAPI_DEBUG_PROBE 1794 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1795 AHCINAME(ahcic), target, 1796 id->atap_config & ATAPI_CFG_CMD_MASK, 1797 id->atap_config & ATAPI_CFG_DRQ_MASK); 1798 #endif 1799 periph = scsipi_alloc_periph(M_NOWAIT); 1800 if (periph == NULL) { 1801 aprint_error_dev(sc->sc_dev, 1802 "unable to allocate periph for drive %d\n", 1803 target); 1804 return; 1805 } 1806 periph->periph_dev = NULL; 1807 periph->periph_channel = chan; 1808 periph->periph_switch = &atapi_probe_periphsw; 1809 periph->periph_target = target; 1810 periph->periph_lun = 0; 1811 periph->periph_quirks = PQUIRK_ONLYBIG; 1812 1813 #ifdef SCSIPI_DEBUG 1814 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1815 SCSIPI_DEBUG_TARGET == target) 1816 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1817 #endif 1818 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1819 if (id->atap_config & ATAPI_CFG_REMOV) 1820 periph->periph_flags |= PERIPH_REMOVABLE; 1821 if (periph->periph_type == T_SEQUENTIAL) { 1822 s = splbio(); 1823 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1824 splx(s); 1825 } 1826 1827 sa.sa_periph = periph; 1828 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1829 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1830 T_REMOV : T_FIXED; 1831 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1832 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1833 20); 1834 scsipi_strvis((u_char *)firmware_revision, 8, 1835 id->atap_revision, 8); 1836 sa.sa_inqbuf.vendor = model; 1837 sa.sa_inqbuf.product = serial_number; 1838 sa.sa_inqbuf.revision = firmware_revision; 1839 1840 /* 1841 * Determine the operating mode capabilities of the device. 1842 */ 1843 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1844 periph->periph_cap |= PERIPH_CAP_CMD16; 1845 /* XXX This is gross. */ 1846 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1847 1848 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1849 1850 if (drvp->drv_softc) 1851 ata_probe_caps(drvp); 1852 else { 1853 s = splbio(); 1854 drvp->drive_type = ATA_DRIVET_NONE; 1855 splx(s); 1856 } 1857 } else { 1858 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1859 "failed for drive %s:%d:%d: error 0x%x\n", 1860 AHCINAME(ahcic), chp->ch_channel, target, 1861 chp->ch_error), DEBUG_PROBE); 1862 s = splbio(); 1863 drvp->drive_type = ATA_DRIVET_NONE; 1864 splx(s); 1865 } 1866 } 1867 #endif /* NATAPIBUS */ 1868
Indexes created Fri Oct 17 00:09:41 GMT 2025