ahcisata_core.c revision 1.34
1 /* $NetBSD: ahcisata_core.c,v 1.34 2012/04/20 20:23:20 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.34 2012/04/20 20:23:20 bouyer Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ic/ahcisatavar.h> 46 47 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 48 49 #include "atapibus.h" 50 51 #ifdef AHCI_DEBUG 52 int ahcidebug_mask = 0x0; 53 #endif 54 55 static void ahci_probe_drive(struct ata_channel *); 56 static void ahci_setup_channel(struct ata_channel *); 57 58 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 59 static void ahci_reset_drive(struct ata_drive_datas *, int); 60 static void ahci_reset_channel(struct ata_channel *, int); 61 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 62 static int ahci_ata_addref(struct ata_drive_datas *); 63 static void ahci_ata_delref(struct ata_drive_datas *); 64 static void ahci_killpending(struct ata_drive_datas *); 65 66 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 67 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 68 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 69 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 70 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 74 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 75 static void ahci_timeout(void *); 76 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 77 78 #if NATAPIBUS > 0 79 static void ahci_atapibus_attach(struct atabus_softc *); 80 static void ahci_atapi_kill_pending(struct scsipi_periph *); 81 static void ahci_atapi_minphys(struct buf *); 82 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 83 scsipi_adapter_req_t, void *); 84 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 85 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 86 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 87 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 88 89 static const struct scsipi_bustype ahci_atapi_bustype = { 90 SCSIPI_BUSTYPE_ATAPI, 91 atapi_scsipi_cmd, 92 atapi_interpret_sense, 93 atapi_print_addr, 94 ahci_atapi_kill_pending, 95 NULL, 96 }; 97 #endif /* NATAPIBUS */ 98 99 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 100 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 101 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 102 103 const struct ata_bustype ahci_ata_bustype = { 104 SCSIPI_BUSTYPE_ATA, 105 ahci_ata_bio, 106 ahci_reset_drive, 107 ahci_reset_channel, 108 ahci_exec_command, 109 ata_get_params, 110 ahci_ata_addref, 111 ahci_ata_delref, 112 ahci_killpending 113 }; 114 115 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 116 static void ahci_setup_port(struct ahci_softc *sc, int i); 117 118 static int 119 ahci_reset(struct ahci_softc *sc) 120 { 121 int i; 122 123 /* reset controller */ 124 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 125 /* wait up to 1s for reset to complete */ 126 for (i = 0; i < 1000; i++) { 127 delay(1000); 128 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 129 break; 130 } 131 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 132 aprint_error("%s: reset failed\n", AHCINAME(sc)); 133 return -1; 134 } 135 /* enable ahci mode */ 136 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 137 return 0; 138 } 139 140 static void 141 ahci_setup_ports(struct ahci_softc *sc) 142 { 143 uint32_t ahci_ports; 144 int i, port; 145 146 ahci_ports = AHCI_READ(sc, AHCI_PI); 147 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 148 if ((ahci_ports & (1 << i)) == 0) 149 continue; 150 if (port >= sc->sc_atac.atac_nchannels) { 151 aprint_error("%s: more ports than announced\n", 152 AHCINAME(sc)); 153 break; 154 } 155 ahci_setup_port(sc, i); 156 } 157 } 158 159 static void 160 ahci_reprobe_drives(struct ahci_softc *sc) 161 { 162 uint32_t ahci_ports; 163 int i, port; 164 struct ahci_channel *achp; 165 struct ata_channel *chp; 166 167 ahci_ports = AHCI_READ(sc, AHCI_PI); 168 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 169 if ((ahci_ports & (1 << i)) == 0) 170 continue; 171 if (port >= sc->sc_atac.atac_nchannels) { 172 aprint_error("%s: more ports than announced\n", 173 AHCINAME(sc)); 174 break; 175 } 176 achp = &sc->sc_channels[i]; 177 chp = &achp->ata_channel; 178 179 ahci_probe_drive(chp); 180 } 181 } 182 183 static void 184 ahci_setup_port(struct ahci_softc *sc, int i) 185 { 186 struct ahci_channel *achp; 187 188 achp = &sc->sc_channels[i]; 189 190 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 191 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 192 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 193 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 194 } 195 196 static void 197 ahci_enable_intrs(struct ahci_softc *sc) 198 { 199 200 /* clear interrupts */ 201 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 202 /* enable interrupts */ 203 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 204 } 205 206 void 207 ahci_attach(struct ahci_softc *sc) 208 { 209 uint32_t ahci_cap, ahci_rev, ahci_ports; 210 int i, j, port; 211 struct ahci_channel *achp; 212 struct ata_channel *chp; 213 int error; 214 int dmasize; 215 char buf[128]; 216 void *cmdhp; 217 void *cmdtblp; 218 219 if (ahci_reset(sc) != 0) 220 return; 221 222 ahci_cap = AHCI_READ(sc, AHCI_CAP); 223 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 224 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 225 ahci_rev = AHCI_READ(sc, AHCI_VS); 226 snprintb(buf, sizeof(buf), "\177\020" 227 /* "f\000\005NP\0" */ 228 "b\005SXS\0" 229 "b\006EMS\0" 230 "b\007CCCS\0" 231 /* "f\010\005NCS\0" */ 232 "b\015PSC\0" 233 "b\016SSC\0" 234 "b\017PMD\0" 235 "b\020FBSS\0" 236 "b\021SPM\0" 237 "b\022SAM\0" 238 "b\023SNZO\0" 239 "f\024\003ISS\0" 240 "=\001Gen1\0" 241 "=\002Gen2\0" 242 "=\003Gen3\0" 243 "b\030SCLO\0" 244 "b\031SAL\0" 245 "b\032SALP\0" 246 "b\033SSS\0" 247 "b\034SMPS\0" 248 "b\035SSNTF\0" 249 "b\036SNCQ\0" 250 "b\037S64A\0" 251 "\0", ahci_cap); 252 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 253 ", %d ports, %d slots, CAP %s\n", 254 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 255 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 256 257 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 258 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 259 sc->sc_atac.atac_pio_cap = 4; 260 sc->sc_atac.atac_dma_cap = 2; 261 sc->sc_atac.atac_udma_cap = 6; 262 sc->sc_atac.atac_channels = sc->sc_chanarray; 263 sc->sc_atac.atac_probe = ahci_probe_drive; 264 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 265 sc->sc_atac.atac_set_modes = ahci_setup_channel; 266 #if NATAPIBUS > 0 267 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 268 #endif 269 270 dmasize = 271 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 272 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 273 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 274 if (error) { 275 aprint_error("%s: unable to allocate command header memory" 276 ", error=%d\n", AHCINAME(sc), error); 277 return; 278 } 279 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 280 sc->sc_cmd_hdr_nseg, dmasize, 281 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 282 if (error) { 283 aprint_error("%s: unable to map command header memory" 284 ", error=%d\n", AHCINAME(sc), error); 285 return; 286 } 287 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 288 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 289 if (error) { 290 aprint_error("%s: unable to create command header map" 291 ", error=%d\n", AHCINAME(sc), error); 292 return; 293 } 294 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 295 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 296 if (error) { 297 aprint_error("%s: unable to load command header map" 298 ", error=%d\n", AHCINAME(sc), error); 299 return; 300 } 301 sc->sc_cmd_hdr = cmdhp; 302 303 ahci_enable_intrs(sc); 304 305 ahci_ports = AHCI_READ(sc, AHCI_PI); 306 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 307 if ((ahci_ports & (1 << i)) == 0) 308 continue; 309 if (port >= sc->sc_atac.atac_nchannels) { 310 aprint_error("%s: more ports than announced\n", 311 AHCINAME(sc)); 312 break; 313 } 314 achp = &sc->sc_channels[i]; 315 chp = &achp->ata_channel; 316 sc->sc_chanarray[i] = chp; 317 chp->ch_channel = i; 318 chp->ch_atac = &sc->sc_atac; 319 chp->ch_queue = malloc(sizeof(struct ata_queue), 320 M_DEVBUF, M_NOWAIT); 321 if (chp->ch_queue == NULL) { 322 aprint_error("%s port %d: can't allocate memory for " 323 "command queue", AHCINAME(sc), i); 324 break; 325 } 326 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 327 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 328 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 329 BUS_DMA_NOWAIT); 330 if (error) { 331 aprint_error("%s: unable to allocate command table " 332 "memory, error=%d\n", AHCINAME(sc), error); 333 break; 334 } 335 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 336 achp->ahcic_cmd_tbl_nseg, dmasize, 337 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 338 if (error) { 339 aprint_error("%s: unable to map command table memory" 340 ", error=%d\n", AHCINAME(sc), error); 341 break; 342 } 343 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 344 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 345 if (error) { 346 aprint_error("%s: unable to create command table map" 347 ", error=%d\n", AHCINAME(sc), error); 348 break; 349 } 350 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 351 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 352 if (error) { 353 aprint_error("%s: unable to load command table map" 354 ", error=%d\n", AHCINAME(sc), error); 355 break; 356 } 357 achp->ahcic_cmdh = (struct ahci_cmd_header *) 358 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 359 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 360 AHCI_CMDH_SIZE * port; 361 achp->ahcic_rfis = (struct ahci_r_fis *) 362 ((char *)cmdhp + 363 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 364 AHCI_RFIS_SIZE * port); 365 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 366 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 367 AHCI_RFIS_SIZE * port; 368 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 369 "rfis %p (0x%" PRIx64 ")\n", i, 370 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 371 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 372 DEBUG_PROBE); 373 374 for (j = 0; j < sc->sc_ncmds; j++) { 375 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 376 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 377 achp->ahcic_bus_cmd_tbl[j] = 378 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 379 AHCI_CMDTBL_SIZE * j; 380 achp->ahcic_cmdh[j].cmdh_cmdtba = 381 htole64(achp->ahcic_bus_cmd_tbl[j]); 382 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 383 achp->ahcic_cmd_tbl[j], 384 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 385 /* The xfer DMA map */ 386 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 387 AHCI_NPRD, 0x400000 /* 4MB */, 0, 388 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 389 &achp->ahcic_datad[j]); 390 if (error) { 391 aprint_error("%s: couldn't alloc xfer DMA map, " 392 "error=%d\n", AHCINAME(sc), error); 393 goto end; 394 } 395 } 396 ahci_setup_port(sc, i); 397 chp->ch_ndrive = 1; 398 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 399 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 400 aprint_error("%s: couldn't map channel %d " 401 "sata_status regs\n", AHCINAME(sc), i); 402 break; 403 } 404 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 405 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 406 aprint_error("%s: couldn't map channel %d " 407 "sata_control regs\n", AHCINAME(sc), i); 408 break; 409 } 410 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 411 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 412 aprint_error("%s: couldn't map channel %d " 413 "sata_error regs\n", AHCINAME(sc), i); 414 break; 415 } 416 ata_channel_attach(chp); 417 port++; 418 end: 419 continue; 420 } 421 } 422 423 int 424 ahci_detach(struct ahci_softc *sc, int flags) 425 { 426 struct atac_softc *atac; 427 struct ahci_channel *achp; 428 struct ata_channel *chp; 429 struct scsipi_adapter *adapt; 430 uint32_t ahci_ports; 431 int i, j; 432 int error; 433 434 atac = &sc->sc_atac; 435 adapt = &atac->atac_atapi_adapter._generic; 436 437 ahci_ports = AHCI_READ(sc, AHCI_PI); 438 for (i = 0; i < AHCI_MAX_PORTS; i++) { 439 achp = &sc->sc_channels[i]; 440 chp = &achp->ata_channel; 441 442 if ((ahci_ports & (1 << i)) == 0) 443 continue; 444 if (i >= sc->sc_atac.atac_nchannels) { 445 aprint_error("%s: more ports than announced\n", 446 AHCINAME(sc)); 447 break; 448 } 449 450 if (chp->atabus == NULL) 451 continue; 452 if ((error = config_detach(chp->atabus, flags)) != 0) 453 return error; 454 455 for (j = 0; j < sc->sc_ncmds; j++) 456 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 457 458 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 459 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 460 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 461 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 462 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 463 achp->ahcic_cmd_tbl_nseg); 464 465 free(chp->ch_queue, M_DEVBUF); 466 chp->atabus = NULL; 467 } 468 469 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 470 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 471 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 472 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 473 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 474 475 if (adapt->adapt_refcnt != 0) 476 return EBUSY; 477 478 return 0; 479 } 480 481 void 482 ahci_resume(struct ahci_softc *sc) 483 { 484 ahci_reset(sc); 485 ahci_setup_ports(sc); 486 ahci_reprobe_drives(sc); 487 ahci_enable_intrs(sc); 488 } 489 490 int 491 ahci_intr(void *v) 492 { 493 struct ahci_softc *sc = v; 494 uint32_t is; 495 int i, r = 0; 496 497 while ((is = AHCI_READ(sc, AHCI_IS))) { 498 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 499 DEBUG_INTR); 500 r = 1; 501 AHCI_WRITE(sc, AHCI_IS, is); 502 for (i = 0; i < AHCI_MAX_PORTS; i++) 503 if (is & (1 << i)) 504 ahci_intr_port(sc, &sc->sc_channels[i]); 505 } 506 return r; 507 } 508 509 static void 510 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 511 { 512 uint32_t is, tfd; 513 struct ata_channel *chp = &achp->ata_channel; 514 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 515 int slot; 516 517 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 518 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 519 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 520 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 521 DEBUG_INTR); 522 523 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 524 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 525 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 526 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 527 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 528 return; 529 /* stop channel */ 530 ahci_channel_stop(sc, chp, 0); 531 if (slot != 0) { 532 printf("ahci_intr_port: slot %d\n", slot); 533 panic("ahci_intr_port"); 534 } 535 if (is & AHCI_P_IX_TFES) { 536 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 537 chp->ch_error = 538 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 539 chp->ch_status = (tfd & 0xff); 540 } else { 541 /* emulate a CRC error */ 542 chp->ch_error = WDCE_CRC; 543 chp->ch_status = WDCS_ERR; 544 } 545 xfer->c_intr(chp, xfer, is); 546 /* if channel has not been restarted, do it now */ 547 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 548 == 0) 549 ahci_channel_start(sc, chp); 550 } else { 551 slot = 0; /* XXX */ 552 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 553 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 554 chp->ch_channel, is, achp->ahcic_cmds_active, 555 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 556 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 557 return; 558 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 559 == 0) { 560 xfer->c_intr(chp, xfer, 0); 561 } 562 } 563 } 564 565 static void 566 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 567 { 568 struct ata_channel *chp = drvp->chnl_softc; 569 ata_reset_channel(chp, flags); 570 return; 571 } 572 573 static void 574 ahci_reset_channel(struct ata_channel *chp, int flags) 575 { 576 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 577 struct ahci_channel *achp = (struct ahci_channel *)chp; 578 int i, tfd; 579 580 ahci_channel_stop(sc, chp, flags); 581 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 582 achp->ahcic_sstatus) != SStatus_DET_DEV) { 583 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 584 /* XXX and then ? */ 585 } 586 if (chp->ch_queue->active_xfer) { 587 chp->ch_queue->active_xfer->c_kill_xfer(chp, 588 chp->ch_queue->active_xfer, KILL_RESET); 589 } 590 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 591 /* clear port interrupt register */ 592 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 593 /* clear SErrors and start operations */ 594 ahci_channel_start(sc, chp); 595 /* wait 31s for BSY to clear */ 596 for (i = 0; i <AHCI_RST_WAIT; i++) { 597 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 598 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 599 & WDCS_BSY) == 0) 600 break; 601 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 602 } 603 if (i == AHCI_RST_WAIT) 604 aprint_error("%s: BSY never cleared, TD 0x%x\n", 605 AHCINAME(sc), tfd); 606 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 607 DEBUG_PROBE); 608 /* clear port interrupt register */ 609 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 610 611 return; 612 } 613 614 static int 615 ahci_ata_addref(struct ata_drive_datas *drvp) 616 { 617 return 0; 618 } 619 620 static void 621 ahci_ata_delref(struct ata_drive_datas *drvp) 622 { 623 return; 624 } 625 626 static void 627 ahci_killpending(struct ata_drive_datas *drvp) 628 { 629 return; 630 } 631 632 static void 633 ahci_probe_drive(struct ata_channel *chp) 634 { 635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 636 struct ahci_channel *achp = (struct ahci_channel *)chp; 637 int i, s; 638 uint32_t sig; 639 640 /* XXX This should be done by other code. */ 641 for (i = 0; i < chp->ch_ndrive; i++) { 642 chp->ch_drive[i].chnl_softc = chp; 643 chp->ch_drive[i].drive = i; 644 } 645 646 /* bring interface up, accept FISs, power up and spin up device */ 647 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 648 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 649 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 650 /* reset the PHY and bring online */ 651 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 652 achp->ahcic_sstatus)) { 653 case SStatus_DET_DEV: 654 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 655 /* clear port interrupt register */ 656 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 657 /* clear SErrors and start operations */ 658 ahci_channel_start(sc, chp); 659 /* wait 31s for BSY to clear */ 660 for (i = 0; i <AHCI_RST_WAIT; i++) { 661 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 662 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 663 & WDCS_BSY) == 0) 664 break; 665 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 666 } 667 if (i == AHCI_RST_WAIT) { 668 aprint_error("%s: BSY never cleared, TD 0x%x\n", 669 AHCINAME(sc), sig); 670 return; 671 } 672 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 673 DEBUG_PROBE); 674 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 675 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 676 AHCINAME(sc), chp->ch_channel, sig, 677 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 678 /* 679 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 680 * cases we get wrong values here, so ignore it. 681 */ 682 s = splbio(); 683 if ((sig & 0xffff0000) == 0xeb140000) { 684 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 685 } else 686 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 687 splx(s); 688 /* clear port interrupt register */ 689 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 690 /* and enable interrupts */ 691 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 692 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 693 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 694 AHCI_P_IX_DHRS); 695 /* wait 500ms before actually starting operations */ 696 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 697 break; 698 699 default: 700 break; 701 } 702 } 703 704 static void 705 ahci_setup_channel(struct ata_channel *chp) 706 { 707 return; 708 } 709 710 static int 711 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 712 { 713 struct ata_channel *chp = drvp->chnl_softc; 714 struct ata_xfer *xfer; 715 int ret; 716 int s; 717 718 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 719 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 720 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 721 DEBUG_XFERS); 722 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 723 ATAXF_NOSLEEP); 724 if (xfer == NULL) { 725 return ATACMD_TRY_AGAIN; 726 } 727 if (ata_c->flags & AT_POLL) 728 xfer->c_flags |= C_POLL; 729 if (ata_c->flags & AT_WAIT) 730 xfer->c_flags |= C_WAIT; 731 xfer->c_drive = drvp->drive; 732 xfer->c_databuf = ata_c->data; 733 xfer->c_bcount = ata_c->bcount; 734 xfer->c_cmd = ata_c; 735 xfer->c_start = ahci_cmd_start; 736 xfer->c_intr = ahci_cmd_complete; 737 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 738 s = splbio(); 739 ata_exec_xfer(chp, xfer); 740 #ifdef DIAGNOSTIC 741 if ((ata_c->flags & AT_POLL) != 0 && 742 (ata_c->flags & AT_DONE) == 0) 743 panic("ahci_exec_command: polled command not done"); 744 #endif 745 if (ata_c->flags & AT_DONE) { 746 ret = ATACMD_COMPLETE; 747 } else { 748 if (ata_c->flags & AT_WAIT) { 749 while ((ata_c->flags & AT_DONE) == 0) { 750 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 751 } 752 ret = ATACMD_COMPLETE; 753 } else { 754 ret = ATACMD_QUEUED; 755 } 756 } 757 splx(s); 758 return ret; 759 } 760 761 static void 762 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 763 { 764 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 765 struct ahci_channel *achp = (struct ahci_channel *)chp; 766 struct ata_command *ata_c = xfer->c_cmd; 767 int slot = 0 /* XXX slot */; 768 struct ahci_cmd_tbl *cmd_tbl; 769 struct ahci_cmd_header *cmd_h; 770 int i; 771 int channel = chp->ch_channel; 772 773 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 774 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 775 776 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 777 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 778 cmd_tbl), DEBUG_XFERS); 779 780 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 781 782 cmd_h = &achp->ahcic_cmdh[slot]; 783 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 784 chp->ch_channel, cmd_h), DEBUG_XFERS); 785 if (ahci_dma_setup(chp, slot, 786 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 787 ata_c->data : NULL, 788 ata_c->bcount, 789 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 790 ata_c->flags |= AT_DF; 791 ahci_cmd_complete(chp, xfer, slot); 792 return; 793 } 794 cmd_h->cmdh_flags = htole16( 795 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 796 RHD_FISLEN / 4); 797 cmd_h->cmdh_prdbc = 0; 798 AHCI_CMDH_SYNC(sc, achp, slot, 799 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 800 801 if (ata_c->flags & AT_POLL) { 802 /* polled command, disable interrupts */ 803 AHCI_WRITE(sc, AHCI_GHC, 804 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 805 } 806 chp->ch_flags |= ATACH_IRQ_WAIT; 807 chp->ch_status = 0; 808 /* start command */ 809 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 810 /* and says we started this command */ 811 achp->ahcic_cmds_active |= 1 << slot; 812 813 if ((ata_c->flags & AT_POLL) == 0) { 814 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 815 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 816 ahci_timeout, chp); 817 return; 818 } 819 /* 820 * Polled command. 821 */ 822 for (i = 0; i < ata_c->timeout / 10; i++) { 823 if (ata_c->flags & AT_DONE) 824 break; 825 ahci_intr_port(sc, achp); 826 if (ata_c->flags & AT_WAIT) 827 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 828 else 829 delay(10000); 830 } 831 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 832 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 833 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 834 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 835 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 836 DEBUG_XFERS); 837 if ((ata_c->flags & AT_DONE) == 0) { 838 ata_c->flags |= AT_TIMEOU; 839 ahci_cmd_complete(chp, xfer, slot); 840 } 841 /* reenable interrupts */ 842 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 843 } 844 845 static void 846 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 847 { 848 struct ata_command *ata_c = xfer->c_cmd; 849 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 850 DEBUG_FUNCS); 851 852 switch (reason) { 853 case KILL_GONE: 854 ata_c->flags |= AT_GONE; 855 break; 856 case KILL_RESET: 857 ata_c->flags |= AT_RESET; 858 break; 859 default: 860 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 861 panic("ahci_cmd_kill_xfer"); 862 } 863 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 864 } 865 866 static int 867 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 868 { 869 int slot = 0; /* XXX slot */ 870 struct ata_command *ata_c = xfer->c_cmd; 871 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 872 struct ahci_channel *achp = (struct ahci_channel *)chp; 873 874 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 875 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 876 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 877 DEBUG_FUNCS); 878 chp->ch_flags &= ~ATACH_IRQ_WAIT; 879 if (xfer->c_flags & C_TIMEOU) { 880 ata_c->flags |= AT_TIMEOU; 881 } else 882 callout_stop(&chp->ch_callout); 883 884 chp->ch_queue->active_xfer = NULL; 885 886 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 887 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 888 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 889 wakeup(&chp->ch_queue->active_xfer); 890 return 0; 891 } 892 893 if (chp->ch_status & WDCS_BSY) { 894 ata_c->flags |= AT_TIMEOU; 895 } else if (chp->ch_status & WDCS_ERR) { 896 ata_c->r_error = chp->ch_error; 897 ata_c->flags |= AT_ERROR; 898 } 899 900 if (ata_c->flags & AT_READREG) 901 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 902 903 ahci_cmd_done(chp, xfer, slot); 904 return 0; 905 } 906 907 static void 908 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 909 { 910 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 911 struct ahci_channel *achp = (struct ahci_channel *)chp; 912 struct ata_command *ata_c = xfer->c_cmd; 913 uint16_t *idwordbuf; 914 int i; 915 916 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 917 DEBUG_FUNCS); 918 919 /* this comamnd is not active any more */ 920 achp->ahcic_cmds_active &= ~(1 << slot); 921 922 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 923 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 924 achp->ahcic_datad[slot]->dm_mapsize, 925 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 926 BUS_DMASYNC_POSTWRITE); 927 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 928 } 929 930 AHCI_CMDH_SYNC(sc, achp, slot, 931 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 932 933 /* ata(4) expects IDENTIFY data to be in host endianess */ 934 if (ata_c->r_command == WDCC_IDENTIFY || 935 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 936 idwordbuf = xfer->c_databuf; 937 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 938 idwordbuf[i] = le16toh(idwordbuf[i]); 939 } 940 } 941 942 ata_c->flags |= AT_DONE; 943 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 944 ata_c->flags |= AT_XFDONE; 945 946 ata_free_xfer(chp, xfer); 947 if (ata_c->flags & AT_WAIT) 948 wakeup(ata_c); 949 else if (ata_c->callback) 950 ata_c->callback(ata_c->callback_arg); 951 atastart(chp); 952 return; 953 } 954 955 static int 956 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 957 { 958 struct ata_channel *chp = drvp->chnl_softc; 959 struct ata_xfer *xfer; 960 961 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 962 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 963 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 964 DEBUG_XFERS); 965 xfer = ata_get_xfer(ATAXF_NOSLEEP); 966 if (xfer == NULL) { 967 return ATACMD_TRY_AGAIN; 968 } 969 if (ata_bio->flags & ATA_POLL) 970 xfer->c_flags |= C_POLL; 971 xfer->c_drive = drvp->drive; 972 xfer->c_cmd = ata_bio; 973 xfer->c_databuf = ata_bio->databuf; 974 xfer->c_bcount = ata_bio->bcount; 975 xfer->c_start = ahci_bio_start; 976 xfer->c_intr = ahci_bio_complete; 977 xfer->c_kill_xfer = ahci_bio_kill_xfer; 978 ata_exec_xfer(chp, xfer); 979 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 980 } 981 982 static void 983 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 984 { 985 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 986 struct ahci_channel *achp = (struct ahci_channel *)chp; 987 struct ata_bio *ata_bio = xfer->c_cmd; 988 int slot = 0 /* XXX slot */; 989 struct ahci_cmd_tbl *cmd_tbl; 990 struct ahci_cmd_header *cmd_h; 991 int i; 992 int channel = chp->ch_channel; 993 994 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 995 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 996 997 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 998 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 999 cmd_tbl), DEBUG_XFERS); 1000 1001 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1002 1003 cmd_h = &achp->ahcic_cmdh[slot]; 1004 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1005 chp->ch_channel, cmd_h), DEBUG_XFERS); 1006 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1007 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1008 ata_bio->error = ERR_DMA; 1009 ata_bio->r_error = 0; 1010 ahci_bio_complete(chp, xfer, slot); 1011 return; 1012 } 1013 cmd_h->cmdh_flags = htole16( 1014 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1015 RHD_FISLEN / 4); 1016 cmd_h->cmdh_prdbc = 0; 1017 AHCI_CMDH_SYNC(sc, achp, slot, 1018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1019 1020 if (xfer->c_flags & C_POLL) { 1021 /* polled command, disable interrupts */ 1022 AHCI_WRITE(sc, AHCI_GHC, 1023 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1024 } 1025 chp->ch_flags |= ATACH_IRQ_WAIT; 1026 chp->ch_status = 0; 1027 /* start command */ 1028 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1029 /* and says we started this command */ 1030 achp->ahcic_cmds_active |= 1 << slot; 1031 1032 if ((xfer->c_flags & C_POLL) == 0) { 1033 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1034 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1035 ahci_timeout, chp); 1036 return; 1037 } 1038 /* 1039 * Polled command. 1040 */ 1041 for (i = 0; i < ATA_DELAY / 10; i++) { 1042 if (ata_bio->flags & ATA_ITSDONE) 1043 break; 1044 ahci_intr_port(sc, achp); 1045 if (ata_bio->flags & ATA_NOSLEEP) 1046 delay(10000); 1047 else 1048 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1049 } 1050 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1051 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1052 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1053 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1054 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1055 DEBUG_XFERS); 1056 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1057 ata_bio->error = TIMEOUT; 1058 ahci_bio_complete(chp, xfer, slot); 1059 } 1060 /* reenable interrupts */ 1061 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1062 } 1063 1064 static void 1065 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1066 { 1067 int slot = 0; /* XXX slot */ 1068 int drive = xfer->c_drive; 1069 struct ata_bio *ata_bio = xfer->c_cmd; 1070 struct ahci_channel *achp = (struct ahci_channel *)chp; 1071 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1072 DEBUG_FUNCS); 1073 1074 achp->ahcic_cmds_active &= ~(1 << slot); 1075 ata_free_xfer(chp, xfer); 1076 ata_bio->flags |= ATA_ITSDONE; 1077 switch (reason) { 1078 case KILL_GONE: 1079 ata_bio->error = ERR_NODEV; 1080 break; 1081 case KILL_RESET: 1082 ata_bio->error = ERR_RESET; 1083 break; 1084 default: 1085 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1086 panic("ahci_bio_kill_xfer"); 1087 } 1088 ata_bio->r_error = WDCE_ABRT; 1089 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1090 } 1091 1092 static int 1093 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1094 { 1095 int slot = 0; /* XXX slot */ 1096 struct ata_bio *ata_bio = xfer->c_cmd; 1097 int drive = xfer->c_drive; 1098 struct ahci_channel *achp = (struct ahci_channel *)chp; 1099 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1100 1101 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1102 DEBUG_FUNCS); 1103 1104 achp->ahcic_cmds_active &= ~(1 << slot); 1105 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1106 if (xfer->c_flags & C_TIMEOU) { 1107 ata_bio->error = TIMEOUT; 1108 } else { 1109 callout_stop(&chp->ch_callout); 1110 ata_bio->error = NOERROR; 1111 } 1112 1113 chp->ch_queue->active_xfer = NULL; 1114 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1115 achp->ahcic_datad[slot]->dm_mapsize, 1116 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1117 BUS_DMASYNC_POSTWRITE); 1118 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1119 1120 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1121 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1122 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1123 wakeup(&chp->ch_queue->active_xfer); 1124 return 0; 1125 } 1126 ata_free_xfer(chp, xfer); 1127 ata_bio->flags |= ATA_ITSDONE; 1128 if (chp->ch_status & WDCS_DWF) { 1129 ata_bio->error = ERR_DF; 1130 } else if (chp->ch_status & WDCS_ERR) { 1131 ata_bio->error = ERROR; 1132 ata_bio->r_error = chp->ch_error; 1133 } else if (chp->ch_status & WDCS_CORR) 1134 ata_bio->flags |= ATA_CORR; 1135 1136 AHCI_CMDH_SYNC(sc, achp, slot, 1137 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1138 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1139 ata_bio->bcount), DEBUG_XFERS); 1140 /* 1141 * if it was a write, complete data buffer may have been transfered 1142 * before error detection; in this case don't use cmdh_prdbc 1143 * as it won't reflect what was written to media. Assume nothing 1144 * was transfered and leave bcount as-is. 1145 */ 1146 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1147 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1148 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1149 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1150 atastart(chp); 1151 return 0; 1152 } 1153 1154 static void 1155 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1156 { 1157 int i; 1158 /* stop channel */ 1159 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1160 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1161 /* wait 1s for channel to stop */ 1162 for (i = 0; i <100; i++) { 1163 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1164 == 0) 1165 break; 1166 if (flags & AT_WAIT) 1167 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1168 else 1169 delay(10000); 1170 } 1171 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1172 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1173 /* XXX controller reset ? */ 1174 return; 1175 } 1176 } 1177 1178 static void 1179 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1180 { 1181 /* clear error */ 1182 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1183 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1184 1185 /* and start controller */ 1186 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1187 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1188 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1189 } 1190 1191 static void 1192 ahci_timeout(void *v) 1193 { 1194 struct ata_channel *chp = (struct ata_channel *)v; 1195 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1196 int s = splbio(); 1197 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1198 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1199 xfer->c_flags |= C_TIMEOU; 1200 xfer->c_intr(chp, xfer, 0); 1201 } 1202 splx(s); 1203 } 1204 1205 static int 1206 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1207 size_t count, int op) 1208 { 1209 int error, seg; 1210 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1211 struct ahci_channel *achp = (struct ahci_channel *)chp; 1212 struct ahci_cmd_tbl *cmd_tbl; 1213 struct ahci_cmd_header *cmd_h; 1214 1215 cmd_h = &achp->ahcic_cmdh[slot]; 1216 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1217 1218 if (data == NULL) { 1219 cmd_h->cmdh_prdtl = 0; 1220 goto end; 1221 } 1222 1223 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1224 data, count, NULL, 1225 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1226 if (error) { 1227 printf("%s port %d: failed to load xfer: %d\n", 1228 AHCINAME(sc), chp->ch_channel, error); 1229 return error; 1230 } 1231 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1232 achp->ahcic_datad[slot]->dm_mapsize, 1233 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1234 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1235 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1236 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1237 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1238 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1239 } 1240 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1241 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1242 end: 1243 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1244 return 0; 1245 } 1246 1247 #if NATAPIBUS > 0 1248 static void 1249 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1250 { 1251 struct ata_channel *chp = ata_sc->sc_chan; 1252 struct atac_softc *atac = chp->ch_atac; 1253 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1254 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1255 /* 1256 * Fill in the scsipi_adapter. 1257 */ 1258 adapt->adapt_dev = atac->atac_dev; 1259 adapt->adapt_nchannels = atac->atac_nchannels; 1260 adapt->adapt_request = ahci_atapi_scsipi_request; 1261 adapt->adapt_minphys = ahci_atapi_minphys; 1262 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1263 1264 /* 1265 * Fill in the scsipi_channel. 1266 */ 1267 memset(chan, 0, sizeof(*chan)); 1268 chan->chan_adapter = adapt; 1269 chan->chan_bustype = &ahci_atapi_bustype; 1270 chan->chan_channel = chp->ch_channel; 1271 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1272 chan->chan_openings = 1; 1273 chan->chan_max_periph = 1; 1274 chan->chan_ntargets = 1; 1275 chan->chan_nluns = 1; 1276 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1277 atapiprint); 1278 } 1279 1280 static void 1281 ahci_atapi_minphys(struct buf *bp) 1282 { 1283 if (bp->b_bcount > MAXPHYS) 1284 bp->b_bcount = MAXPHYS; 1285 minphys(bp); 1286 } 1287 1288 /* 1289 * Kill off all pending xfers for a periph. 1290 * 1291 * Must be called at splbio(). 1292 */ 1293 static void 1294 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1295 { 1296 struct atac_softc *atac = 1297 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1298 struct ata_channel *chp = 1299 atac->atac_channels[periph->periph_channel->chan_channel]; 1300 1301 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1302 } 1303 1304 static void 1305 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1306 scsipi_adapter_req_t req, void *arg) 1307 { 1308 struct scsipi_adapter *adapt = chan->chan_adapter; 1309 struct scsipi_periph *periph; 1310 struct scsipi_xfer *sc_xfer; 1311 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1312 struct atac_softc *atac = &sc->sc_atac; 1313 struct ata_xfer *xfer; 1314 int channel = chan->chan_channel; 1315 int drive, s; 1316 1317 switch (req) { 1318 case ADAPTER_REQ_RUN_XFER: 1319 sc_xfer = arg; 1320 periph = sc_xfer->xs_periph; 1321 drive = periph->periph_target; 1322 if (!device_is_active(atac->atac_dev)) { 1323 sc_xfer->error = XS_DRIVER_STUFFUP; 1324 scsipi_done(sc_xfer); 1325 return; 1326 } 1327 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1328 if (xfer == NULL) { 1329 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1330 scsipi_done(sc_xfer); 1331 return; 1332 } 1333 1334 if (sc_xfer->xs_control & XS_CTL_POLL) 1335 xfer->c_flags |= C_POLL; 1336 xfer->c_drive = drive; 1337 xfer->c_flags |= C_ATAPI; 1338 xfer->c_cmd = sc_xfer; 1339 xfer->c_databuf = sc_xfer->data; 1340 xfer->c_bcount = sc_xfer->datalen; 1341 xfer->c_start = ahci_atapi_start; 1342 xfer->c_intr = ahci_atapi_complete; 1343 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1344 xfer->c_dscpoll = 0; 1345 s = splbio(); 1346 ata_exec_xfer(atac->atac_channels[channel], xfer); 1347 #ifdef DIAGNOSTIC 1348 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1349 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1350 panic("ahci_atapi_scsipi_request: polled command " 1351 "not done"); 1352 #endif 1353 splx(s); 1354 return; 1355 default: 1356 /* Not supported, nothing to do. */ 1357 ; 1358 } 1359 } 1360 1361 static void 1362 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1363 { 1364 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1365 struct ahci_channel *achp = (struct ahci_channel *)chp; 1366 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1367 int slot = 0 /* XXX slot */; 1368 struct ahci_cmd_tbl *cmd_tbl; 1369 struct ahci_cmd_header *cmd_h; 1370 int i; 1371 int channel = chp->ch_channel; 1372 1373 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1374 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1375 1376 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1377 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1378 cmd_tbl), DEBUG_XFERS); 1379 1380 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1381 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1382 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1383 1384 cmd_h = &achp->ahcic_cmdh[slot]; 1385 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1386 chp->ch_channel, cmd_h), DEBUG_XFERS); 1387 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1388 sc_xfer->datalen, 1389 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1390 BUS_DMA_READ : BUS_DMA_WRITE)) { 1391 sc_xfer->error = XS_DRIVER_STUFFUP; 1392 ahci_atapi_complete(chp, xfer, slot); 1393 return; 1394 } 1395 cmd_h->cmdh_flags = htole16( 1396 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1397 RHD_FISLEN / 4 | AHCI_CMDH_F_A); 1398 cmd_h->cmdh_prdbc = 0; 1399 AHCI_CMDH_SYNC(sc, achp, slot, 1400 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1401 1402 if (xfer->c_flags & C_POLL) { 1403 /* polled command, disable interrupts */ 1404 AHCI_WRITE(sc, AHCI_GHC, 1405 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1406 } 1407 chp->ch_flags |= ATACH_IRQ_WAIT; 1408 chp->ch_status = 0; 1409 /* start command */ 1410 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1411 /* and says we started this command */ 1412 achp->ahcic_cmds_active |= 1 << slot; 1413 1414 if ((xfer->c_flags & C_POLL) == 0) { 1415 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1416 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1417 ahci_timeout, chp); 1418 return; 1419 } 1420 /* 1421 * Polled command. 1422 */ 1423 for (i = 0; i < ATA_DELAY / 10; i++) { 1424 if (sc_xfer->xs_status & XS_STS_DONE) 1425 break; 1426 ahci_intr_port(sc, achp); 1427 delay(10000); 1428 } 1429 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1430 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1431 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1432 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1433 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1434 DEBUG_XFERS); 1435 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1436 sc_xfer->error = XS_TIMEOUT; 1437 ahci_atapi_complete(chp, xfer, slot); 1438 } 1439 /* reenable interrupts */ 1440 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1441 } 1442 1443 static int 1444 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1445 { 1446 int slot = 0; /* XXX slot */ 1447 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1448 int drive = xfer->c_drive; 1449 struct ahci_channel *achp = (struct ahci_channel *)chp; 1450 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1451 1452 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1453 DEBUG_FUNCS); 1454 1455 achp->ahcic_cmds_active &= ~(1 << slot); 1456 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1457 if (xfer->c_flags & C_TIMEOU) { 1458 sc_xfer->error = XS_TIMEOUT; 1459 } else { 1460 callout_stop(&chp->ch_callout); 1461 sc_xfer->error = 0; 1462 } 1463 1464 chp->ch_queue->active_xfer = NULL; 1465 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1466 achp->ahcic_datad[slot]->dm_mapsize, 1467 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1468 BUS_DMASYNC_POSTWRITE); 1469 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1470 1471 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1472 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1473 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1474 wakeup(&chp->ch_queue->active_xfer); 1475 return 0; 1476 } 1477 ata_free_xfer(chp, xfer); 1478 1479 AHCI_CMDH_SYNC(sc, achp, slot, 1480 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1481 sc_xfer->resid = sc_xfer->datalen; 1482 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1483 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1484 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1485 if (chp->ch_status & WDCS_ERR && 1486 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1487 sc_xfer->resid == sc_xfer->datalen)) { 1488 sc_xfer->error = XS_SHORTSENSE; 1489 sc_xfer->sense.atapi_sense = chp->ch_error; 1490 if ((sc_xfer->xs_periph->periph_quirks & 1491 PQUIRK_NOSENSE) == 0) { 1492 /* ask scsipi to send a REQUEST_SENSE */ 1493 sc_xfer->error = XS_BUSY; 1494 sc_xfer->status = SCSI_CHECK; 1495 } 1496 } 1497 scsipi_done(sc_xfer); 1498 atastart(chp); 1499 return 0; 1500 } 1501 1502 static void 1503 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1504 { 1505 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1506 struct ahci_channel *achp = (struct ahci_channel *)chp; 1507 int slot = 0; /* XXX slot */ 1508 1509 achp->ahcic_cmds_active &= ~(1 << slot); 1510 1511 /* remove this command from xfer queue */ 1512 switch (reason) { 1513 case KILL_GONE: 1514 sc_xfer->error = XS_DRIVER_STUFFUP; 1515 break; 1516 case KILL_RESET: 1517 sc_xfer->error = XS_RESET; 1518 break; 1519 default: 1520 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1521 panic("ahci_ata_atapi_kill_xfer"); 1522 } 1523 ata_free_xfer(chp, xfer); 1524 scsipi_done(sc_xfer); 1525 } 1526 1527 static void 1528 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1529 { 1530 struct scsipi_channel *chan = sc->sc_channel; 1531 struct scsipi_periph *periph; 1532 struct ataparams ids; 1533 struct ataparams *id = &ids; 1534 struct ahci_softc *ahcic = 1535 device_private(chan->chan_adapter->adapt_dev); 1536 struct atac_softc *atac = &ahcic->sc_atac; 1537 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1538 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1539 struct scsipibus_attach_args sa; 1540 char serial_number[21], model[41], firmware_revision[9]; 1541 int s; 1542 1543 /* skip if already attached */ 1544 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1545 return; 1546 1547 /* if no ATAPI device detected at attach time, skip */ 1548 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1549 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1550 "not present\n", target), DEBUG_PROBE); 1551 return; 1552 } 1553 1554 /* Some ATAPI devices need a bit more time after software reset. */ 1555 delay(5000); 1556 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1557 #ifdef ATAPI_DEBUG_PROBE 1558 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1559 AHCINAME(ahcic), target, 1560 id->atap_config & ATAPI_CFG_CMD_MASK, 1561 id->atap_config & ATAPI_CFG_DRQ_MASK); 1562 #endif 1563 periph = scsipi_alloc_periph(M_NOWAIT); 1564 if (periph == NULL) { 1565 aprint_error_dev(sc->sc_dev, 1566 "unable to allocate periph for drive %d\n", 1567 target); 1568 return; 1569 } 1570 periph->periph_dev = NULL; 1571 periph->periph_channel = chan; 1572 periph->periph_switch = &atapi_probe_periphsw; 1573 periph->periph_target = target; 1574 periph->periph_lun = 0; 1575 periph->periph_quirks = PQUIRK_ONLYBIG; 1576 1577 #ifdef SCSIPI_DEBUG 1578 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1579 SCSIPI_DEBUG_TARGET == target) 1580 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1581 #endif 1582 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1583 if (id->atap_config & ATAPI_CFG_REMOV) 1584 periph->periph_flags |= PERIPH_REMOVABLE; 1585 if (periph->periph_type == T_SEQUENTIAL) { 1586 s = splbio(); 1587 drvp->drive_flags |= DRIVE_ATAPIST; 1588 splx(s); 1589 } 1590 1591 sa.sa_periph = periph; 1592 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1593 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1594 T_REMOV : T_FIXED; 1595 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1596 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1597 20); 1598 scsipi_strvis((u_char *)firmware_revision, 8, 1599 id->atap_revision, 8); 1600 sa.sa_inqbuf.vendor = model; 1601 sa.sa_inqbuf.product = serial_number; 1602 sa.sa_inqbuf.revision = firmware_revision; 1603 1604 /* 1605 * Determine the operating mode capabilities of the device. 1606 */ 1607 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1608 periph->periph_cap |= PERIPH_CAP_CMD16; 1609 /* XXX This is gross. */ 1610 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1611 1612 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1613 1614 if (drvp->drv_softc) 1615 ata_probe_caps(drvp); 1616 else { 1617 s = splbio(); 1618 drvp->drive_flags &= ~DRIVE_ATAPI; 1619 splx(s); 1620 } 1621 } else { 1622 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1623 "failed for drive %s:%d:%d: error 0x%x\n", 1624 AHCINAME(ahcic), chp->ch_channel, target, 1625 chp->ch_error), DEBUG_PROBE); 1626 s = splbio(); 1627 drvp->drive_flags &= ~DRIVE_ATAPI; 1628 splx(s); 1629 } 1630 } 1631 #endif /* NATAPIBUS */ 1632
Indexes created Mon Sep 29 03:10:08 GMT 2025