ahcisata_core.c revision 1.35
1 /* $NetBSD: ahcisata_core.c,v 1.35 2012/07/02 18:15:46 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.35 2012/07/02 18:15:46 bouyer Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #define AHCI_DEBUG 54 #ifdef AHCI_DEBUG 55 int ahcidebug_mask = 0; 56 #endif 57 58 static void ahci_probe_drive(struct ata_channel *); 59 static void ahci_setup_channel(struct ata_channel *); 60 61 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 62 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 73 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 75 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 76 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 77 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 78 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 79 int, int); 80 static void ahci_timeout(void *); 81 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 82 83 #if NATAPIBUS > 0 84 static void ahci_atapibus_attach(struct atabus_softc *); 85 static void ahci_atapi_kill_pending(struct scsipi_periph *); 86 static void ahci_atapi_minphys(struct buf *); 87 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 88 scsipi_adapter_req_t, void *); 89 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 90 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 92 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 93 94 static const struct scsipi_bustype ahci_atapi_bustype = { 95 SCSIPI_BUSTYPE_ATAPI, 96 atapi_scsipi_cmd, 97 atapi_interpret_sense, 98 atapi_print_addr, 99 ahci_atapi_kill_pending, 100 NULL, 101 }; 102 #endif /* NATAPIBUS */ 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 106 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 107 108 const struct ata_bustype ahci_ata_bustype = { 109 SCSIPI_BUSTYPE_ATA, 110 ahci_ata_bio, 111 ahci_reset_drive, 112 ahci_reset_channel, 113 ahci_exec_command, 114 ata_get_params, 115 ahci_ata_addref, 116 ahci_ata_delref, 117 ahci_killpending 118 }; 119 120 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 121 static void ahci_setup_port(struct ahci_softc *sc, int i); 122 123 static int 124 ahci_reset(struct ahci_softc *sc) 125 { 126 int i; 127 128 /* reset controller */ 129 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 130 /* wait up to 1s for reset to complete */ 131 for (i = 0; i < 1000; i++) { 132 delay(1000); 133 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 134 break; 135 } 136 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 137 aprint_error("%s: reset failed\n", AHCINAME(sc)); 138 return -1; 139 } 140 /* enable ahci mode */ 141 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 142 return 0; 143 } 144 145 static void 146 ahci_setup_ports(struct ahci_softc *sc) 147 { 148 uint32_t ahci_ports; 149 int i, port; 150 151 ahci_ports = AHCI_READ(sc, AHCI_PI); 152 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 153 if ((ahci_ports & (1 << i)) == 0) 154 continue; 155 if (port >= sc->sc_atac.atac_nchannels) { 156 aprint_error("%s: more ports than announced\n", 157 AHCINAME(sc)); 158 break; 159 } 160 ahci_setup_port(sc, i); 161 } 162 } 163 164 static void 165 ahci_reprobe_drives(struct ahci_softc *sc) 166 { 167 uint32_t ahci_ports; 168 int i, port; 169 struct ahci_channel *achp; 170 struct ata_channel *chp; 171 172 ahci_ports = AHCI_READ(sc, AHCI_PI); 173 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 174 if ((ahci_ports & (1 << i)) == 0) 175 continue; 176 if (port >= sc->sc_atac.atac_nchannels) { 177 aprint_error("%s: more ports than announced\n", 178 AHCINAME(sc)); 179 break; 180 } 181 achp = &sc->sc_channels[i]; 182 chp = &achp->ata_channel; 183 184 ahci_probe_drive(chp); 185 } 186 } 187 188 static void 189 ahci_setup_port(struct ahci_softc *sc, int i) 190 { 191 struct ahci_channel *achp; 192 193 achp = &sc->sc_channels[i]; 194 195 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 196 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 197 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 198 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 199 } 200 201 static void 202 ahci_enable_intrs(struct ahci_softc *sc) 203 { 204 205 /* clear interrupts */ 206 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 207 /* enable interrupts */ 208 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 209 } 210 211 void 212 ahci_attach(struct ahci_softc *sc) 213 { 214 uint32_t ahci_rev, ahci_ports; 215 int i, j, port; 216 struct ahci_channel *achp; 217 struct ata_channel *chp; 218 int error; 219 int dmasize; 220 char buf[128]; 221 void *cmdhp; 222 void *cmdtblp; 223 224 if (ahci_reset(sc) != 0) 225 return; 226 227 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 228 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 229 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 230 ahci_rev = AHCI_READ(sc, AHCI_VS); 231 snprintb(buf, sizeof(buf), "\177\020" 232 /* "f\000\005NP\0" */ 233 "b\005SXS\0" 234 "b\006EMS\0" 235 "b\007CCCS\0" 236 /* "f\010\005NCS\0" */ 237 "b\015PSC\0" 238 "b\016SSC\0" 239 "b\017PMD\0" 240 "b\020FBSS\0" 241 "b\021SPM\0" 242 "b\022SAM\0" 243 "b\023SNZO\0" 244 "f\024\003ISS\0" 245 "=\001Gen1\0" 246 "=\002Gen2\0" 247 "=\003Gen3\0" 248 "b\030SCLO\0" 249 "b\031SAL\0" 250 "b\032SALP\0" 251 "b\033SSS\0" 252 "b\034SMPS\0" 253 "b\035SSNTF\0" 254 "b\036SNCQ\0" 255 "b\037S64A\0" 256 "\0", sc->sc_ahci_cap); 257 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 258 ", %d ports, %d slots, CAP %s\n", 259 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 260 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 261 262 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 263 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 264 sc->sc_atac.atac_pio_cap = 4; 265 sc->sc_atac.atac_dma_cap = 2; 266 sc->sc_atac.atac_udma_cap = 6; 267 sc->sc_atac.atac_channels = sc->sc_chanarray; 268 sc->sc_atac.atac_probe = ahci_probe_drive; 269 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 270 sc->sc_atac.atac_set_modes = ahci_setup_channel; 271 #if NATAPIBUS > 0 272 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 273 #endif 274 275 dmasize = 276 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 277 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 278 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 279 if (error) { 280 aprint_error("%s: unable to allocate command header memory" 281 ", error=%d\n", AHCINAME(sc), error); 282 return; 283 } 284 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 285 sc->sc_cmd_hdr_nseg, dmasize, 286 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 287 if (error) { 288 aprint_error("%s: unable to map command header memory" 289 ", error=%d\n", AHCINAME(sc), error); 290 return; 291 } 292 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 293 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 294 if (error) { 295 aprint_error("%s: unable to create command header map" 296 ", error=%d\n", AHCINAME(sc), error); 297 return; 298 } 299 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 300 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 301 if (error) { 302 aprint_error("%s: unable to load command header map" 303 ", error=%d\n", AHCINAME(sc), error); 304 return; 305 } 306 sc->sc_cmd_hdr = cmdhp; 307 308 ahci_enable_intrs(sc); 309 310 ahci_ports = AHCI_READ(sc, AHCI_PI); 311 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 312 if ((ahci_ports & (1 << i)) == 0) 313 continue; 314 if (port >= sc->sc_atac.atac_nchannels) { 315 aprint_error("%s: more ports than announced\n", 316 AHCINAME(sc)); 317 break; 318 } 319 achp = &sc->sc_channels[i]; 320 chp = &achp->ata_channel; 321 sc->sc_chanarray[i] = chp; 322 chp->ch_channel = i; 323 chp->ch_atac = &sc->sc_atac; 324 chp->ch_queue = malloc(sizeof(struct ata_queue), 325 M_DEVBUF, M_NOWAIT); 326 if (chp->ch_queue == NULL) { 327 aprint_error("%s port %d: can't allocate memory for " 328 "command queue", AHCINAME(sc), i); 329 break; 330 } 331 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 332 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 333 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 334 BUS_DMA_NOWAIT); 335 if (error) { 336 aprint_error("%s: unable to allocate command table " 337 "memory, error=%d\n", AHCINAME(sc), error); 338 break; 339 } 340 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 341 achp->ahcic_cmd_tbl_nseg, dmasize, 342 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 343 if (error) { 344 aprint_error("%s: unable to map command table memory" 345 ", error=%d\n", AHCINAME(sc), error); 346 break; 347 } 348 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 349 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 350 if (error) { 351 aprint_error("%s: unable to create command table map" 352 ", error=%d\n", AHCINAME(sc), error); 353 break; 354 } 355 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 356 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 357 if (error) { 358 aprint_error("%s: unable to load command table map" 359 ", error=%d\n", AHCINAME(sc), error); 360 break; 361 } 362 achp->ahcic_cmdh = (struct ahci_cmd_header *) 363 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 364 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 365 AHCI_CMDH_SIZE * port; 366 achp->ahcic_rfis = (struct ahci_r_fis *) 367 ((char *)cmdhp + 368 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 369 AHCI_RFIS_SIZE * port); 370 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 371 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 372 AHCI_RFIS_SIZE * port; 373 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 374 "rfis %p (0x%" PRIx64 ")\n", i, 375 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 376 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 377 DEBUG_PROBE); 378 379 for (j = 0; j < sc->sc_ncmds; j++) { 380 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 381 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 382 achp->ahcic_bus_cmd_tbl[j] = 383 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 384 AHCI_CMDTBL_SIZE * j; 385 achp->ahcic_cmdh[j].cmdh_cmdtba = 386 htole64(achp->ahcic_bus_cmd_tbl[j]); 387 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 388 achp->ahcic_cmd_tbl[j], 389 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 390 /* The xfer DMA map */ 391 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 392 AHCI_NPRD, 0x400000 /* 4MB */, 0, 393 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 394 &achp->ahcic_datad[j]); 395 if (error) { 396 aprint_error("%s: couldn't alloc xfer DMA map, " 397 "error=%d\n", AHCINAME(sc), error); 398 goto end; 399 } 400 } 401 ahci_setup_port(sc, i); 402 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 403 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 404 aprint_error("%s: couldn't map channel %d " 405 "sata_status regs\n", AHCINAME(sc), i); 406 break; 407 } 408 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 409 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 410 aprint_error("%s: couldn't map channel %d " 411 "sata_control regs\n", AHCINAME(sc), i); 412 break; 413 } 414 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 415 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 416 aprint_error("%s: couldn't map channel %d " 417 "sata_error regs\n", AHCINAME(sc), i); 418 break; 419 } 420 ata_channel_attach(chp); 421 port++; 422 end: 423 continue; 424 } 425 } 426 427 int 428 ahci_detach(struct ahci_softc *sc, int flags) 429 { 430 struct atac_softc *atac; 431 struct ahci_channel *achp; 432 struct ata_channel *chp; 433 struct scsipi_adapter *adapt; 434 uint32_t ahci_ports; 435 int i, j; 436 int error; 437 438 atac = &sc->sc_atac; 439 adapt = &atac->atac_atapi_adapter._generic; 440 441 ahci_ports = AHCI_READ(sc, AHCI_PI); 442 for (i = 0; i < AHCI_MAX_PORTS; i++) { 443 achp = &sc->sc_channels[i]; 444 chp = &achp->ata_channel; 445 446 if ((ahci_ports & (1 << i)) == 0) 447 continue; 448 if (i >= sc->sc_atac.atac_nchannels) { 449 aprint_error("%s: more ports than announced\n", 450 AHCINAME(sc)); 451 break; 452 } 453 454 if (chp->atabus == NULL) 455 continue; 456 if ((error = config_detach(chp->atabus, flags)) != 0) 457 return error; 458 459 for (j = 0; j < sc->sc_ncmds; j++) 460 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 461 462 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 463 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 464 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 465 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 466 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 467 achp->ahcic_cmd_tbl_nseg); 468 469 free(chp->ch_queue, M_DEVBUF); 470 chp->atabus = NULL; 471 } 472 473 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 474 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 475 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 476 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 477 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 478 479 if (adapt->adapt_refcnt != 0) 480 return EBUSY; 481 482 return 0; 483 } 484 485 void 486 ahci_resume(struct ahci_softc *sc) 487 { 488 ahci_reset(sc); 489 ahci_setup_ports(sc); 490 ahci_reprobe_drives(sc); 491 ahci_enable_intrs(sc); 492 } 493 494 int 495 ahci_intr(void *v) 496 { 497 struct ahci_softc *sc = v; 498 uint32_t is; 499 int i, r = 0; 500 501 while ((is = AHCI_READ(sc, AHCI_IS))) { 502 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 503 DEBUG_INTR); 504 r = 1; 505 AHCI_WRITE(sc, AHCI_IS, is); 506 for (i = 0; i < AHCI_MAX_PORTS; i++) 507 if (is & (1 << i)) 508 ahci_intr_port(sc, &sc->sc_channels[i]); 509 } 510 return r; 511 } 512 513 static void 514 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 515 { 516 uint32_t is, tfd; 517 struct ata_channel *chp = &achp->ata_channel; 518 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 519 int slot; 520 521 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 522 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 523 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 524 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 525 DEBUG_INTR); 526 527 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 528 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 529 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 530 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 531 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 532 return; 533 /* stop channel */ 534 ahci_channel_stop(sc, chp, 0); 535 if (slot != 0) { 536 printf("ahci_intr_port: slot %d\n", slot); 537 panic("ahci_intr_port"); 538 } 539 if (is & AHCI_P_IX_TFES) { 540 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 541 chp->ch_error = 542 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 543 chp->ch_status = (tfd & 0xff); 544 } else { 545 /* emulate a CRC error */ 546 chp->ch_error = WDCE_CRC; 547 chp->ch_status = WDCS_ERR; 548 } 549 if (is & AHCI_P_IX_IFS) { 550 aprint_error("%s port %d: SERR 0x%x\n", 551 AHCINAME(sc), chp->ch_channel, 552 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 553 } 554 xfer->c_intr(chp, xfer, is); 555 /* if channel has not been restarted, do it now */ 556 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 557 == 0) 558 ahci_channel_start(sc, chp, 0, 0); 559 } else { 560 slot = 0; /* XXX */ 561 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 562 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 563 chp->ch_channel, is, achp->ahcic_cmds_active, 564 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 565 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 566 return; 567 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 568 == 0) { 569 xfer->c_intr(chp, xfer, 0); 570 } 571 } 572 } 573 574 static void 575 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 576 { 577 struct ata_channel *chp = drvp->chnl_softc; 578 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 579 AHCI_WRITE(sc, AHCI_GHC, 580 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 581 ahci_channel_stop(sc, chp, flags); 582 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 583 ata_reset_channel(chp, flags); 584 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 585 return; 586 } 587 588 /* return error code from ata_bio */ 589 static int 590 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 591 { 592 struct ahci_channel *achp = (struct ahci_channel *)chp; 593 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 594 int i; 595 uint32_t is; 596 597 timeout = timeout * 10; /* wait is 10ms */ 598 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 599 /* start command */ 600 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 601 for (i = 0; i < timeout; i++) { 602 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 603 return 0; 604 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 605 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 606 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 607 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 608 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 609 /* 610 * we got the D2H FIS anyway, 611 * assume sig is valid. 612 * channel is restarted later 613 */ 614 return ERROR; 615 } 616 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 617 AHCINAME(sc), chp->ch_channel, is); 618 return ERR_DF; 619 } 620 if (flags & AT_WAIT) 621 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 622 else 623 delay(10000); 624 } 625 aprint_debug("%s channel %d: timeout sending FIS\n", 626 AHCINAME(sc), chp->ch_channel); 627 return TIMEOUT; 628 } 629 630 static int 631 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 632 uint32_t *sigp) 633 { 634 struct ahci_channel *achp = (struct ahci_channel *)chp; 635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 636 struct ahci_cmd_tbl *cmd_tbl; 637 struct ahci_cmd_header *cmd_h; 638 int i; 639 uint32_t sig; 640 641 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 642 /* clear port interrupt register */ 643 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 644 /* clear SErrors and start operations */ 645 if ((sc->sc_ahci_cap & (AHCI_CAP_SPM | AHCI_CAP_CLO)) == 646 (AHCI_CAP_SPM | AHCI_CAP_CLO)) { 647 /* 648 * issue a command list override to clear BSY. 649 * This is needed if there's a PMP with no drive 650 * on port 0 651 */ 652 ahci_channel_start(sc, chp, flags, 1); 653 } else { 654 ahci_channel_start(sc, chp, flags, 0); 655 } 656 if (drive > 0) { 657 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 658 } 659 /* polled command, assume interrupts are disabled */ 660 /* use slot 0 to send reset, the channel is idle */ 661 cmd_h = &achp->ahcic_cmdh[0]; 662 cmd_tbl = achp->ahcic_cmd_tbl[0]; 663 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 664 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 665 cmd_h->cmdh_prdbc = 0; 666 memset(cmd_tbl->cmdt_cfis, 0, 64); 667 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 668 cmd_tbl->cmdt_cfis[rhd_c] = drive; 669 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 670 switch(ahci_exec_fis(chp, 1, flags)) { 671 case ERR_DF: 672 case TIMEOUT: 673 aprint_error("%s channel %d: setting WDCTL_RST failed " 674 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 675 if (sigp) 676 *sigp = 0xffffffff; 677 goto end; 678 default: 679 break; 680 } 681 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 682 (drive << AHCI_CMDH_F_PMP_SHIFT)); 683 cmd_h->cmdh_prdbc = 0; 684 memset(cmd_tbl->cmdt_cfis, 0, 64); 685 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 686 cmd_tbl->cmdt_cfis[rhd_c] = drive; 687 cmd_tbl->cmdt_cfis[rhd_control] = 0; 688 switch(ahci_exec_fis(chp, 31, flags)) { 689 case ERR_DF: 690 case TIMEOUT: 691 aprint_error("%s channel %d: clearing WDCTL_RST failed " 692 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 693 if (sigp) 694 *sigp = 0xffffffff; 695 goto end; 696 default: 697 break; 698 } 699 /* 700 * wait 31s for BSY to clear 701 * This should not be needed, but some controllers clear the 702 * command slot before receiving the D2H FIS ... 703 */ 704 for (i = 0; i <AHCI_RST_WAIT; i++) { 705 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 706 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 707 & WDCS_BSY) == 0) 708 break; 709 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 710 } 711 if (i == AHCI_RST_WAIT) { 712 aprint_error("%s: BSY never cleared, TD 0x%x\n", 713 AHCINAME(sc), sig); 714 if (sigp) 715 *sigp = 0xffffffff; 716 goto end; 717 } 718 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 719 DEBUG_PROBE); 720 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 721 if (sigp) 722 *sigp = sig; 723 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 724 AHCINAME(sc), chp->ch_channel, sig, 725 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 726 end: 727 ahci_channel_stop(sc, chp, flags); 728 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 729 /* clear port interrupt register */ 730 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 731 ahci_channel_start(sc, chp, AT_WAIT, 732 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 733 return 0; 734 } 735 736 static void 737 ahci_reset_channel(struct ata_channel *chp, int flags) 738 { 739 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 740 struct ahci_channel *achp = (struct ahci_channel *)chp; 741 int i, tfd; 742 743 ahci_channel_stop(sc, chp, flags); 744 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 745 achp->ahcic_sstatus) != SStatus_DET_DEV) { 746 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 747 /* XXX and then ? */ 748 } 749 if (chp->ch_queue->active_xfer) { 750 chp->ch_queue->active_xfer->c_kill_xfer(chp, 751 chp->ch_queue->active_xfer, KILL_RESET); 752 } 753 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 754 /* clear port interrupt register */ 755 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 756 /* clear SErrors and start operations */ 757 ahci_channel_start(sc, chp, flags, 1); 758 /* wait 31s for BSY to clear */ 759 for (i = 0; i <AHCI_RST_WAIT; i++) { 760 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 761 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 762 & WDCS_BSY) == 0) 763 break; 764 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 765 } 766 if (i == AHCI_RST_WAIT) 767 aprint_error("%s: BSY never cleared, TD 0x%x\n", 768 AHCINAME(sc), tfd); 769 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 770 DEBUG_PROBE); 771 /* clear port interrupt register */ 772 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 773 774 return; 775 } 776 777 static int 778 ahci_ata_addref(struct ata_drive_datas *drvp) 779 { 780 return 0; 781 } 782 783 static void 784 ahci_ata_delref(struct ata_drive_datas *drvp) 785 { 786 return; 787 } 788 789 static void 790 ahci_killpending(struct ata_drive_datas *drvp) 791 { 792 return; 793 } 794 795 static void 796 ahci_probe_drive(struct ata_channel *chp) 797 { 798 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 799 struct ahci_channel *achp = (struct ahci_channel *)chp; 800 uint32_t sig; 801 802 /* bring interface up, accept FISs, power up and spin up device */ 803 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 804 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 805 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 806 /* reset the PHY and bring online */ 807 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 808 achp->ahcic_sstatus)) { 809 case SStatus_DET_DEV: 810 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 811 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 812 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 813 } else { 814 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 815 } 816 sata_interpret_sig(chp, 0, sig); 817 /* if we have a PMP attached, inform the controller */ 818 if (chp->ch_ndrives > PMP_PORT_CTL && 819 chp->ch_drive[PMP_PORT_CTL].drive_type == DRIVET_PM) { 820 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 821 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 822 AHCI_P_CMD_PMA); 823 } 824 /* clear port interrupt register */ 825 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 826 /* and enable interrupts */ 827 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 828 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 829 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 830 AHCI_P_IX_DHRS); 831 /* wait 500ms before actually starting operations */ 832 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 833 break; 834 835 default: 836 break; 837 } 838 } 839 840 static void 841 ahci_setup_channel(struct ata_channel *chp) 842 { 843 return; 844 } 845 846 static int 847 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 848 { 849 struct ata_channel *chp = drvp->chnl_softc; 850 struct ata_xfer *xfer; 851 int ret; 852 int s; 853 854 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 855 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 856 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 857 DEBUG_XFERS); 858 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 859 ATAXF_NOSLEEP); 860 if (xfer == NULL) { 861 return ATACMD_TRY_AGAIN; 862 } 863 if (ata_c->flags & AT_POLL) 864 xfer->c_flags |= C_POLL; 865 if (ata_c->flags & AT_WAIT) 866 xfer->c_flags |= C_WAIT; 867 xfer->c_drive = drvp->drive; 868 xfer->c_databuf = ata_c->data; 869 xfer->c_bcount = ata_c->bcount; 870 xfer->c_cmd = ata_c; 871 xfer->c_start = ahci_cmd_start; 872 xfer->c_intr = ahci_cmd_complete; 873 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 874 s = splbio(); 875 ata_exec_xfer(chp, xfer); 876 #ifdef DIAGNOSTIC 877 if ((ata_c->flags & AT_POLL) != 0 && 878 (ata_c->flags & AT_DONE) == 0) 879 panic("ahci_exec_command: polled command not done"); 880 #endif 881 if (ata_c->flags & AT_DONE) { 882 ret = ATACMD_COMPLETE; 883 } else { 884 if (ata_c->flags & AT_WAIT) { 885 while ((ata_c->flags & AT_DONE) == 0) { 886 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 887 } 888 ret = ATACMD_COMPLETE; 889 } else { 890 ret = ATACMD_QUEUED; 891 } 892 } 893 splx(s); 894 return ret; 895 } 896 897 static void 898 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 899 { 900 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 901 struct ahci_channel *achp = (struct ahci_channel *)chp; 902 struct ata_command *ata_c = xfer->c_cmd; 903 int slot = 0 /* XXX slot */; 904 struct ahci_cmd_tbl *cmd_tbl; 905 struct ahci_cmd_header *cmd_h; 906 int i; 907 int channel = chp->ch_channel; 908 909 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 910 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 911 912 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 913 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 914 cmd_tbl), DEBUG_XFERS); 915 916 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 917 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 918 919 cmd_h = &achp->ahcic_cmdh[slot]; 920 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 921 chp->ch_channel, cmd_h), DEBUG_XFERS); 922 if (ahci_dma_setup(chp, slot, 923 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 924 ata_c->data : NULL, 925 ata_c->bcount, 926 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 927 ata_c->flags |= AT_DF; 928 ahci_cmd_complete(chp, xfer, slot); 929 return; 930 } 931 cmd_h->cmdh_flags = htole16( 932 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 933 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 934 cmd_h->cmdh_prdbc = 0; 935 AHCI_CMDH_SYNC(sc, achp, slot, 936 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 937 938 if (ata_c->flags & AT_POLL) { 939 /* polled command, disable interrupts */ 940 AHCI_WRITE(sc, AHCI_GHC, 941 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 942 } 943 chp->ch_flags |= ATACH_IRQ_WAIT; 944 chp->ch_status = 0; 945 /* start command */ 946 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 947 /* and says we started this command */ 948 achp->ahcic_cmds_active |= 1 << slot; 949 950 if ((ata_c->flags & AT_POLL) == 0) { 951 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 952 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 953 ahci_timeout, chp); 954 return; 955 } 956 /* 957 * Polled command. 958 */ 959 for (i = 0; i < ata_c->timeout / 10; i++) { 960 if (ata_c->flags & AT_DONE) 961 break; 962 ahci_intr_port(sc, achp); 963 if (ata_c->flags & AT_WAIT) 964 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 965 else 966 delay(10000); 967 } 968 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 969 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 970 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 971 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 972 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 973 DEBUG_XFERS); 974 if ((ata_c->flags & AT_DONE) == 0) { 975 ata_c->flags |= AT_TIMEOU; 976 ahci_cmd_complete(chp, xfer, slot); 977 } 978 /* reenable interrupts */ 979 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 980 } 981 982 static void 983 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 984 { 985 struct ata_command *ata_c = xfer->c_cmd; 986 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 987 DEBUG_FUNCS); 988 989 switch (reason) { 990 case KILL_GONE: 991 ata_c->flags |= AT_GONE; 992 break; 993 case KILL_RESET: 994 ata_c->flags |= AT_RESET; 995 break; 996 default: 997 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 998 panic("ahci_cmd_kill_xfer"); 999 } 1000 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1001 } 1002 1003 static int 1004 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1005 { 1006 int slot = 0; /* XXX slot */ 1007 struct ata_command *ata_c = xfer->c_cmd; 1008 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1009 struct ahci_channel *achp = (struct ahci_channel *)chp; 1010 1011 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1012 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1013 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1014 DEBUG_FUNCS); 1015 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1016 if (xfer->c_flags & C_TIMEOU) { 1017 ata_c->flags |= AT_TIMEOU; 1018 } else 1019 callout_stop(&chp->ch_callout); 1020 1021 chp->ch_queue->active_xfer = NULL; 1022 1023 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1024 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1025 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1026 wakeup(&chp->ch_queue->active_xfer); 1027 return 0; 1028 } 1029 1030 if (chp->ch_status & WDCS_BSY) { 1031 ata_c->flags |= AT_TIMEOU; 1032 } else if (chp->ch_status & WDCS_ERR) { 1033 ata_c->r_error = chp->ch_error; 1034 ata_c->flags |= AT_ERROR; 1035 } 1036 1037 if (ata_c->flags & AT_READREG) 1038 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1039 1040 ahci_cmd_done(chp, xfer, slot); 1041 return 0; 1042 } 1043 1044 static void 1045 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1046 { 1047 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1048 struct ahci_channel *achp = (struct ahci_channel *)chp; 1049 struct ata_command *ata_c = xfer->c_cmd; 1050 uint16_t *idwordbuf; 1051 int i; 1052 1053 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 1054 DEBUG_FUNCS); 1055 1056 /* this comamnd is not active any more */ 1057 achp->ahcic_cmds_active &= ~(1 << slot); 1058 1059 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1060 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1061 achp->ahcic_datad[slot]->dm_mapsize, 1062 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1063 BUS_DMASYNC_POSTWRITE); 1064 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1065 } 1066 1067 AHCI_CMDH_SYNC(sc, achp, slot, 1068 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1069 1070 /* ata(4) expects IDENTIFY data to be in host endianess */ 1071 if (ata_c->r_command == WDCC_IDENTIFY || 1072 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1073 idwordbuf = xfer->c_databuf; 1074 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1075 idwordbuf[i] = le16toh(idwordbuf[i]); 1076 } 1077 } 1078 1079 ata_c->flags |= AT_DONE; 1080 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1081 ata_c->flags |= AT_XFDONE; 1082 1083 ata_free_xfer(chp, xfer); 1084 if (ata_c->flags & AT_WAIT) 1085 wakeup(ata_c); 1086 else if (ata_c->callback) 1087 ata_c->callback(ata_c->callback_arg); 1088 atastart(chp); 1089 return; 1090 } 1091 1092 static int 1093 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1094 { 1095 struct ata_channel *chp = drvp->chnl_softc; 1096 struct ata_xfer *xfer; 1097 1098 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1099 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1100 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1101 DEBUG_XFERS); 1102 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1103 if (xfer == NULL) { 1104 return ATACMD_TRY_AGAIN; 1105 } 1106 if (ata_bio->flags & ATA_POLL) 1107 xfer->c_flags |= C_POLL; 1108 xfer->c_drive = drvp->drive; 1109 xfer->c_cmd = ata_bio; 1110 xfer->c_databuf = ata_bio->databuf; 1111 xfer->c_bcount = ata_bio->bcount; 1112 xfer->c_start = ahci_bio_start; 1113 xfer->c_intr = ahci_bio_complete; 1114 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1115 ata_exec_xfer(chp, xfer); 1116 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1117 } 1118 1119 static void 1120 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1121 { 1122 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1123 struct ahci_channel *achp = (struct ahci_channel *)chp; 1124 struct ata_bio *ata_bio = xfer->c_cmd; 1125 int slot = 0 /* XXX slot */; 1126 struct ahci_cmd_tbl *cmd_tbl; 1127 struct ahci_cmd_header *cmd_h; 1128 int i; 1129 int channel = chp->ch_channel; 1130 1131 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1132 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1133 1134 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1135 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1136 cmd_tbl), DEBUG_XFERS); 1137 1138 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1139 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1140 1141 cmd_h = &achp->ahcic_cmdh[slot]; 1142 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1143 chp->ch_channel, cmd_h), DEBUG_XFERS); 1144 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1145 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1146 ata_bio->error = ERR_DMA; 1147 ata_bio->r_error = 0; 1148 ahci_bio_complete(chp, xfer, slot); 1149 return; 1150 } 1151 cmd_h->cmdh_flags = htole16( 1152 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1153 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1154 cmd_h->cmdh_prdbc = 0; 1155 AHCI_CMDH_SYNC(sc, achp, slot, 1156 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1157 1158 if (xfer->c_flags & C_POLL) { 1159 /* polled command, disable interrupts */ 1160 AHCI_WRITE(sc, AHCI_GHC, 1161 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1162 } 1163 chp->ch_flags |= ATACH_IRQ_WAIT; 1164 chp->ch_status = 0; 1165 /* start command */ 1166 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1167 /* and says we started this command */ 1168 achp->ahcic_cmds_active |= 1 << slot; 1169 1170 if ((xfer->c_flags & C_POLL) == 0) { 1171 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1172 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1173 ahci_timeout, chp); 1174 return; 1175 } 1176 /* 1177 * Polled command. 1178 */ 1179 for (i = 0; i < ATA_DELAY / 10; i++) { 1180 if (ata_bio->flags & ATA_ITSDONE) 1181 break; 1182 ahci_intr_port(sc, achp); 1183 if (ata_bio->flags & ATA_NOSLEEP) 1184 delay(10000); 1185 else 1186 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1187 } 1188 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1189 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1190 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1191 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1192 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1193 DEBUG_XFERS); 1194 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1195 ata_bio->error = TIMEOUT; 1196 ahci_bio_complete(chp, xfer, slot); 1197 } 1198 /* reenable interrupts */ 1199 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1200 } 1201 1202 static void 1203 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1204 { 1205 int slot = 0; /* XXX slot */ 1206 int drive = xfer->c_drive; 1207 struct ata_bio *ata_bio = xfer->c_cmd; 1208 struct ahci_channel *achp = (struct ahci_channel *)chp; 1209 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1210 DEBUG_FUNCS); 1211 1212 achp->ahcic_cmds_active &= ~(1 << slot); 1213 ata_free_xfer(chp, xfer); 1214 ata_bio->flags |= ATA_ITSDONE; 1215 switch (reason) { 1216 case KILL_GONE: 1217 ata_bio->error = ERR_NODEV; 1218 break; 1219 case KILL_RESET: 1220 ata_bio->error = ERR_RESET; 1221 break; 1222 default: 1223 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1224 panic("ahci_bio_kill_xfer"); 1225 } 1226 ata_bio->r_error = WDCE_ABRT; 1227 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1228 } 1229 1230 static int 1231 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1232 { 1233 int slot = 0; /* XXX slot */ 1234 struct ata_bio *ata_bio = xfer->c_cmd; 1235 int drive = xfer->c_drive; 1236 struct ahci_channel *achp = (struct ahci_channel *)chp; 1237 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1238 1239 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1240 DEBUG_FUNCS); 1241 1242 achp->ahcic_cmds_active &= ~(1 << slot); 1243 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1244 if (xfer->c_flags & C_TIMEOU) { 1245 ata_bio->error = TIMEOUT; 1246 } else { 1247 callout_stop(&chp->ch_callout); 1248 ata_bio->error = NOERROR; 1249 } 1250 1251 chp->ch_queue->active_xfer = NULL; 1252 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1253 achp->ahcic_datad[slot]->dm_mapsize, 1254 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1255 BUS_DMASYNC_POSTWRITE); 1256 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1257 1258 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1259 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1260 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1261 wakeup(&chp->ch_queue->active_xfer); 1262 return 0; 1263 } 1264 ata_free_xfer(chp, xfer); 1265 ata_bio->flags |= ATA_ITSDONE; 1266 if (chp->ch_status & WDCS_DWF) { 1267 ata_bio->error = ERR_DF; 1268 } else if (chp->ch_status & WDCS_ERR) { 1269 ata_bio->error = ERROR; 1270 ata_bio->r_error = chp->ch_error; 1271 } else if (chp->ch_status & WDCS_CORR) 1272 ata_bio->flags |= ATA_CORR; 1273 1274 AHCI_CMDH_SYNC(sc, achp, slot, 1275 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1276 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1277 ata_bio->bcount), DEBUG_XFERS); 1278 /* 1279 * if it was a write, complete data buffer may have been transfered 1280 * before error detection; in this case don't use cmdh_prdbc 1281 * as it won't reflect what was written to media. Assume nothing 1282 * was transfered and leave bcount as-is. 1283 */ 1284 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1285 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1286 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1287 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1288 atastart(chp); 1289 return 0; 1290 } 1291 1292 static void 1293 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1294 { 1295 int i; 1296 /* stop channel */ 1297 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1298 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1299 /* wait 1s for channel to stop */ 1300 for (i = 0; i <100; i++) { 1301 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1302 == 0) 1303 break; 1304 if (flags & AT_WAIT) 1305 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1306 else 1307 delay(10000); 1308 } 1309 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1310 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1311 /* XXX controller reset ? */ 1312 return; 1313 } 1314 } 1315 1316 static void 1317 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1318 int flags, int clo) 1319 { 1320 int i; 1321 uint32_t p_cmd; 1322 /* clear error */ 1323 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1324 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1325 1326 if (clo) { 1327 /* issue command list override */ 1328 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1329 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1330 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1331 /* wait 1s for AHCI_CAP_CLO to clear */ 1332 for (i = 0; i <100; i++) { 1333 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1334 AHCI_P_CMD_CLO) == 0) 1335 break; 1336 if (flags & AT_WAIT) 1337 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1338 else 1339 delay(10000); 1340 } 1341 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1342 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1343 /* XXX controller reset ? */ 1344 return; 1345 } 1346 } 1347 /* and start controller */ 1348 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1349 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1350 if (chp->ch_ndrives > PMP_PORT_CTL && 1351 chp->ch_drive[PMP_PORT_CTL].drive_type == DRIVET_PM) { 1352 p_cmd |= AHCI_P_CMD_PMA; 1353 } 1354 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1355 } 1356 1357 static void 1358 ahci_timeout(void *v) 1359 { 1360 struct ata_channel *chp = (struct ata_channel *)v; 1361 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1362 int s = splbio(); 1363 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1364 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1365 xfer->c_flags |= C_TIMEOU; 1366 xfer->c_intr(chp, xfer, 0); 1367 } 1368 splx(s); 1369 } 1370 1371 static int 1372 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1373 size_t count, int op) 1374 { 1375 int error, seg; 1376 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1377 struct ahci_channel *achp = (struct ahci_channel *)chp; 1378 struct ahci_cmd_tbl *cmd_tbl; 1379 struct ahci_cmd_header *cmd_h; 1380 1381 cmd_h = &achp->ahcic_cmdh[slot]; 1382 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1383 1384 if (data == NULL) { 1385 cmd_h->cmdh_prdtl = 0; 1386 goto end; 1387 } 1388 1389 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1390 data, count, NULL, 1391 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1392 if (error) { 1393 printf("%s port %d: failed to load xfer: %d\n", 1394 AHCINAME(sc), chp->ch_channel, error); 1395 return error; 1396 } 1397 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1398 achp->ahcic_datad[slot]->dm_mapsize, 1399 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1400 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1401 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1402 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1403 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1404 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1405 } 1406 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1407 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1408 end: 1409 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1410 return 0; 1411 } 1412 1413 #if NATAPIBUS > 0 1414 static void 1415 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1416 { 1417 struct ata_channel *chp = ata_sc->sc_chan; 1418 struct atac_softc *atac = chp->ch_atac; 1419 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1420 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1421 /* 1422 * Fill in the scsipi_adapter. 1423 */ 1424 adapt->adapt_dev = atac->atac_dev; 1425 adapt->adapt_nchannels = atac->atac_nchannels; 1426 adapt->adapt_request = ahci_atapi_scsipi_request; 1427 adapt->adapt_minphys = ahci_atapi_minphys; 1428 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1429 1430 /* 1431 * Fill in the scsipi_channel. 1432 */ 1433 memset(chan, 0, sizeof(*chan)); 1434 chan->chan_adapter = adapt; 1435 chan->chan_bustype = &ahci_atapi_bustype; 1436 chan->chan_channel = chp->ch_channel; 1437 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1438 chan->chan_openings = 1; 1439 chan->chan_max_periph = 1; 1440 chan->chan_ntargets = 1; 1441 chan->chan_nluns = 1; 1442 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1443 atapiprint); 1444 } 1445 1446 static void 1447 ahci_atapi_minphys(struct buf *bp) 1448 { 1449 if (bp->b_bcount > MAXPHYS) 1450 bp->b_bcount = MAXPHYS; 1451 minphys(bp); 1452 } 1453 1454 /* 1455 * Kill off all pending xfers for a periph. 1456 * 1457 * Must be called at splbio(). 1458 */ 1459 static void 1460 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1461 { 1462 struct atac_softc *atac = 1463 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1464 struct ata_channel *chp = 1465 atac->atac_channels[periph->periph_channel->chan_channel]; 1466 1467 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1468 } 1469 1470 static void 1471 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1472 scsipi_adapter_req_t req, void *arg) 1473 { 1474 struct scsipi_adapter *adapt = chan->chan_adapter; 1475 struct scsipi_periph *periph; 1476 struct scsipi_xfer *sc_xfer; 1477 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1478 struct atac_softc *atac = &sc->sc_atac; 1479 struct ata_xfer *xfer; 1480 int channel = chan->chan_channel; 1481 int drive, s; 1482 1483 switch (req) { 1484 case ADAPTER_REQ_RUN_XFER: 1485 sc_xfer = arg; 1486 periph = sc_xfer->xs_periph; 1487 drive = periph->periph_target; 1488 if (!device_is_active(atac->atac_dev)) { 1489 sc_xfer->error = XS_DRIVER_STUFFUP; 1490 scsipi_done(sc_xfer); 1491 return; 1492 } 1493 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1494 if (xfer == NULL) { 1495 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1496 scsipi_done(sc_xfer); 1497 return; 1498 } 1499 1500 if (sc_xfer->xs_control & XS_CTL_POLL) 1501 xfer->c_flags |= C_POLL; 1502 xfer->c_drive = drive; 1503 xfer->c_flags |= C_ATAPI; 1504 xfer->c_cmd = sc_xfer; 1505 xfer->c_databuf = sc_xfer->data; 1506 xfer->c_bcount = sc_xfer->datalen; 1507 xfer->c_start = ahci_atapi_start; 1508 xfer->c_intr = ahci_atapi_complete; 1509 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1510 xfer->c_dscpoll = 0; 1511 s = splbio(); 1512 ata_exec_xfer(atac->atac_channels[channel], xfer); 1513 #ifdef DIAGNOSTIC 1514 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1515 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1516 panic("ahci_atapi_scsipi_request: polled command " 1517 "not done"); 1518 #endif 1519 splx(s); 1520 return; 1521 default: 1522 /* Not supported, nothing to do. */ 1523 ; 1524 } 1525 } 1526 1527 static void 1528 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1529 { 1530 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1531 struct ahci_channel *achp = (struct ahci_channel *)chp; 1532 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1533 int slot = 0 /* XXX slot */; 1534 struct ahci_cmd_tbl *cmd_tbl; 1535 struct ahci_cmd_header *cmd_h; 1536 int i; 1537 int channel = chp->ch_channel; 1538 1539 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1540 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1541 1542 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1543 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1544 cmd_tbl), DEBUG_XFERS); 1545 1546 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1547 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1548 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1549 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1550 1551 cmd_h = &achp->ahcic_cmdh[slot]; 1552 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1553 chp->ch_channel, cmd_h), DEBUG_XFERS); 1554 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1555 sc_xfer->datalen, 1556 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1557 BUS_DMA_READ : BUS_DMA_WRITE)) { 1558 sc_xfer->error = XS_DRIVER_STUFFUP; 1559 ahci_atapi_complete(chp, xfer, slot); 1560 return; 1561 } 1562 cmd_h->cmdh_flags = htole16( 1563 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1564 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1565 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1566 cmd_h->cmdh_prdbc = 0; 1567 AHCI_CMDH_SYNC(sc, achp, slot, 1568 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1569 1570 if (xfer->c_flags & C_POLL) { 1571 /* polled command, disable interrupts */ 1572 AHCI_WRITE(sc, AHCI_GHC, 1573 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1574 } 1575 chp->ch_flags |= ATACH_IRQ_WAIT; 1576 chp->ch_status = 0; 1577 /* start command */ 1578 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1579 /* and says we started this command */ 1580 achp->ahcic_cmds_active |= 1 << slot; 1581 1582 if ((xfer->c_flags & C_POLL) == 0) { 1583 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1584 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1585 ahci_timeout, chp); 1586 return; 1587 } 1588 /* 1589 * Polled command. 1590 */ 1591 for (i = 0; i < ATA_DELAY / 10; i++) { 1592 if (sc_xfer->xs_status & XS_STS_DONE) 1593 break; 1594 ahci_intr_port(sc, achp); 1595 delay(10000); 1596 } 1597 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1598 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1599 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1600 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1601 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1602 DEBUG_XFERS); 1603 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1604 sc_xfer->error = XS_TIMEOUT; 1605 ahci_atapi_complete(chp, xfer, slot); 1606 } 1607 /* reenable interrupts */ 1608 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1609 } 1610 1611 static int 1612 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1613 { 1614 int slot = 0; /* XXX slot */ 1615 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1616 int drive = xfer->c_drive; 1617 struct ahci_channel *achp = (struct ahci_channel *)chp; 1618 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1619 1620 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1621 DEBUG_FUNCS); 1622 1623 achp->ahcic_cmds_active &= ~(1 << slot); 1624 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1625 if (xfer->c_flags & C_TIMEOU) { 1626 sc_xfer->error = XS_TIMEOUT; 1627 } else { 1628 callout_stop(&chp->ch_callout); 1629 sc_xfer->error = 0; 1630 } 1631 1632 chp->ch_queue->active_xfer = NULL; 1633 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1634 achp->ahcic_datad[slot]->dm_mapsize, 1635 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1636 BUS_DMASYNC_POSTWRITE); 1637 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1638 1639 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1640 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1641 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1642 wakeup(&chp->ch_queue->active_xfer); 1643 return 0; 1644 } 1645 ata_free_xfer(chp, xfer); 1646 1647 AHCI_CMDH_SYNC(sc, achp, slot, 1648 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1649 sc_xfer->resid = sc_xfer->datalen; 1650 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1651 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1652 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1653 if (chp->ch_status & WDCS_ERR && 1654 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1655 sc_xfer->resid == sc_xfer->datalen)) { 1656 sc_xfer->error = XS_SHORTSENSE; 1657 sc_xfer->sense.atapi_sense = chp->ch_error; 1658 if ((sc_xfer->xs_periph->periph_quirks & 1659 PQUIRK_NOSENSE) == 0) { 1660 /* ask scsipi to send a REQUEST_SENSE */ 1661 sc_xfer->error = XS_BUSY; 1662 sc_xfer->status = SCSI_CHECK; 1663 } 1664 } 1665 scsipi_done(sc_xfer); 1666 atastart(chp); 1667 return 0; 1668 } 1669 1670 static void 1671 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1672 { 1673 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1674 struct ahci_channel *achp = (struct ahci_channel *)chp; 1675 int slot = 0; /* XXX slot */ 1676 1677 achp->ahcic_cmds_active &= ~(1 << slot); 1678 1679 /* remove this command from xfer queue */ 1680 switch (reason) { 1681 case KILL_GONE: 1682 sc_xfer->error = XS_DRIVER_STUFFUP; 1683 break; 1684 case KILL_RESET: 1685 sc_xfer->error = XS_RESET; 1686 break; 1687 default: 1688 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1689 panic("ahci_ata_atapi_kill_xfer"); 1690 } 1691 ata_free_xfer(chp, xfer); 1692 scsipi_done(sc_xfer); 1693 } 1694 1695 static void 1696 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1697 { 1698 struct scsipi_channel *chan = sc->sc_channel; 1699 struct scsipi_periph *periph; 1700 struct ataparams ids; 1701 struct ataparams *id = &ids; 1702 struct ahci_softc *ahcic = 1703 device_private(chan->chan_adapter->adapt_dev); 1704 struct atac_softc *atac = &ahcic->sc_atac; 1705 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1706 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1707 struct scsipibus_attach_args sa; 1708 char serial_number[21], model[41], firmware_revision[9]; 1709 int s; 1710 1711 /* skip if already attached */ 1712 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1713 return; 1714 1715 /* if no ATAPI device detected at attach time, skip */ 1716 if (drvp->drive_type != DRIVET_ATAPI) { 1717 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1718 "not present\n", target), DEBUG_PROBE); 1719 return; 1720 } 1721 1722 /* Some ATAPI devices need a bit more time after software reset. */ 1723 delay(5000); 1724 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1725 #ifdef ATAPI_DEBUG_PROBE 1726 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1727 AHCINAME(ahcic), target, 1728 id->atap_config & ATAPI_CFG_CMD_MASK, 1729 id->atap_config & ATAPI_CFG_DRQ_MASK); 1730 #endif 1731 periph = scsipi_alloc_periph(M_NOWAIT); 1732 if (periph == NULL) { 1733 aprint_error_dev(sc->sc_dev, 1734 "unable to allocate periph for drive %d\n", 1735 target); 1736 return; 1737 } 1738 periph->periph_dev = NULL; 1739 periph->periph_channel = chan; 1740 periph->periph_switch = &atapi_probe_periphsw; 1741 periph->periph_target = target; 1742 periph->periph_lun = 0; 1743 periph->periph_quirks = PQUIRK_ONLYBIG; 1744 1745 #ifdef SCSIPI_DEBUG 1746 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1747 SCSIPI_DEBUG_TARGET == target) 1748 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1749 #endif 1750 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1751 if (id->atap_config & ATAPI_CFG_REMOV) 1752 periph->periph_flags |= PERIPH_REMOVABLE; 1753 if (periph->periph_type == T_SEQUENTIAL) { 1754 s = splbio(); 1755 drvp->drive_flags |= DRIVE_ATAPIDSCW; 1756 splx(s); 1757 } 1758 1759 sa.sa_periph = periph; 1760 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1761 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1762 T_REMOV : T_FIXED; 1763 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1764 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1765 20); 1766 scsipi_strvis((u_char *)firmware_revision, 8, 1767 id->atap_revision, 8); 1768 sa.sa_inqbuf.vendor = model; 1769 sa.sa_inqbuf.product = serial_number; 1770 sa.sa_inqbuf.revision = firmware_revision; 1771 1772 /* 1773 * Determine the operating mode capabilities of the device. 1774 */ 1775 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1776 periph->periph_cap |= PERIPH_CAP_CMD16; 1777 /* XXX This is gross. */ 1778 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1779 1780 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1781 1782 if (drvp->drv_softc) 1783 ata_probe_caps(drvp); 1784 else { 1785 s = splbio(); 1786 drvp->drive_type = DRIVET_NONE; 1787 splx(s); 1788 } 1789 } else { 1790 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1791 "failed for drive %s:%d:%d: error 0x%x\n", 1792 AHCINAME(ahcic), chp->ch_channel, target, 1793 chp->ch_error), DEBUG_PROBE); 1794 s = splbio(); 1795 drvp->drive_type = DRIVET_NONE; 1796 splx(s); 1797 } 1798 } 1799 #endif /* NATAPIBUS */ 1800
Indexes created Fri Oct 17 00:09:41 GMT 2025