ahcisata_core.c revision 1.4.12.2
1 /* $NetBSD: ahcisata_core.c,v 1.4.12.2 2007/08/31 20:09:23 pavel Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.4.12.2 2007/08/31 20:09:23 pavel Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/ic/wdcreg.h> 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/satavar.h> 48 #include <dev/ata/satareg.h> 49 #include <dev/ic/ahcisatavar.h> 50 51 #ifdef AHCI_DEBUG 52 int ahcidebug_mask = 0x0; 53 #endif 54 55 void ahci_probe_drive(struct ata_channel *); 56 void ahci_setup_channel(struct ata_channel *); 57 58 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 59 void ahci_reset_drive(struct ata_drive_datas *, int); 60 void ahci_reset_channel(struct ata_channel *, int); 61 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 62 int ahci_ata_addref(struct ata_drive_datas *); 63 void ahci_ata_delref(struct ata_drive_datas *); 64 void ahci_killpending(struct ata_drive_datas *); 65 66 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 67 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 68 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 69 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 70 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 71 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 72 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 74 void ahci_timeout(void *); 75 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 76 77 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 78 79 const struct ata_bustype ahci_ata_bustype = { 80 SCSIPI_BUSTYPE_ATA, 81 ahci_ata_bio, 82 ahci_reset_drive, 83 ahci_reset_channel, 84 ahci_exec_command, 85 ata_get_params, 86 ahci_ata_addref, 87 ahci_ata_delref, 88 ahci_killpending 89 }; 90 91 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 92 93 void 94 ahci_attach(struct ahci_softc *sc) 95 { 96 u_int32_t ahci_cap, ahci_rev, ahci_ports; 97 int i, j, port; 98 struct ahci_channel *achp; 99 struct ata_channel *chp; 100 int error; 101 bus_dma_segment_t seg; 102 int rseg; 103 int dmasize; 104 caddr_t cmdhp; 105 caddr_t cmdtblp; 106 107 /* reset controller */ 108 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 109 delay(1000); 110 /* wait up to 1s for reset to complete */ 111 for (i = 0; i < 1000; i++) { 112 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 113 break; 114 } 115 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 116 aprint_error("%s: reset failed\n", AHCINAME(sc)); 117 return; 118 } 119 /* enable ahci mode */ 120 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 121 122 123 ahci_cap = AHCI_READ(sc, AHCI_CAP); 124 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 125 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 126 ahci_rev = AHCI_READ(sc, AHCI_VS); 127 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 128 switch(ahci_rev) { 129 case AHCI_VS_10: 130 aprint_normal("1.0"); 131 break; 132 case AHCI_VS_11: 133 aprint_normal("1.1"); 134 break; 135 default: 136 aprint_normal("0x%x", ahci_rev); 137 break; 138 } 139 140 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 141 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 142 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 143 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 144 sc->sc_atac.atac_pio_cap = 4; 145 sc->sc_atac.atac_dma_cap = 2; 146 sc->sc_atac.atac_udma_cap = 6; 147 sc->sc_atac.atac_channels = sc->sc_chanarray; 148 sc->sc_atac.atac_atapibus_attach = NULL; /* XXX */ 149 sc->sc_atac.atac_probe = ahci_probe_drive; 150 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 151 sc->sc_atac.atac_set_modes = ahci_setup_channel; 152 153 dmasize = 154 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 155 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 156 &seg, 1, &rseg, BUS_DMA_NOWAIT); 157 if (error) { 158 aprint_error("%s: unable to allocate command header memory" 159 ", error=%d\n", AHCINAME(sc), error); 160 return; 161 } 162 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 163 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 164 if (error) { 165 aprint_error("%s: unable to map command header memory" 166 ", error=%d\n", AHCINAME(sc), error); 167 return; 168 } 169 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 170 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 171 if (error) { 172 aprint_error("%s: unable to create command header map" 173 ", error=%d\n", AHCINAME(sc), error); 174 return; 175 } 176 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 177 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 178 if (error) { 179 aprint_error("%s: unable to load command header map" 180 ", error=%d\n", AHCINAME(sc), error); 181 return; 182 } 183 sc->sc_cmd_hdr = cmdhp; 184 185 /* clear interrupts */ 186 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 187 /* enable interrupts */ 188 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 189 190 ahci_ports = AHCI_READ(sc, AHCI_PI); 191 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 192 if ((ahci_ports & (1 << i)) == 0) 193 continue; 194 if (port >= sc->sc_atac.atac_nchannels) { 195 aprint_error("%s: more ports than announced\n", 196 AHCINAME(sc)); 197 break; 198 } 199 achp = &sc->sc_channels[i]; 200 chp = (struct ata_channel *)achp; 201 sc->sc_chanarray[i] = chp; 202 chp->ch_channel = i; 203 chp->ch_atac = &sc->sc_atac; 204 chp->ch_queue = malloc(sizeof(struct ata_queue), 205 M_DEVBUF, M_NOWAIT); 206 if (chp->ch_queue == NULL) { 207 aprint_error("%s port %d: can't allocate memory for " 208 "command queue", AHCINAME(sc), i); 209 break; 210 } 211 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 212 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 213 &seg, 1, &rseg, BUS_DMA_NOWAIT); 214 if (error) { 215 aprint_error("%s: unable to allocate command table " 216 "memory, error=%d\n", AHCINAME(sc), error); 217 break; 218 } 219 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 220 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 221 if (error) { 222 aprint_error("%s: unable to map command table memory" 223 ", error=%d\n", AHCINAME(sc), error); 224 break; 225 } 226 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 227 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 228 if (error) { 229 aprint_error("%s: unable to create command table map" 230 ", error=%d\n", AHCINAME(sc), error); 231 break; 232 } 233 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 234 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 235 if (error) { 236 aprint_error("%s: unable to load command table map" 237 ", error=%d\n", AHCINAME(sc), error); 238 break; 239 } 240 achp->ahcic_cmdh = (struct ahci_cmd_header *) 241 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 242 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 243 AHCI_CMDH_SIZE * port; 244 achp->ahcic_rfis = (struct ahci_r_fis *) 245 ((char *)cmdhp + 246 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 247 AHCI_RFIS_SIZE * port); 248 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 249 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 250 AHCI_RFIS_SIZE * port; 251 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 252 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 253 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 254 DEBUG_PROBE); 255 256 for (j = 0; j < sc->sc_ncmds; j++) { 257 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 258 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 259 achp->ahcic_bus_cmd_tbl[j] = 260 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 261 AHCI_CMDTBL_SIZE * j; 262 achp->ahcic_cmdh[j].cmdh_cmdtba = 263 htole32(achp->ahcic_bus_cmd_tbl[j]); 264 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 265 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 266 achp->ahcic_cmd_tbl[j], 267 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 268 /* The xfer DMA map */ 269 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 270 AHCI_NPRD, 0x400000 /* 4MB */, 0, 271 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 272 &achp->ahcic_datad[j]); 273 if (error) { 274 aprint_error("%s: couldn't alloc xfer DMA map, " 275 "error=%d\n", AHCINAME(sc), error); 276 goto end; 277 } 278 } 279 AHCI_WRITE(sc, AHCI_P_CLB(port), achp->ahcic_bus_cmdh); 280 AHCI_WRITE(sc, AHCI_P_CLBU(port), 0); 281 AHCI_WRITE(sc, AHCI_P_FB(port), achp->ahcic_bus_rfis); 282 AHCI_WRITE(sc, AHCI_P_FBU(port), 0); 283 chp->ch_ndrive = 1; 284 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 285 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 286 aprint_error("%s: couldn't map channel %d " 287 "sata_status regs\n", AHCINAME(sc), i); 288 break; 289 } 290 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 291 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 292 aprint_error("%s: couldn't map channel %d " 293 "sata_control regs\n", AHCINAME(sc), i); 294 break; 295 } 296 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 297 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 298 aprint_error("%s: couldn't map channel %d " 299 "sata_error regs\n", AHCINAME(sc), i); 300 break; 301 } 302 ata_channel_attach(chp); 303 port++; 304 end: 305 continue; 306 } 307 } 308 309 int 310 ahci_intr(void *v) 311 { 312 struct ahci_softc *sc = v; 313 u_int32_t is; 314 int i, r = 0; 315 316 while ((is = AHCI_READ(sc, AHCI_IS))) { 317 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 318 DEBUG_INTR); 319 r = 1; 320 AHCI_WRITE(sc, AHCI_IS, is); 321 for (i = 0; i < AHCI_MAX_PORTS; i++) 322 if (is & (1 << i)) 323 ahci_intr_port(sc, &sc->sc_channels[i]); 324 } 325 return r; 326 } 327 328 void 329 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 330 { 331 u_int32_t is, tfd; 332 struct ata_channel *chp = &achp->ata_channel; 333 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 334 int slot; 335 336 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 337 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 338 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 339 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 340 DEBUG_INTR); 341 342 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 343 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 344 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 345 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 346 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 347 return; 348 /* stop channel */ 349 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 350 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 351 if (slot != 0) { 352 printf("ahci_intr_port: slot %d\n", slot); 353 panic("ahci_intr_port"); 354 } 355 if (is & AHCI_P_IX_TFES) { 356 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 357 chp->ch_error = 358 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 359 chp->ch_status = (tfd & 0xff); 360 } else { 361 /* emulate a CRC error */ 362 chp->ch_error = WDCE_CRC; 363 chp->ch_status = WDCS_ERR; 364 } 365 xfer->c_intr(chp, xfer, is); 366 } else { 367 slot = 0; /* XXX */ 368 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 369 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 370 chp->ch_channel, is, achp->ahcic_cmds_active, 371 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 372 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 373 return; 374 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 375 == 0) { 376 xfer->c_intr(chp, xfer, 0); 377 } 378 } 379 } 380 381 void 382 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 383 { 384 struct ata_channel *chp = drvp->chnl_softc; 385 ata_reset_channel(chp, flags); 386 return; 387 } 388 389 void 390 ahci_reset_channel(struct ata_channel *chp, int flags) 391 { 392 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 393 struct ahci_channel *achp = (struct ahci_channel *)chp; 394 int i; 395 396 /* stop channel */ 397 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 398 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 399 /* wait 1s for channel to stop */ 400 for (i = 0; i <100; i++) { 401 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 402 == 0) 403 break; 404 if (flags & AT_WAIT) 405 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 406 else 407 delay(10000); 408 } 409 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 410 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 411 /* XXX controller reset ? */ 412 return; 413 } 414 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 415 achp->ahcic_sstatus) != SStatus_DET_DEV) { 416 printf("%s: port reset failed\n", AHCINAME(sc)); 417 /* XXX and then ? */ 418 } 419 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 420 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 421 if (chp->ch_queue->active_xfer) { 422 chp->ch_queue->active_xfer->c_kill_xfer(chp, 423 chp->ch_queue->active_xfer, KILL_RESET); 424 } 425 ahci_channel_start(sc, chp); 426 return; 427 } 428 429 int 430 ahci_ata_addref(struct ata_drive_datas *drvp) 431 { 432 return 0; 433 } 434 435 void 436 ahci_ata_delref(struct ata_drive_datas *drvp) 437 { 438 return; 439 } 440 441 void 442 ahci_killpending(struct ata_drive_datas *drvp) 443 { 444 return; 445 } 446 447 void 448 ahci_probe_drive(struct ata_channel *chp) 449 { 450 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 451 struct ahci_channel *achp = (struct ahci_channel *)chp; 452 int i, s; 453 u_int32_t sig; 454 455 /* XXX This should be done by other code. */ 456 for (i = 0; i < chp->ch_ndrive; i++) { 457 chp->ch_drive[i].chnl_softc = chp; 458 chp->ch_drive[i].drive = i; 459 } 460 461 /* bring interface up, power up and spin up device */ 462 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 463 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 464 /* reset the PHY and bring online */ 465 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 466 achp->ahcic_sstatus)) { 467 case SStatus_DET_DEV: 468 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 469 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 470 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 471 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 472 AHCINAME(sc), chp->ch_channel, sig, 473 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 474 /* 475 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 476 * cases we get wrong values here, so ignore it. 477 */ 478 s = splbio(); 479 if ((sig & 0xffff0000) == 0xeb140000) { 480 aprint_error("%s port %d: ATAPI device ignored\n", 481 AHCINAME(sc), chp->ch_channel); 482 chp->ch_drive[0].drive_flags |= 0 /* DRIVE_ATAPI XXX */; 483 } else 484 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 485 splx(s); 486 /* enable interrupts */ 487 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 488 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 489 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 490 AHCI_P_IX_DHRS); 491 /* and start operations */ 492 ahci_channel_start(sc, chp); 493 break; 494 495 default: 496 break; 497 } 498 } 499 500 void 501 ahci_setup_channel(struct ata_channel *chp) 502 { 503 return; 504 } 505 506 int 507 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 508 { 509 struct ata_channel *chp = drvp->chnl_softc; 510 struct ata_xfer *xfer; 511 int ret; 512 int s; 513 514 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 515 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 516 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 517 DEBUG_XFERS); 518 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 519 ATAXF_NOSLEEP); 520 if (xfer == NULL) { 521 return ATACMD_TRY_AGAIN; 522 } 523 if (ata_c->flags & AT_POLL) 524 xfer->c_flags |= C_POLL; 525 if (ata_c->flags & AT_WAIT) 526 xfer->c_flags |= C_WAIT; 527 xfer->c_drive = drvp->drive; 528 xfer->c_databuf = ata_c->data; 529 xfer->c_bcount = ata_c->bcount; 530 xfer->c_cmd = ata_c; 531 xfer->c_start = ahci_cmd_start; 532 xfer->c_intr = ahci_cmd_complete; 533 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 534 s = splbio(); 535 ata_exec_xfer(chp, xfer); 536 #ifdef DIAGNOSTIC 537 if ((ata_c->flags & AT_POLL) != 0 && 538 (ata_c->flags & AT_DONE) == 0) 539 panic("ahci_exec_command: polled command not done"); 540 #endif 541 if (ata_c->flags & AT_DONE) { 542 ret = ATACMD_COMPLETE; 543 } else { 544 if (ata_c->flags & AT_WAIT) { 545 while ((ata_c->flags & AT_DONE) == 0) { 546 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 547 } 548 ret = ATACMD_COMPLETE; 549 } else { 550 ret = ATACMD_QUEUED; 551 } 552 } 553 splx(s); 554 return ret; 555 } 556 557 void 558 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 559 { 560 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 561 struct ahci_channel *achp = (struct ahci_channel *)chp; 562 struct ata_command *ata_c = xfer->c_cmd; 563 int slot = 0 /* XXX slot */; 564 struct ahci_cmd_tbl *cmd_tbl; 565 struct ahci_cmd_header *cmd_h; 566 u_int8_t *fis; 567 int i; 568 int channel = chp->ch_channel; 569 570 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 571 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 572 573 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 574 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 575 cmd_tbl), DEBUG_XFERS); 576 fis = cmd_tbl->cmdt_cfis; 577 578 fis[0] = 0x27; /* host to device */ 579 fis[1] = 0x80; /* command FIS */ 580 fis[2] = ata_c->r_command; 581 fis[3] = ata_c->r_features; 582 fis[4] = ata_c->r_sector; 583 fis[5] = ata_c->r_cyl & 0xff; 584 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 585 fis[7] = ata_c->r_head & 0x0f; 586 fis[8] = 0; 587 fis[9] = 0; 588 fis[10] = 0; 589 fis[11] = 0; 590 fis[12] = ata_c->r_count; 591 fis[13] = 0; 592 fis[14] = 0; 593 fis[15] = WDCTL_4BIT; 594 fis[16] = 0; 595 fis[17] = 0; 596 fis[18] = 0; 597 fis[19] = 0; 598 599 cmd_h = &achp->ahcic_cmdh[slot]; 600 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 601 chp->ch_channel, cmd_h), DEBUG_XFERS); 602 if (ahci_dma_setup(chp, slot, 603 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 604 ata_c->bcount, 605 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 606 ata_c->flags |= AT_DF; 607 ahci_cmd_complete(chp, xfer, slot); 608 return; 609 } 610 cmd_h->cmdh_flags = htole16( 611 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 612 20 /* fis lenght */ / 4); 613 cmd_h->cmdh_prdbc = 0; 614 AHCI_CMDH_SYNC(sc, achp, slot, 615 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 616 617 if (ata_c->flags & AT_POLL) { 618 /* polled command, disable interrupts */ 619 AHCI_WRITE(sc, AHCI_GHC, 620 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 621 } 622 chp->ch_flags |= ATACH_IRQ_WAIT; 623 /* start command */ 624 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 625 /* and says we started this command */ 626 achp->ahcic_cmds_active |= 1 << slot; 627 628 if ((ata_c->flags & AT_POLL) == 0) { 629 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 630 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 631 ahci_timeout, chp); 632 return; 633 } 634 /* 635 * Polled command. 636 */ 637 for (i = 0; i < ata_c->timeout / 10; i++) { 638 if (ata_c->flags & AT_DONE) 639 break; 640 ahci_intr_port(sc, achp); 641 if (ata_c->flags & AT_WAIT) 642 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 643 else 644 delay(10000); 645 } 646 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 647 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 648 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 649 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 650 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 651 DEBUG_XFERS); 652 if ((ata_c->flags & AT_DONE) == 0) { 653 ata_c->flags |= AT_TIMEOU; 654 ahci_cmd_complete(chp, xfer, slot); 655 } 656 /* reenable interrupts */ 657 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 658 } 659 660 void 661 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 662 { 663 struct ata_command *ata_c = xfer->c_cmd; 664 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 665 DEBUG_FUNCS); 666 667 switch (reason) { 668 case KILL_GONE: 669 ata_c->flags |= AT_GONE; 670 break; 671 case KILL_RESET: 672 ata_c->flags |= AT_RESET; 673 break; 674 default: 675 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 676 panic("ahci_cmd_kill_xfer"); 677 } 678 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 679 } 680 681 int 682 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 683 { 684 int slot = 0; /* XXX slot */ 685 struct ata_command *ata_c = xfer->c_cmd; 686 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 687 688 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 689 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 690 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 691 DEBUG_FUNCS); 692 chp->ch_flags &= ~ATACH_IRQ_WAIT; 693 if (xfer->c_flags & C_TIMEOU) { 694 ata_c->flags |= AT_TIMEOU; 695 } else 696 callout_stop(&chp->ch_callout); 697 698 chp->ch_queue->active_xfer = NULL; 699 700 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 701 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 702 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 703 wakeup(&chp->ch_queue->active_xfer); 704 return 0; 705 } 706 if (is) { 707 ata_c->r_head = 0; 708 ata_c->r_count = 0; 709 ata_c->r_sector = 0; 710 ata_c->r_cyl = 0; 711 if (chp->ch_status & WDCS_BSY) { 712 ata_c->flags |= AT_TIMEOU; 713 } else if (chp->ch_status & WDCS_ERR) { 714 ata_c->r_error = chp->ch_error; 715 ata_c->flags |= AT_ERROR; 716 } 717 } 718 ahci_cmd_done(chp, xfer, slot); 719 return 0; 720 } 721 722 void 723 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 724 { 725 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 726 struct ahci_channel *achp = (struct ahci_channel *)chp; 727 struct ata_command *ata_c = xfer->c_cmd; 728 729 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 730 DEBUG_FUNCS); 731 732 /* this comamnd is not active any more */ 733 achp->ahcic_cmds_active &= ~(1 << slot); 734 735 if (ata_c->flags & (AT_READ|AT_WRITE)) { 736 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 737 achp->ahcic_datad[slot]->dm_mapsize, 738 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 739 BUS_DMASYNC_POSTWRITE); 740 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 741 } 742 743 ata_c->flags |= AT_DONE; 744 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 745 ata_c->flags |= AT_XFDONE; 746 747 ata_free_xfer(chp, xfer); 748 if (ata_c->flags & AT_WAIT) 749 wakeup(ata_c); 750 else if (ata_c->callback) 751 ata_c->callback(ata_c->callback_arg); 752 atastart(chp); 753 return; 754 } 755 756 int 757 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 758 { 759 struct ata_channel *chp = drvp->chnl_softc; 760 struct ata_xfer *xfer; 761 762 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 763 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 764 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 765 DEBUG_XFERS); 766 xfer = ata_get_xfer(ATAXF_NOSLEEP); 767 if (xfer == NULL) { 768 return ATACMD_TRY_AGAIN; 769 } 770 if (ata_bio->flags & ATA_POLL) 771 xfer->c_flags |= C_POLL; 772 xfer->c_drive = drvp->drive; 773 xfer->c_cmd = ata_bio; 774 xfer->c_databuf = ata_bio->databuf; 775 xfer->c_bcount = ata_bio->bcount; 776 xfer->c_start = ahci_bio_start; 777 xfer->c_intr = ahci_bio_complete; 778 xfer->c_kill_xfer = ahci_bio_kill_xfer; 779 ata_exec_xfer(chp, xfer); 780 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 781 } 782 783 void 784 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 785 { 786 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 787 struct ahci_channel *achp = (struct ahci_channel *)chp; 788 struct ata_bio *ata_bio = xfer->c_cmd; 789 int slot = 0 /* XXX slot */; 790 struct ahci_cmd_tbl *cmd_tbl; 791 struct ahci_cmd_header *cmd_h; 792 u_int8_t *fis; 793 int i, nblks; 794 int channel = chp->ch_channel; 795 796 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 797 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 798 799 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 800 801 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 802 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 803 cmd_tbl), DEBUG_XFERS); 804 fis = cmd_tbl->cmdt_cfis; 805 806 fis[0] = 0x27; /* host to device */ 807 fis[1] = 0x80; /* command FIS */ 808 if (ata_bio->flags & ATA_LBA48) { 809 fis[2] = (ata_bio->flags & ATA_READ) ? 810 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 811 } else { 812 fis[2] = 813 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 814 } 815 fis[3] = 0; /* features */ 816 fis[4] = ata_bio->blkno & 0xff; 817 fis[5] = (ata_bio->blkno >> 8) & 0xff; 818 fis[6] = (ata_bio->blkno >> 16) & 0xff; 819 if (ata_bio->flags & ATA_LBA48) { 820 fis[7] = WDSD_LBA; 821 fis[8] = (ata_bio->blkno >> 24) & 0xff; 822 fis[9] = (ata_bio->blkno >> 32) & 0xff; 823 fis[10] = (ata_bio->blkno >> 40) & 0xff; 824 } else { 825 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 826 fis[8] = 0; 827 fis[9] = 0; 828 fis[10] = 0; 829 } 830 fis[11] = 0; /* ext features */ 831 fis[12] = nblks & 0xff; 832 fis[13] = (ata_bio->flags & ATA_LBA48) ? 833 ((nblks >> 8) & 0xff) : 0; 834 fis[14] = 0; 835 fis[15] = WDCTL_4BIT; 836 fis[16] = 0; 837 fis[17] = 0; 838 fis[18] = 0; 839 fis[19] = 0; 840 841 cmd_h = &achp->ahcic_cmdh[slot]; 842 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 843 chp->ch_channel, cmd_h), DEBUG_XFERS); 844 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 845 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 846 ata_bio->error = ERR_DMA; 847 ata_bio->r_error = 0; 848 ahci_bio_complete(chp, xfer, slot); 849 return; 850 } 851 cmd_h->cmdh_flags = htole16( 852 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 853 20 /* fis lenght */ / 4); 854 cmd_h->cmdh_prdbc = 0; 855 AHCI_CMDH_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 856 857 if (xfer->c_flags & C_POLL) { 858 /* polled command, disable interrupts */ 859 AHCI_WRITE(sc, AHCI_GHC, 860 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 861 } 862 chp->ch_flags |= ATACH_IRQ_WAIT; 863 /* start command */ 864 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 865 /* and says we started this command */ 866 achp->ahcic_cmds_active |= 1 << slot; 867 868 if ((xfer->c_flags & C_POLL) == 0) { 869 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 870 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 871 ahci_timeout, chp); 872 return; 873 } 874 /* 875 * Polled command. 876 */ 877 for (i = 0; i < ATA_DELAY / 10; i++) { 878 if (ata_bio->flags & ATA_ITSDONE) 879 break; 880 ahci_intr_port(sc, achp); 881 if (ata_bio->flags & ATA_NOSLEEP) 882 delay(10000); 883 else 884 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 885 } 886 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 887 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 888 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 889 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 890 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 891 DEBUG_XFERS); 892 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 893 ata_bio->error = TIMEOUT; 894 ahci_bio_complete(chp, xfer, slot); 895 } 896 /* reenable interrupts */ 897 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 898 } 899 900 void 901 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 902 { 903 int slot = 0; /* XXX slot */ 904 int drive = xfer->c_drive; 905 struct ata_bio *ata_bio = xfer->c_cmd; 906 struct ahci_channel *achp = (struct ahci_channel *)chp; 907 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 908 DEBUG_FUNCS); 909 910 achp->ahcic_cmds_active &= ~(1 << slot); 911 ata_free_xfer(chp, xfer); 912 ata_bio->flags |= ATA_ITSDONE; 913 switch (reason) { 914 case KILL_GONE: 915 ata_bio->error = ERR_NODEV; 916 break; 917 case KILL_RESET: 918 ata_bio->error = ERR_RESET; 919 break; 920 default: 921 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 922 panic("ahci_bio_kill_xfer"); 923 } 924 ata_bio->r_error = WDCE_ABRT; 925 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 926 } 927 928 int 929 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 930 { 931 int slot = 0; /* XXX slot */ 932 struct ata_bio *ata_bio = xfer->c_cmd; 933 int drive = xfer->c_drive; 934 struct ahci_channel *achp = (struct ahci_channel *)chp; 935 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 936 937 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 938 DEBUG_FUNCS); 939 940 achp->ahcic_cmds_active &= ~(1 << slot); 941 chp->ch_flags &= ~ATACH_IRQ_WAIT; 942 callout_stop(&chp->ch_callout); 943 944 chp->ch_queue->active_xfer = NULL; 945 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 946 achp->ahcic_datad[slot]->dm_mapsize, 947 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 948 BUS_DMASYNC_POSTWRITE); 949 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 950 951 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 952 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 953 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 954 wakeup(&chp->ch_queue->active_xfer); 955 return 0; 956 } 957 ata_free_xfer(chp, xfer); 958 ata_bio->flags |= ATA_ITSDONE; 959 if (chp->ch_status & WDCS_DWF) { 960 ata_bio->error = ERR_DF; 961 } else if (chp->ch_status & WDCS_ERR) { 962 ata_bio->error = ERROR; 963 ata_bio->r_error = chp->ch_error; 964 } else if (chp->ch_status & WDCS_CORR) 965 ata_bio->flags |= ATA_CORR; 966 967 AHCI_CMDH_SYNC(sc, achp, slot, 968 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 969 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 970 ata_bio->bcount), DEBUG_XFERS); 971 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 972 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 973 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 974 atastart(chp); 975 return 0; 976 } 977 978 void 979 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 980 { 981 /* clear error */ 982 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 983 984 /* and start controller */ 985 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 986 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 987 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 988 } 989 990 void 991 ahci_timeout(void *v) 992 { 993 struct ata_channel *chp = (struct ata_channel *)v; 994 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 995 int s = splbio(); 996 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 997 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 998 xfer->c_flags |= C_TIMEOU; 999 xfer->c_intr(chp, xfer, 0); 1000 } 1001 splx(s); 1002 } 1003 1004 int 1005 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1006 size_t count, int op) 1007 { 1008 int error, seg; 1009 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1010 struct ahci_channel *achp = (struct ahci_channel *)chp; 1011 struct ahci_cmd_tbl *cmd_tbl; 1012 struct ahci_cmd_header *cmd_h; 1013 1014 cmd_h = &achp->ahcic_cmdh[slot]; 1015 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1016 1017 if (data == NULL) { 1018 cmd_h->cmdh_prdtl = 0; 1019 goto end; 1020 } 1021 1022 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1023 data, count, NULL, 1024 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1025 if (error) { 1026 printf("%s port %d: failed to load xfer: %d\n", 1027 AHCINAME(sc), chp->ch_channel, error); 1028 return error; 1029 } 1030 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1031 achp->ahcic_datad[slot]->dm_mapsize, 1032 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1033 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1034 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1035 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1036 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1037 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1038 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1039 } 1040 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1041 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1042 end: 1043 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1044 return 0; 1045 } 1046
Indexes created Fri Oct 17 00:09:41 GMT 2025