ahcisata_core.c revision 1.4.12.4
1 /* $NetBSD: ahcisata_core.c,v 1.4.12.4 2007/09/16 15:29:05 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.4.12.4 2007/09/16 15:29:05 xtraeme Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/ic/wdcreg.h> 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/satavar.h> 48 #include <dev/ata/satareg.h> 49 #include <dev/ic/ahcisatavar.h> 50 51 #ifdef AHCI_DEBUG 52 int ahcidebug_mask = 0x0; 53 #endif 54 55 void ahci_probe_drive(struct ata_channel *); 56 void ahci_setup_channel(struct ata_channel *); 57 58 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 59 void ahci_reset_drive(struct ata_drive_datas *, int); 60 void ahci_reset_channel(struct ata_channel *, int); 61 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 62 int ahci_ata_addref(struct ata_drive_datas *); 63 void ahci_ata_delref(struct ata_drive_datas *); 64 void ahci_killpending(struct ata_drive_datas *); 65 66 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 67 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 68 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 69 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 70 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 71 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 72 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 74 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 75 void ahci_timeout(void *); 76 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 77 78 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 79 80 const struct ata_bustype ahci_ata_bustype = { 81 SCSIPI_BUSTYPE_ATA, 82 ahci_ata_bio, 83 ahci_reset_drive, 84 ahci_reset_channel, 85 ahci_exec_command, 86 ata_get_params, 87 ahci_ata_addref, 88 ahci_ata_delref, 89 ahci_killpending 90 }; 91 92 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 93 94 void 95 ahci_attach(struct ahci_softc *sc) 96 { 97 u_int32_t ahci_cap, ahci_rev, ahci_ports; 98 int i, j, port; 99 struct ahci_channel *achp; 100 struct ata_channel *chp; 101 int error; 102 bus_dma_segment_t seg; 103 int rseg; 104 int dmasize; 105 caddr_t cmdhp; 106 caddr_t cmdtblp; 107 108 /* reset controller */ 109 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 110 delay(1000); 111 /* wait up to 1s for reset to complete */ 112 for (i = 0; i < 1000; i++) { 113 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 114 break; 115 } 116 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 117 aprint_error("%s: reset failed\n", AHCINAME(sc)); 118 return; 119 } 120 /* enable ahci mode */ 121 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 122 123 124 ahci_cap = AHCI_READ(sc, AHCI_CAP); 125 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 126 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 127 ahci_rev = AHCI_READ(sc, AHCI_VS); 128 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 129 switch(ahci_rev) { 130 case AHCI_VS_10: 131 aprint_normal("1.0"); 132 break; 133 case AHCI_VS_11: 134 aprint_normal("1.1"); 135 break; 136 default: 137 aprint_normal("0x%x", ahci_rev); 138 break; 139 } 140 141 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 142 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 143 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 144 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 145 sc->sc_atac.atac_pio_cap = 4; 146 sc->sc_atac.atac_dma_cap = 2; 147 sc->sc_atac.atac_udma_cap = 6; 148 sc->sc_atac.atac_channels = sc->sc_chanarray; 149 sc->sc_atac.atac_atapibus_attach = NULL; /* XXX */ 150 sc->sc_atac.atac_probe = ahci_probe_drive; 151 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 152 sc->sc_atac.atac_set_modes = ahci_setup_channel; 153 154 dmasize = 155 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 156 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 157 &seg, 1, &rseg, BUS_DMA_NOWAIT); 158 if (error) { 159 aprint_error("%s: unable to allocate command header memory" 160 ", error=%d\n", AHCINAME(sc), error); 161 return; 162 } 163 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 164 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 165 if (error) { 166 aprint_error("%s: unable to map command header memory" 167 ", error=%d\n", AHCINAME(sc), error); 168 return; 169 } 170 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 171 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 172 if (error) { 173 aprint_error("%s: unable to create command header map" 174 ", error=%d\n", AHCINAME(sc), error); 175 return; 176 } 177 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 178 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 179 if (error) { 180 aprint_error("%s: unable to load command header map" 181 ", error=%d\n", AHCINAME(sc), error); 182 return; 183 } 184 sc->sc_cmd_hdr = cmdhp; 185 186 /* clear interrupts */ 187 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 188 /* enable interrupts */ 189 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 190 191 ahci_ports = AHCI_READ(sc, AHCI_PI); 192 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 193 if ((ahci_ports & (1 << i)) == 0) 194 continue; 195 if (port >= sc->sc_atac.atac_nchannels) { 196 aprint_error("%s: more ports than announced\n", 197 AHCINAME(sc)); 198 break; 199 } 200 achp = &sc->sc_channels[i]; 201 chp = (struct ata_channel *)achp; 202 sc->sc_chanarray[i] = chp; 203 chp->ch_channel = i; 204 chp->ch_atac = &sc->sc_atac; 205 chp->ch_queue = malloc(sizeof(struct ata_queue), 206 M_DEVBUF, M_NOWAIT); 207 if (chp->ch_queue == NULL) { 208 aprint_error("%s port %d: can't allocate memory for " 209 "command queue", AHCINAME(sc), i); 210 break; 211 } 212 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 213 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 214 &seg, 1, &rseg, BUS_DMA_NOWAIT); 215 if (error) { 216 aprint_error("%s: unable to allocate command table " 217 "memory, error=%d\n", AHCINAME(sc), error); 218 break; 219 } 220 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 221 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 222 if (error) { 223 aprint_error("%s: unable to map command table memory" 224 ", error=%d\n", AHCINAME(sc), error); 225 break; 226 } 227 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 228 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 229 if (error) { 230 aprint_error("%s: unable to create command table map" 231 ", error=%d\n", AHCINAME(sc), error); 232 break; 233 } 234 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 235 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 236 if (error) { 237 aprint_error("%s: unable to load command table map" 238 ", error=%d\n", AHCINAME(sc), error); 239 break; 240 } 241 achp->ahcic_cmdh = (struct ahci_cmd_header *) 242 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 243 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 244 AHCI_CMDH_SIZE * port; 245 achp->ahcic_rfis = (struct ahci_r_fis *) 246 ((char *)cmdhp + 247 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 248 AHCI_RFIS_SIZE * port); 249 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 250 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 251 AHCI_RFIS_SIZE * port; 252 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 253 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 254 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 255 DEBUG_PROBE); 256 257 for (j = 0; j < sc->sc_ncmds; j++) { 258 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 259 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 260 achp->ahcic_bus_cmd_tbl[j] = 261 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 262 AHCI_CMDTBL_SIZE * j; 263 achp->ahcic_cmdh[j].cmdh_cmdtba = 264 htole32(achp->ahcic_bus_cmd_tbl[j]); 265 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 266 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 267 achp->ahcic_cmd_tbl[j], 268 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 269 /* The xfer DMA map */ 270 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 271 AHCI_NPRD, 0x400000 /* 4MB */, 0, 272 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 273 &achp->ahcic_datad[j]); 274 if (error) { 275 aprint_error("%s: couldn't alloc xfer DMA map, " 276 "error=%d\n", AHCINAME(sc), error); 277 goto end; 278 } 279 } 280 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 281 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 282 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 283 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 284 chp->ch_ndrive = 1; 285 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 286 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 287 aprint_error("%s: couldn't map channel %d " 288 "sata_status regs\n", AHCINAME(sc), i); 289 break; 290 } 291 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 292 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 293 aprint_error("%s: couldn't map channel %d " 294 "sata_control regs\n", AHCINAME(sc), i); 295 break; 296 } 297 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 298 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 299 aprint_error("%s: couldn't map channel %d " 300 "sata_error regs\n", AHCINAME(sc), i); 301 break; 302 } 303 ata_channel_attach(chp); 304 port++; 305 end: 306 continue; 307 } 308 } 309 310 int 311 ahci_intr(void *v) 312 { 313 struct ahci_softc *sc = v; 314 u_int32_t is; 315 int i, r = 0; 316 317 while ((is = AHCI_READ(sc, AHCI_IS))) { 318 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 319 DEBUG_INTR); 320 r = 1; 321 AHCI_WRITE(sc, AHCI_IS, is); 322 for (i = 0; i < AHCI_MAX_PORTS; i++) 323 if (is & (1 << i)) 324 ahci_intr_port(sc, &sc->sc_channels[i]); 325 } 326 return r; 327 } 328 329 void 330 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 331 { 332 u_int32_t is, tfd; 333 struct ata_channel *chp = &achp->ata_channel; 334 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 335 int slot; 336 337 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 338 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 339 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 340 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 341 DEBUG_INTR); 342 343 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 344 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 345 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 346 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 347 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 348 return; 349 /* stop channel */ 350 ahci_channel_stop(sc, chp, 0); 351 if (slot != 0) { 352 printf("ahci_intr_port: slot %d\n", slot); 353 panic("ahci_intr_port"); 354 } 355 if (is & AHCI_P_IX_TFES) { 356 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 357 chp->ch_error = 358 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 359 chp->ch_status = (tfd & 0xff); 360 } else { 361 /* emulate a CRC error */ 362 chp->ch_error = WDCE_CRC; 363 chp->ch_status = WDCS_ERR; 364 } 365 xfer->c_intr(chp, xfer, is); 366 /* if channel has not been restarted, do it now */ 367 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 368 == 0) 369 ahci_channel_start(sc, chp); 370 } else { 371 slot = 0; /* XXX */ 372 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 373 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 374 chp->ch_channel, is, achp->ahcic_cmds_active, 375 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 376 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 377 return; 378 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 379 == 0) { 380 xfer->c_intr(chp, xfer, 0); 381 } 382 } 383 } 384 385 void 386 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 387 { 388 struct ata_channel *chp = drvp->chnl_softc; 389 ata_reset_channel(chp, flags); 390 return; 391 } 392 393 void 394 ahci_reset_channel(struct ata_channel *chp, int flags) 395 { 396 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 397 struct ahci_channel *achp = (struct ahci_channel *)chp; 398 399 ahci_channel_stop(sc, chp, flags); 400 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 401 achp->ahcic_sstatus) != SStatus_DET_DEV) { 402 printf("%s: port reset failed\n", AHCINAME(sc)); 403 /* XXX and then ? */ 404 } 405 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 406 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 407 if (chp->ch_queue->active_xfer) { 408 chp->ch_queue->active_xfer->c_kill_xfer(chp, 409 chp->ch_queue->active_xfer, KILL_RESET); 410 } 411 ahci_channel_start(sc, chp); 412 return; 413 } 414 415 int 416 ahci_ata_addref(struct ata_drive_datas *drvp) 417 { 418 return 0; 419 } 420 421 void 422 ahci_ata_delref(struct ata_drive_datas *drvp) 423 { 424 return; 425 } 426 427 void 428 ahci_killpending(struct ata_drive_datas *drvp) 429 { 430 return; 431 } 432 433 void 434 ahci_probe_drive(struct ata_channel *chp) 435 { 436 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 437 struct ahci_channel *achp = (struct ahci_channel *)chp; 438 int i, s; 439 u_int32_t sig; 440 441 /* XXX This should be done by other code. */ 442 for (i = 0; i < chp->ch_ndrive; i++) { 443 chp->ch_drive[i].chnl_softc = chp; 444 chp->ch_drive[i].drive = i; 445 } 446 447 /* bring interface up, power up and spin up device */ 448 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 449 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 450 /* reset the PHY and bring online */ 451 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 452 achp->ahcic_sstatus)) { 453 case SStatus_DET_DEV: 454 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 455 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 456 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 457 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 458 AHCINAME(sc), chp->ch_channel, sig, 459 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 460 /* 461 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 462 * cases we get wrong values here, so ignore it. 463 */ 464 s = splbio(); 465 if ((sig & 0xffff0000) == 0xeb140000) { 466 aprint_error("%s port %d: ATAPI device ignored\n", 467 AHCINAME(sc), chp->ch_channel); 468 chp->ch_drive[0].drive_flags |= 0 /* DRIVE_ATAPI XXX */; 469 } else 470 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 471 splx(s); 472 /* enable interrupts */ 473 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 474 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 475 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 476 AHCI_P_IX_DHRS); 477 /* and start operations */ 478 ahci_channel_start(sc, chp); 479 break; 480 481 default: 482 break; 483 } 484 } 485 486 void 487 ahci_setup_channel(struct ata_channel *chp) 488 { 489 return; 490 } 491 492 int 493 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 494 { 495 struct ata_channel *chp = drvp->chnl_softc; 496 struct ata_xfer *xfer; 497 int ret; 498 int s; 499 500 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 501 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 502 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 503 DEBUG_XFERS); 504 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 505 ATAXF_NOSLEEP); 506 if (xfer == NULL) { 507 return ATACMD_TRY_AGAIN; 508 } 509 if (ata_c->flags & AT_POLL) 510 xfer->c_flags |= C_POLL; 511 if (ata_c->flags & AT_WAIT) 512 xfer->c_flags |= C_WAIT; 513 xfer->c_drive = drvp->drive; 514 xfer->c_databuf = ata_c->data; 515 xfer->c_bcount = ata_c->bcount; 516 xfer->c_cmd = ata_c; 517 xfer->c_start = ahci_cmd_start; 518 xfer->c_intr = ahci_cmd_complete; 519 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 520 s = splbio(); 521 ata_exec_xfer(chp, xfer); 522 #ifdef DIAGNOSTIC 523 if ((ata_c->flags & AT_POLL) != 0 && 524 (ata_c->flags & AT_DONE) == 0) 525 panic("ahci_exec_command: polled command not done"); 526 #endif 527 if (ata_c->flags & AT_DONE) { 528 ret = ATACMD_COMPLETE; 529 } else { 530 if (ata_c->flags & AT_WAIT) { 531 while ((ata_c->flags & AT_DONE) == 0) { 532 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 533 } 534 ret = ATACMD_COMPLETE; 535 } else { 536 ret = ATACMD_QUEUED; 537 } 538 } 539 splx(s); 540 return ret; 541 } 542 543 void 544 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 545 { 546 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 547 struct ahci_channel *achp = (struct ahci_channel *)chp; 548 struct ata_command *ata_c = xfer->c_cmd; 549 int slot = 0 /* XXX slot */; 550 struct ahci_cmd_tbl *cmd_tbl; 551 struct ahci_cmd_header *cmd_h; 552 u_int8_t *fis; 553 int i; 554 int channel = chp->ch_channel; 555 556 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 557 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 558 559 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 560 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 561 cmd_tbl), DEBUG_XFERS); 562 fis = cmd_tbl->cmdt_cfis; 563 564 fis[0] = 0x27; /* host to device */ 565 fis[1] = 0x80; /* command FIS */ 566 fis[2] = ata_c->r_command; 567 fis[3] = ata_c->r_features; 568 fis[4] = ata_c->r_sector; 569 fis[5] = ata_c->r_cyl & 0xff; 570 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 571 fis[7] = ata_c->r_head & 0x0f; 572 fis[8] = 0; 573 fis[9] = 0; 574 fis[10] = 0; 575 fis[11] = 0; 576 fis[12] = ata_c->r_count; 577 fis[13] = 0; 578 fis[14] = 0; 579 fis[15] = WDCTL_4BIT; 580 fis[16] = 0; 581 fis[17] = 0; 582 fis[18] = 0; 583 fis[19] = 0; 584 585 cmd_h = &achp->ahcic_cmdh[slot]; 586 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 587 chp->ch_channel, cmd_h), DEBUG_XFERS); 588 if (ahci_dma_setup(chp, slot, 589 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 590 ata_c->bcount, 591 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 592 ata_c->flags |= AT_DF; 593 ahci_cmd_complete(chp, xfer, slot); 594 return; 595 } 596 cmd_h->cmdh_flags = htole16( 597 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 598 20 /* fis lenght */ / 4); 599 cmd_h->cmdh_prdbc = 0; 600 AHCI_CMDH_SYNC(sc, achp, slot, 601 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 602 603 if (ata_c->flags & AT_POLL) { 604 /* polled command, disable interrupts */ 605 AHCI_WRITE(sc, AHCI_GHC, 606 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 607 } 608 chp->ch_flags |= ATACH_IRQ_WAIT; 609 chp->ch_status = 0; 610 /* start command */ 611 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 612 /* and says we started this command */ 613 achp->ahcic_cmds_active |= 1 << slot; 614 615 if ((ata_c->flags & AT_POLL) == 0) { 616 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 617 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 618 ahci_timeout, chp); 619 return; 620 } 621 /* 622 * Polled command. 623 */ 624 for (i = 0; i < ata_c->timeout / 10; i++) { 625 if (ata_c->flags & AT_DONE) 626 break; 627 ahci_intr_port(sc, achp); 628 if (ata_c->flags & AT_WAIT) 629 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 630 else 631 delay(10000); 632 } 633 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 634 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 635 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 636 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 637 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 638 DEBUG_XFERS); 639 if ((ata_c->flags & AT_DONE) == 0) { 640 ata_c->flags |= AT_TIMEOU; 641 ahci_cmd_complete(chp, xfer, slot); 642 } 643 /* reenable interrupts */ 644 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 645 } 646 647 void 648 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 649 { 650 struct ata_command *ata_c = xfer->c_cmd; 651 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 652 DEBUG_FUNCS); 653 654 switch (reason) { 655 case KILL_GONE: 656 ata_c->flags |= AT_GONE; 657 break; 658 case KILL_RESET: 659 ata_c->flags |= AT_RESET; 660 break; 661 default: 662 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 663 panic("ahci_cmd_kill_xfer"); 664 } 665 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 666 } 667 668 int 669 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 670 { 671 int slot = 0; /* XXX slot */ 672 struct ata_command *ata_c = xfer->c_cmd; 673 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 674 675 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 676 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 677 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 678 DEBUG_FUNCS); 679 chp->ch_flags &= ~ATACH_IRQ_WAIT; 680 if (xfer->c_flags & C_TIMEOU) { 681 ata_c->flags |= AT_TIMEOU; 682 } else 683 callout_stop(&chp->ch_callout); 684 685 chp->ch_queue->active_xfer = NULL; 686 687 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 688 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 689 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 690 wakeup(&chp->ch_queue->active_xfer); 691 return 0; 692 } 693 if (is) { 694 ata_c->r_head = 0; 695 ata_c->r_count = 0; 696 ata_c->r_sector = 0; 697 ata_c->r_cyl = 0; 698 if (chp->ch_status & WDCS_BSY) { 699 ata_c->flags |= AT_TIMEOU; 700 } else if (chp->ch_status & WDCS_ERR) { 701 ata_c->r_error = chp->ch_error; 702 ata_c->flags |= AT_ERROR; 703 } 704 } 705 ahci_cmd_done(chp, xfer, slot); 706 return 0; 707 } 708 709 void 710 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 711 { 712 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 713 struct ahci_channel *achp = (struct ahci_channel *)chp; 714 struct ata_command *ata_c = xfer->c_cmd; 715 716 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 717 DEBUG_FUNCS); 718 719 /* this comamnd is not active any more */ 720 achp->ahcic_cmds_active &= ~(1 << slot); 721 722 if (ata_c->flags & (AT_READ|AT_WRITE)) { 723 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 724 achp->ahcic_datad[slot]->dm_mapsize, 725 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 726 BUS_DMASYNC_POSTWRITE); 727 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 728 } 729 730 AHCI_CMDH_SYNC(sc, achp, slot, 731 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 732 733 ata_c->flags |= AT_DONE; 734 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 735 ata_c->flags |= AT_XFDONE; 736 737 ata_free_xfer(chp, xfer); 738 if (ata_c->flags & AT_WAIT) 739 wakeup(ata_c); 740 else if (ata_c->callback) 741 ata_c->callback(ata_c->callback_arg); 742 atastart(chp); 743 return; 744 } 745 746 int 747 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 748 { 749 struct ata_channel *chp = drvp->chnl_softc; 750 struct ata_xfer *xfer; 751 752 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 753 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 754 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 755 DEBUG_XFERS); 756 xfer = ata_get_xfer(ATAXF_NOSLEEP); 757 if (xfer == NULL) { 758 return ATACMD_TRY_AGAIN; 759 } 760 if (ata_bio->flags & ATA_POLL) 761 xfer->c_flags |= C_POLL; 762 xfer->c_drive = drvp->drive; 763 xfer->c_cmd = ata_bio; 764 xfer->c_databuf = ata_bio->databuf; 765 xfer->c_bcount = ata_bio->bcount; 766 xfer->c_start = ahci_bio_start; 767 xfer->c_intr = ahci_bio_complete; 768 xfer->c_kill_xfer = ahci_bio_kill_xfer; 769 ata_exec_xfer(chp, xfer); 770 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 771 } 772 773 void 774 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 775 { 776 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 777 struct ahci_channel *achp = (struct ahci_channel *)chp; 778 struct ata_bio *ata_bio = xfer->c_cmd; 779 int slot = 0 /* XXX slot */; 780 struct ahci_cmd_tbl *cmd_tbl; 781 struct ahci_cmd_header *cmd_h; 782 u_int8_t *fis; 783 int i, nblks; 784 int channel = chp->ch_channel; 785 786 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 787 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 788 789 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 790 791 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 792 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 793 cmd_tbl), DEBUG_XFERS); 794 fis = cmd_tbl->cmdt_cfis; 795 796 fis[0] = 0x27; /* host to device */ 797 fis[1] = 0x80; /* command FIS */ 798 if (ata_bio->flags & ATA_LBA48) { 799 fis[2] = (ata_bio->flags & ATA_READ) ? 800 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 801 } else { 802 fis[2] = 803 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 804 } 805 fis[3] = 0; /* features */ 806 fis[4] = ata_bio->blkno & 0xff; 807 fis[5] = (ata_bio->blkno >> 8) & 0xff; 808 fis[6] = (ata_bio->blkno >> 16) & 0xff; 809 if (ata_bio->flags & ATA_LBA48) { 810 fis[7] = WDSD_LBA; 811 fis[8] = (ata_bio->blkno >> 24) & 0xff; 812 fis[9] = (ata_bio->blkno >> 32) & 0xff; 813 fis[10] = (ata_bio->blkno >> 40) & 0xff; 814 } else { 815 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 816 fis[8] = 0; 817 fis[9] = 0; 818 fis[10] = 0; 819 } 820 fis[11] = 0; /* ext features */ 821 fis[12] = nblks & 0xff; 822 fis[13] = (ata_bio->flags & ATA_LBA48) ? 823 ((nblks >> 8) & 0xff) : 0; 824 fis[14] = 0; 825 fis[15] = WDCTL_4BIT; 826 fis[16] = 0; 827 fis[17] = 0; 828 fis[18] = 0; 829 fis[19] = 0; 830 831 cmd_h = &achp->ahcic_cmdh[slot]; 832 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 833 chp->ch_channel, cmd_h), DEBUG_XFERS); 834 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 835 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 836 ata_bio->error = ERR_DMA; 837 ata_bio->r_error = 0; 838 ahci_bio_complete(chp, xfer, slot); 839 return; 840 } 841 cmd_h->cmdh_flags = htole16( 842 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 843 20 /* fis lenght */ / 4); 844 cmd_h->cmdh_prdbc = 0; 845 AHCI_CMDH_SYNC(sc, achp, slot, 846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 847 848 if (xfer->c_flags & C_POLL) { 849 /* polled command, disable interrupts */ 850 AHCI_WRITE(sc, AHCI_GHC, 851 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 852 } 853 chp->ch_flags |= ATACH_IRQ_WAIT; 854 chp->ch_status = 0; 855 /* start command */ 856 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 857 /* and says we started this command */ 858 achp->ahcic_cmds_active |= 1 << slot; 859 860 if ((xfer->c_flags & C_POLL) == 0) { 861 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 862 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 863 ahci_timeout, chp); 864 return; 865 } 866 /* 867 * Polled command. 868 */ 869 for (i = 0; i < ATA_DELAY / 10; i++) { 870 if (ata_bio->flags & ATA_ITSDONE) 871 break; 872 ahci_intr_port(sc, achp); 873 if (ata_bio->flags & ATA_NOSLEEP) 874 delay(10000); 875 else 876 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 877 } 878 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 879 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 880 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 881 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 882 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 883 DEBUG_XFERS); 884 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 885 ata_bio->error = TIMEOUT; 886 ahci_bio_complete(chp, xfer, slot); 887 } 888 /* reenable interrupts */ 889 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 890 } 891 892 void 893 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 894 { 895 int slot = 0; /* XXX slot */ 896 int drive = xfer->c_drive; 897 struct ata_bio *ata_bio = xfer->c_cmd; 898 struct ahci_channel *achp = (struct ahci_channel *)chp; 899 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 900 DEBUG_FUNCS); 901 902 achp->ahcic_cmds_active &= ~(1 << slot); 903 ata_free_xfer(chp, xfer); 904 ata_bio->flags |= ATA_ITSDONE; 905 switch (reason) { 906 case KILL_GONE: 907 ata_bio->error = ERR_NODEV; 908 break; 909 case KILL_RESET: 910 ata_bio->error = ERR_RESET; 911 break; 912 default: 913 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 914 panic("ahci_bio_kill_xfer"); 915 } 916 ata_bio->r_error = WDCE_ABRT; 917 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 918 } 919 920 int 921 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 922 { 923 int slot = 0; /* XXX slot */ 924 struct ata_bio *ata_bio = xfer->c_cmd; 925 int drive = xfer->c_drive; 926 struct ahci_channel *achp = (struct ahci_channel *)chp; 927 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 928 929 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 930 DEBUG_FUNCS); 931 932 achp->ahcic_cmds_active &= ~(1 << slot); 933 chp->ch_flags &= ~ATACH_IRQ_WAIT; 934 if (xfer->c_flags & C_TIMEOU) { 935 ata_bio->error = TIMEOUT; 936 } else { 937 callout_stop(&chp->ch_callout); 938 ata_bio->error = 0; 939 } 940 941 chp->ch_queue->active_xfer = NULL; 942 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 943 achp->ahcic_datad[slot]->dm_mapsize, 944 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 945 BUS_DMASYNC_POSTWRITE); 946 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 947 948 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 949 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 950 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 951 wakeup(&chp->ch_queue->active_xfer); 952 return 0; 953 } 954 ata_free_xfer(chp, xfer); 955 ata_bio->flags |= ATA_ITSDONE; 956 if (chp->ch_status & WDCS_DWF) { 957 ata_bio->error = ERR_DF; 958 } else if (chp->ch_status & WDCS_ERR) { 959 ata_bio->error = ERROR; 960 ata_bio->r_error = chp->ch_error; 961 } else if (chp->ch_status & WDCS_CORR) 962 ata_bio->flags |= ATA_CORR; 963 964 AHCI_CMDH_SYNC(sc, achp, slot, 965 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 966 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 967 ata_bio->bcount), DEBUG_XFERS); 968 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 969 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 970 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 971 atastart(chp); 972 return 0; 973 } 974 975 void 976 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 977 { 978 int i; 979 /* stop channel */ 980 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 981 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 982 /* wait 1s for channel to stop */ 983 for (i = 0; i <100; i++) { 984 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 985 == 0) 986 break; 987 if (flags & AT_WAIT) 988 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 989 else 990 delay(10000); 991 } 992 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 993 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 994 /* XXX controller reset ? */ 995 return; 996 } 997 } 998 999 void 1000 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1001 { 1002 /* clear error */ 1003 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1004 1005 /* and start controller */ 1006 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1007 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1008 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1009 } 1010 1011 void 1012 ahci_timeout(void *v) 1013 { 1014 struct ata_channel *chp = (struct ata_channel *)v; 1015 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1016 int s = splbio(); 1017 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1018 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1019 xfer->c_flags |= C_TIMEOU; 1020 xfer->c_intr(chp, xfer, 0); 1021 } 1022 splx(s); 1023 } 1024 1025 int 1026 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1027 size_t count, int op) 1028 { 1029 int error, seg; 1030 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1031 struct ahci_channel *achp = (struct ahci_channel *)chp; 1032 struct ahci_cmd_tbl *cmd_tbl; 1033 struct ahci_cmd_header *cmd_h; 1034 1035 cmd_h = &achp->ahcic_cmdh[slot]; 1036 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1037 1038 if (data == NULL) { 1039 cmd_h->cmdh_prdtl = 0; 1040 goto end; 1041 } 1042 1043 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1044 data, count, NULL, 1045 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1046 if (error) { 1047 printf("%s port %d: failed to load xfer: %d\n", 1048 AHCINAME(sc), chp->ch_channel, error); 1049 return error; 1050 } 1051 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1052 achp->ahcic_datad[slot]->dm_mapsize, 1053 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1054 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1055 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1056 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1057 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1058 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1059 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1060 } 1061 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1062 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1063 end: 1064 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1065 return 0; 1066 } 1067
Indexes created Fri Oct 17 00:09:41 GMT 2025