ahcisata_core.c revision 1.4.14.4
1 /* $NetBSD: ahcisata_core.c,v 1.4.14.4 2008/06/03 20:47:19 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.4.14.4 2008/06/03 20:47:19 skrll Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 #include <sys/buf.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/ic/wdcreg.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/satavar.h> 50 #include <dev/ata/satareg.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 #include "atapibus.h" 54 55 #ifdef AHCI_DEBUG 56 int ahcidebug_mask = 0x0; 57 #endif 58 59 void ahci_probe_drive(struct ata_channel *); 60 void ahci_setup_channel(struct ata_channel *); 61 62 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 63 void ahci_reset_drive(struct ata_drive_datas *, int); 64 void ahci_reset_channel(struct ata_channel *, int); 65 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 66 int ahci_ata_addref(struct ata_drive_datas *); 67 void ahci_ata_delref(struct ata_drive_datas *); 68 void ahci_killpending(struct ata_drive_datas *); 69 70 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 73 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 75 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 76 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 77 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 78 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 79 void ahci_timeout(void *); 80 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 void ahci_atapibus_attach(struct atabus_softc *); 84 void ahci_atapi_kill_pending(struct scsipi_periph *); 85 void ahci_atapi_minphys(struct buf *); 86 void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 }; 100 #endif /* NATAPIBUS */ 101 102 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 103 104 const struct ata_bustype ahci_ata_bustype = { 105 SCSIPI_BUSTYPE_ATA, 106 ahci_ata_bio, 107 ahci_reset_drive, 108 ahci_reset_channel, 109 ahci_exec_command, 110 ata_get_params, 111 ahci_ata_addref, 112 ahci_ata_delref, 113 ahci_killpending 114 }; 115 116 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 117 118 void 119 ahci_attach(struct ahci_softc *sc) 120 { 121 u_int32_t ahci_cap, ahci_rev, ahci_ports; 122 int i, j, port; 123 struct ahci_channel *achp; 124 struct ata_channel *chp; 125 int error; 126 bus_dma_segment_t seg; 127 int rseg; 128 int dmasize; 129 caddr_t cmdhp; 130 caddr_t cmdtblp; 131 132 /* reset controller */ 133 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 134 /* wait up to 1s for reset to complete */ 135 for (i = 0; i < 1000; i++) { 136 delay(1000); 137 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 138 break; 139 } 140 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 141 aprint_error("%s: reset failed\n", AHCINAME(sc)); 142 return; 143 } 144 /* enable ahci mode */ 145 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 146 147 148 ahci_cap = AHCI_READ(sc, AHCI_CAP); 149 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 150 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 151 ahci_rev = AHCI_READ(sc, AHCI_VS); 152 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 153 switch(ahci_rev) { 154 case AHCI_VS_10: 155 aprint_normal("1.0"); 156 break; 157 case AHCI_VS_11: 158 aprint_normal("1.1"); 159 break; 160 default: 161 aprint_normal("0x%x", ahci_rev); 162 break; 163 } 164 165 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 166 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 167 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 168 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 169 sc->sc_atac.atac_pio_cap = 4; 170 sc->sc_atac.atac_dma_cap = 2; 171 sc->sc_atac.atac_udma_cap = 6; 172 sc->sc_atac.atac_channels = sc->sc_chanarray; 173 sc->sc_atac.atac_probe = ahci_probe_drive; 174 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 175 sc->sc_atac.atac_set_modes = ahci_setup_channel; 176 #if NATAPIBUS > 0 177 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 178 #endif 179 180 dmasize = 181 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 182 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 183 &seg, 1, &rseg, BUS_DMA_NOWAIT); 184 if (error) { 185 aprint_error("%s: unable to allocate command header memory" 186 ", error=%d\n", AHCINAME(sc), error); 187 return; 188 } 189 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 190 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 191 if (error) { 192 aprint_error("%s: unable to map command header memory" 193 ", error=%d\n", AHCINAME(sc), error); 194 return; 195 } 196 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 197 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 198 if (error) { 199 aprint_error("%s: unable to create command header map" 200 ", error=%d\n", AHCINAME(sc), error); 201 return; 202 } 203 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 204 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 205 if (error) { 206 aprint_error("%s: unable to load command header map" 207 ", error=%d\n", AHCINAME(sc), error); 208 return; 209 } 210 sc->sc_cmd_hdr = cmdhp; 211 212 /* clear interrupts */ 213 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 214 /* enable interrupts */ 215 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 216 217 ahci_ports = AHCI_READ(sc, AHCI_PI); 218 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 219 if ((ahci_ports & (1 << i)) == 0) 220 continue; 221 if (port >= sc->sc_atac.atac_nchannels) { 222 aprint_error("%s: more ports than announced\n", 223 AHCINAME(sc)); 224 break; 225 } 226 achp = &sc->sc_channels[i]; 227 chp = (struct ata_channel *)achp; 228 sc->sc_chanarray[i] = chp; 229 chp->ch_channel = i; 230 chp->ch_atac = &sc->sc_atac; 231 chp->ch_queue = malloc(sizeof(struct ata_queue), 232 M_DEVBUF, M_NOWAIT); 233 if (chp->ch_queue == NULL) { 234 aprint_error("%s port %d: can't allocate memory for " 235 "command queue", AHCINAME(sc), i); 236 break; 237 } 238 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 239 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 240 &seg, 1, &rseg, BUS_DMA_NOWAIT); 241 if (error) { 242 aprint_error("%s: unable to allocate command table " 243 "memory, error=%d\n", AHCINAME(sc), error); 244 break; 245 } 246 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 247 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 248 if (error) { 249 aprint_error("%s: unable to map command table memory" 250 ", error=%d\n", AHCINAME(sc), error); 251 break; 252 } 253 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 254 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 255 if (error) { 256 aprint_error("%s: unable to create command table map" 257 ", error=%d\n", AHCINAME(sc), error); 258 break; 259 } 260 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 261 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 262 if (error) { 263 aprint_error("%s: unable to load command table map" 264 ", error=%d\n", AHCINAME(sc), error); 265 break; 266 } 267 achp->ahcic_cmdh = (struct ahci_cmd_header *) 268 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 269 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 270 AHCI_CMDH_SIZE * port; 271 achp->ahcic_rfis = (struct ahci_r_fis *) 272 ((char *)cmdhp + 273 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 274 AHCI_RFIS_SIZE * port); 275 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 276 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 277 AHCI_RFIS_SIZE * port; 278 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 279 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 280 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 281 DEBUG_PROBE); 282 283 for (j = 0; j < sc->sc_ncmds; j++) { 284 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 285 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 286 achp->ahcic_bus_cmd_tbl[j] = 287 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 288 AHCI_CMDTBL_SIZE * j; 289 achp->ahcic_cmdh[j].cmdh_cmdtba = 290 htole32(achp->ahcic_bus_cmd_tbl[j]); 291 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 292 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 293 achp->ahcic_cmd_tbl[j], 294 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 295 /* The xfer DMA map */ 296 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 297 AHCI_NPRD, 0x400000 /* 4MB */, 0, 298 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 299 &achp->ahcic_datad[j]); 300 if (error) { 301 aprint_error("%s: couldn't alloc xfer DMA map, " 302 "error=%d\n", AHCINAME(sc), error); 303 goto end; 304 } 305 } 306 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 307 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 308 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 309 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 310 chp->ch_ndrive = 1; 311 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 312 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 313 aprint_error("%s: couldn't map channel %d " 314 "sata_status regs\n", AHCINAME(sc), i); 315 break; 316 } 317 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 318 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 319 aprint_error("%s: couldn't map channel %d " 320 "sata_control regs\n", AHCINAME(sc), i); 321 break; 322 } 323 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 324 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 325 aprint_error("%s: couldn't map channel %d " 326 "sata_error regs\n", AHCINAME(sc), i); 327 break; 328 } 329 ata_channel_attach(chp); 330 port++; 331 end: 332 continue; 333 } 334 } 335 336 int 337 ahci_intr(void *v) 338 { 339 struct ahci_softc *sc = v; 340 u_int32_t is; 341 int i, r = 0; 342 343 while ((is = AHCI_READ(sc, AHCI_IS))) { 344 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 345 DEBUG_INTR); 346 r = 1; 347 AHCI_WRITE(sc, AHCI_IS, is); 348 for (i = 0; i < AHCI_MAX_PORTS; i++) 349 if (is & (1 << i)) 350 ahci_intr_port(sc, &sc->sc_channels[i]); 351 } 352 return r; 353 } 354 355 void 356 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 357 { 358 u_int32_t is, tfd; 359 struct ata_channel *chp = &achp->ata_channel; 360 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 361 int slot; 362 363 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 364 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 365 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 366 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 367 DEBUG_INTR); 368 369 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 370 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 371 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 372 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 373 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 374 return; 375 /* stop channel */ 376 ahci_channel_stop(sc, chp, 0); 377 if (slot != 0) { 378 printf("ahci_intr_port: slot %d\n", slot); 379 panic("ahci_intr_port"); 380 } 381 if (is & AHCI_P_IX_TFES) { 382 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 383 chp->ch_error = 384 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 385 chp->ch_status = (tfd & 0xff); 386 } else { 387 /* emulate a CRC error */ 388 chp->ch_error = WDCE_CRC; 389 chp->ch_status = WDCS_ERR; 390 } 391 xfer->c_intr(chp, xfer, is); 392 /* if channel has not been restarted, do it now */ 393 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 394 == 0) 395 ahci_channel_start(sc, chp); 396 } else { 397 slot = 0; /* XXX */ 398 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 399 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 400 chp->ch_channel, is, achp->ahcic_cmds_active, 401 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 402 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 403 return; 404 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 405 == 0) { 406 xfer->c_intr(chp, xfer, 0); 407 } 408 } 409 } 410 411 void 412 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 413 { 414 struct ata_channel *chp = drvp->chnl_softc; 415 ata_reset_channel(chp, flags); 416 return; 417 } 418 419 void 420 ahci_reset_channel(struct ata_channel *chp, int flags) 421 { 422 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 423 struct ahci_channel *achp = (struct ahci_channel *)chp; 424 425 ahci_channel_stop(sc, chp, flags); 426 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 427 achp->ahcic_sstatus) != SStatus_DET_DEV) { 428 printf("%s: port reset failed\n", AHCINAME(sc)); 429 /* XXX and then ? */ 430 } 431 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 432 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 433 if (chp->ch_queue->active_xfer) { 434 chp->ch_queue->active_xfer->c_kill_xfer(chp, 435 chp->ch_queue->active_xfer, KILL_RESET); 436 } 437 ahci_channel_start(sc, chp); 438 #if 0 439 /* Wait 15s for device to host FIS to arrive. */ 440 for (i = 0; i <1500; i++) { 441 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) & AHCI_P_IX_DHRS) 442 break; 443 if (flags & AT_WAIT) 444 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 445 else 446 delay (10000); 447 } 448 if (i == 1500) 449 aprint_error("%s port %d: D2H FIS never arrived\n", AHCINAME(sc)); 450 #endif 451 /* clear port interrupt register */ 452 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 453 454 return; 455 } 456 457 int 458 ahci_ata_addref(struct ata_drive_datas *drvp) 459 { 460 return 0; 461 } 462 463 void 464 ahci_ata_delref(struct ata_drive_datas *drvp) 465 { 466 return; 467 } 468 469 void 470 ahci_killpending(struct ata_drive_datas *drvp) 471 { 472 return; 473 } 474 475 void 476 ahci_probe_drive(struct ata_channel *chp) 477 { 478 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 479 struct ahci_channel *achp = (struct ahci_channel *)chp; 480 int i, s; 481 u_int32_t sig; 482 483 /* XXX This should be done by other code. */ 484 for (i = 0; i < chp->ch_ndrive; i++) { 485 chp->ch_drive[i].chnl_softc = chp; 486 chp->ch_drive[i].drive = i; 487 } 488 489 /* bring interface up, power up and spin up device */ 490 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 491 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 492 /* reset the PHY and bring online */ 493 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 494 achp->ahcic_sstatus)) { 495 case SStatus_DET_DEV: 496 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 497 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 498 #if 0 499 /* wait 15s for d2h FIS */ 500 for (i = 0; i <1500; i++) { 501 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) 502 & AHCI_P_IX_DHRS) 503 break; 504 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 505 } 506 if (i == 1500) 507 aprint_error("%s: D2H FIS never arrived\n", 508 AHCINAME(sc)); 509 #endif 510 511 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 512 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 513 AHCINAME(sc), chp->ch_channel, sig, 514 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 515 /* 516 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 517 * cases we get wrong values here, so ignore it. 518 */ 519 s = splbio(); 520 if ((sig & 0xffff0000) == 0xeb140000) { 521 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 522 } else 523 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 524 splx(s); 525 /* enable interrupts */ 526 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 527 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 528 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 529 AHCI_P_IX_DHRS); 530 /* and start operations */ 531 ahci_channel_start(sc, chp); 532 break; 533 534 default: 535 break; 536 } 537 } 538 539 void 540 ahci_setup_channel(struct ata_channel *chp) 541 { 542 return; 543 } 544 545 int 546 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 547 { 548 struct ata_channel *chp = drvp->chnl_softc; 549 struct ata_xfer *xfer; 550 int ret; 551 int s; 552 553 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 554 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 555 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 556 DEBUG_XFERS); 557 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 558 ATAXF_NOSLEEP); 559 if (xfer == NULL) { 560 return ATACMD_TRY_AGAIN; 561 } 562 if (ata_c->flags & AT_POLL) 563 xfer->c_flags |= C_POLL; 564 if (ata_c->flags & AT_WAIT) 565 xfer->c_flags |= C_WAIT; 566 xfer->c_drive = drvp->drive; 567 xfer->c_databuf = ata_c->data; 568 xfer->c_bcount = ata_c->bcount; 569 xfer->c_cmd = ata_c; 570 xfer->c_start = ahci_cmd_start; 571 xfer->c_intr = ahci_cmd_complete; 572 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 573 s = splbio(); 574 ata_exec_xfer(chp, xfer); 575 #ifdef DIAGNOSTIC 576 if ((ata_c->flags & AT_POLL) != 0 && 577 (ata_c->flags & AT_DONE) == 0) 578 panic("ahci_exec_command: polled command not done"); 579 #endif 580 if (ata_c->flags & AT_DONE) { 581 ret = ATACMD_COMPLETE; 582 } else { 583 if (ata_c->flags & AT_WAIT) { 584 while ((ata_c->flags & AT_DONE) == 0) { 585 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 586 } 587 ret = ATACMD_COMPLETE; 588 } else { 589 ret = ATACMD_QUEUED; 590 } 591 } 592 splx(s); 593 return ret; 594 } 595 596 void 597 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 598 { 599 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 600 struct ahci_channel *achp = (struct ahci_channel *)chp; 601 struct ata_command *ata_c = xfer->c_cmd; 602 int slot = 0 /* XXX slot */; 603 struct ahci_cmd_tbl *cmd_tbl; 604 struct ahci_cmd_header *cmd_h; 605 u_int8_t *fis; 606 int i; 607 int channel = chp->ch_channel; 608 609 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 610 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 611 612 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 613 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 614 cmd_tbl), DEBUG_XFERS); 615 fis = cmd_tbl->cmdt_cfis; 616 617 fis[0] = 0x27; /* host to device */ 618 fis[1] = 0x80; /* command FIS */ 619 fis[2] = ata_c->r_command; 620 fis[3] = ata_c->r_features; 621 fis[4] = ata_c->r_sector; 622 fis[5] = ata_c->r_cyl & 0xff; 623 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 624 fis[7] = ata_c->r_head & 0x0f; 625 fis[8] = 0; 626 fis[9] = 0; 627 fis[10] = 0; 628 fis[11] = 0; 629 fis[12] = ata_c->r_count; 630 fis[13] = 0; 631 fis[14] = 0; 632 fis[15] = WDCTL_4BIT; 633 fis[16] = 0; 634 fis[17] = 0; 635 fis[18] = 0; 636 fis[19] = 0; 637 638 cmd_h = &achp->ahcic_cmdh[slot]; 639 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 640 chp->ch_channel, cmd_h), DEBUG_XFERS); 641 if (ahci_dma_setup(chp, slot, 642 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 643 ata_c->bcount, 644 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 645 ata_c->flags |= AT_DF; 646 ahci_cmd_complete(chp, xfer, slot); 647 return; 648 } 649 cmd_h->cmdh_flags = htole16( 650 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 651 20 /* fis lenght */ / 4); 652 cmd_h->cmdh_prdbc = 0; 653 AHCI_CMDH_SYNC(sc, achp, slot, 654 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 655 656 if (ata_c->flags & AT_POLL) { 657 /* polled command, disable interrupts */ 658 AHCI_WRITE(sc, AHCI_GHC, 659 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 660 } 661 chp->ch_flags |= ATACH_IRQ_WAIT; 662 chp->ch_status = 0; 663 /* start command */ 664 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 665 /* and says we started this command */ 666 achp->ahcic_cmds_active |= 1 << slot; 667 668 if ((ata_c->flags & AT_POLL) == 0) { 669 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 670 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 671 ahci_timeout, chp); 672 return; 673 } 674 /* 675 * Polled command. 676 */ 677 for (i = 0; i < ata_c->timeout / 10; i++) { 678 if (ata_c->flags & AT_DONE) 679 break; 680 ahci_intr_port(sc, achp); 681 if (ata_c->flags & AT_WAIT) 682 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 683 else 684 delay(10000); 685 } 686 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 687 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 688 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 689 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 690 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 691 DEBUG_XFERS); 692 if ((ata_c->flags & AT_DONE) == 0) { 693 ata_c->flags |= AT_TIMEOU; 694 ahci_cmd_complete(chp, xfer, slot); 695 } 696 /* reenable interrupts */ 697 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 698 } 699 700 void 701 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 702 { 703 struct ata_command *ata_c = xfer->c_cmd; 704 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 705 DEBUG_FUNCS); 706 707 switch (reason) { 708 case KILL_GONE: 709 ata_c->flags |= AT_GONE; 710 break; 711 case KILL_RESET: 712 ata_c->flags |= AT_RESET; 713 break; 714 default: 715 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 716 panic("ahci_cmd_kill_xfer"); 717 } 718 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 719 } 720 721 int 722 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 723 { 724 int slot = 0; /* XXX slot */ 725 struct ata_command *ata_c = xfer->c_cmd; 726 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 727 728 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 729 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 730 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 731 DEBUG_FUNCS); 732 chp->ch_flags &= ~ATACH_IRQ_WAIT; 733 if (xfer->c_flags & C_TIMEOU) { 734 ata_c->flags |= AT_TIMEOU; 735 } else 736 callout_stop(&chp->ch_callout); 737 738 chp->ch_queue->active_xfer = NULL; 739 740 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 741 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 742 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 743 wakeup(&chp->ch_queue->active_xfer); 744 return 0; 745 } 746 if (is) { 747 ata_c->r_head = 0; 748 ata_c->r_count = 0; 749 ata_c->r_sector = 0; 750 ata_c->r_cyl = 0; 751 if (chp->ch_status & WDCS_BSY) { 752 ata_c->flags |= AT_TIMEOU; 753 } else if (chp->ch_status & WDCS_ERR) { 754 ata_c->r_error = chp->ch_error; 755 ata_c->flags |= AT_ERROR; 756 } 757 } 758 ahci_cmd_done(chp, xfer, slot); 759 return 0; 760 } 761 762 void 763 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 764 { 765 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 766 struct ahci_channel *achp = (struct ahci_channel *)chp; 767 struct ata_command *ata_c = xfer->c_cmd; 768 769 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 770 DEBUG_FUNCS); 771 772 /* this comamnd is not active any more */ 773 achp->ahcic_cmds_active &= ~(1 << slot); 774 775 if (ata_c->flags & (AT_READ|AT_WRITE)) { 776 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 777 achp->ahcic_datad[slot]->dm_mapsize, 778 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 779 BUS_DMASYNC_POSTWRITE); 780 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 781 } 782 783 AHCI_CMDH_SYNC(sc, achp, slot, 784 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 785 786 ata_c->flags |= AT_DONE; 787 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 788 ata_c->flags |= AT_XFDONE; 789 790 ata_free_xfer(chp, xfer); 791 if (ata_c->flags & AT_WAIT) 792 wakeup(ata_c); 793 else if (ata_c->callback) 794 ata_c->callback(ata_c->callback_arg); 795 atastart(chp); 796 return; 797 } 798 799 int 800 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 801 { 802 struct ata_channel *chp = drvp->chnl_softc; 803 struct ata_xfer *xfer; 804 805 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 806 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 807 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 808 DEBUG_XFERS); 809 xfer = ata_get_xfer(ATAXF_NOSLEEP); 810 if (xfer == NULL) { 811 return ATACMD_TRY_AGAIN; 812 } 813 if (ata_bio->flags & ATA_POLL) 814 xfer->c_flags |= C_POLL; 815 xfer->c_drive = drvp->drive; 816 xfer->c_cmd = ata_bio; 817 xfer->c_databuf = ata_bio->databuf; 818 xfer->c_bcount = ata_bio->bcount; 819 xfer->c_start = ahci_bio_start; 820 xfer->c_intr = ahci_bio_complete; 821 xfer->c_kill_xfer = ahci_bio_kill_xfer; 822 ata_exec_xfer(chp, xfer); 823 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 824 } 825 826 void 827 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 828 { 829 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 830 struct ahci_channel *achp = (struct ahci_channel *)chp; 831 struct ata_bio *ata_bio = xfer->c_cmd; 832 int slot = 0 /* XXX slot */; 833 struct ahci_cmd_tbl *cmd_tbl; 834 struct ahci_cmd_header *cmd_h; 835 u_int8_t *fis; 836 int i, nblks; 837 int channel = chp->ch_channel; 838 839 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 840 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 841 842 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 843 844 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 845 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 846 cmd_tbl), DEBUG_XFERS); 847 fis = cmd_tbl->cmdt_cfis; 848 849 fis[0] = 0x27; /* host to device */ 850 fis[1] = 0x80; /* command FIS */ 851 if (ata_bio->flags & ATA_LBA48) { 852 fis[2] = (ata_bio->flags & ATA_READ) ? 853 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 854 } else { 855 fis[2] = 856 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 857 } 858 fis[3] = 0; /* features */ 859 fis[4] = ata_bio->blkno & 0xff; 860 fis[5] = (ata_bio->blkno >> 8) & 0xff; 861 fis[6] = (ata_bio->blkno >> 16) & 0xff; 862 if (ata_bio->flags & ATA_LBA48) { 863 fis[7] = WDSD_LBA; 864 fis[8] = (ata_bio->blkno >> 24) & 0xff; 865 fis[9] = (ata_bio->blkno >> 32) & 0xff; 866 fis[10] = (ata_bio->blkno >> 40) & 0xff; 867 } else { 868 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 869 fis[8] = 0; 870 fis[9] = 0; 871 fis[10] = 0; 872 } 873 fis[11] = 0; /* ext features */ 874 fis[12] = nblks & 0xff; 875 fis[13] = (ata_bio->flags & ATA_LBA48) ? 876 ((nblks >> 8) & 0xff) : 0; 877 fis[14] = 0; 878 fis[15] = WDCTL_4BIT; 879 fis[16] = 0; 880 fis[17] = 0; 881 fis[18] = 0; 882 fis[19] = 0; 883 884 cmd_h = &achp->ahcic_cmdh[slot]; 885 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 886 chp->ch_channel, cmd_h), DEBUG_XFERS); 887 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 888 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 889 ata_bio->error = ERR_DMA; 890 ata_bio->r_error = 0; 891 ahci_bio_complete(chp, xfer, slot); 892 return; 893 } 894 cmd_h->cmdh_flags = htole16( 895 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 896 20 /* fis lenght */ / 4); 897 cmd_h->cmdh_prdbc = 0; 898 AHCI_CMDH_SYNC(sc, achp, slot, 899 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 900 901 if (xfer->c_flags & C_POLL) { 902 /* polled command, disable interrupts */ 903 AHCI_WRITE(sc, AHCI_GHC, 904 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 905 } 906 chp->ch_flags |= ATACH_IRQ_WAIT; 907 chp->ch_status = 0; 908 /* start command */ 909 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 910 /* and says we started this command */ 911 achp->ahcic_cmds_active |= 1 << slot; 912 913 if ((xfer->c_flags & C_POLL) == 0) { 914 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 915 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 916 ahci_timeout, chp); 917 return; 918 } 919 /* 920 * Polled command. 921 */ 922 for (i = 0; i < ATA_DELAY / 10; i++) { 923 if (ata_bio->flags & ATA_ITSDONE) 924 break; 925 ahci_intr_port(sc, achp); 926 if (ata_bio->flags & ATA_NOSLEEP) 927 delay(10000); 928 else 929 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 930 } 931 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 932 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 933 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 934 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 935 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 936 DEBUG_XFERS); 937 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 938 ata_bio->error = TIMEOUT; 939 ahci_bio_complete(chp, xfer, slot); 940 } 941 /* reenable interrupts */ 942 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 943 } 944 945 void 946 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 947 { 948 int slot = 0; /* XXX slot */ 949 int drive = xfer->c_drive; 950 struct ata_bio *ata_bio = xfer->c_cmd; 951 struct ahci_channel *achp = (struct ahci_channel *)chp; 952 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 953 DEBUG_FUNCS); 954 955 achp->ahcic_cmds_active &= ~(1 << slot); 956 ata_free_xfer(chp, xfer); 957 ata_bio->flags |= ATA_ITSDONE; 958 switch (reason) { 959 case KILL_GONE: 960 ata_bio->error = ERR_NODEV; 961 break; 962 case KILL_RESET: 963 ata_bio->error = ERR_RESET; 964 break; 965 default: 966 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 967 panic("ahci_bio_kill_xfer"); 968 } 969 ata_bio->r_error = WDCE_ABRT; 970 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 971 } 972 973 int 974 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 975 { 976 int slot = 0; /* XXX slot */ 977 struct ata_bio *ata_bio = xfer->c_cmd; 978 int drive = xfer->c_drive; 979 struct ahci_channel *achp = (struct ahci_channel *)chp; 980 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 981 982 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 983 DEBUG_FUNCS); 984 985 achp->ahcic_cmds_active &= ~(1 << slot); 986 chp->ch_flags &= ~ATACH_IRQ_WAIT; 987 if (xfer->c_flags & C_TIMEOU) { 988 ata_bio->error = TIMEOUT; 989 } else { 990 callout_stop(&chp->ch_callout); 991 ata_bio->error = 0; 992 } 993 994 chp->ch_queue->active_xfer = NULL; 995 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 996 achp->ahcic_datad[slot]->dm_mapsize, 997 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 998 BUS_DMASYNC_POSTWRITE); 999 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1000 1001 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1002 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1003 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1004 wakeup(&chp->ch_queue->active_xfer); 1005 return 0; 1006 } 1007 ata_free_xfer(chp, xfer); 1008 ata_bio->flags |= ATA_ITSDONE; 1009 if (chp->ch_status & WDCS_DWF) { 1010 ata_bio->error = ERR_DF; 1011 } else if (chp->ch_status & WDCS_ERR) { 1012 ata_bio->error = ERROR; 1013 ata_bio->r_error = chp->ch_error; 1014 } else if (chp->ch_status & WDCS_CORR) 1015 ata_bio->flags |= ATA_CORR; 1016 1017 AHCI_CMDH_SYNC(sc, achp, slot, 1018 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1019 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1020 ata_bio->bcount), DEBUG_XFERS); 1021 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1022 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1023 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1024 atastart(chp); 1025 return 0; 1026 } 1027 1028 void 1029 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1030 { 1031 int i; 1032 /* stop channel */ 1033 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1034 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1035 /* wait 1s for channel to stop */ 1036 for (i = 0; i <100; i++) { 1037 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1038 == 0) 1039 break; 1040 if (flags & AT_WAIT) 1041 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1042 else 1043 delay(10000); 1044 } 1045 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1046 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1047 /* XXX controller reset ? */ 1048 return; 1049 } 1050 } 1051 1052 void 1053 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1054 { 1055 /* clear error */ 1056 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1057 1058 /* and start controller */ 1059 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1060 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1061 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1062 } 1063 1064 void 1065 ahci_timeout(void *v) 1066 { 1067 struct ata_channel *chp = (struct ata_channel *)v; 1068 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1069 int s = splbio(); 1070 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1071 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1072 xfer->c_flags |= C_TIMEOU; 1073 xfer->c_intr(chp, xfer, 0); 1074 } 1075 splx(s); 1076 } 1077 1078 int 1079 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1080 size_t count, int op) 1081 { 1082 int error, seg; 1083 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1084 struct ahci_channel *achp = (struct ahci_channel *)chp; 1085 struct ahci_cmd_tbl *cmd_tbl; 1086 struct ahci_cmd_header *cmd_h; 1087 1088 cmd_h = &achp->ahcic_cmdh[slot]; 1089 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1090 1091 if (data == NULL) { 1092 cmd_h->cmdh_prdtl = 0; 1093 goto end; 1094 } 1095 1096 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1097 data, count, NULL, 1098 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1099 if (error) { 1100 printf("%s port %d: failed to load xfer: %d\n", 1101 AHCINAME(sc), chp->ch_channel, error); 1102 return error; 1103 } 1104 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1105 achp->ahcic_datad[slot]->dm_mapsize, 1106 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1107 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1108 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1109 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1110 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1111 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1112 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1113 } 1114 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1115 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1116 end: 1117 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1118 return 0; 1119 } 1120 1121 #if NATAPIBUS > 0 1122 void 1123 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1124 { 1125 struct ata_channel *chp = ata_sc->sc_chan; 1126 struct atac_softc *atac = chp->ch_atac; 1127 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1128 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1129 /* 1130 * Fill in the scsipi_adapter. 1131 */ 1132 adapt->adapt_dev = &atac->atac_dev; 1133 adapt->adapt_nchannels = atac->atac_nchannels; 1134 adapt->adapt_request = ahci_atapi_scsipi_request; 1135 adapt->adapt_minphys = ahci_atapi_minphys; 1136 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1137 1138 /* 1139 * Fill in the scsipi_channel. 1140 */ 1141 memset(chan, 0, sizeof(*chan)); 1142 chan->chan_adapter = adapt; 1143 chan->chan_bustype = &ahci_atapi_bustype; 1144 chan->chan_channel = chp->ch_channel; 1145 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1146 chan->chan_openings = 1; 1147 chan->chan_max_periph = 1; 1148 chan->chan_ntargets = 1; 1149 chan->chan_nluns = 1; 1150 chp->atapibus = config_found_ia(&ata_sc->sc_dev, "atapi", chan, 1151 atapiprint); 1152 } 1153 1154 void 1155 ahci_atapi_minphys(struct buf *bp) 1156 { 1157 if (bp->b_bcount > MAXPHYS) 1158 bp->b_bcount = MAXPHYS; 1159 minphys(bp); 1160 } 1161 1162 /* 1163 * Kill off all pending xfers for a periph. 1164 * 1165 * Must be called at splbio(). 1166 */ 1167 void 1168 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1169 { 1170 struct atac_softc *atac = 1171 (void *)periph->periph_channel->chan_adapter->adapt_dev; 1172 struct ata_channel *chp = 1173 atac->atac_channels[periph->periph_channel->chan_channel]; 1174 1175 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1176 } 1177 1178 void 1179 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1180 scsipi_adapter_req_t req, void *arg) 1181 { 1182 struct scsipi_adapter *adapt = chan->chan_adapter; 1183 struct scsipi_periph *periph; 1184 struct scsipi_xfer *sc_xfer; 1185 struct ahci_softc *sc = (void *)adapt->adapt_dev; 1186 struct atac_softc *atac = &sc->sc_atac; 1187 struct ata_xfer *xfer; 1188 int channel = chan->chan_channel; 1189 int drive, s; 1190 1191 switch (req) { 1192 case ADAPTER_REQ_RUN_XFER: 1193 sc_xfer = arg; 1194 periph = sc_xfer->xs_periph; 1195 drive = periph->periph_target; 1196 if (!device_is_active(&atac->atac_dev)) { 1197 sc_xfer->error = XS_DRIVER_STUFFUP; 1198 scsipi_done(sc_xfer); 1199 return; 1200 } 1201 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1202 if (xfer == NULL) { 1203 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1204 scsipi_done(sc_xfer); 1205 return; 1206 } 1207 1208 if (sc_xfer->xs_control & XS_CTL_POLL) 1209 xfer->c_flags |= C_POLL; 1210 xfer->c_drive = drive; 1211 xfer->c_flags |= C_ATAPI; 1212 xfer->c_cmd = sc_xfer; 1213 xfer->c_databuf = sc_xfer->data; 1214 xfer->c_bcount = sc_xfer->datalen; 1215 xfer->c_start = ahci_atapi_start; 1216 xfer->c_intr = ahci_atapi_complete; 1217 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1218 xfer->c_dscpoll = 0; 1219 s = splbio(); 1220 ata_exec_xfer(atac->atac_channels[channel], xfer); 1221 #ifdef DIAGNOSTIC 1222 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1223 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1224 panic("ahci_atapi_scsipi_request: polled command " 1225 "not done"); 1226 #endif 1227 splx(s); 1228 return; 1229 default: 1230 /* Not supported, nothing to do. */ 1231 ; 1232 } 1233 } 1234 1235 void 1236 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1237 { 1238 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1239 struct ahci_channel *achp = (struct ahci_channel *)chp; 1240 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1241 int slot = 0 /* XXX slot */; 1242 struct ahci_cmd_tbl *cmd_tbl; 1243 struct ahci_cmd_header *cmd_h; 1244 u_int8_t *fis; 1245 int i; 1246 int channel = chp->ch_channel; 1247 1248 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1249 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1250 1251 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1252 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1253 cmd_tbl), DEBUG_XFERS); 1254 fis = cmd_tbl->cmdt_cfis; 1255 1256 fis[0] = 0x27; /* host to device */ 1257 fis[1] = 0x80; /* command FIS */ 1258 fis[2] = ATAPI_PKT_CMD; 1259 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1260 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1261 fis[3] = (sc_xfer->datalen ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1262 fis[4] = 0; 1263 fis[5] = 0; 1264 fis[6] = 0; 1265 fis[7] = WDSD_LBA; 1266 fis[8] = 0; 1267 fis[9] = 0; 1268 fis[10] = 0; 1269 fis[11] = 0; /* ext features */ 1270 fis[12] = 0; 1271 fis[13] = 0; 1272 fis[14] = 0; 1273 fis[15] = WDCTL_4BIT; 1274 fis[16] = 0; 1275 fis[17] = 0; 1276 fis[18] = 0; 1277 fis[19] = 0; 1278 1279 cmd_h = &achp->ahcic_cmdh[slot]; 1280 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1281 chp->ch_channel, cmd_h), DEBUG_XFERS); 1282 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1283 sc_xfer->datalen, 1284 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1285 BUS_DMA_READ : BUS_DMA_WRITE)) { 1286 sc_xfer->error = XS_DRIVER_STUFFUP; 1287 ahci_atapi_complete(chp, xfer, slot); 1288 return; 1289 } 1290 cmd_h->cmdh_flags = htole16( 1291 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1292 20 /* fis lenght */ / 4 | AHCI_CMDH_F_A); 1293 cmd_h->cmdh_prdbc = 0; 1294 AHCI_CMDH_SYNC(sc, achp, slot, 1295 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1296 1297 if (xfer->c_flags & C_POLL) { 1298 /* polled command, disable interrupts */ 1299 AHCI_WRITE(sc, AHCI_GHC, 1300 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1301 } 1302 chp->ch_flags |= ATACH_IRQ_WAIT; 1303 chp->ch_status = 0; 1304 /* start command */ 1305 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1306 /* and says we started this command */ 1307 achp->ahcic_cmds_active |= 1 << slot; 1308 1309 if ((xfer->c_flags & C_POLL) == 0) { 1310 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1311 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1312 ahci_timeout, chp); 1313 return; 1314 } 1315 /* 1316 * Polled command. 1317 */ 1318 for (i = 0; i < ATA_DELAY / 10; i++) { 1319 if (sc_xfer->xs_status & XS_STS_DONE) 1320 break; 1321 ahci_intr_port(sc, achp); 1322 delay(10000); 1323 } 1324 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1325 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1326 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1327 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1328 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1329 DEBUG_XFERS); 1330 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1331 sc_xfer->error = XS_TIMEOUT; 1332 ahci_atapi_complete(chp, xfer, slot); 1333 } 1334 /* reenable interrupts */ 1335 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1336 } 1337 1338 int 1339 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1340 { 1341 int slot = 0; /* XXX slot */ 1342 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1343 int drive = xfer->c_drive; 1344 struct ahci_channel *achp = (struct ahci_channel *)chp; 1345 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1346 1347 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1348 DEBUG_FUNCS); 1349 1350 achp->ahcic_cmds_active &= ~(1 << slot); 1351 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1352 if (xfer->c_flags & C_TIMEOU) { 1353 sc_xfer->error = XS_TIMEOUT; 1354 } else { 1355 callout_stop(&chp->ch_callout); 1356 sc_xfer->error = 0; 1357 } 1358 1359 chp->ch_queue->active_xfer = NULL; 1360 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1361 achp->ahcic_datad[slot]->dm_mapsize, 1362 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1363 BUS_DMASYNC_POSTWRITE); 1364 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1365 1366 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1367 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1368 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1369 wakeup(&chp->ch_queue->active_xfer); 1370 return 0; 1371 } 1372 ata_free_xfer(chp, xfer); 1373 1374 if (chp->ch_status & WDCS_ERR) { 1375 sc_xfer->error = XS_SHORTSENSE; 1376 sc_xfer->sense.atapi_sense = chp->ch_error; 1377 } 1378 1379 AHCI_CMDH_SYNC(sc, achp, slot, 1380 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1381 sc_xfer->resid = sc_xfer->datalen; 1382 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1383 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1384 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1385 scsipi_done(sc_xfer); 1386 atastart(chp); 1387 return 0; 1388 } 1389 1390 void 1391 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1392 { 1393 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1394 struct ahci_channel *achp = (struct ahci_channel *)chp; 1395 int slot = 0; /* XXX slot */ 1396 1397 achp->ahcic_cmds_active &= ~(1 << slot); 1398 1399 /* remove this command from xfer queue */ 1400 switch (reason) { 1401 case KILL_GONE: 1402 sc_xfer->error = XS_DRIVER_STUFFUP; 1403 break; 1404 case KILL_RESET: 1405 sc_xfer->error = XS_RESET; 1406 break; 1407 default: 1408 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1409 panic("ahci_ata_atapi_kill_xfer"); 1410 } 1411 ata_free_xfer(chp, xfer); 1412 scsipi_done(sc_xfer); 1413 } 1414 1415 void 1416 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1417 { 1418 struct scsipi_channel *chan = sc->sc_channel; 1419 struct scsipi_periph *periph; 1420 struct ataparams ids; 1421 struct ataparams *id = &ids; 1422 struct ahci_softc *ahcic = (void *)chan->chan_adapter->adapt_dev; 1423 struct atac_softc *atac = &ahcic->sc_atac; 1424 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1425 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1426 struct scsipibus_attach_args sa; 1427 char serial_number[21], model[41], firmware_revision[9]; 1428 int s; 1429 1430 /* skip if already attached */ 1431 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1432 return; 1433 1434 /* if no ATAPI device detected at attach time, skip */ 1435 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1436 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1437 "not present\n", target), DEBUG_PROBE); 1438 return; 1439 } 1440 1441 /* Some ATAPI devices need a bit more time after software reset. */ 1442 delay(5000); 1443 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1444 #ifdef ATAPI_DEBUG_PROBE 1445 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1446 AHCINAME(sc), target, 1447 id->atap_config & ATAPI_CFG_CMD_MASK, 1448 id->atap_config & ATAPI_CFG_DRQ_MASK); 1449 #endif 1450 periph = scsipi_alloc_periph(M_NOWAIT); 1451 if (periph == NULL) { 1452 printf("%s: unable to allocate periph for drive %d\n", 1453 sc->sc_dev.dv_xname, target); 1454 return; 1455 } 1456 periph->periph_dev = NULL; 1457 periph->periph_channel = chan; 1458 periph->periph_switch = &atapi_probe_periphsw; 1459 periph->periph_target = target; 1460 periph->periph_lun = 0; 1461 periph->periph_quirks = PQUIRK_ONLYBIG; 1462 1463 #ifdef SCSIPI_DEBUG 1464 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1465 SCSIPI_DEBUG_TARGET == target) 1466 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1467 #endif 1468 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1469 if (id->atap_config & ATAPI_CFG_REMOV) 1470 periph->periph_flags |= PERIPH_REMOVABLE; 1471 if (periph->periph_type == T_SEQUENTIAL) { 1472 s = splbio(); 1473 drvp->drive_flags |= DRIVE_ATAPIST; 1474 splx(s); 1475 } 1476 1477 sa.sa_periph = periph; 1478 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1479 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1480 T_REMOV : T_FIXED; 1481 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1482 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1483 20); 1484 scsipi_strvis((u_char *)firmware_revision, 8, 1485 id->atap_revision, 8); 1486 sa.sa_inqbuf.vendor = model; 1487 sa.sa_inqbuf.product = serial_number; 1488 sa.sa_inqbuf.revision = firmware_revision; 1489 1490 /* 1491 * Determine the operating mode capabilities of the device. 1492 */ 1493 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1494 periph->periph_cap |= PERIPH_CAP_CMD16; 1495 /* XXX This is gross. */ 1496 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1497 1498 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1499 1500 if (drvp->drv_softc) 1501 ata_probe_caps(drvp); 1502 else { 1503 s = splbio(); 1504 drvp->drive_flags &= ~DRIVE_ATAPI; 1505 splx(s); 1506 } 1507 } else { 1508 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1509 "failed for drive %s:%d:%d: error 0x%x\n", 1510 AHCINAME(ahcic), chp->ch_channel, target, 1511 chp->ch_error), DEBUG_PROBE); 1512 s = splbio(); 1513 drvp->drive_flags &= ~DRIVE_ATAPI; 1514 splx(s); 1515 } 1516 } 1517 #endif /* NATAPIBUS */ 1518
Indexes created Fri Oct 17 00:09:41 GMT 2025