ahcisata_core.c revision 1.4.8.1
1 /* $NetBSD: ahcisata_core.c,v 1.4.8.1 2007/08/04 18:20:50 he Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.4.8.1 2007/08/04 18:20:50 he Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/ic/wdcreg.h> 47 #include <dev/ata/atareg.h> 48 #include <dev/ata/satavar.h> 49 #include <dev/ata/satareg.h> 50 #include <dev/ic/ahcisatavar.h> 51 52 #ifdef AHCI_DEBUG 53 int ahcidebug_mask = 0x0; 54 #endif 55 56 void ahci_probe_drive(struct ata_channel *); 57 void ahci_setup_channel(struct ata_channel *); 58 59 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 60 void ahci_reset_drive(struct ata_drive_datas *, int); 61 void ahci_reset_channel(struct ata_channel *, int); 62 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 63 int ahci_ata_addref(struct ata_drive_datas *); 64 void ahci_ata_delref(struct ata_drive_datas *); 65 void ahci_killpending(struct ata_drive_datas *); 66 67 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 68 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 69 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 70 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 71 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 72 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 73 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 75 void ahci_timeout(void *); 76 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 77 78 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 79 80 const struct ata_bustype ahci_ata_bustype = { 81 SCSIPI_BUSTYPE_ATA, 82 ahci_ata_bio, 83 ahci_reset_drive, 84 ahci_reset_channel, 85 ahci_exec_command, 86 ata_get_params, 87 ahci_ata_addref, 88 ahci_ata_delref, 89 ahci_killpending 90 }; 91 92 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 93 94 static void ahci_setup_port(struct ahci_softc *sc, int i); 95 96 97 int 98 ahci_reset(struct ahci_softc *sc) 99 { 100 int i; 101 102 /* reset controller */ 103 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 104 delay(1000); 105 /* wait up to 1s for reset to complete */ 106 for (i = 0; i < 1000; i++) { 107 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 108 break; 109 } 110 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 111 aprint_error("%s: reset failed\n", AHCINAME(sc)); 112 return -1; 113 } 114 /* enable ahci mode */ 115 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 116 return 0; 117 } 118 119 void 120 ahci_setup_ports(struct ahci_softc *sc) 121 { 122 u_int32_t ahci_ports; 123 int i, port; 124 125 ahci_ports = AHCI_READ(sc, AHCI_PI); 126 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 127 if ((ahci_ports & (1 << i)) == 0) 128 continue; 129 if (port >= sc->sc_atac.atac_nchannels) { 130 aprint_error("%s: more ports than announced\n", 131 AHCINAME(sc)); 132 break; 133 } 134 ahci_setup_port(sc, i); 135 } 136 } 137 138 void 139 ahci_reprobe_drives(struct ahci_softc *sc) 140 { 141 u_int32_t ahci_ports; 142 int i, port; 143 struct ahci_channel *achp; 144 struct ata_channel *chp; 145 146 ahci_ports = AHCI_READ(sc, AHCI_PI); 147 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 148 if ((ahci_ports & (1 << i)) == 0) 149 continue; 150 if (port >= sc->sc_atac.atac_nchannels) { 151 aprint_error("%s: more ports than announced\n", 152 AHCINAME(sc)); 153 break; 154 } 155 achp = &sc->sc_channels[i]; 156 chp = &achp->ata_channel; 157 158 ahci_probe_drive(chp); 159 } 160 } 161 162 static void 163 ahci_setup_port(struct ahci_softc *sc, int i) 164 { 165 struct ahci_channel *achp; 166 167 achp = &sc->sc_channels[i]; 168 169 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 170 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 171 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 172 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 173 } 174 175 void 176 ahci_enable_intrs(struct ahci_softc *sc) 177 { 178 179 /* clear interrupts */ 180 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 181 /* enable interrupts */ 182 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 183 } 184 185 void 186 ahci_attach(struct ahci_softc *sc) 187 { 188 u_int32_t ahci_cap, ahci_rev, ahci_ports; 189 int i, j, port; 190 struct ahci_channel *achp; 191 struct ata_channel *chp; 192 int error; 193 bus_dma_segment_t seg; 194 int rseg; 195 int dmasize; 196 void *cmdhp; 197 void *cmdtblp; 198 199 if (ahci_reset(sc) != 0) 200 return; 201 202 ahci_cap = AHCI_READ(sc, AHCI_CAP); 203 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 204 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 205 ahci_rev = AHCI_READ(sc, AHCI_VS); 206 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 207 switch(ahci_rev) { 208 case AHCI_VS_10: 209 aprint_normal("1.0"); 210 break; 211 case AHCI_VS_11: 212 aprint_normal("1.1"); 213 break; 214 default: 215 aprint_normal("0x%x", ahci_rev); 216 break; 217 } 218 219 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 220 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 221 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 222 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 223 sc->sc_atac.atac_pio_cap = 4; 224 sc->sc_atac.atac_dma_cap = 2; 225 sc->sc_atac.atac_udma_cap = 6; 226 sc->sc_atac.atac_channels = sc->sc_chanarray; 227 sc->sc_atac.atac_atapibus_attach = NULL; /* XXX */ 228 sc->sc_atac.atac_probe = ahci_probe_drive; 229 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 230 sc->sc_atac.atac_set_modes = ahci_setup_channel; 231 232 dmasize = 233 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 234 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 235 &seg, 1, &rseg, BUS_DMA_NOWAIT); 236 if (error) { 237 aprint_error("%s: unable to allocate command header memory" 238 ", error=%d\n", AHCINAME(sc), error); 239 return; 240 } 241 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 242 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 243 if (error) { 244 aprint_error("%s: unable to map command header memory" 245 ", error=%d\n", AHCINAME(sc), error); 246 return; 247 } 248 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 249 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 250 if (error) { 251 aprint_error("%s: unable to create command header map" 252 ", error=%d\n", AHCINAME(sc), error); 253 return; 254 } 255 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 256 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 257 if (error) { 258 aprint_error("%s: unable to load command header map" 259 ", error=%d\n", AHCINAME(sc), error); 260 return; 261 } 262 sc->sc_cmd_hdr = cmdhp; 263 264 ahci_enable_intrs(sc); 265 266 ahci_ports = AHCI_READ(sc, AHCI_PI); 267 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 268 if ((ahci_ports & (1 << i)) == 0) 269 continue; 270 if (port >= sc->sc_atac.atac_nchannels) { 271 aprint_error("%s: more ports than announced\n", 272 AHCINAME(sc)); 273 break; 274 } 275 achp = &sc->sc_channels[i]; 276 chp = (struct ata_channel *)achp; 277 sc->sc_chanarray[i] = chp; 278 chp->ch_channel = i; 279 chp->ch_atac = &sc->sc_atac; 280 chp->ch_queue = malloc(sizeof(struct ata_queue), 281 M_DEVBUF, M_NOWAIT); 282 if (chp->ch_queue == NULL) { 283 aprint_error("%s port %d: can't allocate memory for " 284 "command queue", AHCINAME(sc), i); 285 break; 286 } 287 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 288 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 289 &seg, 1, &rseg, BUS_DMA_NOWAIT); 290 if (error) { 291 aprint_error("%s: unable to allocate command table " 292 "memory, error=%d\n", AHCINAME(sc), error); 293 break; 294 } 295 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 296 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 297 if (error) { 298 aprint_error("%s: unable to map command table memory" 299 ", error=%d\n", AHCINAME(sc), error); 300 break; 301 } 302 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 303 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 304 if (error) { 305 aprint_error("%s: unable to create command table map" 306 ", error=%d\n", AHCINAME(sc), error); 307 break; 308 } 309 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 310 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 311 if (error) { 312 aprint_error("%s: unable to load command table map" 313 ", error=%d\n", AHCINAME(sc), error); 314 break; 315 } 316 achp->ahcic_cmdh = (struct ahci_cmd_header *) 317 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 318 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 319 AHCI_CMDH_SIZE * port; 320 achp->ahcic_rfis = (struct ahci_r_fis *) 321 ((char *)cmdhp + 322 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 323 AHCI_RFIS_SIZE * port); 324 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 325 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 326 AHCI_RFIS_SIZE * port; 327 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 328 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 329 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 330 DEBUG_PROBE); 331 332 for (j = 0; j < sc->sc_ncmds; j++) { 333 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 334 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 335 achp->ahcic_bus_cmd_tbl[j] = 336 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 337 AHCI_CMDTBL_SIZE * j; 338 achp->ahcic_cmdh[j].cmdh_cmdtba = 339 htole32(achp->ahcic_bus_cmd_tbl[j]); 340 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 341 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 342 achp->ahcic_cmd_tbl[j], 343 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 344 /* The xfer DMA map */ 345 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 346 AHCI_NPRD, 0x400000 /* 4MB */, 0, 347 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 348 &achp->ahcic_datad[j]); 349 if (error) { 350 aprint_error("%s: couldn't alloc xfer DMA map, " 351 "error=%d\n", AHCINAME(sc), error); 352 goto end; 353 } 354 } 355 ahci_setup_port(sc, i); 356 chp->ch_ndrive = 1; 357 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 358 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 359 aprint_error("%s: couldn't map channel %d " 360 "sata_status regs\n", AHCINAME(sc), i); 361 break; 362 } 363 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 364 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 365 aprint_error("%s: couldn't map channel %d " 366 "sata_control regs\n", AHCINAME(sc), i); 367 break; 368 } 369 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 370 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 371 aprint_error("%s: couldn't map channel %d " 372 "sata_error regs\n", AHCINAME(sc), i); 373 break; 374 } 375 ata_channel_attach(chp); 376 port++; 377 end: 378 continue; 379 } 380 } 381 382 int 383 ahci_intr(void *v) 384 { 385 struct ahci_softc *sc = v; 386 u_int32_t is; 387 int i, r = 0; 388 389 while ((is = AHCI_READ(sc, AHCI_IS))) { 390 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 391 DEBUG_INTR); 392 r = 1; 393 AHCI_WRITE(sc, AHCI_IS, is); 394 for (i = 0; i < AHCI_MAX_PORTS; i++) 395 if (is & (1 << i)) 396 ahci_intr_port(sc, &sc->sc_channels[i]); 397 } 398 return r; 399 } 400 401 void 402 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 403 { 404 u_int32_t is, tfd; 405 struct ata_channel *chp = &achp->ata_channel; 406 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 407 int slot; 408 409 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 410 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 411 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 412 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 413 DEBUG_INTR); 414 415 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 416 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 417 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 418 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 419 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 420 return; 421 /* stop channel */ 422 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 423 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 424 if (slot != 0) { 425 printf("ahci_intr_port: slot %d\n", slot); 426 panic("ahci_intr_port"); 427 } 428 if (is & AHCI_P_IX_TFES) { 429 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 430 chp->ch_error = 431 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 432 chp->ch_status = (tfd & 0xff); 433 } else { 434 /* emulate a CRC error */ 435 chp->ch_error = WDCE_CRC; 436 chp->ch_status = WDCS_ERR; 437 } 438 xfer->c_intr(chp, xfer, is); 439 } else { 440 slot = 0; /* XXX */ 441 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 442 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 443 chp->ch_channel, is, achp->ahcic_cmds_active, 444 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 445 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 446 return; 447 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 448 == 0) { 449 xfer->c_intr(chp, xfer, 0); 450 } 451 } 452 } 453 454 void 455 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 456 { 457 struct ata_channel *chp = drvp->chnl_softc; 458 ata_reset_channel(chp, flags); 459 return; 460 } 461 462 void 463 ahci_reset_channel(struct ata_channel *chp, int flags) 464 { 465 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 466 struct ahci_channel *achp = (struct ahci_channel *)chp; 467 int i; 468 469 /* stop channel */ 470 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 471 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 472 /* wait 1s for channel to stop */ 473 for (i = 0; i <100; i++) { 474 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 475 == 0) 476 break; 477 if (flags & AT_WAIT) 478 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 479 else 480 delay(10000); 481 } 482 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 483 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 484 /* XXX controller reset ? */ 485 return; 486 } 487 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 488 achp->ahcic_sstatus) != SStatus_DET_DEV) { 489 printf("%s: port reset failed\n", AHCINAME(sc)); 490 /* XXX and then ? */ 491 } 492 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 493 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 494 if (chp->ch_queue->active_xfer) { 495 chp->ch_queue->active_xfer->c_kill_xfer(chp, 496 chp->ch_queue->active_xfer, KILL_RESET); 497 } 498 ahci_channel_start(sc, chp); 499 return; 500 } 501 502 int 503 ahci_ata_addref(struct ata_drive_datas *drvp) 504 { 505 return 0; 506 } 507 508 void 509 ahci_ata_delref(struct ata_drive_datas *drvp) 510 { 511 return; 512 } 513 514 void 515 ahci_killpending(struct ata_drive_datas *drvp) 516 { 517 return; 518 } 519 520 void 521 ahci_probe_drive(struct ata_channel *chp) 522 { 523 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 524 struct ahci_channel *achp = (struct ahci_channel *)chp; 525 int i, s; 526 u_int32_t sig; 527 528 /* XXX This should be done by other code. */ 529 for (i = 0; i < chp->ch_ndrive; i++) { 530 chp->ch_drive[i].chnl_softc = chp; 531 chp->ch_drive[i].drive = i; 532 } 533 534 /* bring interface up, power up and spin up device */ 535 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 536 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 537 /* reset the PHY and bring online */ 538 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 539 achp->ahcic_sstatus)) { 540 case SStatus_DET_DEV: 541 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 542 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 543 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 544 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 545 AHCINAME(sc), chp->ch_channel, sig, 546 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 547 /* 548 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 549 * cases we get wrong values here, so ignore it. 550 */ 551 s = splbio(); 552 if ((sig & 0xffff0000) == 0xeb140000) { 553 aprint_error("%s port %d: ATAPI device ignored\n", 554 AHCINAME(sc), chp->ch_channel); 555 chp->ch_drive[0].drive_flags |= 0 /* DRIVE_ATAPI XXX */; 556 } else 557 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 558 splx(s); 559 /* enable interrupts */ 560 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 561 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 562 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 563 AHCI_P_IX_DHRS); 564 /* and start operations */ 565 ahci_channel_start(sc, chp); 566 break; 567 568 default: 569 break; 570 } 571 } 572 573 void 574 ahci_setup_channel(struct ata_channel *chp) 575 { 576 return; 577 } 578 579 int 580 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 581 { 582 struct ata_channel *chp = drvp->chnl_softc; 583 struct ata_xfer *xfer; 584 int ret; 585 int s; 586 587 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 588 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 589 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 590 DEBUG_XFERS); 591 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 592 ATAXF_NOSLEEP); 593 if (xfer == NULL) { 594 return ATACMD_TRY_AGAIN; 595 } 596 if (ata_c->flags & AT_POLL) 597 xfer->c_flags |= C_POLL; 598 if (ata_c->flags & AT_WAIT) 599 xfer->c_flags |= C_WAIT; 600 xfer->c_drive = drvp->drive; 601 xfer->c_databuf = ata_c->data; 602 xfer->c_bcount = ata_c->bcount; 603 xfer->c_cmd = ata_c; 604 xfer->c_start = ahci_cmd_start; 605 xfer->c_intr = ahci_cmd_complete; 606 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 607 s = splbio(); 608 ata_exec_xfer(chp, xfer); 609 #ifdef DIAGNOSTIC 610 if ((ata_c->flags & AT_POLL) != 0 && 611 (ata_c->flags & AT_DONE) == 0) 612 panic("ahci_exec_command: polled command not done"); 613 #endif 614 if (ata_c->flags & AT_DONE) { 615 ret = ATACMD_COMPLETE; 616 } else { 617 if (ata_c->flags & AT_WAIT) { 618 while ((ata_c->flags & AT_DONE) == 0) { 619 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 620 } 621 ret = ATACMD_COMPLETE; 622 } else { 623 ret = ATACMD_QUEUED; 624 } 625 } 626 splx(s); 627 return ret; 628 } 629 630 void 631 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 632 { 633 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 634 struct ahci_channel *achp = (struct ahci_channel *)chp; 635 struct ata_command *ata_c = xfer->c_cmd; 636 int slot = 0 /* XXX slot */; 637 struct ahci_cmd_tbl *cmd_tbl; 638 struct ahci_cmd_header *cmd_h; 639 u_int8_t *fis; 640 int i; 641 int channel = chp->ch_channel; 642 643 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 644 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 645 646 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 647 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 648 cmd_tbl), DEBUG_XFERS); 649 fis = cmd_tbl->cmdt_cfis; 650 651 fis[0] = 0x27; /* host to device */ 652 fis[1] = 0x80; /* command FIS */ 653 fis[2] = ata_c->r_command; 654 fis[3] = ata_c->r_features; 655 fis[4] = ata_c->r_sector; 656 fis[5] = ata_c->r_cyl & 0xff; 657 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 658 fis[7] = ata_c->r_head & 0x0f; 659 fis[8] = 0; 660 fis[9] = 0; 661 fis[10] = 0; 662 fis[11] = 0; 663 fis[12] = ata_c->r_count; 664 fis[13] = 0; 665 fis[14] = 0; 666 fis[15] = WDCTL_4BIT; 667 fis[16] = 0; 668 fis[17] = 0; 669 fis[18] = 0; 670 fis[19] = 0; 671 672 cmd_h = &achp->ahcic_cmdh[slot]; 673 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 674 chp->ch_channel, cmd_h), DEBUG_XFERS); 675 if (ahci_dma_setup(chp, slot, 676 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 677 ata_c->bcount, 678 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 679 ata_c->flags |= AT_DF; 680 ahci_cmd_complete(chp, xfer, slot); 681 return; 682 } 683 cmd_h->cmdh_flags = htole16( 684 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 685 20 /* fis lenght */ / 4); 686 cmd_h->cmdh_prdbc = 0; 687 AHCI_CMDH_SYNC(sc, achp, slot, 688 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 689 690 if (ata_c->flags & AT_POLL) { 691 /* polled command, disable interrupts */ 692 AHCI_WRITE(sc, AHCI_GHC, 693 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 694 } 695 chp->ch_flags |= ATACH_IRQ_WAIT; 696 /* start command */ 697 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 698 /* and says we started this command */ 699 achp->ahcic_cmds_active |= 1 << slot; 700 701 if ((ata_c->flags & AT_POLL) == 0) { 702 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 703 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 704 ahci_timeout, chp); 705 return; 706 } 707 /* 708 * Polled command. 709 */ 710 for (i = 0; i < ata_c->timeout / 10; i++) { 711 if (ata_c->flags & AT_DONE) 712 break; 713 ahci_intr_port(sc, achp); 714 if (ata_c->flags & AT_WAIT) 715 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 716 else 717 delay(10000); 718 } 719 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 720 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 721 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 722 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 723 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 724 DEBUG_XFERS); 725 if ((ata_c->flags & AT_DONE) == 0) { 726 ata_c->flags |= AT_TIMEOU; 727 ahci_cmd_complete(chp, xfer, slot); 728 } 729 /* reenable interrupts */ 730 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 731 } 732 733 void 734 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 735 { 736 struct ata_command *ata_c = xfer->c_cmd; 737 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 738 DEBUG_FUNCS); 739 740 switch (reason) { 741 case KILL_GONE: 742 ata_c->flags |= AT_GONE; 743 break; 744 case KILL_RESET: 745 ata_c->flags |= AT_RESET; 746 break; 747 default: 748 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 749 panic("ahci_cmd_kill_xfer"); 750 } 751 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 752 } 753 754 int 755 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 756 { 757 int slot = 0; /* XXX slot */ 758 struct ata_command *ata_c = xfer->c_cmd; 759 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 760 761 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 762 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 763 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 764 DEBUG_FUNCS); 765 chp->ch_flags &= ~ATACH_IRQ_WAIT; 766 if (xfer->c_flags & C_TIMEOU) { 767 ata_c->flags |= AT_TIMEOU; 768 } else 769 callout_stop(&chp->ch_callout); 770 771 chp->ch_queue->active_xfer = NULL; 772 773 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 774 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 775 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 776 wakeup(&chp->ch_queue->active_xfer); 777 return 0; 778 } 779 if (is) { 780 ata_c->r_head = 0; 781 ata_c->r_count = 0; 782 ata_c->r_sector = 0; 783 ata_c->r_cyl = 0; 784 if (chp->ch_status & WDCS_BSY) { 785 ata_c->flags |= AT_TIMEOU; 786 } else if (chp->ch_status & WDCS_ERR) { 787 ata_c->r_error = chp->ch_error; 788 ata_c->flags |= AT_ERROR; 789 } 790 } 791 ahci_cmd_done(chp, xfer, slot); 792 return 0; 793 } 794 795 void 796 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 797 { 798 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 799 struct ahci_channel *achp = (struct ahci_channel *)chp; 800 struct ata_command *ata_c = xfer->c_cmd; 801 802 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 803 DEBUG_FUNCS); 804 805 /* this comamnd is not active any more */ 806 achp->ahcic_cmds_active &= ~(1 << slot); 807 808 if (ata_c->flags & (AT_READ|AT_WRITE)) { 809 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 810 achp->ahcic_datad[slot]->dm_mapsize, 811 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 812 BUS_DMASYNC_POSTWRITE); 813 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 814 } 815 816 AHCI_CMDH_SYNC(sc, achp, slot, 817 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 818 819 ata_c->flags |= AT_DONE; 820 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 821 ata_c->flags |= AT_XFDONE; 822 823 ata_free_xfer(chp, xfer); 824 if (ata_c->flags & AT_WAIT) 825 wakeup(ata_c); 826 else if (ata_c->callback) 827 ata_c->callback(ata_c->callback_arg); 828 atastart(chp); 829 return; 830 } 831 832 int 833 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 834 { 835 struct ata_channel *chp = drvp->chnl_softc; 836 struct ata_xfer *xfer; 837 838 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 839 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 840 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 841 DEBUG_XFERS); 842 xfer = ata_get_xfer(ATAXF_NOSLEEP); 843 if (xfer == NULL) { 844 return ATACMD_TRY_AGAIN; 845 } 846 if (ata_bio->flags & ATA_POLL) 847 xfer->c_flags |= C_POLL; 848 xfer->c_drive = drvp->drive; 849 xfer->c_cmd = ata_bio; 850 xfer->c_databuf = ata_bio->databuf; 851 xfer->c_bcount = ata_bio->bcount; 852 xfer->c_start = ahci_bio_start; 853 xfer->c_intr = ahci_bio_complete; 854 xfer->c_kill_xfer = ahci_bio_kill_xfer; 855 ata_exec_xfer(chp, xfer); 856 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 857 } 858 859 void 860 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 861 { 862 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 863 struct ahci_channel *achp = (struct ahci_channel *)chp; 864 struct ata_bio *ata_bio = xfer->c_cmd; 865 int slot = 0 /* XXX slot */; 866 struct ahci_cmd_tbl *cmd_tbl; 867 struct ahci_cmd_header *cmd_h; 868 u_int8_t *fis; 869 int i, nblks; 870 int channel = chp->ch_channel; 871 872 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 873 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 874 875 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 876 877 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 878 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 879 cmd_tbl), DEBUG_XFERS); 880 fis = cmd_tbl->cmdt_cfis; 881 882 fis[0] = 0x27; /* host to device */ 883 fis[1] = 0x80; /* command FIS */ 884 if (ata_bio->flags & ATA_LBA48) { 885 fis[2] = (ata_bio->flags & ATA_READ) ? 886 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 887 } else { 888 fis[2] = 889 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 890 } 891 fis[3] = 0; /* features */ 892 fis[4] = ata_bio->blkno & 0xff; 893 fis[5] = (ata_bio->blkno >> 8) & 0xff; 894 fis[6] = (ata_bio->blkno >> 16) & 0xff; 895 if (ata_bio->flags & ATA_LBA48) { 896 fis[7] = WDSD_LBA; 897 fis[8] = (ata_bio->blkno >> 24) & 0xff; 898 fis[9] = (ata_bio->blkno >> 32) & 0xff; 899 fis[10] = (ata_bio->blkno >> 40) & 0xff; 900 } else { 901 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 902 fis[8] = 0; 903 fis[9] = 0; 904 fis[10] = 0; 905 } 906 fis[11] = 0; /* ext features */ 907 fis[12] = nblks & 0xff; 908 fis[13] = (ata_bio->flags & ATA_LBA48) ? 909 ((nblks >> 8) & 0xff) : 0; 910 fis[14] = 0; 911 fis[15] = WDCTL_4BIT; 912 fis[16] = 0; 913 fis[17] = 0; 914 fis[18] = 0; 915 fis[19] = 0; 916 917 cmd_h = &achp->ahcic_cmdh[slot]; 918 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 919 chp->ch_channel, cmd_h), DEBUG_XFERS); 920 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 921 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 922 ata_bio->error = ERR_DMA; 923 ata_bio->r_error = 0; 924 ahci_bio_complete(chp, xfer, slot); 925 return; 926 } 927 cmd_h->cmdh_flags = htole16( 928 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 929 20 /* fis lenght */ / 4); 930 cmd_h->cmdh_prdbc = 0; 931 AHCI_CMDH_SYNC(sc, achp, slot, 932 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 933 934 if (xfer->c_flags & C_POLL) { 935 /* polled command, disable interrupts */ 936 AHCI_WRITE(sc, AHCI_GHC, 937 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 938 } 939 chp->ch_flags |= ATACH_IRQ_WAIT; 940 /* start command */ 941 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 942 /* and says we started this command */ 943 achp->ahcic_cmds_active |= 1 << slot; 944 945 if ((xfer->c_flags & C_POLL) == 0) { 946 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 947 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 948 ahci_timeout, chp); 949 return; 950 } 951 /* 952 * Polled command. 953 */ 954 for (i = 0; i < ATA_DELAY / 10; i++) { 955 if (ata_bio->flags & ATA_ITSDONE) 956 break; 957 ahci_intr_port(sc, achp); 958 if (ata_bio->flags & ATA_NOSLEEP) 959 delay(10000); 960 else 961 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 962 } 963 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 964 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 965 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 966 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 967 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 968 DEBUG_XFERS); 969 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 970 ata_bio->error = TIMEOUT; 971 ahci_bio_complete(chp, xfer, slot); 972 } 973 /* reenable interrupts */ 974 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 975 } 976 977 void 978 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 979 { 980 int slot = 0; /* XXX slot */ 981 int drive = xfer->c_drive; 982 struct ata_bio *ata_bio = xfer->c_cmd; 983 struct ahci_channel *achp = (struct ahci_channel *)chp; 984 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 985 DEBUG_FUNCS); 986 987 achp->ahcic_cmds_active &= ~(1 << slot); 988 ata_free_xfer(chp, xfer); 989 ata_bio->flags |= ATA_ITSDONE; 990 switch (reason) { 991 case KILL_GONE: 992 ata_bio->error = ERR_NODEV; 993 break; 994 case KILL_RESET: 995 ata_bio->error = ERR_RESET; 996 break; 997 default: 998 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 999 panic("ahci_bio_kill_xfer"); 1000 } 1001 ata_bio->r_error = WDCE_ABRT; 1002 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1003 } 1004 1005 int 1006 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1007 { 1008 int slot = 0; /* XXX slot */ 1009 struct ata_bio *ata_bio = xfer->c_cmd; 1010 int drive = xfer->c_drive; 1011 struct ahci_channel *achp = (struct ahci_channel *)chp; 1012 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1013 1014 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1015 DEBUG_FUNCS); 1016 1017 achp->ahcic_cmds_active &= ~(1 << slot); 1018 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1019 callout_stop(&chp->ch_callout); 1020 1021 chp->ch_queue->active_xfer = NULL; 1022 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1023 achp->ahcic_datad[slot]->dm_mapsize, 1024 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1025 BUS_DMASYNC_POSTWRITE); 1026 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1027 1028 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1029 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1030 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1031 wakeup(&chp->ch_queue->active_xfer); 1032 return 0; 1033 } 1034 ata_free_xfer(chp, xfer); 1035 ata_bio->flags |= ATA_ITSDONE; 1036 if (chp->ch_status & WDCS_DWF) { 1037 ata_bio->error = ERR_DF; 1038 } else if (chp->ch_status & WDCS_ERR) { 1039 ata_bio->error = ERROR; 1040 ata_bio->r_error = chp->ch_error; 1041 } else if (chp->ch_status & WDCS_CORR) 1042 ata_bio->flags |= ATA_CORR; 1043 1044 AHCI_CMDH_SYNC(sc, achp, slot, 1045 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1046 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1047 ata_bio->bcount), DEBUG_XFERS); 1048 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1049 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1050 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1051 atastart(chp); 1052 return 0; 1053 } 1054 1055 void 1056 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1057 { 1058 /* clear error */ 1059 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1060 1061 /* and start controller */ 1062 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1063 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1064 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1065 } 1066 1067 void 1068 ahci_timeout(void *v) 1069 { 1070 struct ata_channel *chp = (struct ata_channel *)v; 1071 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1072 int s = splbio(); 1073 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1074 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1075 xfer->c_flags |= C_TIMEOU; 1076 xfer->c_intr(chp, xfer, 0); 1077 } 1078 splx(s); 1079 } 1080 1081 int 1082 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1083 size_t count, int op) 1084 { 1085 int error, seg; 1086 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1087 struct ahci_channel *achp = (struct ahci_channel *)chp; 1088 struct ahci_cmd_tbl *cmd_tbl; 1089 struct ahci_cmd_header *cmd_h; 1090 1091 cmd_h = &achp->ahcic_cmdh[slot]; 1092 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1093 1094 if (data == NULL) { 1095 cmd_h->cmdh_prdtl = 0; 1096 goto end; 1097 } 1098 1099 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1100 data, count, NULL, 1101 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1102 if (error) { 1103 printf("%s port %d: failed to load xfer: %d\n", 1104 AHCINAME(sc), chp->ch_channel, error); 1105 return error; 1106 } 1107 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1108 achp->ahcic_datad[slot]->dm_mapsize, 1109 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1110 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1111 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1112 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1113 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1114 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1115 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1116 } 1117 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1118 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1119 end: 1120 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1121 return 0; 1122 } 1123
Indexes created Fri Oct 17 00:09:41 GMT 2025