ahcisata_core.c revision 1.4.8.2
1 /* $NetBSD: ahcisata_core.c,v 1.4.8.2 2007/10/02 18:28:22 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.4.8.2 2007/10/02 18:28:22 joerg Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/ic/wdcreg.h> 47 #include <dev/ata/atareg.h> 48 #include <dev/ata/satavar.h> 49 #include <dev/ata/satareg.h> 50 #include <dev/ic/ahcisatavar.h> 51 52 #ifdef AHCI_DEBUG 53 int ahcidebug_mask = 0x0; 54 #endif 55 56 void ahci_probe_drive(struct ata_channel *); 57 void ahci_setup_channel(struct ata_channel *); 58 59 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 60 void ahci_reset_drive(struct ata_drive_datas *, int); 61 void ahci_reset_channel(struct ata_channel *, int); 62 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 63 int ahci_ata_addref(struct ata_drive_datas *); 64 void ahci_ata_delref(struct ata_drive_datas *); 65 void ahci_killpending(struct ata_drive_datas *); 66 67 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 68 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 69 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 70 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 71 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 72 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 73 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 75 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 76 void ahci_timeout(void *); 77 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 78 79 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 80 81 const struct ata_bustype ahci_ata_bustype = { 82 SCSIPI_BUSTYPE_ATA, 83 ahci_ata_bio, 84 ahci_reset_drive, 85 ahci_reset_channel, 86 ahci_exec_command, 87 ata_get_params, 88 ahci_ata_addref, 89 ahci_ata_delref, 90 ahci_killpending 91 }; 92 93 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 94 95 static void ahci_setup_port(struct ahci_softc *sc, int i); 96 97 98 int 99 ahci_reset(struct ahci_softc *sc) 100 { 101 int i; 102 103 /* reset controller */ 104 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 105 delay(1000); 106 /* wait up to 1s for reset to complete */ 107 for (i = 0; i < 1000; i++) { 108 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 109 break; 110 } 111 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 112 aprint_error("%s: reset failed\n", AHCINAME(sc)); 113 return -1; 114 } 115 /* enable ahci mode */ 116 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 117 return 0; 118 } 119 120 void 121 ahci_setup_ports(struct ahci_softc *sc) 122 { 123 u_int32_t ahci_ports; 124 int i, port; 125 126 ahci_ports = AHCI_READ(sc, AHCI_PI); 127 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 128 if ((ahci_ports & (1 << i)) == 0) 129 continue; 130 if (port >= sc->sc_atac.atac_nchannels) { 131 aprint_error("%s: more ports than announced\n", 132 AHCINAME(sc)); 133 break; 134 } 135 ahci_setup_port(sc, i); 136 } 137 } 138 139 void 140 ahci_reprobe_drives(struct ahci_softc *sc) 141 { 142 u_int32_t ahci_ports; 143 int i, port; 144 struct ahci_channel *achp; 145 struct ata_channel *chp; 146 147 ahci_ports = AHCI_READ(sc, AHCI_PI); 148 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 149 if ((ahci_ports & (1 << i)) == 0) 150 continue; 151 if (port >= sc->sc_atac.atac_nchannels) { 152 aprint_error("%s: more ports than announced\n", 153 AHCINAME(sc)); 154 break; 155 } 156 achp = &sc->sc_channels[i]; 157 chp = &achp->ata_channel; 158 159 ahci_probe_drive(chp); 160 } 161 } 162 163 static void 164 ahci_setup_port(struct ahci_softc *sc, int i) 165 { 166 struct ahci_channel *achp; 167 168 achp = &sc->sc_channels[i]; 169 170 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 171 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 172 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 173 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 174 } 175 176 void 177 ahci_enable_intrs(struct ahci_softc *sc) 178 { 179 180 /* clear interrupts */ 181 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 182 /* enable interrupts */ 183 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 184 } 185 186 void 187 ahci_attach(struct ahci_softc *sc) 188 { 189 u_int32_t ahci_cap, ahci_rev, ahci_ports; 190 int i, j, port; 191 struct ahci_channel *achp; 192 struct ata_channel *chp; 193 int error; 194 bus_dma_segment_t seg; 195 int rseg; 196 int dmasize; 197 void *cmdhp; 198 void *cmdtblp; 199 200 if (ahci_reset(sc) != 0) 201 return; 202 203 ahci_cap = AHCI_READ(sc, AHCI_CAP); 204 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 205 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 206 ahci_rev = AHCI_READ(sc, AHCI_VS); 207 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 208 switch(ahci_rev) { 209 case AHCI_VS_10: 210 aprint_normal("1.0"); 211 break; 212 case AHCI_VS_11: 213 aprint_normal("1.1"); 214 break; 215 default: 216 aprint_normal("0x%x", ahci_rev); 217 break; 218 } 219 220 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 221 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 222 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 223 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 224 sc->sc_atac.atac_pio_cap = 4; 225 sc->sc_atac.atac_dma_cap = 2; 226 sc->sc_atac.atac_udma_cap = 6; 227 sc->sc_atac.atac_channels = sc->sc_chanarray; 228 sc->sc_atac.atac_atapibus_attach = NULL; /* XXX */ 229 sc->sc_atac.atac_probe = ahci_probe_drive; 230 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 231 sc->sc_atac.atac_set_modes = ahci_setup_channel; 232 233 dmasize = 234 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 235 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 236 &seg, 1, &rseg, BUS_DMA_NOWAIT); 237 if (error) { 238 aprint_error("%s: unable to allocate command header memory" 239 ", error=%d\n", AHCINAME(sc), error); 240 return; 241 } 242 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 243 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 244 if (error) { 245 aprint_error("%s: unable to map command header memory" 246 ", error=%d\n", AHCINAME(sc), error); 247 return; 248 } 249 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 250 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 251 if (error) { 252 aprint_error("%s: unable to create command header map" 253 ", error=%d\n", AHCINAME(sc), error); 254 return; 255 } 256 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 257 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 258 if (error) { 259 aprint_error("%s: unable to load command header map" 260 ", error=%d\n", AHCINAME(sc), error); 261 return; 262 } 263 sc->sc_cmd_hdr = cmdhp; 264 265 ahci_enable_intrs(sc); 266 267 ahci_ports = AHCI_READ(sc, AHCI_PI); 268 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 269 if ((ahci_ports & (1 << i)) == 0) 270 continue; 271 if (port >= sc->sc_atac.atac_nchannels) { 272 aprint_error("%s: more ports than announced\n", 273 AHCINAME(sc)); 274 break; 275 } 276 achp = &sc->sc_channels[i]; 277 chp = (struct ata_channel *)achp; 278 sc->sc_chanarray[i] = chp; 279 chp->ch_channel = i; 280 chp->ch_atac = &sc->sc_atac; 281 chp->ch_queue = malloc(sizeof(struct ata_queue), 282 M_DEVBUF, M_NOWAIT); 283 if (chp->ch_queue == NULL) { 284 aprint_error("%s port %d: can't allocate memory for " 285 "command queue", AHCINAME(sc), i); 286 break; 287 } 288 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 289 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 290 &seg, 1, &rseg, BUS_DMA_NOWAIT); 291 if (error) { 292 aprint_error("%s: unable to allocate command table " 293 "memory, error=%d\n", AHCINAME(sc), error); 294 break; 295 } 296 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 297 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 298 if (error) { 299 aprint_error("%s: unable to map command table memory" 300 ", error=%d\n", AHCINAME(sc), error); 301 break; 302 } 303 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 304 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 305 if (error) { 306 aprint_error("%s: unable to create command table map" 307 ", error=%d\n", AHCINAME(sc), error); 308 break; 309 } 310 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 311 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 312 if (error) { 313 aprint_error("%s: unable to load command table map" 314 ", error=%d\n", AHCINAME(sc), error); 315 break; 316 } 317 achp->ahcic_cmdh = (struct ahci_cmd_header *) 318 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 319 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 320 AHCI_CMDH_SIZE * port; 321 achp->ahcic_rfis = (struct ahci_r_fis *) 322 ((char *)cmdhp + 323 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 324 AHCI_RFIS_SIZE * port); 325 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 326 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 327 AHCI_RFIS_SIZE * port; 328 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 329 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 330 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 331 DEBUG_PROBE); 332 333 for (j = 0; j < sc->sc_ncmds; j++) { 334 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 335 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 336 achp->ahcic_bus_cmd_tbl[j] = 337 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 338 AHCI_CMDTBL_SIZE * j; 339 achp->ahcic_cmdh[j].cmdh_cmdtba = 340 htole32(achp->ahcic_bus_cmd_tbl[j]); 341 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 342 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 343 achp->ahcic_cmd_tbl[j], 344 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 345 /* The xfer DMA map */ 346 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 347 AHCI_NPRD, 0x400000 /* 4MB */, 0, 348 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 349 &achp->ahcic_datad[j]); 350 if (error) { 351 aprint_error("%s: couldn't alloc xfer DMA map, " 352 "error=%d\n", AHCINAME(sc), error); 353 goto end; 354 } 355 } 356 ahci_setup_port(sc, i); 357 chp->ch_ndrive = 1; 358 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 359 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 360 aprint_error("%s: couldn't map channel %d " 361 "sata_status regs\n", AHCINAME(sc), i); 362 break; 363 } 364 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 365 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 366 aprint_error("%s: couldn't map channel %d " 367 "sata_control regs\n", AHCINAME(sc), i); 368 break; 369 } 370 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 371 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 372 aprint_error("%s: couldn't map channel %d " 373 "sata_error regs\n", AHCINAME(sc), i); 374 break; 375 } 376 ata_channel_attach(chp); 377 port++; 378 end: 379 continue; 380 } 381 } 382 383 int 384 ahci_intr(void *v) 385 { 386 struct ahci_softc *sc = v; 387 u_int32_t is; 388 int i, r = 0; 389 390 while ((is = AHCI_READ(sc, AHCI_IS))) { 391 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 392 DEBUG_INTR); 393 r = 1; 394 AHCI_WRITE(sc, AHCI_IS, is); 395 for (i = 0; i < AHCI_MAX_PORTS; i++) 396 if (is & (1 << i)) 397 ahci_intr_port(sc, &sc->sc_channels[i]); 398 } 399 return r; 400 } 401 402 void 403 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 404 { 405 u_int32_t is, tfd; 406 struct ata_channel *chp = &achp->ata_channel; 407 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 408 int slot; 409 410 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 411 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 412 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 413 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 414 DEBUG_INTR); 415 416 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 417 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 418 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 419 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 420 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 421 return; 422 /* stop channel */ 423 ahci_channel_stop(sc, chp, 0); 424 if (slot != 0) { 425 printf("ahci_intr_port: slot %d\n", slot); 426 panic("ahci_intr_port"); 427 } 428 if (is & AHCI_P_IX_TFES) { 429 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 430 chp->ch_error = 431 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 432 chp->ch_status = (tfd & 0xff); 433 } else { 434 /* emulate a CRC error */ 435 chp->ch_error = WDCE_CRC; 436 chp->ch_status = WDCS_ERR; 437 } 438 xfer->c_intr(chp, xfer, is); 439 /* if channel has not been restarted, do it now */ 440 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 441 == 0) 442 ahci_channel_start(sc, chp); 443 } else { 444 slot = 0; /* XXX */ 445 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 446 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 447 chp->ch_channel, is, achp->ahcic_cmds_active, 448 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 449 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 450 return; 451 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 452 == 0) { 453 xfer->c_intr(chp, xfer, 0); 454 } 455 } 456 } 457 458 void 459 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 460 { 461 struct ata_channel *chp = drvp->chnl_softc; 462 ata_reset_channel(chp, flags); 463 return; 464 } 465 466 void 467 ahci_reset_channel(struct ata_channel *chp, int flags) 468 { 469 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 470 struct ahci_channel *achp = (struct ahci_channel *)chp; 471 472 ahci_channel_stop(sc, chp, flags); 473 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 474 achp->ahcic_sstatus) != SStatus_DET_DEV) { 475 printf("%s: port reset failed\n", AHCINAME(sc)); 476 /* XXX and then ? */ 477 } 478 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 479 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 480 if (chp->ch_queue->active_xfer) { 481 chp->ch_queue->active_xfer->c_kill_xfer(chp, 482 chp->ch_queue->active_xfer, KILL_RESET); 483 } 484 ahci_channel_start(sc, chp); 485 return; 486 } 487 488 int 489 ahci_ata_addref(struct ata_drive_datas *drvp) 490 { 491 return 0; 492 } 493 494 void 495 ahci_ata_delref(struct ata_drive_datas *drvp) 496 { 497 return; 498 } 499 500 void 501 ahci_killpending(struct ata_drive_datas *drvp) 502 { 503 return; 504 } 505 506 void 507 ahci_probe_drive(struct ata_channel *chp) 508 { 509 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 510 struct ahci_channel *achp = (struct ahci_channel *)chp; 511 int i, s; 512 u_int32_t sig; 513 514 /* XXX This should be done by other code. */ 515 for (i = 0; i < chp->ch_ndrive; i++) { 516 chp->ch_drive[i].chnl_softc = chp; 517 chp->ch_drive[i].drive = i; 518 } 519 520 /* bring interface up, power up and spin up device */ 521 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 522 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 523 /* reset the PHY and bring online */ 524 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 525 achp->ahcic_sstatus)) { 526 case SStatus_DET_DEV: 527 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 528 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 529 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 530 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 531 AHCINAME(sc), chp->ch_channel, sig, 532 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 533 /* 534 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 535 * cases we get wrong values here, so ignore it. 536 */ 537 s = splbio(); 538 if ((sig & 0xffff0000) == 0xeb140000) { 539 aprint_error("%s port %d: ATAPI device ignored\n", 540 AHCINAME(sc), chp->ch_channel); 541 chp->ch_drive[0].drive_flags |= 0 /* DRIVE_ATAPI XXX */; 542 } else 543 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 544 splx(s); 545 /* enable interrupts */ 546 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 547 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 548 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 549 AHCI_P_IX_DHRS); 550 /* and start operations */ 551 ahci_channel_start(sc, chp); 552 break; 553 554 default: 555 break; 556 } 557 } 558 559 void 560 ahci_setup_channel(struct ata_channel *chp) 561 { 562 return; 563 } 564 565 int 566 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 567 { 568 struct ata_channel *chp = drvp->chnl_softc; 569 struct ata_xfer *xfer; 570 int ret; 571 int s; 572 573 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 574 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 575 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 576 DEBUG_XFERS); 577 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 578 ATAXF_NOSLEEP); 579 if (xfer == NULL) { 580 return ATACMD_TRY_AGAIN; 581 } 582 if (ata_c->flags & AT_POLL) 583 xfer->c_flags |= C_POLL; 584 if (ata_c->flags & AT_WAIT) 585 xfer->c_flags |= C_WAIT; 586 xfer->c_drive = drvp->drive; 587 xfer->c_databuf = ata_c->data; 588 xfer->c_bcount = ata_c->bcount; 589 xfer->c_cmd = ata_c; 590 xfer->c_start = ahci_cmd_start; 591 xfer->c_intr = ahci_cmd_complete; 592 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 593 s = splbio(); 594 ata_exec_xfer(chp, xfer); 595 #ifdef DIAGNOSTIC 596 if ((ata_c->flags & AT_POLL) != 0 && 597 (ata_c->flags & AT_DONE) == 0) 598 panic("ahci_exec_command: polled command not done"); 599 #endif 600 if (ata_c->flags & AT_DONE) { 601 ret = ATACMD_COMPLETE; 602 } else { 603 if (ata_c->flags & AT_WAIT) { 604 while ((ata_c->flags & AT_DONE) == 0) { 605 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 606 } 607 ret = ATACMD_COMPLETE; 608 } else { 609 ret = ATACMD_QUEUED; 610 } 611 } 612 splx(s); 613 return ret; 614 } 615 616 void 617 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 618 { 619 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 620 struct ahci_channel *achp = (struct ahci_channel *)chp; 621 struct ata_command *ata_c = xfer->c_cmd; 622 int slot = 0 /* XXX slot */; 623 struct ahci_cmd_tbl *cmd_tbl; 624 struct ahci_cmd_header *cmd_h; 625 u_int8_t *fis; 626 int i; 627 int channel = chp->ch_channel; 628 629 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 630 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 631 632 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 633 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 634 cmd_tbl), DEBUG_XFERS); 635 fis = cmd_tbl->cmdt_cfis; 636 637 fis[0] = 0x27; /* host to device */ 638 fis[1] = 0x80; /* command FIS */ 639 fis[2] = ata_c->r_command; 640 fis[3] = ata_c->r_features; 641 fis[4] = ata_c->r_sector; 642 fis[5] = ata_c->r_cyl & 0xff; 643 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 644 fis[7] = ata_c->r_head & 0x0f; 645 fis[8] = 0; 646 fis[9] = 0; 647 fis[10] = 0; 648 fis[11] = 0; 649 fis[12] = ata_c->r_count; 650 fis[13] = 0; 651 fis[14] = 0; 652 fis[15] = WDCTL_4BIT; 653 fis[16] = 0; 654 fis[17] = 0; 655 fis[18] = 0; 656 fis[19] = 0; 657 658 cmd_h = &achp->ahcic_cmdh[slot]; 659 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 660 chp->ch_channel, cmd_h), DEBUG_XFERS); 661 if (ahci_dma_setup(chp, slot, 662 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 663 ata_c->bcount, 664 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 665 ata_c->flags |= AT_DF; 666 ahci_cmd_complete(chp, xfer, slot); 667 return; 668 } 669 cmd_h->cmdh_flags = htole16( 670 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 671 20 /* fis lenght */ / 4); 672 cmd_h->cmdh_prdbc = 0; 673 AHCI_CMDH_SYNC(sc, achp, slot, 674 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 675 676 if (ata_c->flags & AT_POLL) { 677 /* polled command, disable interrupts */ 678 AHCI_WRITE(sc, AHCI_GHC, 679 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 680 } 681 chp->ch_flags |= ATACH_IRQ_WAIT; 682 chp->ch_status = 0; 683 /* start command */ 684 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 685 /* and says we started this command */ 686 achp->ahcic_cmds_active |= 1 << slot; 687 688 if ((ata_c->flags & AT_POLL) == 0) { 689 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 690 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 691 ahci_timeout, chp); 692 return; 693 } 694 /* 695 * Polled command. 696 */ 697 for (i = 0; i < ata_c->timeout / 10; i++) { 698 if (ata_c->flags & AT_DONE) 699 break; 700 ahci_intr_port(sc, achp); 701 if (ata_c->flags & AT_WAIT) 702 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 703 else 704 delay(10000); 705 } 706 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 707 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 708 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 709 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 710 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 711 DEBUG_XFERS); 712 if ((ata_c->flags & AT_DONE) == 0) { 713 ata_c->flags |= AT_TIMEOU; 714 ahci_cmd_complete(chp, xfer, slot); 715 } 716 /* reenable interrupts */ 717 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 718 } 719 720 void 721 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 722 { 723 struct ata_command *ata_c = xfer->c_cmd; 724 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 725 DEBUG_FUNCS); 726 727 switch (reason) { 728 case KILL_GONE: 729 ata_c->flags |= AT_GONE; 730 break; 731 case KILL_RESET: 732 ata_c->flags |= AT_RESET; 733 break; 734 default: 735 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 736 panic("ahci_cmd_kill_xfer"); 737 } 738 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 739 } 740 741 int 742 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 743 { 744 int slot = 0; /* XXX slot */ 745 struct ata_command *ata_c = xfer->c_cmd; 746 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 747 748 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 749 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 750 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 751 DEBUG_FUNCS); 752 chp->ch_flags &= ~ATACH_IRQ_WAIT; 753 if (xfer->c_flags & C_TIMEOU) { 754 ata_c->flags |= AT_TIMEOU; 755 } else 756 callout_stop(&chp->ch_callout); 757 758 chp->ch_queue->active_xfer = NULL; 759 760 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 761 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 762 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 763 wakeup(&chp->ch_queue->active_xfer); 764 return 0; 765 } 766 if (is) { 767 ata_c->r_head = 0; 768 ata_c->r_count = 0; 769 ata_c->r_sector = 0; 770 ata_c->r_cyl = 0; 771 if (chp->ch_status & WDCS_BSY) { 772 ata_c->flags |= AT_TIMEOU; 773 } else if (chp->ch_status & WDCS_ERR) { 774 ata_c->r_error = chp->ch_error; 775 ata_c->flags |= AT_ERROR; 776 } 777 } 778 ahci_cmd_done(chp, xfer, slot); 779 return 0; 780 } 781 782 void 783 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 784 { 785 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 786 struct ahci_channel *achp = (struct ahci_channel *)chp; 787 struct ata_command *ata_c = xfer->c_cmd; 788 789 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 790 DEBUG_FUNCS); 791 792 /* this comamnd is not active any more */ 793 achp->ahcic_cmds_active &= ~(1 << slot); 794 795 if (ata_c->flags & (AT_READ|AT_WRITE)) { 796 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 797 achp->ahcic_datad[slot]->dm_mapsize, 798 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 799 BUS_DMASYNC_POSTWRITE); 800 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 801 } 802 803 AHCI_CMDH_SYNC(sc, achp, slot, 804 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 805 806 ata_c->flags |= AT_DONE; 807 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 808 ata_c->flags |= AT_XFDONE; 809 810 ata_free_xfer(chp, xfer); 811 if (ata_c->flags & AT_WAIT) 812 wakeup(ata_c); 813 else if (ata_c->callback) 814 ata_c->callback(ata_c->callback_arg); 815 atastart(chp); 816 return; 817 } 818 819 int 820 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 821 { 822 struct ata_channel *chp = drvp->chnl_softc; 823 struct ata_xfer *xfer; 824 825 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 826 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 827 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 828 DEBUG_XFERS); 829 xfer = ata_get_xfer(ATAXF_NOSLEEP); 830 if (xfer == NULL) { 831 return ATACMD_TRY_AGAIN; 832 } 833 if (ata_bio->flags & ATA_POLL) 834 xfer->c_flags |= C_POLL; 835 xfer->c_drive = drvp->drive; 836 xfer->c_cmd = ata_bio; 837 xfer->c_databuf = ata_bio->databuf; 838 xfer->c_bcount = ata_bio->bcount; 839 xfer->c_start = ahci_bio_start; 840 xfer->c_intr = ahci_bio_complete; 841 xfer->c_kill_xfer = ahci_bio_kill_xfer; 842 ata_exec_xfer(chp, xfer); 843 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 844 } 845 846 void 847 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 848 { 849 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 850 struct ahci_channel *achp = (struct ahci_channel *)chp; 851 struct ata_bio *ata_bio = xfer->c_cmd; 852 int slot = 0 /* XXX slot */; 853 struct ahci_cmd_tbl *cmd_tbl; 854 struct ahci_cmd_header *cmd_h; 855 u_int8_t *fis; 856 int i, nblks; 857 int channel = chp->ch_channel; 858 859 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 860 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 861 862 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 863 864 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 865 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 866 cmd_tbl), DEBUG_XFERS); 867 fis = cmd_tbl->cmdt_cfis; 868 869 fis[0] = 0x27; /* host to device */ 870 fis[1] = 0x80; /* command FIS */ 871 if (ata_bio->flags & ATA_LBA48) { 872 fis[2] = (ata_bio->flags & ATA_READ) ? 873 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 874 } else { 875 fis[2] = 876 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 877 } 878 fis[3] = 0; /* features */ 879 fis[4] = ata_bio->blkno & 0xff; 880 fis[5] = (ata_bio->blkno >> 8) & 0xff; 881 fis[6] = (ata_bio->blkno >> 16) & 0xff; 882 if (ata_bio->flags & ATA_LBA48) { 883 fis[7] = WDSD_LBA; 884 fis[8] = (ata_bio->blkno >> 24) & 0xff; 885 fis[9] = (ata_bio->blkno >> 32) & 0xff; 886 fis[10] = (ata_bio->blkno >> 40) & 0xff; 887 } else { 888 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 889 fis[8] = 0; 890 fis[9] = 0; 891 fis[10] = 0; 892 } 893 fis[11] = 0; /* ext features */ 894 fis[12] = nblks & 0xff; 895 fis[13] = (ata_bio->flags & ATA_LBA48) ? 896 ((nblks >> 8) & 0xff) : 0; 897 fis[14] = 0; 898 fis[15] = WDCTL_4BIT; 899 fis[16] = 0; 900 fis[17] = 0; 901 fis[18] = 0; 902 fis[19] = 0; 903 904 cmd_h = &achp->ahcic_cmdh[slot]; 905 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 906 chp->ch_channel, cmd_h), DEBUG_XFERS); 907 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 908 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 909 ata_bio->error = ERR_DMA; 910 ata_bio->r_error = 0; 911 ahci_bio_complete(chp, xfer, slot); 912 return; 913 } 914 cmd_h->cmdh_flags = htole16( 915 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 916 20 /* fis lenght */ / 4); 917 cmd_h->cmdh_prdbc = 0; 918 AHCI_CMDH_SYNC(sc, achp, slot, 919 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 920 921 if (xfer->c_flags & C_POLL) { 922 /* polled command, disable interrupts */ 923 AHCI_WRITE(sc, AHCI_GHC, 924 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 925 } 926 chp->ch_flags |= ATACH_IRQ_WAIT; 927 chp->ch_status = 0; 928 /* start command */ 929 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 930 /* and says we started this command */ 931 achp->ahcic_cmds_active |= 1 << slot; 932 933 if ((xfer->c_flags & C_POLL) == 0) { 934 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 935 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 936 ahci_timeout, chp); 937 return; 938 } 939 /* 940 * Polled command. 941 */ 942 for (i = 0; i < ATA_DELAY / 10; i++) { 943 if (ata_bio->flags & ATA_ITSDONE) 944 break; 945 ahci_intr_port(sc, achp); 946 if (ata_bio->flags & ATA_NOSLEEP) 947 delay(10000); 948 else 949 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 950 } 951 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 952 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 953 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 954 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 955 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 956 DEBUG_XFERS); 957 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 958 ata_bio->error = TIMEOUT; 959 ahci_bio_complete(chp, xfer, slot); 960 } 961 /* reenable interrupts */ 962 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 963 } 964 965 void 966 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 967 { 968 int slot = 0; /* XXX slot */ 969 int drive = xfer->c_drive; 970 struct ata_bio *ata_bio = xfer->c_cmd; 971 struct ahci_channel *achp = (struct ahci_channel *)chp; 972 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 973 DEBUG_FUNCS); 974 975 achp->ahcic_cmds_active &= ~(1 << slot); 976 ata_free_xfer(chp, xfer); 977 ata_bio->flags |= ATA_ITSDONE; 978 switch (reason) { 979 case KILL_GONE: 980 ata_bio->error = ERR_NODEV; 981 break; 982 case KILL_RESET: 983 ata_bio->error = ERR_RESET; 984 break; 985 default: 986 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 987 panic("ahci_bio_kill_xfer"); 988 } 989 ata_bio->r_error = WDCE_ABRT; 990 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 991 } 992 993 int 994 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 995 { 996 int slot = 0; /* XXX slot */ 997 struct ata_bio *ata_bio = xfer->c_cmd; 998 int drive = xfer->c_drive; 999 struct ahci_channel *achp = (struct ahci_channel *)chp; 1000 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1001 1002 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1003 DEBUG_FUNCS); 1004 1005 achp->ahcic_cmds_active &= ~(1 << slot); 1006 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1007 if (xfer->c_flags & C_TIMEOU) { 1008 ata_bio->error = TIMEOUT; 1009 } else { 1010 callout_stop(&chp->ch_callout); 1011 ata_bio->error = 0; 1012 } 1013 1014 chp->ch_queue->active_xfer = NULL; 1015 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1016 achp->ahcic_datad[slot]->dm_mapsize, 1017 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1018 BUS_DMASYNC_POSTWRITE); 1019 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1020 1021 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1022 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1023 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1024 wakeup(&chp->ch_queue->active_xfer); 1025 return 0; 1026 } 1027 ata_free_xfer(chp, xfer); 1028 ata_bio->flags |= ATA_ITSDONE; 1029 if (chp->ch_status & WDCS_DWF) { 1030 ata_bio->error = ERR_DF; 1031 } else if (chp->ch_status & WDCS_ERR) { 1032 ata_bio->error = ERROR; 1033 ata_bio->r_error = chp->ch_error; 1034 } else if (chp->ch_status & WDCS_CORR) 1035 ata_bio->flags |= ATA_CORR; 1036 1037 AHCI_CMDH_SYNC(sc, achp, slot, 1038 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1039 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1040 ata_bio->bcount), DEBUG_XFERS); 1041 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1042 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1043 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1044 atastart(chp); 1045 return 0; 1046 } 1047 1048 void 1049 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1050 { 1051 int i; 1052 /* stop channel */ 1053 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1054 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1055 /* wait 1s for channel to stop */ 1056 for (i = 0; i <100; i++) { 1057 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1058 == 0) 1059 break; 1060 if (flags & AT_WAIT) 1061 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1062 else 1063 delay(10000); 1064 } 1065 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1066 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1067 /* XXX controller reset ? */ 1068 return; 1069 } 1070 } 1071 1072 void 1073 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1074 { 1075 /* clear error */ 1076 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1077 1078 /* and start controller */ 1079 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1080 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1081 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1082 } 1083 1084 void 1085 ahci_timeout(void *v) 1086 { 1087 struct ata_channel *chp = (struct ata_channel *)v; 1088 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1089 int s = splbio(); 1090 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1091 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1092 xfer->c_flags |= C_TIMEOU; 1093 xfer->c_intr(chp, xfer, 0); 1094 } 1095 splx(s); 1096 } 1097 1098 int 1099 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1100 size_t count, int op) 1101 { 1102 int error, seg; 1103 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1104 struct ahci_channel *achp = (struct ahci_channel *)chp; 1105 struct ahci_cmd_tbl *cmd_tbl; 1106 struct ahci_cmd_header *cmd_h; 1107 1108 cmd_h = &achp->ahcic_cmdh[slot]; 1109 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1110 1111 if (data == NULL) { 1112 cmd_h->cmdh_prdtl = 0; 1113 goto end; 1114 } 1115 1116 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1117 data, count, NULL, 1118 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1119 if (error) { 1120 printf("%s port %d: failed to load xfer: %d\n", 1121 AHCINAME(sc), chp->ch_channel, error); 1122 return error; 1123 } 1124 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1125 achp->ahcic_datad[slot]->dm_mapsize, 1126 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1127 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1128 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1129 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1130 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1131 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1132 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1133 } 1134 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1135 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1136 end: 1137 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1138 return 0; 1139 } 1140
Indexes created Fri Oct 17 00:09:41 GMT 2025