ahcisata_core.c revision 1.40
1 /* $NetBSD: ahcisata_core.c,v 1.40 2012/07/31 15:50:34 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.40 2012/07/31 15:50:34 bouyer Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #define AHCI_DEBUG 54 #ifdef AHCI_DEBUG 55 int ahcidebug_mask = 0; 56 #endif 57 58 static void ahci_probe_drive(struct ata_channel *); 59 static void ahci_setup_channel(struct ata_channel *); 60 61 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 62 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 73 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 75 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 76 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 77 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 78 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 79 int, int); 80 static void ahci_timeout(void *); 81 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 82 83 #if NATAPIBUS > 0 84 static void ahci_atapibus_attach(struct atabus_softc *); 85 static void ahci_atapi_kill_pending(struct scsipi_periph *); 86 static void ahci_atapi_minphys(struct buf *); 87 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 88 scsipi_adapter_req_t, void *); 89 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 90 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 92 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 93 94 static const struct scsipi_bustype ahci_atapi_bustype = { 95 SCSIPI_BUSTYPE_ATAPI, 96 atapi_scsipi_cmd, 97 atapi_interpret_sense, 98 atapi_print_addr, 99 ahci_atapi_kill_pending, 100 NULL, 101 }; 102 #endif /* NATAPIBUS */ 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 106 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 107 108 const struct ata_bustype ahci_ata_bustype = { 109 SCSIPI_BUSTYPE_ATA, 110 ahci_ata_bio, 111 ahci_reset_drive, 112 ahci_reset_channel, 113 ahci_exec_command, 114 ata_get_params, 115 ahci_ata_addref, 116 ahci_ata_delref, 117 ahci_killpending 118 }; 119 120 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 121 static void ahci_setup_port(struct ahci_softc *sc, int i); 122 123 static int 124 ahci_reset(struct ahci_softc *sc) 125 { 126 int i; 127 128 /* reset controller */ 129 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 130 /* wait up to 1s for reset to complete */ 131 for (i = 0; i < 1000; i++) { 132 delay(1000); 133 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 134 break; 135 } 136 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 137 aprint_error("%s: reset failed\n", AHCINAME(sc)); 138 return -1; 139 } 140 /* enable ahci mode */ 141 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 142 return 0; 143 } 144 145 static void 146 ahci_setup_ports(struct ahci_softc *sc) 147 { 148 uint32_t ahci_ports; 149 int i, port; 150 151 ahci_ports = AHCI_READ(sc, AHCI_PI); 152 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 153 if ((ahci_ports & (1 << i)) == 0) 154 continue; 155 if (port >= sc->sc_atac.atac_nchannels) { 156 aprint_error("%s: more ports than announced\n", 157 AHCINAME(sc)); 158 break; 159 } 160 ahci_setup_port(sc, i); 161 } 162 } 163 164 static void 165 ahci_reprobe_drives(struct ahci_softc *sc) 166 { 167 uint32_t ahci_ports; 168 int i, port; 169 struct ahci_channel *achp; 170 struct ata_channel *chp; 171 172 ahci_ports = AHCI_READ(sc, AHCI_PI); 173 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 174 if ((ahci_ports & (1 << i)) == 0) 175 continue; 176 if (port >= sc->sc_atac.atac_nchannels) { 177 aprint_error("%s: more ports than announced\n", 178 AHCINAME(sc)); 179 break; 180 } 181 achp = &sc->sc_channels[i]; 182 chp = &achp->ata_channel; 183 184 ahci_probe_drive(chp); 185 } 186 } 187 188 static void 189 ahci_setup_port(struct ahci_softc *sc, int i) 190 { 191 struct ahci_channel *achp; 192 193 achp = &sc->sc_channels[i]; 194 195 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 196 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 197 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 198 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 199 } 200 201 static void 202 ahci_enable_intrs(struct ahci_softc *sc) 203 { 204 205 /* clear interrupts */ 206 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 207 /* enable interrupts */ 208 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 209 } 210 211 void 212 ahci_attach(struct ahci_softc *sc) 213 { 214 uint32_t ahci_rev, ahci_ports; 215 int i, j, port; 216 struct ahci_channel *achp; 217 struct ata_channel *chp; 218 int error; 219 int dmasize; 220 char buf[128]; 221 void *cmdhp; 222 void *cmdtblp; 223 224 if (ahci_reset(sc) != 0) 225 return; 226 227 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 228 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 229 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 230 ahci_rev = AHCI_READ(sc, AHCI_VS); 231 snprintb(buf, sizeof(buf), "\177\020" 232 /* "f\000\005NP\0" */ 233 "b\005SXS\0" 234 "b\006EMS\0" 235 "b\007CCCS\0" 236 /* "f\010\005NCS\0" */ 237 "b\015PSC\0" 238 "b\016SSC\0" 239 "b\017PMD\0" 240 "b\020FBSS\0" 241 "b\021SPM\0" 242 "b\022SAM\0" 243 "b\023SNZO\0" 244 "f\024\003ISS\0" 245 "=\001Gen1\0" 246 "=\002Gen2\0" 247 "=\003Gen3\0" 248 "b\030SCLO\0" 249 "b\031SAL\0" 250 "b\032SALP\0" 251 "b\033SSS\0" 252 "b\034SMPS\0" 253 "b\035SSNTF\0" 254 "b\036SNCQ\0" 255 "b\037S64A\0" 256 "\0", sc->sc_ahci_cap); 257 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 258 ", %d ports, %d slots, CAP %s\n", 259 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 260 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 261 262 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 263 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 264 sc->sc_atac.atac_pio_cap = 4; 265 sc->sc_atac.atac_dma_cap = 2; 266 sc->sc_atac.atac_udma_cap = 6; 267 sc->sc_atac.atac_channels = sc->sc_chanarray; 268 sc->sc_atac.atac_probe = ahci_probe_drive; 269 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 270 sc->sc_atac.atac_set_modes = ahci_setup_channel; 271 #if NATAPIBUS > 0 272 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 273 #endif 274 275 dmasize = 276 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 277 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 278 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 279 if (error) { 280 aprint_error("%s: unable to allocate command header memory" 281 ", error=%d\n", AHCINAME(sc), error); 282 return; 283 } 284 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 285 sc->sc_cmd_hdr_nseg, dmasize, 286 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 287 if (error) { 288 aprint_error("%s: unable to map command header memory" 289 ", error=%d\n", AHCINAME(sc), error); 290 return; 291 } 292 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 293 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 294 if (error) { 295 aprint_error("%s: unable to create command header map" 296 ", error=%d\n", AHCINAME(sc), error); 297 return; 298 } 299 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 300 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 301 if (error) { 302 aprint_error("%s: unable to load command header map" 303 ", error=%d\n", AHCINAME(sc), error); 304 return; 305 } 306 sc->sc_cmd_hdr = cmdhp; 307 308 ahci_enable_intrs(sc); 309 310 ahci_ports = AHCI_READ(sc, AHCI_PI); 311 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 312 if ((ahci_ports & (1 << i)) == 0) 313 continue; 314 if (port >= sc->sc_atac.atac_nchannels) { 315 aprint_error("%s: more ports than announced\n", 316 AHCINAME(sc)); 317 break; 318 } 319 achp = &sc->sc_channels[i]; 320 chp = &achp->ata_channel; 321 sc->sc_chanarray[i] = chp; 322 chp->ch_channel = i; 323 chp->ch_atac = &sc->sc_atac; 324 chp->ch_queue = malloc(sizeof(struct ata_queue), 325 M_DEVBUF, M_NOWAIT); 326 if (chp->ch_queue == NULL) { 327 aprint_error("%s port %d: can't allocate memory for " 328 "command queue", AHCINAME(sc), i); 329 break; 330 } 331 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 332 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 333 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 334 BUS_DMA_NOWAIT); 335 if (error) { 336 aprint_error("%s: unable to allocate command table " 337 "memory, error=%d\n", AHCINAME(sc), error); 338 break; 339 } 340 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 341 achp->ahcic_cmd_tbl_nseg, dmasize, 342 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 343 if (error) { 344 aprint_error("%s: unable to map command table memory" 345 ", error=%d\n", AHCINAME(sc), error); 346 break; 347 } 348 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 349 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 350 if (error) { 351 aprint_error("%s: unable to create command table map" 352 ", error=%d\n", AHCINAME(sc), error); 353 break; 354 } 355 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 356 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 357 if (error) { 358 aprint_error("%s: unable to load command table map" 359 ", error=%d\n", AHCINAME(sc), error); 360 break; 361 } 362 achp->ahcic_cmdh = (struct ahci_cmd_header *) 363 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 364 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 365 AHCI_CMDH_SIZE * port; 366 achp->ahcic_rfis = (struct ahci_r_fis *) 367 ((char *)cmdhp + 368 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 369 AHCI_RFIS_SIZE * port); 370 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 371 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 372 AHCI_RFIS_SIZE * port; 373 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 374 "rfis %p (0x%" PRIx64 ")\n", i, 375 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 376 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 377 DEBUG_PROBE); 378 379 for (j = 0; j < sc->sc_ncmds; j++) { 380 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 381 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 382 achp->ahcic_bus_cmd_tbl[j] = 383 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 384 AHCI_CMDTBL_SIZE * j; 385 achp->ahcic_cmdh[j].cmdh_cmdtba = 386 htole64(achp->ahcic_bus_cmd_tbl[j]); 387 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 388 achp->ahcic_cmd_tbl[j], 389 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 390 /* The xfer DMA map */ 391 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 392 AHCI_NPRD, 0x400000 /* 4MB */, 0, 393 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 394 &achp->ahcic_datad[j]); 395 if (error) { 396 aprint_error("%s: couldn't alloc xfer DMA map, " 397 "error=%d\n", AHCINAME(sc), error); 398 goto end; 399 } 400 } 401 ahci_setup_port(sc, i); 402 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 403 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 404 aprint_error("%s: couldn't map channel %d " 405 "sata_status regs\n", AHCINAME(sc), i); 406 break; 407 } 408 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 409 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 410 aprint_error("%s: couldn't map channel %d " 411 "sata_control regs\n", AHCINAME(sc), i); 412 break; 413 } 414 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 415 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 416 aprint_error("%s: couldn't map channel %d " 417 "sata_error regs\n", AHCINAME(sc), i); 418 break; 419 } 420 ata_channel_attach(chp); 421 port++; 422 end: 423 continue; 424 } 425 } 426 427 int 428 ahci_detach(struct ahci_softc *sc, int flags) 429 { 430 struct atac_softc *atac; 431 struct ahci_channel *achp; 432 struct ata_channel *chp; 433 struct scsipi_adapter *adapt; 434 uint32_t ahci_ports; 435 int i, j; 436 int error; 437 438 atac = &sc->sc_atac; 439 adapt = &atac->atac_atapi_adapter._generic; 440 441 ahci_ports = AHCI_READ(sc, AHCI_PI); 442 for (i = 0; i < AHCI_MAX_PORTS; i++) { 443 achp = &sc->sc_channels[i]; 444 chp = &achp->ata_channel; 445 446 if ((ahci_ports & (1 << i)) == 0) 447 continue; 448 if (i >= sc->sc_atac.atac_nchannels) { 449 aprint_error("%s: more ports than announced\n", 450 AHCINAME(sc)); 451 break; 452 } 453 454 if (chp->atabus == NULL) 455 continue; 456 if ((error = config_detach(chp->atabus, flags)) != 0) 457 return error; 458 459 for (j = 0; j < sc->sc_ncmds; j++) 460 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 461 462 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 463 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 464 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 465 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 466 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 467 achp->ahcic_cmd_tbl_nseg); 468 469 free(chp->ch_queue, M_DEVBUF); 470 chp->atabus = NULL; 471 } 472 473 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 474 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 475 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 476 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 477 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 478 479 if (adapt->adapt_refcnt != 0) 480 return EBUSY; 481 482 return 0; 483 } 484 485 void 486 ahci_resume(struct ahci_softc *sc) 487 { 488 ahci_reset(sc); 489 ahci_setup_ports(sc); 490 ahci_reprobe_drives(sc); 491 ahci_enable_intrs(sc); 492 } 493 494 int 495 ahci_intr(void *v) 496 { 497 struct ahci_softc *sc = v; 498 uint32_t is; 499 int i, r = 0; 500 501 while ((is = AHCI_READ(sc, AHCI_IS))) { 502 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 503 DEBUG_INTR); 504 r = 1; 505 AHCI_WRITE(sc, AHCI_IS, is); 506 for (i = 0; i < AHCI_MAX_PORTS; i++) 507 if (is & (1 << i)) 508 ahci_intr_port(sc, &sc->sc_channels[i]); 509 } 510 return r; 511 } 512 513 static void 514 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 515 { 516 uint32_t is, tfd; 517 struct ata_channel *chp = &achp->ata_channel; 518 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 519 int slot; 520 521 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 522 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 523 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 524 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 525 DEBUG_INTR); 526 527 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 528 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 529 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 530 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 531 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 532 return; 533 /* stop channel */ 534 ahci_channel_stop(sc, chp, 0); 535 if (slot != 0) { 536 printf("ahci_intr_port: slot %d\n", slot); 537 panic("ahci_intr_port"); 538 } 539 if (is & AHCI_P_IX_TFES) { 540 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 541 chp->ch_error = 542 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 543 chp->ch_status = (tfd & 0xff); 544 } else { 545 /* emulate a CRC error */ 546 chp->ch_error = WDCE_CRC; 547 chp->ch_status = WDCS_ERR; 548 } 549 if (is & AHCI_P_IX_IFS) { 550 aprint_error("%s port %d: SERR 0x%x\n", 551 AHCINAME(sc), chp->ch_channel, 552 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 553 } 554 xfer->c_intr(chp, xfer, is); 555 /* if channel has not been restarted, do it now */ 556 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 557 == 0) 558 ahci_channel_start(sc, chp, 0, 0); 559 } else { 560 slot = 0; /* XXX */ 561 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 562 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 563 chp->ch_channel, is, achp->ahcic_cmds_active, 564 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 565 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 566 return; 567 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 568 == 0) { 569 xfer->c_intr(chp, xfer, 0); 570 } 571 } 572 } 573 574 static void 575 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 576 { 577 struct ata_channel *chp = drvp->chnl_softc; 578 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 579 AHCI_WRITE(sc, AHCI_GHC, 580 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 581 ahci_channel_stop(sc, chp, flags); 582 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 583 ata_reset_channel(chp, flags); 584 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 585 return; 586 } 587 588 /* return error code from ata_bio */ 589 static int 590 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 591 { 592 struct ahci_channel *achp = (struct ahci_channel *)chp; 593 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 594 int i; 595 uint32_t is; 596 597 timeout = timeout * 10; /* wait is 10ms */ 598 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 599 /* start command */ 600 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 601 for (i = 0; i < timeout; i++) { 602 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 603 return 0; 604 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 605 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 606 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 607 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 608 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 609 /* 610 * we got the D2H FIS anyway, 611 * assume sig is valid. 612 * channel is restarted later 613 */ 614 return ERROR; 615 } 616 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 617 AHCINAME(sc), chp->ch_channel, is); 618 return ERR_DF; 619 } 620 if (flags & AT_WAIT) 621 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 622 else 623 delay(10000); 624 } 625 aprint_debug("%s channel %d: timeout sending FIS\n", 626 AHCINAME(sc), chp->ch_channel); 627 return TIMEOUT; 628 } 629 630 static int 631 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 632 uint32_t *sigp) 633 { 634 struct ahci_channel *achp = (struct ahci_channel *)chp; 635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 636 struct ahci_cmd_tbl *cmd_tbl; 637 struct ahci_cmd_header *cmd_h; 638 int i; 639 uint32_t sig; 640 641 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 642 /* clear port interrupt register */ 643 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 644 /* clear SErrors and start operations */ 645 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 646 /* 647 * issue a command list override to clear BSY. 648 * This is needed if there's a PMP with no drive 649 * on port 0 650 */ 651 ahci_channel_start(sc, chp, flags, 1); 652 } else { 653 ahci_channel_start(sc, chp, flags, 0); 654 } 655 if (drive > 0) { 656 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 657 } 658 /* polled command, assume interrupts are disabled */ 659 /* use slot 0 to send reset, the channel is idle */ 660 cmd_h = &achp->ahcic_cmdh[0]; 661 cmd_tbl = achp->ahcic_cmd_tbl[0]; 662 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 663 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 664 cmd_h->cmdh_prdbc = 0; 665 memset(cmd_tbl->cmdt_cfis, 0, 64); 666 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 667 cmd_tbl->cmdt_cfis[rhd_c] = drive; 668 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 669 switch(ahci_exec_fis(chp, 1, flags)) { 670 case ERR_DF: 671 case TIMEOUT: 672 aprint_error("%s channel %d: setting WDCTL_RST failed " 673 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 674 if (sigp) 675 *sigp = 0xffffffff; 676 goto end; 677 default: 678 break; 679 } 680 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 681 (drive << AHCI_CMDH_F_PMP_SHIFT)); 682 cmd_h->cmdh_prdbc = 0; 683 memset(cmd_tbl->cmdt_cfis, 0, 64); 684 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 685 cmd_tbl->cmdt_cfis[rhd_c] = drive; 686 cmd_tbl->cmdt_cfis[rhd_control] = 0; 687 switch(ahci_exec_fis(chp, 31, flags)) { 688 case ERR_DF: 689 case TIMEOUT: 690 aprint_error("%s channel %d: clearing WDCTL_RST failed " 691 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 692 if (sigp) 693 *sigp = 0xffffffff; 694 goto end; 695 default: 696 break; 697 } 698 /* 699 * wait 31s for BSY to clear 700 * This should not be needed, but some controllers clear the 701 * command slot before receiving the D2H FIS ... 702 */ 703 for (i = 0; i <AHCI_RST_WAIT; i++) { 704 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 705 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 706 & WDCS_BSY) == 0) 707 break; 708 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 709 } 710 if (i == AHCI_RST_WAIT) { 711 aprint_error("%s: BSY never cleared, TD 0x%x\n", 712 AHCINAME(sc), sig); 713 if (sigp) 714 *sigp = 0xffffffff; 715 goto end; 716 } 717 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 718 DEBUG_PROBE); 719 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 720 if (sigp) 721 *sigp = sig; 722 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 723 AHCINAME(sc), chp->ch_channel, sig, 724 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 725 end: 726 ahci_channel_stop(sc, chp, flags); 727 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 728 /* clear port interrupt register */ 729 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 730 ahci_channel_start(sc, chp, AT_WAIT, 731 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 732 return 0; 733 } 734 735 static void 736 ahci_reset_channel(struct ata_channel *chp, int flags) 737 { 738 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 739 struct ahci_channel *achp = (struct ahci_channel *)chp; 740 int i, tfd; 741 742 ahci_channel_stop(sc, chp, flags); 743 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 744 achp->ahcic_sstatus) != SStatus_DET_DEV) { 745 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 746 /* XXX and then ? */ 747 } 748 if (chp->ch_queue->active_xfer) { 749 chp->ch_queue->active_xfer->c_kill_xfer(chp, 750 chp->ch_queue->active_xfer, KILL_RESET); 751 } 752 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 753 /* clear port interrupt register */ 754 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 755 /* clear SErrors and start operations */ 756 ahci_channel_start(sc, chp, flags, 1); 757 /* wait 31s for BSY to clear */ 758 for (i = 0; i <AHCI_RST_WAIT; i++) { 759 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 760 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 761 & WDCS_BSY) == 0) 762 break; 763 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 764 } 765 if (i == AHCI_RST_WAIT) 766 aprint_error("%s: BSY never cleared, TD 0x%x\n", 767 AHCINAME(sc), tfd); 768 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 769 DEBUG_PROBE); 770 /* clear port interrupt register */ 771 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 772 773 return; 774 } 775 776 static int 777 ahci_ata_addref(struct ata_drive_datas *drvp) 778 { 779 return 0; 780 } 781 782 static void 783 ahci_ata_delref(struct ata_drive_datas *drvp) 784 { 785 return; 786 } 787 788 static void 789 ahci_killpending(struct ata_drive_datas *drvp) 790 { 791 return; 792 } 793 794 static void 795 ahci_probe_drive(struct ata_channel *chp) 796 { 797 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 798 struct ahci_channel *achp = (struct ahci_channel *)chp; 799 uint32_t sig; 800 801 /* bring interface up, accept FISs, power up and spin up device */ 802 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 803 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 804 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 805 /* reset the PHY and bring online */ 806 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 807 achp->ahcic_sstatus)) { 808 case SStatus_DET_DEV: 809 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 810 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 811 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 812 } else { 813 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 814 } 815 sata_interpret_sig(chp, 0, sig); 816 /* if we have a PMP attached, inform the controller */ 817 if (chp->ch_ndrives > PMP_PORT_CTL && 818 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 819 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 820 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 821 AHCI_P_CMD_PMA); 822 } 823 /* clear port interrupt register */ 824 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 825 /* and enable interrupts */ 826 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 827 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 828 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 829 AHCI_P_IX_DHRS); 830 /* wait 500ms before actually starting operations */ 831 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 832 break; 833 834 default: 835 break; 836 } 837 } 838 839 static void 840 ahci_setup_channel(struct ata_channel *chp) 841 { 842 return; 843 } 844 845 static int 846 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 847 { 848 struct ata_channel *chp = drvp->chnl_softc; 849 struct ata_xfer *xfer; 850 int ret; 851 int s; 852 853 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 854 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 855 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 856 DEBUG_XFERS); 857 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 858 ATAXF_NOSLEEP); 859 if (xfer == NULL) { 860 return ATACMD_TRY_AGAIN; 861 } 862 if (ata_c->flags & AT_POLL) 863 xfer->c_flags |= C_POLL; 864 if (ata_c->flags & AT_WAIT) 865 xfer->c_flags |= C_WAIT; 866 xfer->c_drive = drvp->drive; 867 xfer->c_databuf = ata_c->data; 868 xfer->c_bcount = ata_c->bcount; 869 xfer->c_cmd = ata_c; 870 xfer->c_start = ahci_cmd_start; 871 xfer->c_intr = ahci_cmd_complete; 872 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 873 s = splbio(); 874 ata_exec_xfer(chp, xfer); 875 #ifdef DIAGNOSTIC 876 if ((ata_c->flags & AT_POLL) != 0 && 877 (ata_c->flags & AT_DONE) == 0) 878 panic("ahci_exec_command: polled command not done"); 879 #endif 880 if (ata_c->flags & AT_DONE) { 881 ret = ATACMD_COMPLETE; 882 } else { 883 if (ata_c->flags & AT_WAIT) { 884 while ((ata_c->flags & AT_DONE) == 0) { 885 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 886 } 887 ret = ATACMD_COMPLETE; 888 } else { 889 ret = ATACMD_QUEUED; 890 } 891 } 892 splx(s); 893 return ret; 894 } 895 896 static void 897 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 898 { 899 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 900 struct ahci_channel *achp = (struct ahci_channel *)chp; 901 struct ata_command *ata_c = xfer->c_cmd; 902 int slot = 0 /* XXX slot */; 903 struct ahci_cmd_tbl *cmd_tbl; 904 struct ahci_cmd_header *cmd_h; 905 int i; 906 int channel = chp->ch_channel; 907 908 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 909 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 910 911 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 912 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 913 cmd_tbl), DEBUG_XFERS); 914 915 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 916 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 917 918 cmd_h = &achp->ahcic_cmdh[slot]; 919 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 920 chp->ch_channel, cmd_h), DEBUG_XFERS); 921 if (ahci_dma_setup(chp, slot, 922 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 923 ata_c->data : NULL, 924 ata_c->bcount, 925 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 926 ata_c->flags |= AT_DF; 927 ahci_cmd_complete(chp, xfer, slot); 928 return; 929 } 930 cmd_h->cmdh_flags = htole16( 931 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 932 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 933 cmd_h->cmdh_prdbc = 0; 934 AHCI_CMDH_SYNC(sc, achp, slot, 935 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 936 937 if (ata_c->flags & AT_POLL) { 938 /* polled command, disable interrupts */ 939 AHCI_WRITE(sc, AHCI_GHC, 940 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 941 } 942 chp->ch_flags |= ATACH_IRQ_WAIT; 943 chp->ch_status = 0; 944 /* start command */ 945 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 946 /* and says we started this command */ 947 achp->ahcic_cmds_active |= 1 << slot; 948 949 if ((ata_c->flags & AT_POLL) == 0) { 950 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 951 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 952 ahci_timeout, chp); 953 return; 954 } 955 /* 956 * Polled command. 957 */ 958 for (i = 0; i < ata_c->timeout / 10; i++) { 959 if (ata_c->flags & AT_DONE) 960 break; 961 ahci_intr_port(sc, achp); 962 if (ata_c->flags & AT_WAIT) 963 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 964 else 965 delay(10000); 966 } 967 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 968 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 969 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 970 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 971 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 972 DEBUG_XFERS); 973 if ((ata_c->flags & AT_DONE) == 0) { 974 ata_c->flags |= AT_TIMEOU; 975 ahci_cmd_complete(chp, xfer, slot); 976 } 977 /* reenable interrupts */ 978 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 979 } 980 981 static void 982 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 983 { 984 struct ata_command *ata_c = xfer->c_cmd; 985 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 986 DEBUG_FUNCS); 987 988 switch (reason) { 989 case KILL_GONE: 990 ata_c->flags |= AT_GONE; 991 break; 992 case KILL_RESET: 993 ata_c->flags |= AT_RESET; 994 break; 995 default: 996 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 997 panic("ahci_cmd_kill_xfer"); 998 } 999 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1000 } 1001 1002 static int 1003 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1004 { 1005 int slot = 0; /* XXX slot */ 1006 struct ata_command *ata_c = xfer->c_cmd; 1007 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1008 struct ahci_channel *achp = (struct ahci_channel *)chp; 1009 1010 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1011 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1012 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1013 DEBUG_FUNCS); 1014 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1015 if (xfer->c_flags & C_TIMEOU) { 1016 ata_c->flags |= AT_TIMEOU; 1017 } else 1018 callout_stop(&chp->ch_callout); 1019 1020 chp->ch_queue->active_xfer = NULL; 1021 1022 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1023 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1024 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1025 wakeup(&chp->ch_queue->active_xfer); 1026 return 0; 1027 } 1028 1029 if (chp->ch_status & WDCS_BSY) { 1030 ata_c->flags |= AT_TIMEOU; 1031 } else if (chp->ch_status & WDCS_ERR) { 1032 ata_c->r_error = chp->ch_error; 1033 ata_c->flags |= AT_ERROR; 1034 } 1035 1036 if (ata_c->flags & AT_READREG) 1037 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1038 1039 ahci_cmd_done(chp, xfer, slot); 1040 return 0; 1041 } 1042 1043 static void 1044 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1045 { 1046 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1047 struct ahci_channel *achp = (struct ahci_channel *)chp; 1048 struct ata_command *ata_c = xfer->c_cmd; 1049 uint16_t *idwordbuf; 1050 int i; 1051 1052 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 1053 DEBUG_FUNCS); 1054 1055 /* this comamnd is not active any more */ 1056 achp->ahcic_cmds_active &= ~(1 << slot); 1057 1058 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1059 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1060 achp->ahcic_datad[slot]->dm_mapsize, 1061 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1062 BUS_DMASYNC_POSTWRITE); 1063 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1064 } 1065 1066 AHCI_CMDH_SYNC(sc, achp, slot, 1067 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1068 1069 /* ata(4) expects IDENTIFY data to be in host endianess */ 1070 if (ata_c->r_command == WDCC_IDENTIFY || 1071 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1072 idwordbuf = xfer->c_databuf; 1073 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1074 idwordbuf[i] = le16toh(idwordbuf[i]); 1075 } 1076 } 1077 1078 ata_c->flags |= AT_DONE; 1079 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1080 ata_c->flags |= AT_XFDONE; 1081 1082 ata_free_xfer(chp, xfer); 1083 if (ata_c->flags & AT_WAIT) 1084 wakeup(ata_c); 1085 else if (ata_c->callback) 1086 ata_c->callback(ata_c->callback_arg); 1087 atastart(chp); 1088 return; 1089 } 1090 1091 static int 1092 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1093 { 1094 struct ata_channel *chp = drvp->chnl_softc; 1095 struct ata_xfer *xfer; 1096 1097 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1098 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1099 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1100 DEBUG_XFERS); 1101 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1102 if (xfer == NULL) { 1103 return ATACMD_TRY_AGAIN; 1104 } 1105 if (ata_bio->flags & ATA_POLL) 1106 xfer->c_flags |= C_POLL; 1107 xfer->c_drive = drvp->drive; 1108 xfer->c_cmd = ata_bio; 1109 xfer->c_databuf = ata_bio->databuf; 1110 xfer->c_bcount = ata_bio->bcount; 1111 xfer->c_start = ahci_bio_start; 1112 xfer->c_intr = ahci_bio_complete; 1113 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1114 ata_exec_xfer(chp, xfer); 1115 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1116 } 1117 1118 static void 1119 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1120 { 1121 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1122 struct ahci_channel *achp = (struct ahci_channel *)chp; 1123 struct ata_bio *ata_bio = xfer->c_cmd; 1124 int slot = 0 /* XXX slot */; 1125 struct ahci_cmd_tbl *cmd_tbl; 1126 struct ahci_cmd_header *cmd_h; 1127 int i; 1128 int channel = chp->ch_channel; 1129 1130 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1131 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1132 1133 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1134 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1135 cmd_tbl), DEBUG_XFERS); 1136 1137 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1138 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1139 1140 cmd_h = &achp->ahcic_cmdh[slot]; 1141 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1142 chp->ch_channel, cmd_h), DEBUG_XFERS); 1143 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1144 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1145 ata_bio->error = ERR_DMA; 1146 ata_bio->r_error = 0; 1147 ahci_bio_complete(chp, xfer, slot); 1148 return; 1149 } 1150 cmd_h->cmdh_flags = htole16( 1151 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1152 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1153 cmd_h->cmdh_prdbc = 0; 1154 AHCI_CMDH_SYNC(sc, achp, slot, 1155 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1156 1157 if (xfer->c_flags & C_POLL) { 1158 /* polled command, disable interrupts */ 1159 AHCI_WRITE(sc, AHCI_GHC, 1160 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1161 } 1162 chp->ch_flags |= ATACH_IRQ_WAIT; 1163 chp->ch_status = 0; 1164 /* start command */ 1165 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1166 /* and says we started this command */ 1167 achp->ahcic_cmds_active |= 1 << slot; 1168 1169 if ((xfer->c_flags & C_POLL) == 0) { 1170 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1171 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1172 ahci_timeout, chp); 1173 return; 1174 } 1175 /* 1176 * Polled command. 1177 */ 1178 for (i = 0; i < ATA_DELAY / 10; i++) { 1179 if (ata_bio->flags & ATA_ITSDONE) 1180 break; 1181 ahci_intr_port(sc, achp); 1182 if (ata_bio->flags & ATA_NOSLEEP) 1183 delay(10000); 1184 else 1185 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1186 } 1187 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1188 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1189 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1190 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1191 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1192 DEBUG_XFERS); 1193 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1194 ata_bio->error = TIMEOUT; 1195 ahci_bio_complete(chp, xfer, slot); 1196 } 1197 /* reenable interrupts */ 1198 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1199 } 1200 1201 static void 1202 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1203 { 1204 int slot = 0; /* XXX slot */ 1205 int drive = xfer->c_drive; 1206 struct ata_bio *ata_bio = xfer->c_cmd; 1207 struct ahci_channel *achp = (struct ahci_channel *)chp; 1208 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1209 DEBUG_FUNCS); 1210 1211 achp->ahcic_cmds_active &= ~(1 << slot); 1212 ata_free_xfer(chp, xfer); 1213 ata_bio->flags |= ATA_ITSDONE; 1214 switch (reason) { 1215 case KILL_GONE: 1216 ata_bio->error = ERR_NODEV; 1217 break; 1218 case KILL_RESET: 1219 ata_bio->error = ERR_RESET; 1220 break; 1221 default: 1222 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1223 panic("ahci_bio_kill_xfer"); 1224 } 1225 ata_bio->r_error = WDCE_ABRT; 1226 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1227 } 1228 1229 static int 1230 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1231 { 1232 int slot = 0; /* XXX slot */ 1233 struct ata_bio *ata_bio = xfer->c_cmd; 1234 int drive = xfer->c_drive; 1235 struct ahci_channel *achp = (struct ahci_channel *)chp; 1236 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1237 1238 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1239 DEBUG_FUNCS); 1240 1241 achp->ahcic_cmds_active &= ~(1 << slot); 1242 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1243 if (xfer->c_flags & C_TIMEOU) { 1244 ata_bio->error = TIMEOUT; 1245 } else { 1246 callout_stop(&chp->ch_callout); 1247 ata_bio->error = NOERROR; 1248 } 1249 1250 chp->ch_queue->active_xfer = NULL; 1251 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1252 achp->ahcic_datad[slot]->dm_mapsize, 1253 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1254 BUS_DMASYNC_POSTWRITE); 1255 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1256 1257 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1258 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1259 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1260 wakeup(&chp->ch_queue->active_xfer); 1261 return 0; 1262 } 1263 ata_free_xfer(chp, xfer); 1264 ata_bio->flags |= ATA_ITSDONE; 1265 if (chp->ch_status & WDCS_DWF) { 1266 ata_bio->error = ERR_DF; 1267 } else if (chp->ch_status & WDCS_ERR) { 1268 ata_bio->error = ERROR; 1269 ata_bio->r_error = chp->ch_error; 1270 } else if (chp->ch_status & WDCS_CORR) 1271 ata_bio->flags |= ATA_CORR; 1272 1273 AHCI_CMDH_SYNC(sc, achp, slot, 1274 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1275 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1276 ata_bio->bcount), DEBUG_XFERS); 1277 /* 1278 * if it was a write, complete data buffer may have been transfered 1279 * before error detection; in this case don't use cmdh_prdbc 1280 * as it won't reflect what was written to media. Assume nothing 1281 * was transfered and leave bcount as-is. 1282 */ 1283 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1284 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1285 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1286 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1287 atastart(chp); 1288 return 0; 1289 } 1290 1291 static void 1292 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1293 { 1294 int i; 1295 /* stop channel */ 1296 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1297 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1298 /* wait 1s for channel to stop */ 1299 for (i = 0; i <100; i++) { 1300 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1301 == 0) 1302 break; 1303 if (flags & AT_WAIT) 1304 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1305 else 1306 delay(10000); 1307 } 1308 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1309 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1310 /* XXX controller reset ? */ 1311 return; 1312 } 1313 } 1314 1315 static void 1316 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1317 int flags, int clo) 1318 { 1319 int i; 1320 uint32_t p_cmd; 1321 /* clear error */ 1322 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1323 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1324 1325 if (clo) { 1326 /* issue command list override */ 1327 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1328 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1329 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1330 /* wait 1s for AHCI_CAP_CLO to clear */ 1331 for (i = 0; i <100; i++) { 1332 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1333 AHCI_P_CMD_CLO) == 0) 1334 break; 1335 if (flags & AT_WAIT) 1336 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1337 else 1338 delay(10000); 1339 } 1340 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1341 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1342 /* XXX controller reset ? */ 1343 return; 1344 } 1345 } 1346 /* and start controller */ 1347 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1348 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1349 if (chp->ch_ndrives > PMP_PORT_CTL && 1350 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1351 p_cmd |= AHCI_P_CMD_PMA; 1352 } 1353 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1354 } 1355 1356 static void 1357 ahci_timeout(void *v) 1358 { 1359 struct ata_channel *chp = (struct ata_channel *)v; 1360 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1361 int s = splbio(); 1362 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1363 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1364 xfer->c_flags |= C_TIMEOU; 1365 xfer->c_intr(chp, xfer, 0); 1366 } 1367 splx(s); 1368 } 1369 1370 static int 1371 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1372 size_t count, int op) 1373 { 1374 int error, seg; 1375 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1376 struct ahci_channel *achp = (struct ahci_channel *)chp; 1377 struct ahci_cmd_tbl *cmd_tbl; 1378 struct ahci_cmd_header *cmd_h; 1379 1380 cmd_h = &achp->ahcic_cmdh[slot]; 1381 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1382 1383 if (data == NULL) { 1384 cmd_h->cmdh_prdtl = 0; 1385 goto end; 1386 } 1387 1388 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1389 data, count, NULL, 1390 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1391 if (error) { 1392 printf("%s port %d: failed to load xfer: %d\n", 1393 AHCINAME(sc), chp->ch_channel, error); 1394 return error; 1395 } 1396 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1397 achp->ahcic_datad[slot]->dm_mapsize, 1398 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1399 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1400 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1401 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1402 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1403 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1404 } 1405 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1406 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1407 end: 1408 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1409 return 0; 1410 } 1411 1412 #if NATAPIBUS > 0 1413 static void 1414 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1415 { 1416 struct ata_channel *chp = ata_sc->sc_chan; 1417 struct atac_softc *atac = chp->ch_atac; 1418 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1419 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1420 /* 1421 * Fill in the scsipi_adapter. 1422 */ 1423 adapt->adapt_dev = atac->atac_dev; 1424 adapt->adapt_nchannels = atac->atac_nchannels; 1425 adapt->adapt_request = ahci_atapi_scsipi_request; 1426 adapt->adapt_minphys = ahci_atapi_minphys; 1427 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1428 1429 /* 1430 * Fill in the scsipi_channel. 1431 */ 1432 memset(chan, 0, sizeof(*chan)); 1433 chan->chan_adapter = adapt; 1434 chan->chan_bustype = &ahci_atapi_bustype; 1435 chan->chan_channel = chp->ch_channel; 1436 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1437 chan->chan_openings = 1; 1438 chan->chan_max_periph = 1; 1439 chan->chan_ntargets = 1; 1440 chan->chan_nluns = 1; 1441 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1442 atapiprint); 1443 } 1444 1445 static void 1446 ahci_atapi_minphys(struct buf *bp) 1447 { 1448 if (bp->b_bcount > MAXPHYS) 1449 bp->b_bcount = MAXPHYS; 1450 minphys(bp); 1451 } 1452 1453 /* 1454 * Kill off all pending xfers for a periph. 1455 * 1456 * Must be called at splbio(). 1457 */ 1458 static void 1459 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1460 { 1461 struct atac_softc *atac = 1462 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1463 struct ata_channel *chp = 1464 atac->atac_channels[periph->periph_channel->chan_channel]; 1465 1466 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1467 } 1468 1469 static void 1470 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1471 scsipi_adapter_req_t req, void *arg) 1472 { 1473 struct scsipi_adapter *adapt = chan->chan_adapter; 1474 struct scsipi_periph *periph; 1475 struct scsipi_xfer *sc_xfer; 1476 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1477 struct atac_softc *atac = &sc->sc_atac; 1478 struct ata_xfer *xfer; 1479 int channel = chan->chan_channel; 1480 int drive, s; 1481 1482 switch (req) { 1483 case ADAPTER_REQ_RUN_XFER: 1484 sc_xfer = arg; 1485 periph = sc_xfer->xs_periph; 1486 drive = periph->periph_target; 1487 if (!device_is_active(atac->atac_dev)) { 1488 sc_xfer->error = XS_DRIVER_STUFFUP; 1489 scsipi_done(sc_xfer); 1490 return; 1491 } 1492 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1493 if (xfer == NULL) { 1494 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1495 scsipi_done(sc_xfer); 1496 return; 1497 } 1498 1499 if (sc_xfer->xs_control & XS_CTL_POLL) 1500 xfer->c_flags |= C_POLL; 1501 xfer->c_drive = drive; 1502 xfer->c_flags |= C_ATAPI; 1503 xfer->c_cmd = sc_xfer; 1504 xfer->c_databuf = sc_xfer->data; 1505 xfer->c_bcount = sc_xfer->datalen; 1506 xfer->c_start = ahci_atapi_start; 1507 xfer->c_intr = ahci_atapi_complete; 1508 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1509 xfer->c_dscpoll = 0; 1510 s = splbio(); 1511 ata_exec_xfer(atac->atac_channels[channel], xfer); 1512 #ifdef DIAGNOSTIC 1513 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1514 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1515 panic("ahci_atapi_scsipi_request: polled command " 1516 "not done"); 1517 #endif 1518 splx(s); 1519 return; 1520 default: 1521 /* Not supported, nothing to do. */ 1522 ; 1523 } 1524 } 1525 1526 static void 1527 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1528 { 1529 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1530 struct ahci_channel *achp = (struct ahci_channel *)chp; 1531 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1532 int slot = 0 /* XXX slot */; 1533 struct ahci_cmd_tbl *cmd_tbl; 1534 struct ahci_cmd_header *cmd_h; 1535 int i; 1536 int channel = chp->ch_channel; 1537 1538 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1539 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1540 1541 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1542 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1543 cmd_tbl), DEBUG_XFERS); 1544 1545 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1546 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1547 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1548 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1549 1550 cmd_h = &achp->ahcic_cmdh[slot]; 1551 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1552 chp->ch_channel, cmd_h), DEBUG_XFERS); 1553 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1554 sc_xfer->datalen, 1555 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1556 BUS_DMA_READ : BUS_DMA_WRITE)) { 1557 sc_xfer->error = XS_DRIVER_STUFFUP; 1558 ahci_atapi_complete(chp, xfer, slot); 1559 return; 1560 } 1561 cmd_h->cmdh_flags = htole16( 1562 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1563 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1564 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1565 cmd_h->cmdh_prdbc = 0; 1566 AHCI_CMDH_SYNC(sc, achp, slot, 1567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1568 1569 if (xfer->c_flags & C_POLL) { 1570 /* polled command, disable interrupts */ 1571 AHCI_WRITE(sc, AHCI_GHC, 1572 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1573 } 1574 chp->ch_flags |= ATACH_IRQ_WAIT; 1575 chp->ch_status = 0; 1576 /* start command */ 1577 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1578 /* and says we started this command */ 1579 achp->ahcic_cmds_active |= 1 << slot; 1580 1581 if ((xfer->c_flags & C_POLL) == 0) { 1582 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1583 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1584 ahci_timeout, chp); 1585 return; 1586 } 1587 /* 1588 * Polled command. 1589 */ 1590 for (i = 0; i < ATA_DELAY / 10; i++) { 1591 if (sc_xfer->xs_status & XS_STS_DONE) 1592 break; 1593 ahci_intr_port(sc, achp); 1594 delay(10000); 1595 } 1596 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1597 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1598 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1599 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1600 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1601 DEBUG_XFERS); 1602 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1603 sc_xfer->error = XS_TIMEOUT; 1604 ahci_atapi_complete(chp, xfer, slot); 1605 } 1606 /* reenable interrupts */ 1607 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1608 } 1609 1610 static int 1611 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1612 { 1613 int slot = 0; /* XXX slot */ 1614 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1615 int drive = xfer->c_drive; 1616 struct ahci_channel *achp = (struct ahci_channel *)chp; 1617 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1618 1619 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1620 DEBUG_FUNCS); 1621 1622 achp->ahcic_cmds_active &= ~(1 << slot); 1623 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1624 if (xfer->c_flags & C_TIMEOU) { 1625 sc_xfer->error = XS_TIMEOUT; 1626 } else { 1627 callout_stop(&chp->ch_callout); 1628 sc_xfer->error = 0; 1629 } 1630 1631 chp->ch_queue->active_xfer = NULL; 1632 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1633 achp->ahcic_datad[slot]->dm_mapsize, 1634 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1635 BUS_DMASYNC_POSTWRITE); 1636 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1637 1638 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1639 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1640 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1641 wakeup(&chp->ch_queue->active_xfer); 1642 return 0; 1643 } 1644 ata_free_xfer(chp, xfer); 1645 1646 AHCI_CMDH_SYNC(sc, achp, slot, 1647 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1648 sc_xfer->resid = sc_xfer->datalen; 1649 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1650 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1651 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1652 if (chp->ch_status & WDCS_ERR && 1653 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1654 sc_xfer->resid == sc_xfer->datalen)) { 1655 sc_xfer->error = XS_SHORTSENSE; 1656 sc_xfer->sense.atapi_sense = chp->ch_error; 1657 if ((sc_xfer->xs_periph->periph_quirks & 1658 PQUIRK_NOSENSE) == 0) { 1659 /* ask scsipi to send a REQUEST_SENSE */ 1660 sc_xfer->error = XS_BUSY; 1661 sc_xfer->status = SCSI_CHECK; 1662 } 1663 } 1664 scsipi_done(sc_xfer); 1665 atastart(chp); 1666 return 0; 1667 } 1668 1669 static void 1670 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1671 { 1672 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1673 struct ahci_channel *achp = (struct ahci_channel *)chp; 1674 int slot = 0; /* XXX slot */ 1675 1676 achp->ahcic_cmds_active &= ~(1 << slot); 1677 1678 /* remove this command from xfer queue */ 1679 switch (reason) { 1680 case KILL_GONE: 1681 sc_xfer->error = XS_DRIVER_STUFFUP; 1682 break; 1683 case KILL_RESET: 1684 sc_xfer->error = XS_RESET; 1685 break; 1686 default: 1687 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1688 panic("ahci_ata_atapi_kill_xfer"); 1689 } 1690 ata_free_xfer(chp, xfer); 1691 scsipi_done(sc_xfer); 1692 } 1693 1694 static void 1695 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1696 { 1697 struct scsipi_channel *chan = sc->sc_channel; 1698 struct scsipi_periph *periph; 1699 struct ataparams ids; 1700 struct ataparams *id = &ids; 1701 struct ahci_softc *ahcic = 1702 device_private(chan->chan_adapter->adapt_dev); 1703 struct atac_softc *atac = &ahcic->sc_atac; 1704 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1705 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1706 struct scsipibus_attach_args sa; 1707 char serial_number[21], model[41], firmware_revision[9]; 1708 int s; 1709 1710 /* skip if already attached */ 1711 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1712 return; 1713 1714 /* if no ATAPI device detected at attach time, skip */ 1715 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1716 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1717 "not present\n", target), DEBUG_PROBE); 1718 return; 1719 } 1720 1721 /* Some ATAPI devices need a bit more time after software reset. */ 1722 delay(5000); 1723 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1724 #ifdef ATAPI_DEBUG_PROBE 1725 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1726 AHCINAME(ahcic), target, 1727 id->atap_config & ATAPI_CFG_CMD_MASK, 1728 id->atap_config & ATAPI_CFG_DRQ_MASK); 1729 #endif 1730 periph = scsipi_alloc_periph(M_NOWAIT); 1731 if (periph == NULL) { 1732 aprint_error_dev(sc->sc_dev, 1733 "unable to allocate periph for drive %d\n", 1734 target); 1735 return; 1736 } 1737 periph->periph_dev = NULL; 1738 periph->periph_channel = chan; 1739 periph->periph_switch = &atapi_probe_periphsw; 1740 periph->periph_target = target; 1741 periph->periph_lun = 0; 1742 periph->periph_quirks = PQUIRK_ONLYBIG; 1743 1744 #ifdef SCSIPI_DEBUG 1745 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1746 SCSIPI_DEBUG_TARGET == target) 1747 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1748 #endif 1749 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1750 if (id->atap_config & ATAPI_CFG_REMOV) 1751 periph->periph_flags |= PERIPH_REMOVABLE; 1752 if (periph->periph_type == T_SEQUENTIAL) { 1753 s = splbio(); 1754 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1755 splx(s); 1756 } 1757 1758 sa.sa_periph = periph; 1759 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1760 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1761 T_REMOV : T_FIXED; 1762 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1763 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1764 20); 1765 scsipi_strvis((u_char *)firmware_revision, 8, 1766 id->atap_revision, 8); 1767 sa.sa_inqbuf.vendor = model; 1768 sa.sa_inqbuf.product = serial_number; 1769 sa.sa_inqbuf.revision = firmware_revision; 1770 1771 /* 1772 * Determine the operating mode capabilities of the device. 1773 */ 1774 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1775 periph->periph_cap |= PERIPH_CAP_CMD16; 1776 /* XXX This is gross. */ 1777 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1778 1779 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1780 1781 if (drvp->drv_softc) 1782 ata_probe_caps(drvp); 1783 else { 1784 s = splbio(); 1785 drvp->drive_type = ATA_DRIVET_NONE; 1786 splx(s); 1787 } 1788 } else { 1789 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1790 "failed for drive %s:%d:%d: error 0x%x\n", 1791 AHCINAME(ahcic), chp->ch_channel, target, 1792 chp->ch_error), DEBUG_PROBE); 1793 s = splbio(); 1794 drvp->drive_type = ATA_DRIVET_NONE; 1795 splx(s); 1796 } 1797 } 1798 #endif /* NATAPIBUS */ 1799
Indexes created Fri Sep 26 20:09:58 GMT 2025