ahcisata_core.c revision 1.41
1 /* $NetBSD: ahcisata_core.c,v 1.41 2012/08/10 16:35:00 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.41 2012/08/10 16:35:00 bouyer Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #define AHCI_DEBUG 54 #ifdef AHCI_DEBUG 55 int ahcidebug_mask = 0; 56 #endif 57 58 static void ahci_probe_drive(struct ata_channel *); 59 static void ahci_setup_channel(struct ata_channel *); 60 61 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 62 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 73 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 75 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 76 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 77 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 78 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 79 int, int); 80 static void ahci_timeout(void *); 81 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 82 83 #if NATAPIBUS > 0 84 static void ahci_atapibus_attach(struct atabus_softc *); 85 static void ahci_atapi_kill_pending(struct scsipi_periph *); 86 static void ahci_atapi_minphys(struct buf *); 87 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 88 scsipi_adapter_req_t, void *); 89 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 90 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 92 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 93 94 static const struct scsipi_bustype ahci_atapi_bustype = { 95 SCSIPI_BUSTYPE_ATAPI, 96 atapi_scsipi_cmd, 97 atapi_interpret_sense, 98 atapi_print_addr, 99 ahci_atapi_kill_pending, 100 NULL, 101 }; 102 #endif /* NATAPIBUS */ 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 106 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 107 108 const struct ata_bustype ahci_ata_bustype = { 109 SCSIPI_BUSTYPE_ATA, 110 ahci_ata_bio, 111 ahci_reset_drive, 112 ahci_reset_channel, 113 ahci_exec_command, 114 ata_get_params, 115 ahci_ata_addref, 116 ahci_ata_delref, 117 ahci_killpending 118 }; 119 120 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 121 static void ahci_setup_port(struct ahci_softc *sc, int i); 122 123 static int 124 ahci_reset(struct ahci_softc *sc) 125 { 126 int i; 127 128 /* reset controller */ 129 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 130 /* wait up to 1s for reset to complete */ 131 for (i = 0; i < 1000; i++) { 132 delay(1000); 133 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 134 break; 135 } 136 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 137 aprint_error("%s: reset failed\n", AHCINAME(sc)); 138 return -1; 139 } 140 /* enable ahci mode */ 141 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 142 return 0; 143 } 144 145 static void 146 ahci_setup_ports(struct ahci_softc *sc) 147 { 148 uint32_t ahci_ports; 149 int i, port; 150 151 ahci_ports = AHCI_READ(sc, AHCI_PI); 152 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 153 if ((ahci_ports & (1 << i)) == 0) 154 continue; 155 if (port >= sc->sc_atac.atac_nchannels) { 156 aprint_error("%s: more ports than announced\n", 157 AHCINAME(sc)); 158 break; 159 } 160 ahci_setup_port(sc, i); 161 } 162 } 163 164 static void 165 ahci_reprobe_drives(struct ahci_softc *sc) 166 { 167 uint32_t ahci_ports; 168 int i, port; 169 struct ahci_channel *achp; 170 struct ata_channel *chp; 171 172 ahci_ports = AHCI_READ(sc, AHCI_PI); 173 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 174 if ((ahci_ports & (1 << i)) == 0) 175 continue; 176 if (port >= sc->sc_atac.atac_nchannels) { 177 aprint_error("%s: more ports than announced\n", 178 AHCINAME(sc)); 179 break; 180 } 181 achp = &sc->sc_channels[i]; 182 chp = &achp->ata_channel; 183 184 ahci_probe_drive(chp); 185 } 186 } 187 188 static void 189 ahci_setup_port(struct ahci_softc *sc, int i) 190 { 191 struct ahci_channel *achp; 192 193 achp = &sc->sc_channels[i]; 194 195 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 196 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 197 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 198 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 199 } 200 201 static void 202 ahci_enable_intrs(struct ahci_softc *sc) 203 { 204 205 /* clear interrupts */ 206 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 207 /* enable interrupts */ 208 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 209 } 210 211 void 212 ahci_attach(struct ahci_softc *sc) 213 { 214 uint32_t ahci_rev, ahci_ports; 215 int i, j, port; 216 struct ahci_channel *achp; 217 struct ata_channel *chp; 218 int error; 219 int dmasize; 220 char buf[128]; 221 void *cmdhp; 222 void *cmdtblp; 223 224 if (ahci_reset(sc) != 0) 225 return; 226 227 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 228 if (sc->sc_achi_quirks & AHCI_QUIRK_BADPMP) { 229 aprint_verbose_dev(sc->sc_atac.atac_dev, 230 "ignoring broken port multiplier support\n"); 231 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 232 } 233 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 234 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 235 ahci_rev = AHCI_READ(sc, AHCI_VS); 236 snprintb(buf, sizeof(buf), "\177\020" 237 /* "f\000\005NP\0" */ 238 "b\005SXS\0" 239 "b\006EMS\0" 240 "b\007CCCS\0" 241 /* "f\010\005NCS\0" */ 242 "b\015PSC\0" 243 "b\016SSC\0" 244 "b\017PMD\0" 245 "b\020FBSS\0" 246 "b\021SPM\0" 247 "b\022SAM\0" 248 "b\023SNZO\0" 249 "f\024\003ISS\0" 250 "=\001Gen1\0" 251 "=\002Gen2\0" 252 "=\003Gen3\0" 253 "b\030SCLO\0" 254 "b\031SAL\0" 255 "b\032SALP\0" 256 "b\033SSS\0" 257 "b\034SMPS\0" 258 "b\035SSNTF\0" 259 "b\036SNCQ\0" 260 "b\037S64A\0" 261 "\0", sc->sc_ahci_cap); 262 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 263 ", %d ports, %d slots, CAP %s\n", 264 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 265 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 266 267 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 268 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 269 sc->sc_atac.atac_pio_cap = 4; 270 sc->sc_atac.atac_dma_cap = 2; 271 sc->sc_atac.atac_udma_cap = 6; 272 sc->sc_atac.atac_channels = sc->sc_chanarray; 273 sc->sc_atac.atac_probe = ahci_probe_drive; 274 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 275 sc->sc_atac.atac_set_modes = ahci_setup_channel; 276 #if NATAPIBUS > 0 277 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 278 #endif 279 280 dmasize = 281 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 282 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 283 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 284 if (error) { 285 aprint_error("%s: unable to allocate command header memory" 286 ", error=%d\n", AHCINAME(sc), error); 287 return; 288 } 289 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 290 sc->sc_cmd_hdr_nseg, dmasize, 291 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 292 if (error) { 293 aprint_error("%s: unable to map command header memory" 294 ", error=%d\n", AHCINAME(sc), error); 295 return; 296 } 297 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 298 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 299 if (error) { 300 aprint_error("%s: unable to create command header map" 301 ", error=%d\n", AHCINAME(sc), error); 302 return; 303 } 304 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 305 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 306 if (error) { 307 aprint_error("%s: unable to load command header map" 308 ", error=%d\n", AHCINAME(sc), error); 309 return; 310 } 311 sc->sc_cmd_hdr = cmdhp; 312 313 ahci_enable_intrs(sc); 314 315 ahci_ports = AHCI_READ(sc, AHCI_PI); 316 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 317 if ((ahci_ports & (1 << i)) == 0) 318 continue; 319 if (port >= sc->sc_atac.atac_nchannels) { 320 aprint_error("%s: more ports than announced\n", 321 AHCINAME(sc)); 322 break; 323 } 324 achp = &sc->sc_channels[i]; 325 chp = &achp->ata_channel; 326 sc->sc_chanarray[i] = chp; 327 chp->ch_channel = i; 328 chp->ch_atac = &sc->sc_atac; 329 chp->ch_queue = malloc(sizeof(struct ata_queue), 330 M_DEVBUF, M_NOWAIT); 331 if (chp->ch_queue == NULL) { 332 aprint_error("%s port %d: can't allocate memory for " 333 "command queue", AHCINAME(sc), i); 334 break; 335 } 336 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 337 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 338 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 339 BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error("%s: unable to allocate command table " 342 "memory, error=%d\n", AHCINAME(sc), error); 343 break; 344 } 345 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 346 achp->ahcic_cmd_tbl_nseg, dmasize, 347 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 348 if (error) { 349 aprint_error("%s: unable to map command table memory" 350 ", error=%d\n", AHCINAME(sc), error); 351 break; 352 } 353 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 354 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 355 if (error) { 356 aprint_error("%s: unable to create command table map" 357 ", error=%d\n", AHCINAME(sc), error); 358 break; 359 } 360 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 361 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 362 if (error) { 363 aprint_error("%s: unable to load command table map" 364 ", error=%d\n", AHCINAME(sc), error); 365 break; 366 } 367 achp->ahcic_cmdh = (struct ahci_cmd_header *) 368 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 369 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 370 AHCI_CMDH_SIZE * port; 371 achp->ahcic_rfis = (struct ahci_r_fis *) 372 ((char *)cmdhp + 373 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 374 AHCI_RFIS_SIZE * port); 375 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 376 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 377 AHCI_RFIS_SIZE * port; 378 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 379 "rfis %p (0x%" PRIx64 ")\n", i, 380 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 381 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 382 DEBUG_PROBE); 383 384 for (j = 0; j < sc->sc_ncmds; j++) { 385 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 386 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 387 achp->ahcic_bus_cmd_tbl[j] = 388 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 389 AHCI_CMDTBL_SIZE * j; 390 achp->ahcic_cmdh[j].cmdh_cmdtba = 391 htole64(achp->ahcic_bus_cmd_tbl[j]); 392 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 393 achp->ahcic_cmd_tbl[j], 394 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 395 /* The xfer DMA map */ 396 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 397 AHCI_NPRD, 0x400000 /* 4MB */, 0, 398 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 399 &achp->ahcic_datad[j]); 400 if (error) { 401 aprint_error("%s: couldn't alloc xfer DMA map, " 402 "error=%d\n", AHCINAME(sc), error); 403 goto end; 404 } 405 } 406 ahci_setup_port(sc, i); 407 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 408 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 409 aprint_error("%s: couldn't map channel %d " 410 "sata_status regs\n", AHCINAME(sc), i); 411 break; 412 } 413 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 414 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 415 aprint_error("%s: couldn't map channel %d " 416 "sata_control regs\n", AHCINAME(sc), i); 417 break; 418 } 419 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 420 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 421 aprint_error("%s: couldn't map channel %d " 422 "sata_error regs\n", AHCINAME(sc), i); 423 break; 424 } 425 ata_channel_attach(chp); 426 port++; 427 end: 428 continue; 429 } 430 } 431 432 int 433 ahci_detach(struct ahci_softc *sc, int flags) 434 { 435 struct atac_softc *atac; 436 struct ahci_channel *achp; 437 struct ata_channel *chp; 438 struct scsipi_adapter *adapt; 439 uint32_t ahci_ports; 440 int i, j; 441 int error; 442 443 atac = &sc->sc_atac; 444 adapt = &atac->atac_atapi_adapter._generic; 445 446 ahci_ports = AHCI_READ(sc, AHCI_PI); 447 for (i = 0; i < AHCI_MAX_PORTS; i++) { 448 achp = &sc->sc_channels[i]; 449 chp = &achp->ata_channel; 450 451 if ((ahci_ports & (1 << i)) == 0) 452 continue; 453 if (i >= sc->sc_atac.atac_nchannels) { 454 aprint_error("%s: more ports than announced\n", 455 AHCINAME(sc)); 456 break; 457 } 458 459 if (chp->atabus == NULL) 460 continue; 461 if ((error = config_detach(chp->atabus, flags)) != 0) 462 return error; 463 464 for (j = 0; j < sc->sc_ncmds; j++) 465 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 466 467 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 468 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 469 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 470 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 471 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 472 achp->ahcic_cmd_tbl_nseg); 473 474 free(chp->ch_queue, M_DEVBUF); 475 chp->atabus = NULL; 476 } 477 478 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 479 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 480 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 481 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 482 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 483 484 if (adapt->adapt_refcnt != 0) 485 return EBUSY; 486 487 return 0; 488 } 489 490 void 491 ahci_resume(struct ahci_softc *sc) 492 { 493 ahci_reset(sc); 494 ahci_setup_ports(sc); 495 ahci_reprobe_drives(sc); 496 ahci_enable_intrs(sc); 497 } 498 499 int 500 ahci_intr(void *v) 501 { 502 struct ahci_softc *sc = v; 503 uint32_t is; 504 int i, r = 0; 505 506 while ((is = AHCI_READ(sc, AHCI_IS))) { 507 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 508 DEBUG_INTR); 509 r = 1; 510 AHCI_WRITE(sc, AHCI_IS, is); 511 for (i = 0; i < AHCI_MAX_PORTS; i++) 512 if (is & (1 << i)) 513 ahci_intr_port(sc, &sc->sc_channels[i]); 514 } 515 return r; 516 } 517 518 static void 519 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 520 { 521 uint32_t is, tfd; 522 struct ata_channel *chp = &achp->ata_channel; 523 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 524 int slot; 525 526 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 527 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 528 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 529 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 530 DEBUG_INTR); 531 532 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 533 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 534 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 535 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 536 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 537 return; 538 /* stop channel */ 539 ahci_channel_stop(sc, chp, 0); 540 if (slot != 0) { 541 printf("ahci_intr_port: slot %d\n", slot); 542 panic("ahci_intr_port"); 543 } 544 if (is & AHCI_P_IX_TFES) { 545 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 546 chp->ch_error = 547 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 548 chp->ch_status = (tfd & 0xff); 549 } else { 550 /* emulate a CRC error */ 551 chp->ch_error = WDCE_CRC; 552 chp->ch_status = WDCS_ERR; 553 } 554 if (is & AHCI_P_IX_IFS) { 555 aprint_error("%s port %d: SERR 0x%x\n", 556 AHCINAME(sc), chp->ch_channel, 557 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 558 } 559 xfer->c_intr(chp, xfer, is); 560 /* if channel has not been restarted, do it now */ 561 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 562 == 0) 563 ahci_channel_start(sc, chp, 0, 0); 564 } else { 565 slot = 0; /* XXX */ 566 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 567 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 568 chp->ch_channel, is, achp->ahcic_cmds_active, 569 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 570 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 571 return; 572 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 573 == 0) { 574 xfer->c_intr(chp, xfer, 0); 575 } 576 } 577 } 578 579 static void 580 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 581 { 582 struct ata_channel *chp = drvp->chnl_softc; 583 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 584 AHCI_WRITE(sc, AHCI_GHC, 585 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 586 ahci_channel_stop(sc, chp, flags); 587 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 588 ata_reset_channel(chp, flags); 589 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 590 return; 591 } 592 593 /* return error code from ata_bio */ 594 static int 595 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 596 { 597 struct ahci_channel *achp = (struct ahci_channel *)chp; 598 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 599 int i; 600 uint32_t is; 601 602 timeout = timeout * 10; /* wait is 10ms */ 603 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 604 /* start command */ 605 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 606 for (i = 0; i < timeout; i++) { 607 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 608 return 0; 609 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 610 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 611 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 612 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 613 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 614 /* 615 * we got the D2H FIS anyway, 616 * assume sig is valid. 617 * channel is restarted later 618 */ 619 return ERROR; 620 } 621 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 622 AHCINAME(sc), chp->ch_channel, is); 623 return ERR_DF; 624 } 625 if (flags & AT_WAIT) 626 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 627 else 628 delay(10000); 629 } 630 aprint_debug("%s channel %d: timeout sending FIS\n", 631 AHCINAME(sc), chp->ch_channel); 632 return TIMEOUT; 633 } 634 635 static int 636 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 637 uint32_t *sigp) 638 { 639 struct ahci_channel *achp = (struct ahci_channel *)chp; 640 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 641 struct ahci_cmd_tbl *cmd_tbl; 642 struct ahci_cmd_header *cmd_h; 643 int i; 644 uint32_t sig; 645 646 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 647 /* clear port interrupt register */ 648 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 649 /* clear SErrors and start operations */ 650 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 651 /* 652 * issue a command list override to clear BSY. 653 * This is needed if there's a PMP with no drive 654 * on port 0 655 */ 656 ahci_channel_start(sc, chp, flags, 1); 657 } else { 658 ahci_channel_start(sc, chp, flags, 0); 659 } 660 if (drive > 0) { 661 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 662 } 663 again: 664 /* polled command, assume interrupts are disabled */ 665 /* use slot 0 to send reset, the channel is idle */ 666 cmd_h = &achp->ahcic_cmdh[0]; 667 cmd_tbl = achp->ahcic_cmd_tbl[0]; 668 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 669 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 670 cmd_h->cmdh_prdbc = 0; 671 memset(cmd_tbl->cmdt_cfis, 0, 64); 672 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 673 cmd_tbl->cmdt_cfis[rhd_c] = drive; 674 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 675 switch(ahci_exec_fis(chp, 1, flags)) { 676 case ERR_DF: 677 case TIMEOUT: 678 aprint_error("%s channel %d: setting WDCTL_RST failed " 679 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 680 if (sigp) 681 *sigp = 0xffffffff; 682 goto end; 683 default: 684 break; 685 } 686 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 687 (drive << AHCI_CMDH_F_PMP_SHIFT)); 688 cmd_h->cmdh_prdbc = 0; 689 memset(cmd_tbl->cmdt_cfis, 0, 64); 690 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 691 cmd_tbl->cmdt_cfis[rhd_c] = drive; 692 cmd_tbl->cmdt_cfis[rhd_control] = 0; 693 switch(ahci_exec_fis(chp, 31, flags)) { 694 case ERR_DF: 695 case TIMEOUT: 696 if ((sc->sc_achi_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 697 drive == PMP_PORT_CTL) { 698 /* 699 * some controllers fails to reset when 700 * targeting a PMP but a single drive is attached. 701 * try again with port 0 702 */ 703 drive = 0; 704 goto again; 705 } 706 aprint_error("%s channel %d: clearing WDCTL_RST failed " 707 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 708 if (sigp) 709 *sigp = 0xffffffff; 710 goto end; 711 default: 712 break; 713 } 714 /* 715 * wait 31s for BSY to clear 716 * This should not be needed, but some controllers clear the 717 * command slot before receiving the D2H FIS ... 718 */ 719 for (i = 0; i <AHCI_RST_WAIT; i++) { 720 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 721 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 722 & WDCS_BSY) == 0) 723 break; 724 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 725 } 726 if (i == AHCI_RST_WAIT) { 727 aprint_error("%s: BSY never cleared, TD 0x%x\n", 728 AHCINAME(sc), sig); 729 if (sigp) 730 *sigp = 0xffffffff; 731 goto end; 732 } 733 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 734 DEBUG_PROBE); 735 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 736 if (sigp) 737 *sigp = sig; 738 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 739 AHCINAME(sc), chp->ch_channel, sig, 740 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 741 end: 742 ahci_channel_stop(sc, chp, flags); 743 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 744 /* clear port interrupt register */ 745 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 746 ahci_channel_start(sc, chp, AT_WAIT, 747 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 748 return 0; 749 } 750 751 static void 752 ahci_reset_channel(struct ata_channel *chp, int flags) 753 { 754 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 755 struct ahci_channel *achp = (struct ahci_channel *)chp; 756 int i, tfd; 757 758 ahci_channel_stop(sc, chp, flags); 759 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 760 achp->ahcic_sstatus) != SStatus_DET_DEV) { 761 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 762 /* XXX and then ? */ 763 } 764 if (chp->ch_queue->active_xfer) { 765 chp->ch_queue->active_xfer->c_kill_xfer(chp, 766 chp->ch_queue->active_xfer, KILL_RESET); 767 } 768 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 769 /* clear port interrupt register */ 770 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 771 /* clear SErrors and start operations */ 772 ahci_channel_start(sc, chp, flags, 1); 773 /* wait 31s for BSY to clear */ 774 for (i = 0; i <AHCI_RST_WAIT; i++) { 775 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 776 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 777 & WDCS_BSY) == 0) 778 break; 779 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 780 } 781 if (i == AHCI_RST_WAIT) 782 aprint_error("%s: BSY never cleared, TD 0x%x\n", 783 AHCINAME(sc), tfd); 784 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 785 DEBUG_PROBE); 786 /* clear port interrupt register */ 787 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 788 789 return; 790 } 791 792 static int 793 ahci_ata_addref(struct ata_drive_datas *drvp) 794 { 795 return 0; 796 } 797 798 static void 799 ahci_ata_delref(struct ata_drive_datas *drvp) 800 { 801 return; 802 } 803 804 static void 805 ahci_killpending(struct ata_drive_datas *drvp) 806 { 807 return; 808 } 809 810 static void 811 ahci_probe_drive(struct ata_channel *chp) 812 { 813 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 814 struct ahci_channel *achp = (struct ahci_channel *)chp; 815 uint32_t sig; 816 817 /* bring interface up, accept FISs, power up and spin up device */ 818 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 819 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 820 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 821 /* reset the PHY and bring online */ 822 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 823 achp->ahcic_sstatus)) { 824 case SStatus_DET_DEV: 825 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 826 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 827 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 828 } else { 829 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 830 } 831 sata_interpret_sig(chp, 0, sig); 832 /* if we have a PMP attached, inform the controller */ 833 if (chp->ch_ndrives > PMP_PORT_CTL && 834 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 835 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 836 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 837 AHCI_P_CMD_PMA); 838 } 839 /* clear port interrupt register */ 840 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 841 /* and enable interrupts */ 842 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 843 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 844 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 845 AHCI_P_IX_DHRS); 846 /* wait 500ms before actually starting operations */ 847 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 848 break; 849 850 default: 851 break; 852 } 853 } 854 855 static void 856 ahci_setup_channel(struct ata_channel *chp) 857 { 858 return; 859 } 860 861 static int 862 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 863 { 864 struct ata_channel *chp = drvp->chnl_softc; 865 struct ata_xfer *xfer; 866 int ret; 867 int s; 868 869 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 870 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 871 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 872 DEBUG_XFERS); 873 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 874 ATAXF_NOSLEEP); 875 if (xfer == NULL) { 876 return ATACMD_TRY_AGAIN; 877 } 878 if (ata_c->flags & AT_POLL) 879 xfer->c_flags |= C_POLL; 880 if (ata_c->flags & AT_WAIT) 881 xfer->c_flags |= C_WAIT; 882 xfer->c_drive = drvp->drive; 883 xfer->c_databuf = ata_c->data; 884 xfer->c_bcount = ata_c->bcount; 885 xfer->c_cmd = ata_c; 886 xfer->c_start = ahci_cmd_start; 887 xfer->c_intr = ahci_cmd_complete; 888 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 889 s = splbio(); 890 ata_exec_xfer(chp, xfer); 891 #ifdef DIAGNOSTIC 892 if ((ata_c->flags & AT_POLL) != 0 && 893 (ata_c->flags & AT_DONE) == 0) 894 panic("ahci_exec_command: polled command not done"); 895 #endif 896 if (ata_c->flags & AT_DONE) { 897 ret = ATACMD_COMPLETE; 898 } else { 899 if (ata_c->flags & AT_WAIT) { 900 while ((ata_c->flags & AT_DONE) == 0) { 901 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 902 } 903 ret = ATACMD_COMPLETE; 904 } else { 905 ret = ATACMD_QUEUED; 906 } 907 } 908 splx(s); 909 return ret; 910 } 911 912 static void 913 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 914 { 915 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 916 struct ahci_channel *achp = (struct ahci_channel *)chp; 917 struct ata_command *ata_c = xfer->c_cmd; 918 int slot = 0 /* XXX slot */; 919 struct ahci_cmd_tbl *cmd_tbl; 920 struct ahci_cmd_header *cmd_h; 921 int i; 922 int channel = chp->ch_channel; 923 924 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 925 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 926 927 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 928 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 929 cmd_tbl), DEBUG_XFERS); 930 931 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 932 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 933 934 cmd_h = &achp->ahcic_cmdh[slot]; 935 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 936 chp->ch_channel, cmd_h), DEBUG_XFERS); 937 if (ahci_dma_setup(chp, slot, 938 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 939 ata_c->data : NULL, 940 ata_c->bcount, 941 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 942 ata_c->flags |= AT_DF; 943 ahci_cmd_complete(chp, xfer, slot); 944 return; 945 } 946 cmd_h->cmdh_flags = htole16( 947 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 948 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 949 cmd_h->cmdh_prdbc = 0; 950 AHCI_CMDH_SYNC(sc, achp, slot, 951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 952 953 if (ata_c->flags & AT_POLL) { 954 /* polled command, disable interrupts */ 955 AHCI_WRITE(sc, AHCI_GHC, 956 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 957 } 958 chp->ch_flags |= ATACH_IRQ_WAIT; 959 chp->ch_status = 0; 960 /* start command */ 961 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 962 /* and says we started this command */ 963 achp->ahcic_cmds_active |= 1 << slot; 964 965 if ((ata_c->flags & AT_POLL) == 0) { 966 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 967 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 968 ahci_timeout, chp); 969 return; 970 } 971 /* 972 * Polled command. 973 */ 974 for (i = 0; i < ata_c->timeout / 10; i++) { 975 if (ata_c->flags & AT_DONE) 976 break; 977 ahci_intr_port(sc, achp); 978 if (ata_c->flags & AT_WAIT) 979 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 980 else 981 delay(10000); 982 } 983 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 984 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 985 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 986 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 987 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 988 DEBUG_XFERS); 989 if ((ata_c->flags & AT_DONE) == 0) { 990 ata_c->flags |= AT_TIMEOU; 991 ahci_cmd_complete(chp, xfer, slot); 992 } 993 /* reenable interrupts */ 994 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 995 } 996 997 static void 998 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 999 { 1000 struct ata_command *ata_c = xfer->c_cmd; 1001 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1002 DEBUG_FUNCS); 1003 1004 switch (reason) { 1005 case KILL_GONE: 1006 ata_c->flags |= AT_GONE; 1007 break; 1008 case KILL_RESET: 1009 ata_c->flags |= AT_RESET; 1010 break; 1011 default: 1012 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1013 panic("ahci_cmd_kill_xfer"); 1014 } 1015 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1016 } 1017 1018 static int 1019 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1020 { 1021 int slot = 0; /* XXX slot */ 1022 struct ata_command *ata_c = xfer->c_cmd; 1023 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1024 struct ahci_channel *achp = (struct ahci_channel *)chp; 1025 1026 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1027 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1028 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1029 DEBUG_FUNCS); 1030 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1031 if (xfer->c_flags & C_TIMEOU) { 1032 ata_c->flags |= AT_TIMEOU; 1033 } else 1034 callout_stop(&chp->ch_callout); 1035 1036 chp->ch_queue->active_xfer = NULL; 1037 1038 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1039 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1040 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1041 wakeup(&chp->ch_queue->active_xfer); 1042 return 0; 1043 } 1044 1045 if (chp->ch_status & WDCS_BSY) { 1046 ata_c->flags |= AT_TIMEOU; 1047 } else if (chp->ch_status & WDCS_ERR) { 1048 ata_c->r_error = chp->ch_error; 1049 ata_c->flags |= AT_ERROR; 1050 } 1051 1052 if (ata_c->flags & AT_READREG) 1053 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1054 1055 ahci_cmd_done(chp, xfer, slot); 1056 return 0; 1057 } 1058 1059 static void 1060 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1061 { 1062 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1063 struct ahci_channel *achp = (struct ahci_channel *)chp; 1064 struct ata_command *ata_c = xfer->c_cmd; 1065 uint16_t *idwordbuf; 1066 int i; 1067 1068 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 1069 DEBUG_FUNCS); 1070 1071 /* this comamnd is not active any more */ 1072 achp->ahcic_cmds_active &= ~(1 << slot); 1073 1074 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1075 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1076 achp->ahcic_datad[slot]->dm_mapsize, 1077 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1078 BUS_DMASYNC_POSTWRITE); 1079 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1080 } 1081 1082 AHCI_CMDH_SYNC(sc, achp, slot, 1083 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1084 1085 /* ata(4) expects IDENTIFY data to be in host endianess */ 1086 if (ata_c->r_command == WDCC_IDENTIFY || 1087 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1088 idwordbuf = xfer->c_databuf; 1089 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1090 idwordbuf[i] = le16toh(idwordbuf[i]); 1091 } 1092 } 1093 1094 ata_c->flags |= AT_DONE; 1095 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1096 ata_c->flags |= AT_XFDONE; 1097 1098 ata_free_xfer(chp, xfer); 1099 if (ata_c->flags & AT_WAIT) 1100 wakeup(ata_c); 1101 else if (ata_c->callback) 1102 ata_c->callback(ata_c->callback_arg); 1103 atastart(chp); 1104 return; 1105 } 1106 1107 static int 1108 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1109 { 1110 struct ata_channel *chp = drvp->chnl_softc; 1111 struct ata_xfer *xfer; 1112 1113 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1114 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1115 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1116 DEBUG_XFERS); 1117 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1118 if (xfer == NULL) { 1119 return ATACMD_TRY_AGAIN; 1120 } 1121 if (ata_bio->flags & ATA_POLL) 1122 xfer->c_flags |= C_POLL; 1123 xfer->c_drive = drvp->drive; 1124 xfer->c_cmd = ata_bio; 1125 xfer->c_databuf = ata_bio->databuf; 1126 xfer->c_bcount = ata_bio->bcount; 1127 xfer->c_start = ahci_bio_start; 1128 xfer->c_intr = ahci_bio_complete; 1129 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1130 ata_exec_xfer(chp, xfer); 1131 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1132 } 1133 1134 static void 1135 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1136 { 1137 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1138 struct ahci_channel *achp = (struct ahci_channel *)chp; 1139 struct ata_bio *ata_bio = xfer->c_cmd; 1140 int slot = 0 /* XXX slot */; 1141 struct ahci_cmd_tbl *cmd_tbl; 1142 struct ahci_cmd_header *cmd_h; 1143 int i; 1144 int channel = chp->ch_channel; 1145 1146 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1147 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1148 1149 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1150 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1151 cmd_tbl), DEBUG_XFERS); 1152 1153 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1154 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1155 1156 cmd_h = &achp->ahcic_cmdh[slot]; 1157 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1158 chp->ch_channel, cmd_h), DEBUG_XFERS); 1159 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1160 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1161 ata_bio->error = ERR_DMA; 1162 ata_bio->r_error = 0; 1163 ahci_bio_complete(chp, xfer, slot); 1164 return; 1165 } 1166 cmd_h->cmdh_flags = htole16( 1167 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1168 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1169 cmd_h->cmdh_prdbc = 0; 1170 AHCI_CMDH_SYNC(sc, achp, slot, 1171 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1172 1173 if (xfer->c_flags & C_POLL) { 1174 /* polled command, disable interrupts */ 1175 AHCI_WRITE(sc, AHCI_GHC, 1176 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1177 } 1178 chp->ch_flags |= ATACH_IRQ_WAIT; 1179 chp->ch_status = 0; 1180 /* start command */ 1181 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1182 /* and says we started this command */ 1183 achp->ahcic_cmds_active |= 1 << slot; 1184 1185 if ((xfer->c_flags & C_POLL) == 0) { 1186 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1187 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1188 ahci_timeout, chp); 1189 return; 1190 } 1191 /* 1192 * Polled command. 1193 */ 1194 for (i = 0; i < ATA_DELAY / 10; i++) { 1195 if (ata_bio->flags & ATA_ITSDONE) 1196 break; 1197 ahci_intr_port(sc, achp); 1198 if (ata_bio->flags & ATA_NOSLEEP) 1199 delay(10000); 1200 else 1201 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1202 } 1203 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1204 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1205 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1206 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1207 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1208 DEBUG_XFERS); 1209 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1210 ata_bio->error = TIMEOUT; 1211 ahci_bio_complete(chp, xfer, slot); 1212 } 1213 /* reenable interrupts */ 1214 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1215 } 1216 1217 static void 1218 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1219 { 1220 int slot = 0; /* XXX slot */ 1221 int drive = xfer->c_drive; 1222 struct ata_bio *ata_bio = xfer->c_cmd; 1223 struct ahci_channel *achp = (struct ahci_channel *)chp; 1224 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1225 DEBUG_FUNCS); 1226 1227 achp->ahcic_cmds_active &= ~(1 << slot); 1228 ata_free_xfer(chp, xfer); 1229 ata_bio->flags |= ATA_ITSDONE; 1230 switch (reason) { 1231 case KILL_GONE: 1232 ata_bio->error = ERR_NODEV; 1233 break; 1234 case KILL_RESET: 1235 ata_bio->error = ERR_RESET; 1236 break; 1237 default: 1238 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1239 panic("ahci_bio_kill_xfer"); 1240 } 1241 ata_bio->r_error = WDCE_ABRT; 1242 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1243 } 1244 1245 static int 1246 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1247 { 1248 int slot = 0; /* XXX slot */ 1249 struct ata_bio *ata_bio = xfer->c_cmd; 1250 int drive = xfer->c_drive; 1251 struct ahci_channel *achp = (struct ahci_channel *)chp; 1252 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1253 1254 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1255 DEBUG_FUNCS); 1256 1257 achp->ahcic_cmds_active &= ~(1 << slot); 1258 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1259 if (xfer->c_flags & C_TIMEOU) { 1260 ata_bio->error = TIMEOUT; 1261 } else { 1262 callout_stop(&chp->ch_callout); 1263 ata_bio->error = NOERROR; 1264 } 1265 1266 chp->ch_queue->active_xfer = NULL; 1267 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1268 achp->ahcic_datad[slot]->dm_mapsize, 1269 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1270 BUS_DMASYNC_POSTWRITE); 1271 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1272 1273 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1274 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1275 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1276 wakeup(&chp->ch_queue->active_xfer); 1277 return 0; 1278 } 1279 ata_free_xfer(chp, xfer); 1280 ata_bio->flags |= ATA_ITSDONE; 1281 if (chp->ch_status & WDCS_DWF) { 1282 ata_bio->error = ERR_DF; 1283 } else if (chp->ch_status & WDCS_ERR) { 1284 ata_bio->error = ERROR; 1285 ata_bio->r_error = chp->ch_error; 1286 } else if (chp->ch_status & WDCS_CORR) 1287 ata_bio->flags |= ATA_CORR; 1288 1289 AHCI_CMDH_SYNC(sc, achp, slot, 1290 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1291 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1292 ata_bio->bcount), DEBUG_XFERS); 1293 /* 1294 * if it was a write, complete data buffer may have been transfered 1295 * before error detection; in this case don't use cmdh_prdbc 1296 * as it won't reflect what was written to media. Assume nothing 1297 * was transfered and leave bcount as-is. 1298 */ 1299 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1300 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1301 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1302 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1303 atastart(chp); 1304 return 0; 1305 } 1306 1307 static void 1308 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1309 { 1310 int i; 1311 /* stop channel */ 1312 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1313 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1314 /* wait 1s for channel to stop */ 1315 for (i = 0; i <100; i++) { 1316 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1317 == 0) 1318 break; 1319 if (flags & AT_WAIT) 1320 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1321 else 1322 delay(10000); 1323 } 1324 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1325 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1326 /* XXX controller reset ? */ 1327 return; 1328 } 1329 } 1330 1331 static void 1332 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1333 int flags, int clo) 1334 { 1335 int i; 1336 uint32_t p_cmd; 1337 /* clear error */ 1338 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1339 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1340 1341 if (clo) { 1342 /* issue command list override */ 1343 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1344 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1345 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1346 /* wait 1s for AHCI_CAP_CLO to clear */ 1347 for (i = 0; i <100; i++) { 1348 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1349 AHCI_P_CMD_CLO) == 0) 1350 break; 1351 if (flags & AT_WAIT) 1352 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1353 else 1354 delay(10000); 1355 } 1356 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1357 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1358 /* XXX controller reset ? */ 1359 return; 1360 } 1361 } 1362 /* and start controller */ 1363 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1364 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1365 if (chp->ch_ndrives > PMP_PORT_CTL && 1366 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1367 p_cmd |= AHCI_P_CMD_PMA; 1368 } 1369 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1370 } 1371 1372 static void 1373 ahci_timeout(void *v) 1374 { 1375 struct ata_channel *chp = (struct ata_channel *)v; 1376 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1377 int s = splbio(); 1378 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1379 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1380 xfer->c_flags |= C_TIMEOU; 1381 xfer->c_intr(chp, xfer, 0); 1382 } 1383 splx(s); 1384 } 1385 1386 static int 1387 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1388 size_t count, int op) 1389 { 1390 int error, seg; 1391 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1392 struct ahci_channel *achp = (struct ahci_channel *)chp; 1393 struct ahci_cmd_tbl *cmd_tbl; 1394 struct ahci_cmd_header *cmd_h; 1395 1396 cmd_h = &achp->ahcic_cmdh[slot]; 1397 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1398 1399 if (data == NULL) { 1400 cmd_h->cmdh_prdtl = 0; 1401 goto end; 1402 } 1403 1404 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1405 data, count, NULL, 1406 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1407 if (error) { 1408 printf("%s port %d: failed to load xfer: %d\n", 1409 AHCINAME(sc), chp->ch_channel, error); 1410 return error; 1411 } 1412 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1413 achp->ahcic_datad[slot]->dm_mapsize, 1414 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1415 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1416 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1417 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1418 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1419 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1420 } 1421 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1422 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1423 end: 1424 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1425 return 0; 1426 } 1427 1428 #if NATAPIBUS > 0 1429 static void 1430 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1431 { 1432 struct ata_channel *chp = ata_sc->sc_chan; 1433 struct atac_softc *atac = chp->ch_atac; 1434 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1435 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1436 /* 1437 * Fill in the scsipi_adapter. 1438 */ 1439 adapt->adapt_dev = atac->atac_dev; 1440 adapt->adapt_nchannels = atac->atac_nchannels; 1441 adapt->adapt_request = ahci_atapi_scsipi_request; 1442 adapt->adapt_minphys = ahci_atapi_minphys; 1443 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1444 1445 /* 1446 * Fill in the scsipi_channel. 1447 */ 1448 memset(chan, 0, sizeof(*chan)); 1449 chan->chan_adapter = adapt; 1450 chan->chan_bustype = &ahci_atapi_bustype; 1451 chan->chan_channel = chp->ch_channel; 1452 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1453 chan->chan_openings = 1; 1454 chan->chan_max_periph = 1; 1455 chan->chan_ntargets = 1; 1456 chan->chan_nluns = 1; 1457 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1458 atapiprint); 1459 } 1460 1461 static void 1462 ahci_atapi_minphys(struct buf *bp) 1463 { 1464 if (bp->b_bcount > MAXPHYS) 1465 bp->b_bcount = MAXPHYS; 1466 minphys(bp); 1467 } 1468 1469 /* 1470 * Kill off all pending xfers for a periph. 1471 * 1472 * Must be called at splbio(). 1473 */ 1474 static void 1475 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1476 { 1477 struct atac_softc *atac = 1478 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1479 struct ata_channel *chp = 1480 atac->atac_channels[periph->periph_channel->chan_channel]; 1481 1482 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1483 } 1484 1485 static void 1486 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1487 scsipi_adapter_req_t req, void *arg) 1488 { 1489 struct scsipi_adapter *adapt = chan->chan_adapter; 1490 struct scsipi_periph *periph; 1491 struct scsipi_xfer *sc_xfer; 1492 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1493 struct atac_softc *atac = &sc->sc_atac; 1494 struct ata_xfer *xfer; 1495 int channel = chan->chan_channel; 1496 int drive, s; 1497 1498 switch (req) { 1499 case ADAPTER_REQ_RUN_XFER: 1500 sc_xfer = arg; 1501 periph = sc_xfer->xs_periph; 1502 drive = periph->periph_target; 1503 if (!device_is_active(atac->atac_dev)) { 1504 sc_xfer->error = XS_DRIVER_STUFFUP; 1505 scsipi_done(sc_xfer); 1506 return; 1507 } 1508 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1509 if (xfer == NULL) { 1510 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1511 scsipi_done(sc_xfer); 1512 return; 1513 } 1514 1515 if (sc_xfer->xs_control & XS_CTL_POLL) 1516 xfer->c_flags |= C_POLL; 1517 xfer->c_drive = drive; 1518 xfer->c_flags |= C_ATAPI; 1519 xfer->c_cmd = sc_xfer; 1520 xfer->c_databuf = sc_xfer->data; 1521 xfer->c_bcount = sc_xfer->datalen; 1522 xfer->c_start = ahci_atapi_start; 1523 xfer->c_intr = ahci_atapi_complete; 1524 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1525 xfer->c_dscpoll = 0; 1526 s = splbio(); 1527 ata_exec_xfer(atac->atac_channels[channel], xfer); 1528 #ifdef DIAGNOSTIC 1529 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1530 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1531 panic("ahci_atapi_scsipi_request: polled command " 1532 "not done"); 1533 #endif 1534 splx(s); 1535 return; 1536 default: 1537 /* Not supported, nothing to do. */ 1538 ; 1539 } 1540 } 1541 1542 static void 1543 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1544 { 1545 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1546 struct ahci_channel *achp = (struct ahci_channel *)chp; 1547 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1548 int slot = 0 /* XXX slot */; 1549 struct ahci_cmd_tbl *cmd_tbl; 1550 struct ahci_cmd_header *cmd_h; 1551 int i; 1552 int channel = chp->ch_channel; 1553 1554 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1555 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1556 1557 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1558 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1559 cmd_tbl), DEBUG_XFERS); 1560 1561 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1562 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1563 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1564 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1565 1566 cmd_h = &achp->ahcic_cmdh[slot]; 1567 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1568 chp->ch_channel, cmd_h), DEBUG_XFERS); 1569 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1570 sc_xfer->datalen, 1571 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1572 BUS_DMA_READ : BUS_DMA_WRITE)) { 1573 sc_xfer->error = XS_DRIVER_STUFFUP; 1574 ahci_atapi_complete(chp, xfer, slot); 1575 return; 1576 } 1577 cmd_h->cmdh_flags = htole16( 1578 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1579 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1580 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1581 cmd_h->cmdh_prdbc = 0; 1582 AHCI_CMDH_SYNC(sc, achp, slot, 1583 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1584 1585 if (xfer->c_flags & C_POLL) { 1586 /* polled command, disable interrupts */ 1587 AHCI_WRITE(sc, AHCI_GHC, 1588 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1589 } 1590 chp->ch_flags |= ATACH_IRQ_WAIT; 1591 chp->ch_status = 0; 1592 /* start command */ 1593 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1594 /* and says we started this command */ 1595 achp->ahcic_cmds_active |= 1 << slot; 1596 1597 if ((xfer->c_flags & C_POLL) == 0) { 1598 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1599 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1600 ahci_timeout, chp); 1601 return; 1602 } 1603 /* 1604 * Polled command. 1605 */ 1606 for (i = 0; i < ATA_DELAY / 10; i++) { 1607 if (sc_xfer->xs_status & XS_STS_DONE) 1608 break; 1609 ahci_intr_port(sc, achp); 1610 delay(10000); 1611 } 1612 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1613 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1614 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1615 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1616 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1617 DEBUG_XFERS); 1618 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1619 sc_xfer->error = XS_TIMEOUT; 1620 ahci_atapi_complete(chp, xfer, slot); 1621 } 1622 /* reenable interrupts */ 1623 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1624 } 1625 1626 static int 1627 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1628 { 1629 int slot = 0; /* XXX slot */ 1630 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1631 int drive = xfer->c_drive; 1632 struct ahci_channel *achp = (struct ahci_channel *)chp; 1633 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1634 1635 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1636 DEBUG_FUNCS); 1637 1638 achp->ahcic_cmds_active &= ~(1 << slot); 1639 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1640 if (xfer->c_flags & C_TIMEOU) { 1641 sc_xfer->error = XS_TIMEOUT; 1642 } else { 1643 callout_stop(&chp->ch_callout); 1644 sc_xfer->error = 0; 1645 } 1646 1647 chp->ch_queue->active_xfer = NULL; 1648 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1649 achp->ahcic_datad[slot]->dm_mapsize, 1650 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1651 BUS_DMASYNC_POSTWRITE); 1652 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1653 1654 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1655 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1656 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1657 wakeup(&chp->ch_queue->active_xfer); 1658 return 0; 1659 } 1660 ata_free_xfer(chp, xfer); 1661 1662 AHCI_CMDH_SYNC(sc, achp, slot, 1663 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1664 sc_xfer->resid = sc_xfer->datalen; 1665 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1666 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1667 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1668 if (chp->ch_status & WDCS_ERR && 1669 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1670 sc_xfer->resid == sc_xfer->datalen)) { 1671 sc_xfer->error = XS_SHORTSENSE; 1672 sc_xfer->sense.atapi_sense = chp->ch_error; 1673 if ((sc_xfer->xs_periph->periph_quirks & 1674 PQUIRK_NOSENSE) == 0) { 1675 /* ask scsipi to send a REQUEST_SENSE */ 1676 sc_xfer->error = XS_BUSY; 1677 sc_xfer->status = SCSI_CHECK; 1678 } 1679 } 1680 scsipi_done(sc_xfer); 1681 atastart(chp); 1682 return 0; 1683 } 1684 1685 static void 1686 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1687 { 1688 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1689 struct ahci_channel *achp = (struct ahci_channel *)chp; 1690 int slot = 0; /* XXX slot */ 1691 1692 achp->ahcic_cmds_active &= ~(1 << slot); 1693 1694 /* remove this command from xfer queue */ 1695 switch (reason) { 1696 case KILL_GONE: 1697 sc_xfer->error = XS_DRIVER_STUFFUP; 1698 break; 1699 case KILL_RESET: 1700 sc_xfer->error = XS_RESET; 1701 break; 1702 default: 1703 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1704 panic("ahci_ata_atapi_kill_xfer"); 1705 } 1706 ata_free_xfer(chp, xfer); 1707 scsipi_done(sc_xfer); 1708 } 1709 1710 static void 1711 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1712 { 1713 struct scsipi_channel *chan = sc->sc_channel; 1714 struct scsipi_periph *periph; 1715 struct ataparams ids; 1716 struct ataparams *id = &ids; 1717 struct ahci_softc *ahcic = 1718 device_private(chan->chan_adapter->adapt_dev); 1719 struct atac_softc *atac = &ahcic->sc_atac; 1720 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1721 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1722 struct scsipibus_attach_args sa; 1723 char serial_number[21], model[41], firmware_revision[9]; 1724 int s; 1725 1726 /* skip if already attached */ 1727 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1728 return; 1729 1730 /* if no ATAPI device detected at attach time, skip */ 1731 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1732 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1733 "not present\n", target), DEBUG_PROBE); 1734 return; 1735 } 1736 1737 /* Some ATAPI devices need a bit more time after software reset. */ 1738 delay(5000); 1739 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1740 #ifdef ATAPI_DEBUG_PROBE 1741 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1742 AHCINAME(ahcic), target, 1743 id->atap_config & ATAPI_CFG_CMD_MASK, 1744 id->atap_config & ATAPI_CFG_DRQ_MASK); 1745 #endif 1746 periph = scsipi_alloc_periph(M_NOWAIT); 1747 if (periph == NULL) { 1748 aprint_error_dev(sc->sc_dev, 1749 "unable to allocate periph for drive %d\n", 1750 target); 1751 return; 1752 } 1753 periph->periph_dev = NULL; 1754 periph->periph_channel = chan; 1755 periph->periph_switch = &atapi_probe_periphsw; 1756 periph->periph_target = target; 1757 periph->periph_lun = 0; 1758 periph->periph_quirks = PQUIRK_ONLYBIG; 1759 1760 #ifdef SCSIPI_DEBUG 1761 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1762 SCSIPI_DEBUG_TARGET == target) 1763 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1764 #endif 1765 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1766 if (id->atap_config & ATAPI_CFG_REMOV) 1767 periph->periph_flags |= PERIPH_REMOVABLE; 1768 if (periph->periph_type == T_SEQUENTIAL) { 1769 s = splbio(); 1770 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1771 splx(s); 1772 } 1773 1774 sa.sa_periph = periph; 1775 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1776 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1777 T_REMOV : T_FIXED; 1778 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1779 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1780 20); 1781 scsipi_strvis((u_char *)firmware_revision, 8, 1782 id->atap_revision, 8); 1783 sa.sa_inqbuf.vendor = model; 1784 sa.sa_inqbuf.product = serial_number; 1785 sa.sa_inqbuf.revision = firmware_revision; 1786 1787 /* 1788 * Determine the operating mode capabilities of the device. 1789 */ 1790 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1791 periph->periph_cap |= PERIPH_CAP_CMD16; 1792 /* XXX This is gross. */ 1793 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1794 1795 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1796 1797 if (drvp->drv_softc) 1798 ata_probe_caps(drvp); 1799 else { 1800 s = splbio(); 1801 drvp->drive_type = ATA_DRIVET_NONE; 1802 splx(s); 1803 } 1804 } else { 1805 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1806 "failed for drive %s:%d:%d: error 0x%x\n", 1807 AHCINAME(ahcic), chp->ch_channel, target, 1808 chp->ch_error), DEBUG_PROBE); 1809 s = splbio(); 1810 drvp->drive_type = ATA_DRIVET_NONE; 1811 splx(s); 1812 } 1813 } 1814 #endif /* NATAPIBUS */ 1815
Indexes created Tue Sep 23 23:09:58 GMT 2025