ahcisata_core.c revision 1.43.2.2
1 /* $NetBSD: ahcisata_core.c,v 1.43.2.2 2012/11/20 03:02:02 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.43.2.2 2012/11/20 03:02:02 tls Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 62 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 63 static void ahci_reset_channel(struct ata_channel *, int); 64 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 65 static int ahci_ata_addref(struct ata_drive_datas *); 66 static void ahci_ata_delref(struct ata_drive_datas *); 67 static void ahci_killpending(struct ata_drive_datas *); 68 69 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 70 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 74 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 75 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 77 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 78 int, int); 79 static void ahci_timeout(void *); 80 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 static void ahci_atapibus_attach(struct atabus_softc *); 84 static void ahci_atapi_kill_pending(struct scsipi_periph *); 85 static void ahci_atapi_minphys(struct buf *); 86 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 NULL, 100 }; 101 #endif /* NATAPIBUS */ 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 105 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 106 107 const struct ata_bustype ahci_ata_bustype = { 108 SCSIPI_BUSTYPE_ATA, 109 ahci_ata_bio, 110 ahci_reset_drive, 111 ahci_reset_channel, 112 ahci_exec_command, 113 ata_get_params, 114 ahci_ata_addref, 115 ahci_ata_delref, 116 ahci_killpending 117 }; 118 119 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 static int 123 ahci_reset(struct ahci_softc *sc) 124 { 125 int i; 126 127 /* reset controller */ 128 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 129 /* wait up to 1s for reset to complete */ 130 for (i = 0; i < 1000; i++) { 131 delay(1000); 132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 133 break; 134 } 135 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 136 aprint_error("%s: reset failed\n", AHCINAME(sc)); 137 return -1; 138 } 139 /* enable ahci mode */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 141 return 0; 142 } 143 144 static void 145 ahci_setup_ports(struct ahci_softc *sc) 146 { 147 uint32_t ahci_ports; 148 int i, port; 149 150 ahci_ports = AHCI_READ(sc, AHCI_PI); 151 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 152 if ((ahci_ports & (1 << i)) == 0) 153 continue; 154 if (port >= sc->sc_atac.atac_nchannels) { 155 aprint_error("%s: more ports than announced\n", 156 AHCINAME(sc)); 157 break; 158 } 159 ahci_setup_port(sc, i); 160 } 161 } 162 163 static void 164 ahci_reprobe_drives(struct ahci_softc *sc) 165 { 166 uint32_t ahci_ports; 167 int i, port; 168 struct ahci_channel *achp; 169 struct ata_channel *chp; 170 171 ahci_ports = AHCI_READ(sc, AHCI_PI); 172 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 173 if ((ahci_ports & (1 << i)) == 0) 174 continue; 175 if (port >= sc->sc_atac.atac_nchannels) { 176 aprint_error("%s: more ports than announced\n", 177 AHCINAME(sc)); 178 break; 179 } 180 achp = &sc->sc_channels[i]; 181 chp = &achp->ata_channel; 182 183 ahci_probe_drive(chp); 184 } 185 } 186 187 static void 188 ahci_setup_port(struct ahci_softc *sc, int i) 189 { 190 struct ahci_channel *achp; 191 192 achp = &sc->sc_channels[i]; 193 194 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 195 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 196 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 197 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 198 } 199 200 static void 201 ahci_enable_intrs(struct ahci_softc *sc) 202 { 203 204 /* clear interrupts */ 205 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 206 /* enable interrupts */ 207 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 208 } 209 210 void 211 ahci_attach(struct ahci_softc *sc) 212 { 213 uint32_t ahci_rev, ahci_ports; 214 int i, j, port; 215 struct ahci_channel *achp; 216 struct ata_channel *chp; 217 int error; 218 int dmasize; 219 char buf[128]; 220 void *cmdhp; 221 void *cmdtblp; 222 223 if (ahci_reset(sc) != 0) 224 return; 225 226 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 227 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 228 aprint_verbose_dev(sc->sc_atac.atac_dev, 229 "ignoring broken port multiplier support\n"); 230 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 231 } 232 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 233 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 234 ahci_rev = AHCI_READ(sc, AHCI_VS); 235 snprintb(buf, sizeof(buf), "\177\020" 236 /* "f\000\005NP\0" */ 237 "b\005SXS\0" 238 "b\006EMS\0" 239 "b\007CCCS\0" 240 /* "f\010\005NCS\0" */ 241 "b\015PSC\0" 242 "b\016SSC\0" 243 "b\017PMD\0" 244 "b\020FBSS\0" 245 "b\021SPM\0" 246 "b\022SAM\0" 247 "b\023SNZO\0" 248 "f\024\003ISS\0" 249 "=\001Gen1\0" 250 "=\002Gen2\0" 251 "=\003Gen3\0" 252 "b\030SCLO\0" 253 "b\031SAL\0" 254 "b\032SALP\0" 255 "b\033SSS\0" 256 "b\034SMPS\0" 257 "b\035SSNTF\0" 258 "b\036SNCQ\0" 259 "b\037S64A\0" 260 "\0", sc->sc_ahci_cap); 261 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 262 ", %d ports, %d slots, CAP %s\n", 263 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 264 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 265 266 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 267 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 268 sc->sc_atac.atac_pio_cap = 4; 269 sc->sc_atac.atac_dma_cap = 2; 270 sc->sc_atac.atac_udma_cap = 6; 271 sc->sc_atac.atac_channels = sc->sc_chanarray; 272 sc->sc_atac.atac_probe = ahci_probe_drive; 273 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 274 sc->sc_atac.atac_set_modes = ahci_setup_channel; 275 #if NATAPIBUS > 0 276 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 277 #endif 278 279 dmasize = 280 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 281 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 282 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 283 if (error) { 284 aprint_error("%s: unable to allocate command header memory" 285 ", error=%d\n", AHCINAME(sc), error); 286 return; 287 } 288 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 289 sc->sc_cmd_hdr_nseg, dmasize, 290 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 291 if (error) { 292 aprint_error("%s: unable to map command header memory" 293 ", error=%d\n", AHCINAME(sc), error); 294 return; 295 } 296 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 297 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 298 if (error) { 299 aprint_error("%s: unable to create command header map" 300 ", error=%d\n", AHCINAME(sc), error); 301 return; 302 } 303 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 304 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 305 if (error) { 306 aprint_error("%s: unable to load command header map" 307 ", error=%d\n", AHCINAME(sc), error); 308 return; 309 } 310 sc->sc_cmd_hdr = cmdhp; 311 312 ahci_enable_intrs(sc); 313 314 ahci_ports = AHCI_READ(sc, AHCI_PI); 315 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 316 if ((ahci_ports & (1 << i)) == 0) 317 continue; 318 if (port >= sc->sc_atac.atac_nchannels) { 319 aprint_error("%s: more ports than announced\n", 320 AHCINAME(sc)); 321 break; 322 } 323 achp = &sc->sc_channels[i]; 324 chp = &achp->ata_channel; 325 sc->sc_chanarray[i] = chp; 326 chp->ch_channel = i; 327 chp->ch_atac = &sc->sc_atac; 328 chp->ch_queue = malloc(sizeof(struct ata_queue), 329 M_DEVBUF, M_NOWAIT); 330 if (chp->ch_queue == NULL) { 331 aprint_error("%s port %d: can't allocate memory for " 332 "command queue", AHCINAME(sc), i); 333 break; 334 } 335 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 338 BUS_DMA_NOWAIT); 339 if (error) { 340 aprint_error("%s: unable to allocate command table " 341 "memory, error=%d\n", AHCINAME(sc), error); 342 break; 343 } 344 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 345 achp->ahcic_cmd_tbl_nseg, dmasize, 346 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 347 if (error) { 348 aprint_error("%s: unable to map command table memory" 349 ", error=%d\n", AHCINAME(sc), error); 350 break; 351 } 352 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 353 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 354 if (error) { 355 aprint_error("%s: unable to create command table map" 356 ", error=%d\n", AHCINAME(sc), error); 357 break; 358 } 359 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 360 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 361 if (error) { 362 aprint_error("%s: unable to load command table map" 363 ", error=%d\n", AHCINAME(sc), error); 364 break; 365 } 366 achp->ahcic_cmdh = (struct ahci_cmd_header *) 367 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 368 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 369 AHCI_CMDH_SIZE * port; 370 achp->ahcic_rfis = (struct ahci_r_fis *) 371 ((char *)cmdhp + 372 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 373 AHCI_RFIS_SIZE * port); 374 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 375 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 376 AHCI_RFIS_SIZE * port; 377 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 378 "rfis %p (0x%" PRIx64 ")\n", i, 379 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 380 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 381 DEBUG_PROBE); 382 383 for (j = 0; j < sc->sc_ncmds; j++) { 384 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 385 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 386 achp->ahcic_bus_cmd_tbl[j] = 387 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 388 AHCI_CMDTBL_SIZE * j; 389 achp->ahcic_cmdh[j].cmdh_cmdtba = 390 htole64(achp->ahcic_bus_cmd_tbl[j]); 391 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 392 achp->ahcic_cmd_tbl[j], 393 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 394 /* The xfer DMA map */ 395 error = bus_dmamap_create(sc->sc_dmat, 396 sc->sc_atac.atac_dev->dv_maxphys, 397 AHCI_NPRD, 0x400000 /* 4MB */, 0, 398 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 399 &achp->ahcic_datad[j]); 400 if (error) { 401 aprint_error("%s: couldn't alloc xfer DMA map, " 402 "error=%d\n", AHCINAME(sc), error); 403 goto end; 404 } 405 } 406 ahci_setup_port(sc, i); 407 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 408 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 409 aprint_error("%s: couldn't map channel %d " 410 "sata_status regs\n", AHCINAME(sc), i); 411 break; 412 } 413 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 414 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 415 aprint_error("%s: couldn't map channel %d " 416 "sata_control regs\n", AHCINAME(sc), i); 417 break; 418 } 419 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 420 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 421 aprint_error("%s: couldn't map channel %d " 422 "sata_error regs\n", AHCINAME(sc), i); 423 break; 424 } 425 ata_channel_attach(chp); 426 port++; 427 end: 428 continue; 429 } 430 } 431 432 int 433 ahci_detach(struct ahci_softc *sc, int flags) 434 { 435 struct atac_softc *atac; 436 struct ahci_channel *achp; 437 struct ata_channel *chp; 438 struct scsipi_adapter *adapt; 439 uint32_t ahci_ports; 440 int i, j; 441 int error; 442 443 atac = &sc->sc_atac; 444 adapt = &atac->atac_atapi_adapter._generic; 445 446 ahci_ports = AHCI_READ(sc, AHCI_PI); 447 for (i = 0; i < AHCI_MAX_PORTS; i++) { 448 achp = &sc->sc_channels[i]; 449 chp = &achp->ata_channel; 450 451 if ((ahci_ports & (1 << i)) == 0) 452 continue; 453 if (i >= sc->sc_atac.atac_nchannels) { 454 aprint_error("%s: more ports than announced\n", 455 AHCINAME(sc)); 456 break; 457 } 458 459 if (chp->atabus == NULL) 460 continue; 461 if ((error = config_detach(chp->atabus, flags)) != 0) 462 return error; 463 464 for (j = 0; j < sc->sc_ncmds; j++) 465 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 466 467 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 468 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 469 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 470 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 471 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 472 achp->ahcic_cmd_tbl_nseg); 473 474 free(chp->ch_queue, M_DEVBUF); 475 chp->atabus = NULL; 476 } 477 478 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 479 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 480 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 481 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 482 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 483 484 if (adapt->adapt_refcnt != 0) 485 return EBUSY; 486 487 return 0; 488 } 489 490 void 491 ahci_resume(struct ahci_softc *sc) 492 { 493 ahci_reset(sc); 494 ahci_setup_ports(sc); 495 ahci_reprobe_drives(sc); 496 ahci_enable_intrs(sc); 497 } 498 499 int 500 ahci_intr(void *v) 501 { 502 struct ahci_softc *sc = v; 503 uint32_t is; 504 int i, r = 0; 505 506 while ((is = AHCI_READ(sc, AHCI_IS))) { 507 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 508 DEBUG_INTR); 509 r = 1; 510 AHCI_WRITE(sc, AHCI_IS, is); 511 for (i = 0; i < AHCI_MAX_PORTS; i++) 512 if (is & (1 << i)) 513 ahci_intr_port(sc, &sc->sc_channels[i]); 514 } 515 return r; 516 } 517 518 static void 519 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 520 { 521 uint32_t is, tfd; 522 struct ata_channel *chp = &achp->ata_channel; 523 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 524 int slot; 525 526 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 527 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 528 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 529 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 530 DEBUG_INTR); 531 532 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 533 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 534 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 535 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 536 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 537 return; 538 /* stop channel */ 539 ahci_channel_stop(sc, chp, 0); 540 if (slot != 0) { 541 printf("ahci_intr_port: slot %d\n", slot); 542 panic("ahci_intr_port"); 543 } 544 if (is & AHCI_P_IX_TFES) { 545 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 546 chp->ch_error = 547 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 548 chp->ch_status = (tfd & 0xff); 549 } else { 550 /* emulate a CRC error */ 551 chp->ch_error = WDCE_CRC; 552 chp->ch_status = WDCS_ERR; 553 } 554 if (is & AHCI_P_IX_IFS) { 555 aprint_error("%s port %d: SERR 0x%x\n", 556 AHCINAME(sc), chp->ch_channel, 557 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 558 } 559 xfer->c_intr(chp, xfer, is); 560 /* if channel has not been restarted, do it now */ 561 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 562 == 0) 563 ahci_channel_start(sc, chp, 0, 0); 564 } else { 565 slot = 0; /* XXX */ 566 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 567 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 568 chp->ch_channel, is, achp->ahcic_cmds_active, 569 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 570 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 571 return; 572 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 573 == 0) { 574 xfer->c_intr(chp, xfer, 0); 575 } 576 } 577 } 578 579 static void 580 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 581 { 582 struct ata_channel *chp = drvp->chnl_softc; 583 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 584 AHCI_WRITE(sc, AHCI_GHC, 585 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 586 ahci_channel_stop(sc, chp, flags); 587 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 588 ata_reset_channel(chp, flags); 589 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 590 return; 591 } 592 593 /* return error code from ata_bio */ 594 static int 595 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 596 { 597 struct ahci_channel *achp = (struct ahci_channel *)chp; 598 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 599 int i; 600 uint32_t is; 601 602 timeout = timeout * 10; /* wait is 10ms */ 603 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 604 /* start command */ 605 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 606 for (i = 0; i < timeout; i++) { 607 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 608 return 0; 609 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 610 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 611 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 612 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 613 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 614 /* 615 * we got the D2H FIS anyway, 616 * assume sig is valid. 617 * channel is restarted later 618 */ 619 return ERROR; 620 } 621 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 622 AHCINAME(sc), chp->ch_channel, is); 623 return ERR_DF; 624 } 625 if (flags & AT_WAIT) 626 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 627 else 628 delay(10000); 629 } 630 aprint_debug("%s channel %d: timeout sending FIS\n", 631 AHCINAME(sc), chp->ch_channel); 632 return TIMEOUT; 633 } 634 635 static int 636 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 637 uint32_t *sigp) 638 { 639 struct ahci_channel *achp = (struct ahci_channel *)chp; 640 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 641 struct ahci_cmd_tbl *cmd_tbl; 642 struct ahci_cmd_header *cmd_h; 643 int i; 644 uint32_t sig; 645 646 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 647 again: 648 /* clear port interrupt register */ 649 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 650 /* clear SErrors and start operations */ 651 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 652 /* 653 * issue a command list override to clear BSY. 654 * This is needed if there's a PMP with no drive 655 * on port 0 656 */ 657 ahci_channel_start(sc, chp, flags, 1); 658 } else { 659 ahci_channel_start(sc, chp, flags, 0); 660 } 661 if (drive > 0) { 662 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 663 } 664 /* polled command, assume interrupts are disabled */ 665 /* use slot 0 to send reset, the channel is idle */ 666 cmd_h = &achp->ahcic_cmdh[0]; 667 cmd_tbl = achp->ahcic_cmd_tbl[0]; 668 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 669 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 670 cmd_h->cmdh_prdbc = 0; 671 memset(cmd_tbl->cmdt_cfis, 0, 64); 672 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 673 cmd_tbl->cmdt_cfis[rhd_c] = drive; 674 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 675 switch(ahci_exec_fis(chp, 1, flags)) { 676 case ERR_DF: 677 case TIMEOUT: 678 aprint_error("%s channel %d: setting WDCTL_RST failed " 679 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 680 if (sigp) 681 *sigp = 0xffffffff; 682 goto end; 683 default: 684 break; 685 } 686 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 687 (drive << AHCI_CMDH_F_PMP_SHIFT)); 688 cmd_h->cmdh_prdbc = 0; 689 memset(cmd_tbl->cmdt_cfis, 0, 64); 690 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 691 cmd_tbl->cmdt_cfis[rhd_c] = drive; 692 cmd_tbl->cmdt_cfis[rhd_control] = 0; 693 switch(ahci_exec_fis(chp, 31, flags)) { 694 case ERR_DF: 695 case TIMEOUT: 696 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 697 drive == PMP_PORT_CTL) { 698 /* 699 * some controllers fails to reset when 700 * targeting a PMP but a single drive is attached. 701 * try again with port 0 702 */ 703 drive = 0; 704 ahci_channel_stop(sc, chp, flags); 705 goto again; 706 } 707 aprint_error("%s channel %d: clearing WDCTL_RST failed " 708 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 709 if (sigp) 710 *sigp = 0xffffffff; 711 goto end; 712 default: 713 break; 714 } 715 /* 716 * wait 31s for BSY to clear 717 * This should not be needed, but some controllers clear the 718 * command slot before receiving the D2H FIS ... 719 */ 720 for (i = 0; i <AHCI_RST_WAIT; i++) { 721 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 722 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 723 & WDCS_BSY) == 0) 724 break; 725 if (flags & AT_WAIT) 726 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 727 else 728 delay(10000); 729 } 730 if (i == AHCI_RST_WAIT) { 731 aprint_error("%s: BSY never cleared, TD 0x%x\n", 732 AHCINAME(sc), sig); 733 if (sigp) 734 *sigp = 0xffffffff; 735 goto end; 736 } 737 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 738 DEBUG_PROBE); 739 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 740 if (sigp) 741 *sigp = sig; 742 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 743 AHCINAME(sc), chp->ch_channel, sig, 744 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 745 end: 746 ahci_channel_stop(sc, chp, flags); 747 if (flags & AT_WAIT) 748 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 749 else 750 delay(500000); 751 /* clear port interrupt register */ 752 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 753 ahci_channel_start(sc, chp, AT_WAIT, 754 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 755 return 0; 756 } 757 758 static void 759 ahci_reset_channel(struct ata_channel *chp, int flags) 760 { 761 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 762 struct ahci_channel *achp = (struct ahci_channel *)chp; 763 int i, tfd; 764 765 ahci_channel_stop(sc, chp, flags); 766 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 767 achp->ahcic_sstatus) != SStatus_DET_DEV) { 768 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 769 /* XXX and then ? */ 770 } 771 if (chp->ch_queue->active_xfer) { 772 chp->ch_queue->active_xfer->c_kill_xfer(chp, 773 chp->ch_queue->active_xfer, KILL_RESET); 774 } 775 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 776 /* clear port interrupt register */ 777 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 778 /* clear SErrors and start operations */ 779 ahci_channel_start(sc, chp, flags, 1); 780 /* wait 31s for BSY to clear */ 781 for (i = 0; i <AHCI_RST_WAIT; i++) { 782 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 783 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 784 & WDCS_BSY) == 0) 785 break; 786 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 787 } 788 if (i == AHCI_RST_WAIT) 789 aprint_error("%s: BSY never cleared, TD 0x%x\n", 790 AHCINAME(sc), tfd); 791 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 792 DEBUG_PROBE); 793 /* clear port interrupt register */ 794 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 795 796 return; 797 } 798 799 static int 800 ahci_ata_addref(struct ata_drive_datas *drvp) 801 { 802 return 0; 803 } 804 805 static void 806 ahci_ata_delref(struct ata_drive_datas *drvp) 807 { 808 return; 809 } 810 811 static void 812 ahci_killpending(struct ata_drive_datas *drvp) 813 { 814 return; 815 } 816 817 static void 818 ahci_probe_drive(struct ata_channel *chp) 819 { 820 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 821 struct ahci_channel *achp = (struct ahci_channel *)chp; 822 uint32_t sig; 823 824 /* bring interface up, accept FISs, power up and spin up device */ 825 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 826 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 827 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 828 /* reset the PHY and bring online */ 829 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 830 achp->ahcic_sstatus)) { 831 case SStatus_DET_DEV: 832 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 833 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 834 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 835 } else { 836 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 837 } 838 sata_interpret_sig(chp, 0, sig); 839 /* if we have a PMP attached, inform the controller */ 840 if (chp->ch_ndrives > PMP_PORT_CTL && 841 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 842 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 843 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 844 AHCI_P_CMD_PMA); 845 } 846 /* clear port interrupt register */ 847 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 848 849 /* and enable interrupts */ 850 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 851 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 852 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 853 AHCI_P_IX_PSS | AHCI_P_IX_DHRS); 854 /* wait 500ms before actually starting operations */ 855 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 856 break; 857 858 default: 859 break; 860 } 861 } 862 863 static void 864 ahci_setup_channel(struct ata_channel *chp) 865 { 866 return; 867 } 868 869 static int 870 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 871 { 872 struct ata_channel *chp = drvp->chnl_softc; 873 struct ata_xfer *xfer; 874 int ret; 875 int s; 876 877 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 878 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 879 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 880 DEBUG_XFERS); 881 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 882 ATAXF_NOSLEEP); 883 if (xfer == NULL) { 884 return ATACMD_TRY_AGAIN; 885 } 886 if (ata_c->flags & AT_POLL) 887 xfer->c_flags |= C_POLL; 888 if (ata_c->flags & AT_WAIT) 889 xfer->c_flags |= C_WAIT; 890 xfer->c_drive = drvp->drive; 891 xfer->c_databuf = ata_c->data; 892 xfer->c_bcount = ata_c->bcount; 893 xfer->c_cmd = ata_c; 894 xfer->c_start = ahci_cmd_start; 895 xfer->c_intr = ahci_cmd_complete; 896 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 897 s = splbio(); 898 ata_exec_xfer(chp, xfer); 899 #ifdef DIAGNOSTIC 900 if ((ata_c->flags & AT_POLL) != 0 && 901 (ata_c->flags & AT_DONE) == 0) 902 panic("ahci_exec_command: polled command not done"); 903 #endif 904 if (ata_c->flags & AT_DONE) { 905 ret = ATACMD_COMPLETE; 906 } else { 907 if (ata_c->flags & AT_WAIT) { 908 while ((ata_c->flags & AT_DONE) == 0) { 909 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 910 } 911 ret = ATACMD_COMPLETE; 912 } else { 913 ret = ATACMD_QUEUED; 914 } 915 } 916 splx(s); 917 return ret; 918 } 919 920 static void 921 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 922 { 923 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 924 struct ahci_channel *achp = (struct ahci_channel *)chp; 925 struct ata_command *ata_c = xfer->c_cmd; 926 int slot = 0 /* XXX slot */; 927 struct ahci_cmd_tbl *cmd_tbl; 928 struct ahci_cmd_header *cmd_h; 929 int i; 930 int channel = chp->ch_channel; 931 932 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n", 933 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout), 934 DEBUG_XFERS); 935 936 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 937 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 938 cmd_tbl), DEBUG_XFERS); 939 940 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 941 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 942 943 cmd_h = &achp->ahcic_cmdh[slot]; 944 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 945 chp->ch_channel, cmd_h), DEBUG_XFERS); 946 if (ahci_dma_setup(chp, slot, 947 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 948 ata_c->data : NULL, 949 ata_c->bcount, 950 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 951 ata_c->flags |= AT_DF; 952 ahci_cmd_complete(chp, xfer, slot); 953 return; 954 } 955 cmd_h->cmdh_flags = htole16( 956 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 957 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 958 cmd_h->cmdh_prdbc = 0; 959 AHCI_CMDH_SYNC(sc, achp, slot, 960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 961 962 if (ata_c->flags & AT_POLL) { 963 /* polled command, disable interrupts */ 964 AHCI_WRITE(sc, AHCI_GHC, 965 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 966 } 967 chp->ch_flags |= ATACH_IRQ_WAIT; 968 chp->ch_status = 0; 969 /* start command */ 970 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 971 /* and says we started this command */ 972 achp->ahcic_cmds_active |= 1 << slot; 973 974 if ((ata_c->flags & AT_POLL) == 0) { 975 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 976 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 977 ahci_timeout, chp); 978 return; 979 } 980 /* 981 * Polled command. 982 */ 983 for (i = 0; i < ata_c->timeout / 10; i++) { 984 if (ata_c->flags & AT_DONE) 985 break; 986 ahci_intr_port(sc, achp); 987 if (ata_c->flags & AT_WAIT) 988 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 989 else 990 delay(10000); 991 } 992 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 993 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 994 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 995 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 996 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 997 DEBUG_XFERS); 998 if ((ata_c->flags & AT_DONE) == 0) { 999 ata_c->flags |= AT_TIMEOU; 1000 ahci_cmd_complete(chp, xfer, slot); 1001 } 1002 /* reenable interrupts */ 1003 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1004 } 1005 1006 static void 1007 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1008 { 1009 struct ata_command *ata_c = xfer->c_cmd; 1010 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1011 DEBUG_FUNCS); 1012 1013 switch (reason) { 1014 case KILL_GONE: 1015 ata_c->flags |= AT_GONE; 1016 break; 1017 case KILL_RESET: 1018 ata_c->flags |= AT_RESET; 1019 break; 1020 default: 1021 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1022 panic("ahci_cmd_kill_xfer"); 1023 } 1024 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1025 } 1026 1027 static int 1028 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1029 { 1030 int slot = 0; /* XXX slot */ 1031 struct ata_command *ata_c = xfer->c_cmd; 1032 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1033 struct ahci_channel *achp = (struct ahci_channel *)chp; 1034 1035 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1036 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1037 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1038 DEBUG_FUNCS); 1039 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1040 if (xfer->c_flags & C_TIMEOU) { 1041 ata_c->flags |= AT_TIMEOU; 1042 } else 1043 callout_stop(&chp->ch_callout); 1044 1045 chp->ch_queue->active_xfer = NULL; 1046 1047 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1048 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1049 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1050 wakeup(&chp->ch_queue->active_xfer); 1051 return 0; 1052 } 1053 1054 if (chp->ch_status & WDCS_BSY) { 1055 ata_c->flags |= AT_TIMEOU; 1056 } else if (chp->ch_status & WDCS_ERR) { 1057 ata_c->r_error = chp->ch_error; 1058 ata_c->flags |= AT_ERROR; 1059 } 1060 1061 if (ata_c->flags & AT_READREG) 1062 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1063 1064 ahci_cmd_done(chp, xfer, slot); 1065 return 0; 1066 } 1067 1068 static void 1069 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1070 { 1071 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1072 struct ahci_channel *achp = (struct ahci_channel *)chp; 1073 struct ata_command *ata_c = xfer->c_cmd; 1074 uint16_t *idwordbuf; 1075 int i; 1076 1077 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n", 1078 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1079 1080 /* this comamnd is not active any more */ 1081 achp->ahcic_cmds_active &= ~(1 << slot); 1082 1083 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1084 bus_dmamap_t map = achp->ahcic_datad[slot]; 1085 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1086 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1087 BUS_DMASYNC_POSTWRITE); 1088 bus_dmamap_unload(sc->sc_dmat, map); 1089 } 1090 1091 AHCI_CMDH_SYNC(sc, achp, slot, 1092 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1093 1094 /* ata(4) expects IDENTIFY data to be in host endianess */ 1095 if (ata_c->r_command == WDCC_IDENTIFY || 1096 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1097 idwordbuf = xfer->c_databuf; 1098 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1099 idwordbuf[i] = le16toh(idwordbuf[i]); 1100 } 1101 } 1102 1103 ata_c->flags |= AT_DONE; 1104 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1105 ata_c->flags |= AT_XFDONE; 1106 1107 ata_free_xfer(chp, xfer); 1108 if (ata_c->flags & AT_WAIT) 1109 wakeup(ata_c); 1110 else if (ata_c->callback) 1111 ata_c->callback(ata_c->callback_arg); 1112 atastart(chp); 1113 return; 1114 } 1115 1116 static int 1117 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1118 { 1119 struct ata_channel *chp = drvp->chnl_softc; 1120 struct ata_xfer *xfer; 1121 1122 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1123 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1124 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1125 DEBUG_XFERS); 1126 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1127 if (xfer == NULL) { 1128 return ATACMD_TRY_AGAIN; 1129 } 1130 if (ata_bio->flags & ATA_POLL) 1131 xfer->c_flags |= C_POLL; 1132 xfer->c_drive = drvp->drive; 1133 xfer->c_cmd = ata_bio; 1134 xfer->c_databuf = ata_bio->databuf; 1135 xfer->c_bcount = ata_bio->bcount; 1136 xfer->c_start = ahci_bio_start; 1137 xfer->c_intr = ahci_bio_complete; 1138 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1139 ata_exec_xfer(chp, xfer); 1140 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1141 } 1142 1143 static void 1144 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1145 { 1146 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1147 struct ahci_channel *achp = (struct ahci_channel *)chp; 1148 struct ata_bio *ata_bio = xfer->c_cmd; 1149 int slot = 0 /* XXX slot */; 1150 struct ahci_cmd_tbl *cmd_tbl; 1151 struct ahci_cmd_header *cmd_h; 1152 int i; 1153 int channel = chp->ch_channel; 1154 1155 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1156 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1157 1158 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1159 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1160 cmd_tbl), DEBUG_XFERS); 1161 1162 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1163 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1164 1165 cmd_h = &achp->ahcic_cmdh[slot]; 1166 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1167 chp->ch_channel, cmd_h), DEBUG_XFERS); 1168 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1169 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1170 ata_bio->error = ERR_DMA; 1171 ata_bio->r_error = 0; 1172 ahci_bio_complete(chp, xfer, slot); 1173 return; 1174 } 1175 cmd_h->cmdh_flags = htole16( 1176 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1177 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1178 cmd_h->cmdh_prdbc = 0; 1179 AHCI_CMDH_SYNC(sc, achp, slot, 1180 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1181 1182 if (xfer->c_flags & C_POLL) { 1183 /* polled command, disable interrupts */ 1184 AHCI_WRITE(sc, AHCI_GHC, 1185 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1186 } 1187 chp->ch_flags |= ATACH_IRQ_WAIT; 1188 chp->ch_status = 0; 1189 /* start command */ 1190 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1191 /* and says we started this command */ 1192 achp->ahcic_cmds_active |= 1 << slot; 1193 1194 if ((xfer->c_flags & C_POLL) == 0) { 1195 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1196 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1197 ahci_timeout, chp); 1198 return; 1199 } 1200 /* 1201 * Polled command. 1202 */ 1203 for (i = 0; i < ATA_DELAY / 10; i++) { 1204 if (ata_bio->flags & ATA_ITSDONE) 1205 break; 1206 ahci_intr_port(sc, achp); 1207 if (ata_bio->flags & ATA_NOSLEEP) 1208 delay(10000); 1209 else 1210 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1211 } 1212 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1213 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1214 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1215 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1216 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1217 DEBUG_XFERS); 1218 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1219 ata_bio->error = TIMEOUT; 1220 ahci_bio_complete(chp, xfer, slot); 1221 } 1222 /* reenable interrupts */ 1223 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1224 } 1225 1226 static void 1227 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1228 { 1229 int slot = 0; /* XXX slot */ 1230 int drive = xfer->c_drive; 1231 struct ata_bio *ata_bio = xfer->c_cmd; 1232 struct ahci_channel *achp = (struct ahci_channel *)chp; 1233 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1234 DEBUG_FUNCS); 1235 1236 achp->ahcic_cmds_active &= ~(1 << slot); 1237 ata_free_xfer(chp, xfer); 1238 ata_bio->flags |= ATA_ITSDONE; 1239 switch (reason) { 1240 case KILL_GONE: 1241 ata_bio->error = ERR_NODEV; 1242 break; 1243 case KILL_RESET: 1244 ata_bio->error = ERR_RESET; 1245 break; 1246 default: 1247 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1248 panic("ahci_bio_kill_xfer"); 1249 } 1250 ata_bio->r_error = WDCE_ABRT; 1251 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1252 } 1253 1254 static int 1255 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1256 { 1257 int slot = 0; /* XXX slot */ 1258 struct ata_bio *ata_bio = xfer->c_cmd; 1259 int drive = xfer->c_drive; 1260 struct ahci_channel *achp = (struct ahci_channel *)chp; 1261 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1262 1263 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1264 DEBUG_FUNCS); 1265 1266 achp->ahcic_cmds_active &= ~(1 << slot); 1267 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1268 if (xfer->c_flags & C_TIMEOU) { 1269 ata_bio->error = TIMEOUT; 1270 } else { 1271 callout_stop(&chp->ch_callout); 1272 ata_bio->error = NOERROR; 1273 } 1274 1275 chp->ch_queue->active_xfer = NULL; 1276 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1277 achp->ahcic_datad[slot]->dm_mapsize, 1278 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1279 BUS_DMASYNC_POSTWRITE); 1280 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1281 1282 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1283 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1284 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1285 wakeup(&chp->ch_queue->active_xfer); 1286 return 0; 1287 } 1288 ata_free_xfer(chp, xfer); 1289 ata_bio->flags |= ATA_ITSDONE; 1290 if (chp->ch_status & WDCS_DWF) { 1291 ata_bio->error = ERR_DF; 1292 } else if (chp->ch_status & WDCS_ERR) { 1293 ata_bio->error = ERROR; 1294 ata_bio->r_error = chp->ch_error; 1295 } else if (chp->ch_status & WDCS_CORR) 1296 ata_bio->flags |= ATA_CORR; 1297 1298 AHCI_CMDH_SYNC(sc, achp, slot, 1299 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1300 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1301 ata_bio->bcount), DEBUG_XFERS); 1302 /* 1303 * if it was a write, complete data buffer may have been transfered 1304 * before error detection; in this case don't use cmdh_prdbc 1305 * as it won't reflect what was written to media. Assume nothing 1306 * was transfered and leave bcount as-is. 1307 */ 1308 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1309 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1310 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1311 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1312 atastart(chp); 1313 return 0; 1314 } 1315 1316 static void 1317 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1318 { 1319 int i; 1320 /* stop channel */ 1321 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1322 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1323 /* wait 1s for channel to stop */ 1324 for (i = 0; i <100; i++) { 1325 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1326 == 0) 1327 break; 1328 if (flags & AT_WAIT) 1329 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1330 else 1331 delay(10000); 1332 } 1333 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1334 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1335 /* XXX controller reset ? */ 1336 return; 1337 } 1338 } 1339 1340 static void 1341 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1342 int flags, int clo) 1343 { 1344 int i; 1345 uint32_t p_cmd; 1346 /* clear error */ 1347 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1348 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1349 1350 if (clo) { 1351 /* issue command list override */ 1352 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1353 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1354 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1355 /* wait 1s for AHCI_CAP_CLO to clear */ 1356 for (i = 0; i <100; i++) { 1357 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1358 AHCI_P_CMD_CLO) == 0) 1359 break; 1360 if (flags & AT_WAIT) 1361 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1362 else 1363 delay(10000); 1364 } 1365 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1366 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1367 /* XXX controller reset ? */ 1368 return; 1369 } 1370 } 1371 /* and start controller */ 1372 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1373 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1374 if (chp->ch_ndrives > PMP_PORT_CTL && 1375 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1376 p_cmd |= AHCI_P_CMD_PMA; 1377 } 1378 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1379 } 1380 1381 static void 1382 ahci_timeout(void *v) 1383 { 1384 struct ata_channel *chp = (struct ata_channel *)v; 1385 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1386 #ifdef AHCI_DEBUG 1387 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1388 #endif 1389 int s = splbio(); 1390 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel))), DEBUG_INTR); 1391 1392 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1393 xfer->c_flags |= C_TIMEOU; 1394 xfer->c_intr(chp, xfer, 0); 1395 } 1396 splx(s); 1397 } 1398 1399 static int 1400 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1401 size_t count, int op) 1402 { 1403 int error, seg; 1404 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1405 struct ahci_channel *achp = (struct ahci_channel *)chp; 1406 struct ahci_cmd_tbl *cmd_tbl; 1407 struct ahci_cmd_header *cmd_h; 1408 1409 cmd_h = &achp->ahcic_cmdh[slot]; 1410 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1411 1412 if (data == NULL) { 1413 cmd_h->cmdh_prdtl = 0; 1414 goto end; 1415 } 1416 1417 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1418 data, count, NULL, 1419 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1420 if (error) { 1421 printf("%s port %d: failed to load xfer: %d\n", 1422 AHCINAME(sc), chp->ch_channel, error); 1423 return error; 1424 } 1425 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1426 achp->ahcic_datad[slot]->dm_mapsize, 1427 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1428 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1429 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1430 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1431 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1432 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1433 } 1434 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1435 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1436 end: 1437 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1438 return 0; 1439 } 1440 1441 #if NATAPIBUS > 0 1442 static void 1443 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1444 { 1445 struct ata_channel *chp = ata_sc->sc_chan; 1446 struct atac_softc *atac = chp->ch_atac; 1447 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1448 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1449 /* 1450 * Fill in the scsipi_adapter. 1451 */ 1452 adapt->adapt_dev = atac->atac_dev; 1453 adapt->adapt_nchannels = atac->atac_nchannels; 1454 adapt->adapt_request = ahci_atapi_scsipi_request; 1455 adapt->adapt_minphys = ahci_atapi_minphys; 1456 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1457 1458 /* 1459 * Fill in the scsipi_channel. 1460 */ 1461 memset(chan, 0, sizeof(*chan)); 1462 chan->chan_adapter = adapt; 1463 chan->chan_bustype = &ahci_atapi_bustype; 1464 chan->chan_channel = chp->ch_channel; 1465 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1466 chan->chan_openings = 1; 1467 chan->chan_max_periph = 1; 1468 chan->chan_ntargets = 1; 1469 chan->chan_nluns = 1; 1470 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1471 atapiprint); 1472 } 1473 1474 static void 1475 ahci_atapi_minphys(struct buf *bp) 1476 { 1477 if (bp->b_bcount > MACHINE_MAXPHYS) 1478 bp->b_bcount = MACHINE_MAXPHYS; 1479 minphys(bp); 1480 } 1481 1482 /* 1483 * Kill off all pending xfers for a periph. 1484 * 1485 * Must be called at splbio(). 1486 */ 1487 static void 1488 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1489 { 1490 struct atac_softc *atac = 1491 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1492 struct ata_channel *chp = 1493 atac->atac_channels[periph->periph_channel->chan_channel]; 1494 1495 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1496 } 1497 1498 static void 1499 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1500 scsipi_adapter_req_t req, void *arg) 1501 { 1502 struct scsipi_adapter *adapt = chan->chan_adapter; 1503 struct scsipi_periph *periph; 1504 struct scsipi_xfer *sc_xfer; 1505 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1506 struct atac_softc *atac = &sc->sc_atac; 1507 struct ata_xfer *xfer; 1508 int channel = chan->chan_channel; 1509 int drive, s; 1510 1511 switch (req) { 1512 case ADAPTER_REQ_RUN_XFER: 1513 sc_xfer = arg; 1514 periph = sc_xfer->xs_periph; 1515 drive = periph->periph_target; 1516 if (!device_is_active(atac->atac_dev)) { 1517 sc_xfer->error = XS_DRIVER_STUFFUP; 1518 scsipi_done(sc_xfer); 1519 return; 1520 } 1521 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1522 if (xfer == NULL) { 1523 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1524 scsipi_done(sc_xfer); 1525 return; 1526 } 1527 1528 if (sc_xfer->xs_control & XS_CTL_POLL) 1529 xfer->c_flags |= C_POLL; 1530 xfer->c_drive = drive; 1531 xfer->c_flags |= C_ATAPI; 1532 xfer->c_cmd = sc_xfer; 1533 xfer->c_databuf = sc_xfer->data; 1534 xfer->c_bcount = sc_xfer->datalen; 1535 xfer->c_start = ahci_atapi_start; 1536 xfer->c_intr = ahci_atapi_complete; 1537 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1538 xfer->c_dscpoll = 0; 1539 s = splbio(); 1540 ata_exec_xfer(atac->atac_channels[channel], xfer); 1541 #ifdef DIAGNOSTIC 1542 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1543 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1544 panic("ahci_atapi_scsipi_request: polled command " 1545 "not done"); 1546 #endif 1547 splx(s); 1548 return; 1549 default: 1550 /* Not supported, nothing to do. */ 1551 ; 1552 } 1553 } 1554 1555 static void 1556 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1557 { 1558 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1559 struct ahci_channel *achp = (struct ahci_channel *)chp; 1560 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1561 int slot = 0 /* XXX slot */; 1562 struct ahci_cmd_tbl *cmd_tbl; 1563 struct ahci_cmd_header *cmd_h; 1564 int i; 1565 int channel = chp->ch_channel; 1566 1567 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1568 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1569 1570 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1571 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1572 cmd_tbl), DEBUG_XFERS); 1573 1574 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1575 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1576 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1577 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1578 1579 cmd_h = &achp->ahcic_cmdh[slot]; 1580 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1581 chp->ch_channel, cmd_h), DEBUG_XFERS); 1582 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1583 sc_xfer->datalen, 1584 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1585 BUS_DMA_READ : BUS_DMA_WRITE)) { 1586 sc_xfer->error = XS_DRIVER_STUFFUP; 1587 ahci_atapi_complete(chp, xfer, slot); 1588 return; 1589 } 1590 cmd_h->cmdh_flags = htole16( 1591 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1592 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1593 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1594 cmd_h->cmdh_prdbc = 0; 1595 AHCI_CMDH_SYNC(sc, achp, slot, 1596 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1597 1598 if (xfer->c_flags & C_POLL) { 1599 /* polled command, disable interrupts */ 1600 AHCI_WRITE(sc, AHCI_GHC, 1601 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1602 } 1603 chp->ch_flags |= ATACH_IRQ_WAIT; 1604 chp->ch_status = 0; 1605 /* start command */ 1606 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1607 /* and says we started this command */ 1608 achp->ahcic_cmds_active |= 1 << slot; 1609 1610 if ((xfer->c_flags & C_POLL) == 0) { 1611 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1612 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1613 ahci_timeout, chp); 1614 return; 1615 } 1616 /* 1617 * Polled command. 1618 */ 1619 for (i = 0; i < ATA_DELAY / 10; i++) { 1620 if (sc_xfer->xs_status & XS_STS_DONE) 1621 break; 1622 ahci_intr_port(sc, achp); 1623 delay(10000); 1624 } 1625 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1626 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1627 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1628 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1629 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1630 DEBUG_XFERS); 1631 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1632 sc_xfer->error = XS_TIMEOUT; 1633 ahci_atapi_complete(chp, xfer, slot); 1634 } 1635 /* reenable interrupts */ 1636 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1637 } 1638 1639 static int 1640 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1641 { 1642 int slot = 0; /* XXX slot */ 1643 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1644 int drive = xfer->c_drive; 1645 struct ahci_channel *achp = (struct ahci_channel *)chp; 1646 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1647 1648 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1649 DEBUG_FUNCS); 1650 1651 achp->ahcic_cmds_active &= ~(1 << slot); 1652 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1653 if (xfer->c_flags & C_TIMEOU) { 1654 sc_xfer->error = XS_TIMEOUT; 1655 } else { 1656 callout_stop(&chp->ch_callout); 1657 sc_xfer->error = 0; 1658 } 1659 1660 chp->ch_queue->active_xfer = NULL; 1661 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1662 achp->ahcic_datad[slot]->dm_mapsize, 1663 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1664 BUS_DMASYNC_POSTWRITE); 1665 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1666 1667 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1668 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1669 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1670 wakeup(&chp->ch_queue->active_xfer); 1671 return 0; 1672 } 1673 ata_free_xfer(chp, xfer); 1674 1675 AHCI_CMDH_SYNC(sc, achp, slot, 1676 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1677 sc_xfer->resid = sc_xfer->datalen; 1678 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1679 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1680 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1681 if (chp->ch_status & WDCS_ERR && 1682 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1683 sc_xfer->resid == sc_xfer->datalen)) { 1684 sc_xfer->error = XS_SHORTSENSE; 1685 sc_xfer->sense.atapi_sense = chp->ch_error; 1686 if ((sc_xfer->xs_periph->periph_quirks & 1687 PQUIRK_NOSENSE) == 0) { 1688 /* ask scsipi to send a REQUEST_SENSE */ 1689 sc_xfer->error = XS_BUSY; 1690 sc_xfer->status = SCSI_CHECK; 1691 } 1692 } 1693 scsipi_done(sc_xfer); 1694 atastart(chp); 1695 return 0; 1696 } 1697 1698 static void 1699 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1700 { 1701 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1702 struct ahci_channel *achp = (struct ahci_channel *)chp; 1703 int slot = 0; /* XXX slot */ 1704 1705 achp->ahcic_cmds_active &= ~(1 << slot); 1706 1707 /* remove this command from xfer queue */ 1708 switch (reason) { 1709 case KILL_GONE: 1710 sc_xfer->error = XS_DRIVER_STUFFUP; 1711 break; 1712 case KILL_RESET: 1713 sc_xfer->error = XS_RESET; 1714 break; 1715 default: 1716 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1717 panic("ahci_ata_atapi_kill_xfer"); 1718 } 1719 ata_free_xfer(chp, xfer); 1720 scsipi_done(sc_xfer); 1721 } 1722 1723 static void 1724 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1725 { 1726 struct scsipi_channel *chan = sc->sc_channel; 1727 struct scsipi_periph *periph; 1728 struct ataparams ids; 1729 struct ataparams *id = &ids; 1730 struct ahci_softc *ahcic = 1731 device_private(chan->chan_adapter->adapt_dev); 1732 struct atac_softc *atac = &ahcic->sc_atac; 1733 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1734 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1735 struct scsipibus_attach_args sa; 1736 char serial_number[21], model[41], firmware_revision[9]; 1737 int s; 1738 1739 /* skip if already attached */ 1740 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1741 return; 1742 1743 /* if no ATAPI device detected at attach time, skip */ 1744 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1745 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1746 "not present\n", target), DEBUG_PROBE); 1747 return; 1748 } 1749 1750 /* Some ATAPI devices need a bit more time after software reset. */ 1751 delay(5000); 1752 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1753 #ifdef ATAPI_DEBUG_PROBE 1754 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1755 AHCINAME(ahcic), target, 1756 id->atap_config & ATAPI_CFG_CMD_MASK, 1757 id->atap_config & ATAPI_CFG_DRQ_MASK); 1758 #endif 1759 periph = scsipi_alloc_periph(M_NOWAIT); 1760 if (periph == NULL) { 1761 aprint_error_dev(sc->sc_dev, 1762 "unable to allocate periph for drive %d\n", 1763 target); 1764 return; 1765 } 1766 periph->periph_dev = NULL; 1767 periph->periph_channel = chan; 1768 periph->periph_switch = &atapi_probe_periphsw; 1769 periph->periph_target = target; 1770 periph->periph_lun = 0; 1771 periph->periph_quirks = PQUIRK_ONLYBIG; 1772 1773 #ifdef SCSIPI_DEBUG 1774 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1775 SCSIPI_DEBUG_TARGET == target) 1776 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1777 #endif 1778 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1779 if (id->atap_config & ATAPI_CFG_REMOV) 1780 periph->periph_flags |= PERIPH_REMOVABLE; 1781 if (periph->periph_type == T_SEQUENTIAL) { 1782 s = splbio(); 1783 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1784 splx(s); 1785 } 1786 1787 sa.sa_periph = periph; 1788 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1789 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1790 T_REMOV : T_FIXED; 1791 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1792 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1793 20); 1794 scsipi_strvis((u_char *)firmware_revision, 8, 1795 id->atap_revision, 8); 1796 sa.sa_inqbuf.vendor = model; 1797 sa.sa_inqbuf.product = serial_number; 1798 sa.sa_inqbuf.revision = firmware_revision; 1799 1800 /* 1801 * Determine the operating mode capabilities of the device. 1802 */ 1803 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1804 periph->periph_cap |= PERIPH_CAP_CMD16; 1805 /* XXX This is gross. */ 1806 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1807 1808 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1809 1810 if (drvp->drv_softc) 1811 ata_probe_caps(drvp); 1812 else { 1813 s = splbio(); 1814 drvp->drive_type = ATA_DRIVET_NONE; 1815 splx(s); 1816 } 1817 } else { 1818 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1819 "failed for drive %s:%d:%d: error 0x%x\n", 1820 AHCINAME(ahcic), chp->ch_channel, target, 1821 chp->ch_error), DEBUG_PROBE); 1822 s = splbio(); 1823 drvp->drive_type = ATA_DRIVET_NONE; 1824 splx(s); 1825 } 1826 } 1827 #endif /* NATAPIBUS */ 1828
Indexes created Fri Oct 17 00:09:41 GMT 2025