ahcisata_core.c revision 1.43.2.5
1 /* $NetBSD: ahcisata_core.c,v 1.43.2.5 2014/08/20 00:03:37 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.43.2.5 2014/08/20 00:03:37 tls Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 62 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 63 static void ahci_reset_channel(struct ata_channel *, int); 64 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 65 static int ahci_ata_addref(struct ata_drive_datas *); 66 static void ahci_ata_delref(struct ata_drive_datas *); 67 static void ahci_killpending(struct ata_drive_datas *); 68 69 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 70 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 74 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 75 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 77 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 78 int, int); 79 static void ahci_timeout(void *); 80 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 static void ahci_atapibus_attach(struct atabus_softc *); 84 static void ahci_atapi_kill_pending(struct scsipi_periph *); 85 static void ahci_atapi_minphys(struct buf *); 86 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 NULL, 100 }; 101 #endif /* NATAPIBUS */ 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 105 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 106 107 const struct ata_bustype ahci_ata_bustype = { 108 SCSIPI_BUSTYPE_ATA, 109 ahci_ata_bio, 110 ahci_reset_drive, 111 ahci_reset_channel, 112 ahci_exec_command, 113 ata_get_params, 114 ahci_ata_addref, 115 ahci_ata_delref, 116 ahci_killpending 117 }; 118 119 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 static void 123 ahci_enable(struct ahci_softc *sc) 124 { 125 uint32_t ghc; 126 127 ghc = AHCI_READ(sc, AHCI_GHC); 128 if (!(ghc & AHCI_GHC_AE)) { 129 ghc |= AHCI_GHC_AE; 130 AHCI_WRITE(sc, AHCI_GHC, ghc); 131 } 132 } 133 134 static int 135 ahci_reset(struct ahci_softc *sc) 136 { 137 int i; 138 139 /* reset controller */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 141 /* wait up to 1s for reset to complete */ 142 for (i = 0; i < 1000; i++) { 143 delay(1000); 144 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 145 break; 146 } 147 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 148 aprint_error("%s: reset failed\n", AHCINAME(sc)); 149 return -1; 150 } 151 /* enable ahci mode */ 152 ahci_enable(sc); 153 154 if (sc->sc_save_init_data) { 155 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 156 if (sc->sc_init_data.cap2) 157 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 158 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 159 } 160 161 return 0; 162 } 163 164 static void 165 ahci_setup_ports(struct ahci_softc *sc) 166 { 167 int i, port; 168 169 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 170 if ((sc->sc_ahci_ports & (1 << i)) == 0) 171 continue; 172 if (port >= sc->sc_atac.atac_nchannels) { 173 aprint_error("%s: more ports than announced\n", 174 AHCINAME(sc)); 175 break; 176 } 177 ahci_setup_port(sc, i); 178 } 179 } 180 181 static void 182 ahci_reprobe_drives(struct ahci_softc *sc) 183 { 184 int i, port; 185 struct ahci_channel *achp; 186 struct ata_channel *chp; 187 188 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 189 if ((sc->sc_ahci_ports & (1 << i)) == 0) 190 continue; 191 if (port >= sc->sc_atac.atac_nchannels) { 192 aprint_error("%s: more ports than announced\n", 193 AHCINAME(sc)); 194 break; 195 } 196 achp = &sc->sc_channels[i]; 197 chp = &achp->ata_channel; 198 199 ahci_probe_drive(chp); 200 } 201 } 202 203 static void 204 ahci_setup_port(struct ahci_softc *sc, int i) 205 { 206 struct ahci_channel *achp; 207 208 achp = &sc->sc_channels[i]; 209 210 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 211 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 212 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 213 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 214 } 215 216 static void 217 ahci_enable_intrs(struct ahci_softc *sc) 218 { 219 220 /* clear interrupts */ 221 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 222 /* enable interrupts */ 223 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 224 } 225 226 void 227 ahci_attach(struct ahci_softc *sc) 228 { 229 uint32_t ahci_rev; 230 int i, j, port; 231 struct ahci_channel *achp; 232 struct ata_channel *chp; 233 int error; 234 int dmasize; 235 char buf[128]; 236 void *cmdhp; 237 void *cmdtblp; 238 239 if (sc->sc_save_init_data) { 240 ahci_enable(sc); 241 242 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 243 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 244 245 ahci_rev = AHCI_READ(sc, AHCI_VS); 246 if (AHCI_VS_MJR(ahci_rev) > 1 || 247 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 248 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 249 } else { 250 sc->sc_init_data.cap2 = 0; 251 } 252 if (sc->sc_init_data.ports == 0) { 253 sc->sc_init_data.ports = sc->sc_ahci_ports; 254 } 255 } 256 257 if (ahci_reset(sc) != 0) 258 return; 259 260 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 261 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 262 aprint_verbose_dev(sc->sc_atac.atac_dev, 263 "ignoring broken port multiplier support\n"); 264 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 265 } 266 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 267 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 268 ahci_rev = AHCI_READ(sc, AHCI_VS); 269 snprintb(buf, sizeof(buf), "\177\020" 270 /* "f\000\005NP\0" */ 271 "b\005SXS\0" 272 "b\006EMS\0" 273 "b\007CCCS\0" 274 /* "f\010\005NCS\0" */ 275 "b\015PSC\0" 276 "b\016SSC\0" 277 "b\017PMD\0" 278 "b\020FBSS\0" 279 "b\021SPM\0" 280 "b\022SAM\0" 281 "b\023SNZO\0" 282 "f\024\003ISS\0" 283 "=\001Gen1\0" 284 "=\002Gen2\0" 285 "=\003Gen3\0" 286 "b\030SCLO\0" 287 "b\031SAL\0" 288 "b\032SALP\0" 289 "b\033SSS\0" 290 "b\034SMPS\0" 291 "b\035SSNTF\0" 292 "b\036SNCQ\0" 293 "b\037S64A\0" 294 "\0", sc->sc_ahci_cap); 295 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 296 ", %d port%s, %d slot%s, CAP %s\n", 297 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 298 sc->sc_atac.atac_nchannels, 299 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 300 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 301 302 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 303 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 304 sc->sc_atac.atac_pio_cap = 4; 305 sc->sc_atac.atac_dma_cap = 2; 306 sc->sc_atac.atac_udma_cap = 6; 307 sc->sc_atac.atac_channels = sc->sc_chanarray; 308 sc->sc_atac.atac_probe = ahci_probe_drive; 309 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 310 sc->sc_atac.atac_set_modes = ahci_setup_channel; 311 #if NATAPIBUS > 0 312 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 313 #endif 314 315 dmasize = 316 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 318 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 319 if (error) { 320 aprint_error("%s: unable to allocate command header memory" 321 ", error=%d\n", AHCINAME(sc), error); 322 return; 323 } 324 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 325 sc->sc_cmd_hdr_nseg, dmasize, 326 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 327 if (error) { 328 aprint_error("%s: unable to map command header memory" 329 ", error=%d\n", AHCINAME(sc), error); 330 return; 331 } 332 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 333 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 334 if (error) { 335 aprint_error("%s: unable to create command header map" 336 ", error=%d\n", AHCINAME(sc), error); 337 return; 338 } 339 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 340 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error("%s: unable to load command header map" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 sc->sc_cmd_hdr = cmdhp; 347 348 ahci_enable_intrs(sc); 349 350 if (sc->sc_ahci_ports == 0) { 351 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 352 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 353 DEBUG_PROBE); 354 } 355 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 356 if ((sc->sc_ahci_ports & (1 << i)) == 0) 357 continue; 358 if (port >= sc->sc_atac.atac_nchannels) { 359 aprint_error("%s: more ports than announced\n", 360 AHCINAME(sc)); 361 break; 362 } 363 achp = &sc->sc_channels[i]; 364 chp = &achp->ata_channel; 365 sc->sc_chanarray[i] = chp; 366 chp->ch_channel = i; 367 chp->ch_atac = &sc->sc_atac; 368 chp->ch_queue = malloc(sizeof(struct ata_queue), 369 M_DEVBUF, M_NOWAIT|M_ZERO); 370 if (chp->ch_queue == NULL) { 371 aprint_error("%s port %d: can't allocate memory for " 372 "command queue", AHCINAME(sc), i); 373 break; 374 } 375 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 376 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 377 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 378 BUS_DMA_NOWAIT); 379 if (error) { 380 aprint_error("%s: unable to allocate command table " 381 "memory, error=%d\n", AHCINAME(sc), error); 382 break; 383 } 384 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 385 achp->ahcic_cmd_tbl_nseg, dmasize, 386 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 387 if (error) { 388 aprint_error("%s: unable to map command table memory" 389 ", error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 393 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 394 if (error) { 395 aprint_error("%s: unable to create command table map" 396 ", error=%d\n", AHCINAME(sc), error); 397 break; 398 } 399 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 400 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 401 if (error) { 402 aprint_error("%s: unable to load command table map" 403 ", error=%d\n", AHCINAME(sc), error); 404 break; 405 } 406 achp->ahcic_cmdh = (struct ahci_cmd_header *) 407 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 408 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 409 AHCI_CMDH_SIZE * port; 410 achp->ahcic_rfis = (struct ahci_r_fis *) 411 ((char *)cmdhp + 412 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 413 AHCI_RFIS_SIZE * port); 414 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 415 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 416 AHCI_RFIS_SIZE * port; 417 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 418 "rfis %p (0x%" PRIx64 ")\n", i, 419 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 420 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 421 DEBUG_PROBE); 422 423 for (j = 0; j < sc->sc_ncmds; j++) { 424 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 425 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 426 achp->ahcic_bus_cmd_tbl[j] = 427 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 428 AHCI_CMDTBL_SIZE * j; 429 achp->ahcic_cmdh[j].cmdh_cmdtba = 430 htole64(achp->ahcic_bus_cmd_tbl[j]); 431 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 432 achp->ahcic_cmd_tbl[j], 433 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 434 /* The xfer DMA map */ 435 error = bus_dmamap_create(sc->sc_dmat, 436 sc->sc_atac.atac_dev->dv_maxphys, 437 AHCI_NPRD, 0x400000 /* 4MB */, 0, 438 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 439 &achp->ahcic_datad[j]); 440 if (error) { 441 aprint_error("%s: couldn't alloc xfer DMA map, " 442 "error=%d\n", AHCINAME(sc), error); 443 goto end; 444 } 445 } 446 ahci_setup_port(sc, i); 447 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 448 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 449 aprint_error("%s: couldn't map channel %d " 450 "sata_status regs\n", AHCINAME(sc), i); 451 break; 452 } 453 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 454 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 455 aprint_error("%s: couldn't map channel %d " 456 "sata_control regs\n", AHCINAME(sc), i); 457 break; 458 } 459 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 460 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 461 aprint_error("%s: couldn't map channel %d " 462 "sata_error regs\n", AHCINAME(sc), i); 463 break; 464 } 465 ata_channel_attach(chp); 466 port++; 467 end: 468 continue; 469 } 470 } 471 472 int 473 ahci_detach(struct ahci_softc *sc, int flags) 474 { 475 struct atac_softc *atac; 476 struct ahci_channel *achp; 477 struct ata_channel *chp; 478 struct scsipi_adapter *adapt; 479 int i, j; 480 int error; 481 482 atac = &sc->sc_atac; 483 adapt = &atac->atac_atapi_adapter._generic; 484 485 for (i = 0; i < AHCI_MAX_PORTS; i++) { 486 achp = &sc->sc_channels[i]; 487 chp = &achp->ata_channel; 488 489 if ((sc->sc_ahci_ports & (1 << i)) == 0) 490 continue; 491 if (i >= sc->sc_atac.atac_nchannels) { 492 aprint_error("%s: more ports than announced\n", 493 AHCINAME(sc)); 494 break; 495 } 496 497 if (chp->atabus == NULL) 498 continue; 499 if ((error = config_detach(chp->atabus, flags)) != 0) 500 return error; 501 502 for (j = 0; j < sc->sc_ncmds; j++) 503 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 504 505 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 506 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 507 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 508 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 509 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 510 achp->ahcic_cmd_tbl_nseg); 511 512 free(chp->ch_queue, M_DEVBUF); 513 chp->atabus = NULL; 514 } 515 516 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 517 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 518 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 519 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 520 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 521 522 if (adapt->adapt_refcnt != 0) 523 return EBUSY; 524 525 return 0; 526 } 527 528 void 529 ahci_resume(struct ahci_softc *sc) 530 { 531 ahci_reset(sc); 532 ahci_setup_ports(sc); 533 ahci_reprobe_drives(sc); 534 ahci_enable_intrs(sc); 535 } 536 537 int 538 ahci_intr(void *v) 539 { 540 struct ahci_softc *sc = v; 541 uint32_t is; 542 int i, r = 0; 543 544 while ((is = AHCI_READ(sc, AHCI_IS))) { 545 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 546 DEBUG_INTR); 547 r = 1; 548 AHCI_WRITE(sc, AHCI_IS, is); 549 for (i = 0; i < AHCI_MAX_PORTS; i++) 550 if (is & (1 << i)) 551 ahci_intr_port(sc, &sc->sc_channels[i]); 552 } 553 return r; 554 } 555 556 static void 557 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 558 { 559 uint32_t is, tfd; 560 struct ata_channel *chp = &achp->ata_channel; 561 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 562 int slot; 563 564 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 565 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 566 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 567 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 568 DEBUG_INTR); 569 570 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 571 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 572 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 573 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 574 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 575 return; 576 /* stop channel */ 577 ahci_channel_stop(sc, chp, 0); 578 if (slot != 0) { 579 printf("ahci_intr_port: slot %d\n", slot); 580 panic("ahci_intr_port"); 581 } 582 if (is & AHCI_P_IX_TFES) { 583 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 584 chp->ch_error = 585 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 586 chp->ch_status = (tfd & 0xff); 587 } else { 588 /* emulate a CRC error */ 589 chp->ch_error = WDCE_CRC; 590 chp->ch_status = WDCS_ERR; 591 } 592 if (is & AHCI_P_IX_IFS) { 593 aprint_error("%s port %d: SERR 0x%x\n", 594 AHCINAME(sc), chp->ch_channel, 595 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 596 } 597 xfer->c_intr(chp, xfer, is); 598 /* if channel has not been restarted, do it now */ 599 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 600 == 0) 601 ahci_channel_start(sc, chp, 0, 0); 602 } else { 603 slot = 0; /* XXX */ 604 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 605 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 606 chp->ch_channel, is, achp->ahcic_cmds_active, 607 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 608 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 609 return; 610 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 611 == 0) { 612 xfer->c_intr(chp, xfer, 0); 613 } 614 } 615 } 616 617 static void 618 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 619 { 620 struct ata_channel *chp = drvp->chnl_softc; 621 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 622 AHCI_WRITE(sc, AHCI_GHC, 623 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 624 ahci_channel_stop(sc, chp, flags); 625 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 626 ata_reset_channel(chp, flags); 627 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 628 return; 629 } 630 631 /* return error code from ata_bio */ 632 static int 633 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 634 { 635 struct ahci_channel *achp = (struct ahci_channel *)chp; 636 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 637 int i; 638 uint32_t is; 639 640 timeout = timeout * 10; /* wait is 10ms */ 641 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 642 /* start command */ 643 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 644 for (i = 0; i < timeout; i++) { 645 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 646 return 0; 647 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 648 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 649 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 650 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 651 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 652 /* 653 * we got the D2H FIS anyway, 654 * assume sig is valid. 655 * channel is restarted later 656 */ 657 return ERROR; 658 } 659 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 660 AHCINAME(sc), chp->ch_channel, is); 661 return ERR_DF; 662 } 663 if (flags & AT_WAIT) 664 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 665 else 666 delay(10000); 667 } 668 aprint_debug("%s channel %d: timeout sending FIS\n", 669 AHCINAME(sc), chp->ch_channel); 670 return TIMEOUT; 671 } 672 673 static int 674 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 675 uint32_t *sigp) 676 { 677 struct ahci_channel *achp = (struct ahci_channel *)chp; 678 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 679 struct ahci_cmd_tbl *cmd_tbl; 680 struct ahci_cmd_header *cmd_h; 681 int i; 682 uint32_t sig; 683 684 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 685 again: 686 /* clear port interrupt register */ 687 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 688 /* clear SErrors and start operations */ 689 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 690 /* 691 * issue a command list override to clear BSY. 692 * This is needed if there's a PMP with no drive 693 * on port 0 694 */ 695 ahci_channel_start(sc, chp, flags, 1); 696 } else { 697 ahci_channel_start(sc, chp, flags, 0); 698 } 699 if (drive > 0) { 700 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 701 } 702 /* polled command, assume interrupts are disabled */ 703 /* use slot 0 to send reset, the channel is idle */ 704 cmd_h = &achp->ahcic_cmdh[0]; 705 cmd_tbl = achp->ahcic_cmd_tbl[0]; 706 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 707 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 708 cmd_h->cmdh_prdbc = 0; 709 memset(cmd_tbl->cmdt_cfis, 0, 64); 710 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 711 cmd_tbl->cmdt_cfis[rhd_c] = drive; 712 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 713 switch(ahci_exec_fis(chp, 1, flags)) { 714 case ERR_DF: 715 case TIMEOUT: 716 aprint_error("%s channel %d: setting WDCTL_RST failed " 717 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 718 if (sigp) 719 *sigp = 0xffffffff; 720 goto end; 721 default: 722 break; 723 } 724 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 725 (drive << AHCI_CMDH_F_PMP_SHIFT)); 726 cmd_h->cmdh_prdbc = 0; 727 memset(cmd_tbl->cmdt_cfis, 0, 64); 728 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 729 cmd_tbl->cmdt_cfis[rhd_c] = drive; 730 cmd_tbl->cmdt_cfis[rhd_control] = 0; 731 switch(ahci_exec_fis(chp, 31, flags)) { 732 case ERR_DF: 733 case TIMEOUT: 734 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 735 drive == PMP_PORT_CTL) { 736 /* 737 * some controllers fails to reset when 738 * targeting a PMP but a single drive is attached. 739 * try again with port 0 740 */ 741 drive = 0; 742 ahci_channel_stop(sc, chp, flags); 743 goto again; 744 } 745 aprint_error("%s channel %d: clearing WDCTL_RST failed " 746 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 747 if (sigp) 748 *sigp = 0xffffffff; 749 goto end; 750 default: 751 break; 752 } 753 /* 754 * wait 31s for BSY to clear 755 * This should not be needed, but some controllers clear the 756 * command slot before receiving the D2H FIS ... 757 */ 758 for (i = 0; i < AHCI_RST_WAIT; i++) { 759 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 760 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 761 break; 762 if (flags & AT_WAIT) 763 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 764 else 765 delay(10000); 766 } 767 if (i == AHCI_RST_WAIT) { 768 aprint_error("%s: BSY never cleared, TD 0x%x\n", 769 AHCINAME(sc), sig); 770 if (sigp) 771 *sigp = 0xffffffff; 772 goto end; 773 } 774 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 775 DEBUG_PROBE); 776 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 777 if (sigp) 778 *sigp = sig; 779 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 780 AHCINAME(sc), chp->ch_channel, sig, 781 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 782 end: 783 ahci_channel_stop(sc, chp, flags); 784 if (flags & AT_WAIT) 785 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 786 else 787 delay(500000); 788 /* clear port interrupt register */ 789 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 790 ahci_channel_start(sc, chp, flags, 791 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 792 return 0; 793 } 794 795 static void 796 ahci_reset_channel(struct ata_channel *chp, int flags) 797 { 798 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 799 struct ahci_channel *achp = (struct ahci_channel *)chp; 800 int i, tfd; 801 802 ahci_channel_stop(sc, chp, flags); 803 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 804 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 805 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 806 /* XXX and then ? */ 807 } 808 if (chp->ch_queue->active_xfer) { 809 chp->ch_queue->active_xfer->c_kill_xfer(chp, 810 chp->ch_queue->active_xfer, KILL_RESET); 811 } 812 ata_delay(500, "ahcirst", flags); 813 /* clear port interrupt register */ 814 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 815 /* clear SErrors and start operations */ 816 ahci_channel_start(sc, chp, flags, 1); 817 /* wait 31s for BSY to clear */ 818 for (i = 0; i <AHCI_RST_WAIT; i++) { 819 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 820 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 821 & WDCS_BSY) == 0) 822 break; 823 ata_delay(10, "ahcid2h", flags); 824 } 825 if (i == AHCI_RST_WAIT) 826 aprint_error("%s: BSY never cleared, TD 0x%x\n", 827 AHCINAME(sc), tfd); 828 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 829 DEBUG_PROBE); 830 /* clear port interrupt register */ 831 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 832 833 return; 834 } 835 836 static int 837 ahci_ata_addref(struct ata_drive_datas *drvp) 838 { 839 return 0; 840 } 841 842 static void 843 ahci_ata_delref(struct ata_drive_datas *drvp) 844 { 845 return; 846 } 847 848 static void 849 ahci_killpending(struct ata_drive_datas *drvp) 850 { 851 return; 852 } 853 854 static void 855 ahci_probe_drive(struct ata_channel *chp) 856 { 857 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 858 struct ahci_channel *achp = (struct ahci_channel *)chp; 859 uint32_t sig; 860 861 /* bring interface up, accept FISs, power up and spin up device */ 862 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 863 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 864 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 865 /* reset the PHY and bring online */ 866 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 867 achp->ahcic_sstatus, AT_WAIT)) { 868 case SStatus_DET_DEV: 869 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 870 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 871 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 872 } else { 873 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 874 } 875 sata_interpret_sig(chp, 0, sig); 876 /* if we have a PMP attached, inform the controller */ 877 if (chp->ch_ndrives > PMP_PORT_CTL && 878 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 879 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 880 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 881 AHCI_P_CMD_PMA); 882 } 883 /* clear port interrupt register */ 884 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 885 886 /* and enable interrupts */ 887 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 888 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 889 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 890 AHCI_P_IX_PSS | AHCI_P_IX_DHRS); 891 /* wait 500ms before actually starting operations */ 892 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 893 break; 894 895 default: 896 break; 897 } 898 } 899 900 static void 901 ahci_setup_channel(struct ata_channel *chp) 902 { 903 return; 904 } 905 906 static int 907 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 908 { 909 struct ata_channel *chp = drvp->chnl_softc; 910 struct ata_xfer *xfer; 911 int ret; 912 int s; 913 914 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 915 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 916 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 917 DEBUG_XFERS); 918 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 919 ATAXF_NOSLEEP); 920 if (xfer == NULL) { 921 return ATACMD_TRY_AGAIN; 922 } 923 if (ata_c->flags & AT_POLL) 924 xfer->c_flags |= C_POLL; 925 if (ata_c->flags & AT_WAIT) 926 xfer->c_flags |= C_WAIT; 927 xfer->c_drive = drvp->drive; 928 xfer->c_databuf = ata_c->data; 929 xfer->c_bcount = ata_c->bcount; 930 xfer->c_cmd = ata_c; 931 xfer->c_start = ahci_cmd_start; 932 xfer->c_intr = ahci_cmd_complete; 933 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 934 s = splbio(); 935 ata_exec_xfer(chp, xfer); 936 #ifdef DIAGNOSTIC 937 if ((ata_c->flags & AT_POLL) != 0 && 938 (ata_c->flags & AT_DONE) == 0) 939 panic("ahci_exec_command: polled command not done"); 940 #endif 941 if (ata_c->flags & AT_DONE) { 942 ret = ATACMD_COMPLETE; 943 } else { 944 if (ata_c->flags & AT_WAIT) { 945 while ((ata_c->flags & AT_DONE) == 0) { 946 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 947 } 948 ret = ATACMD_COMPLETE; 949 } else { 950 ret = ATACMD_QUEUED; 951 } 952 } 953 splx(s); 954 return ret; 955 } 956 957 static void 958 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 959 { 960 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 961 struct ahci_channel *achp = (struct ahci_channel *)chp; 962 struct ata_command *ata_c = xfer->c_cmd; 963 int slot = 0 /* XXX slot */; 964 struct ahci_cmd_tbl *cmd_tbl; 965 struct ahci_cmd_header *cmd_h; 966 int i; 967 int channel = chp->ch_channel; 968 969 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n", 970 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout), 971 DEBUG_XFERS); 972 973 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 974 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 975 cmd_tbl), DEBUG_XFERS); 976 977 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 978 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 979 980 cmd_h = &achp->ahcic_cmdh[slot]; 981 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 982 chp->ch_channel, cmd_h), DEBUG_XFERS); 983 if (ahci_dma_setup(chp, slot, 984 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 985 ata_c->data : NULL, 986 ata_c->bcount, 987 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 988 ata_c->flags |= AT_DF; 989 ahci_cmd_complete(chp, xfer, slot); 990 return; 991 } 992 cmd_h->cmdh_flags = htole16( 993 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 994 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 995 cmd_h->cmdh_prdbc = 0; 996 AHCI_CMDH_SYNC(sc, achp, slot, 997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 998 999 if (ata_c->flags & AT_POLL) { 1000 /* polled command, disable interrupts */ 1001 AHCI_WRITE(sc, AHCI_GHC, 1002 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1003 } 1004 chp->ch_flags |= ATACH_IRQ_WAIT; 1005 chp->ch_status = 0; 1006 /* start command */ 1007 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1008 /* and says we started this command */ 1009 achp->ahcic_cmds_active |= 1 << slot; 1010 1011 if ((ata_c->flags & AT_POLL) == 0) { 1012 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1013 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 1014 ahci_timeout, chp); 1015 return; 1016 } 1017 /* 1018 * Polled command. 1019 */ 1020 for (i = 0; i < ata_c->timeout / 10; i++) { 1021 if (ata_c->flags & AT_DONE) 1022 break; 1023 ahci_intr_port(sc, achp); 1024 if (ata_c->flags & AT_WAIT) 1025 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1026 else 1027 delay(10000); 1028 } 1029 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1030 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1031 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1032 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1033 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1034 DEBUG_XFERS); 1035 if ((ata_c->flags & AT_DONE) == 0) { 1036 ata_c->flags |= AT_TIMEOU; 1037 ahci_cmd_complete(chp, xfer, slot); 1038 } 1039 /* reenable interrupts */ 1040 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1041 } 1042 1043 static void 1044 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1045 { 1046 struct ata_command *ata_c = xfer->c_cmd; 1047 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1048 DEBUG_FUNCS); 1049 1050 switch (reason) { 1051 case KILL_GONE: 1052 ata_c->flags |= AT_GONE; 1053 break; 1054 case KILL_RESET: 1055 ata_c->flags |= AT_RESET; 1056 break; 1057 default: 1058 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1059 panic("ahci_cmd_kill_xfer"); 1060 } 1061 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1062 } 1063 1064 static int 1065 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1066 { 1067 int slot = 0; /* XXX slot */ 1068 struct ata_command *ata_c = xfer->c_cmd; 1069 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1070 struct ahci_channel *achp = (struct ahci_channel *)chp; 1071 1072 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1073 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1074 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1075 DEBUG_FUNCS); 1076 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1077 if (xfer->c_flags & C_TIMEOU) { 1078 ata_c->flags |= AT_TIMEOU; 1079 } else 1080 callout_stop(&chp->ch_callout); 1081 1082 chp->ch_queue->active_xfer = NULL; 1083 1084 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1085 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1086 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1087 wakeup(&chp->ch_queue->active_xfer); 1088 return 0; 1089 } 1090 1091 if (chp->ch_status & WDCS_BSY) { 1092 ata_c->flags |= AT_TIMEOU; 1093 } else if (chp->ch_status & WDCS_ERR) { 1094 ata_c->r_error = chp->ch_error; 1095 ata_c->flags |= AT_ERROR; 1096 } 1097 1098 if (ata_c->flags & AT_READREG) 1099 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1100 1101 ahci_cmd_done(chp, xfer, slot); 1102 return 0; 1103 } 1104 1105 static void 1106 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1107 { 1108 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1109 struct ahci_channel *achp = (struct ahci_channel *)chp; 1110 struct ata_command *ata_c = xfer->c_cmd; 1111 uint16_t *idwordbuf; 1112 int i; 1113 1114 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n", 1115 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1116 1117 /* this comamnd is not active any more */ 1118 achp->ahcic_cmds_active &= ~(1 << slot); 1119 1120 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1121 bus_dmamap_t map = achp->ahcic_datad[slot]; 1122 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1123 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1124 BUS_DMASYNC_POSTWRITE); 1125 bus_dmamap_unload(sc->sc_dmat, map); 1126 } 1127 1128 AHCI_CMDH_SYNC(sc, achp, slot, 1129 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1130 1131 /* ata(4) expects IDENTIFY data to be in host endianess */ 1132 if (ata_c->r_command == WDCC_IDENTIFY || 1133 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1134 idwordbuf = xfer->c_databuf; 1135 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1136 idwordbuf[i] = le16toh(idwordbuf[i]); 1137 } 1138 } 1139 1140 ata_c->flags |= AT_DONE; 1141 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1142 ata_c->flags |= AT_XFDONE; 1143 1144 ata_free_xfer(chp, xfer); 1145 if (ata_c->flags & AT_WAIT) 1146 wakeup(ata_c); 1147 else if (ata_c->callback) 1148 ata_c->callback(ata_c->callback_arg); 1149 atastart(chp); 1150 return; 1151 } 1152 1153 static int 1154 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1155 { 1156 struct ata_channel *chp = drvp->chnl_softc; 1157 struct ata_xfer *xfer; 1158 1159 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1160 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1161 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1162 DEBUG_XFERS); 1163 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1164 if (xfer == NULL) { 1165 return ATACMD_TRY_AGAIN; 1166 } 1167 if (ata_bio->flags & ATA_POLL) 1168 xfer->c_flags |= C_POLL; 1169 xfer->c_drive = drvp->drive; 1170 xfer->c_cmd = ata_bio; 1171 xfer->c_databuf = ata_bio->databuf; 1172 xfer->c_bcount = ata_bio->bcount; 1173 xfer->c_start = ahci_bio_start; 1174 xfer->c_intr = ahci_bio_complete; 1175 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1176 ata_exec_xfer(chp, xfer); 1177 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1178 } 1179 1180 static void 1181 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1182 { 1183 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1184 struct ahci_channel *achp = (struct ahci_channel *)chp; 1185 struct ata_bio *ata_bio = xfer->c_cmd; 1186 int slot = 0 /* XXX slot */; 1187 struct ahci_cmd_tbl *cmd_tbl; 1188 struct ahci_cmd_header *cmd_h; 1189 int i; 1190 int channel = chp->ch_channel; 1191 1192 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1193 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1194 1195 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1196 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1197 cmd_tbl), DEBUG_XFERS); 1198 1199 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1200 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1201 1202 cmd_h = &achp->ahcic_cmdh[slot]; 1203 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1204 chp->ch_channel, cmd_h), DEBUG_XFERS); 1205 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1206 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1207 ata_bio->error = ERR_DMA; 1208 ata_bio->r_error = 0; 1209 ahci_bio_complete(chp, xfer, slot); 1210 return; 1211 } 1212 cmd_h->cmdh_flags = htole16( 1213 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1214 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1215 cmd_h->cmdh_prdbc = 0; 1216 AHCI_CMDH_SYNC(sc, achp, slot, 1217 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1218 1219 if (xfer->c_flags & C_POLL) { 1220 /* polled command, disable interrupts */ 1221 AHCI_WRITE(sc, AHCI_GHC, 1222 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1223 } 1224 chp->ch_flags |= ATACH_IRQ_WAIT; 1225 chp->ch_status = 0; 1226 /* start command */ 1227 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1228 /* and says we started this command */ 1229 achp->ahcic_cmds_active |= 1 << slot; 1230 1231 if ((xfer->c_flags & C_POLL) == 0) { 1232 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1233 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1234 ahci_timeout, chp); 1235 return; 1236 } 1237 /* 1238 * Polled command. 1239 */ 1240 for (i = 0; i < ATA_DELAY * 10; i++) { 1241 if (ata_bio->flags & ATA_ITSDONE) 1242 break; 1243 ahci_intr_port(sc, achp); 1244 delay(100); 1245 } 1246 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1247 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1248 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1249 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1250 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1251 DEBUG_XFERS); 1252 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1253 ata_bio->error = TIMEOUT; 1254 ahci_bio_complete(chp, xfer, slot); 1255 } 1256 /* reenable interrupts */ 1257 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1258 } 1259 1260 static void 1261 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1262 { 1263 int slot = 0; /* XXX slot */ 1264 int drive = xfer->c_drive; 1265 struct ata_bio *ata_bio = xfer->c_cmd; 1266 struct ahci_channel *achp = (struct ahci_channel *)chp; 1267 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1268 DEBUG_FUNCS); 1269 1270 achp->ahcic_cmds_active &= ~(1 << slot); 1271 ata_free_xfer(chp, xfer); 1272 ata_bio->flags |= ATA_ITSDONE; 1273 switch (reason) { 1274 case KILL_GONE: 1275 ata_bio->error = ERR_NODEV; 1276 break; 1277 case KILL_RESET: 1278 ata_bio->error = ERR_RESET; 1279 break; 1280 default: 1281 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1282 panic("ahci_bio_kill_xfer"); 1283 } 1284 ata_bio->r_error = WDCE_ABRT; 1285 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1286 } 1287 1288 static int 1289 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1290 { 1291 int slot = 0; /* XXX slot */ 1292 struct ata_bio *ata_bio = xfer->c_cmd; 1293 int drive = xfer->c_drive; 1294 struct ahci_channel *achp = (struct ahci_channel *)chp; 1295 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1296 1297 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1298 DEBUG_FUNCS); 1299 1300 achp->ahcic_cmds_active &= ~(1 << slot); 1301 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1302 if (xfer->c_flags & C_TIMEOU) { 1303 ata_bio->error = TIMEOUT; 1304 } else { 1305 callout_stop(&chp->ch_callout); 1306 ata_bio->error = NOERROR; 1307 } 1308 1309 chp->ch_queue->active_xfer = NULL; 1310 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1311 achp->ahcic_datad[slot]->dm_mapsize, 1312 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1313 BUS_DMASYNC_POSTWRITE); 1314 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1315 1316 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1317 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1318 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1319 wakeup(&chp->ch_queue->active_xfer); 1320 return 0; 1321 } 1322 ata_free_xfer(chp, xfer); 1323 ata_bio->flags |= ATA_ITSDONE; 1324 if (chp->ch_status & WDCS_DWF) { 1325 ata_bio->error = ERR_DF; 1326 } else if (chp->ch_status & WDCS_ERR) { 1327 ata_bio->error = ERROR; 1328 ata_bio->r_error = chp->ch_error; 1329 } else if (chp->ch_status & WDCS_CORR) 1330 ata_bio->flags |= ATA_CORR; 1331 1332 AHCI_CMDH_SYNC(sc, achp, slot, 1333 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1334 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1335 ata_bio->bcount), DEBUG_XFERS); 1336 /* 1337 * if it was a write, complete data buffer may have been transfered 1338 * before error detection; in this case don't use cmdh_prdbc 1339 * as it won't reflect what was written to media. Assume nothing 1340 * was transfered and leave bcount as-is. 1341 */ 1342 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1343 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1344 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1345 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1346 atastart(chp); 1347 return 0; 1348 } 1349 1350 static void 1351 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1352 { 1353 int i; 1354 /* stop channel */ 1355 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1356 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1357 /* wait 1s for channel to stop */ 1358 for (i = 0; i <100; i++) { 1359 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1360 == 0) 1361 break; 1362 if (flags & AT_WAIT) 1363 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1364 else 1365 delay(10000); 1366 } 1367 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1368 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1369 /* XXX controller reset ? */ 1370 return; 1371 } 1372 1373 if (sc->sc_channel_stop) 1374 sc->sc_channel_stop(sc, chp); 1375 } 1376 1377 static void 1378 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1379 int flags, int clo) 1380 { 1381 int i; 1382 uint32_t p_cmd; 1383 /* clear error */ 1384 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1385 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1386 1387 if (clo) { 1388 /* issue command list override */ 1389 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1390 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1391 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1392 /* wait 1s for AHCI_CAP_CLO to clear */ 1393 for (i = 0; i <100; i++) { 1394 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1395 AHCI_P_CMD_CLO) == 0) 1396 break; 1397 if (flags & AT_WAIT) 1398 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1399 else 1400 delay(10000); 1401 } 1402 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1403 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1404 /* XXX controller reset ? */ 1405 return; 1406 } 1407 } 1408 1409 if (sc->sc_channel_start) 1410 sc->sc_channel_start(sc, chp); 1411 1412 /* and start controller */ 1413 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1414 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1415 if (chp->ch_ndrives > PMP_PORT_CTL && 1416 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1417 p_cmd |= AHCI_P_CMD_PMA; 1418 } 1419 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1420 } 1421 1422 static void 1423 ahci_timeout(void *v) 1424 { 1425 struct ata_channel *chp = (struct ata_channel *)v; 1426 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1427 #ifdef AHCI_DEBUG 1428 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1429 #endif 1430 int s = splbio(); 1431 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x ghc %08x is %08x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)), AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS)), DEBUG_INTR); 1432 1433 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1434 xfer->c_flags |= C_TIMEOU; 1435 xfer->c_intr(chp, xfer, 0); 1436 } 1437 splx(s); 1438 } 1439 1440 static int 1441 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1442 size_t count, int op) 1443 { 1444 int error, seg; 1445 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1446 struct ahci_channel *achp = (struct ahci_channel *)chp; 1447 struct ahci_cmd_tbl *cmd_tbl; 1448 struct ahci_cmd_header *cmd_h; 1449 1450 cmd_h = &achp->ahcic_cmdh[slot]; 1451 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1452 1453 if (data == NULL) { 1454 cmd_h->cmdh_prdtl = 0; 1455 goto end; 1456 } 1457 1458 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1459 data, count, NULL, 1460 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1461 if (error) { 1462 printf("%s port %d: failed to load xfer: %d\n", 1463 AHCINAME(sc), chp->ch_channel, error); 1464 return error; 1465 } 1466 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1467 achp->ahcic_datad[slot]->dm_mapsize, 1468 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1469 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1470 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1471 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1472 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1473 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1474 } 1475 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1476 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1477 end: 1478 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1479 return 0; 1480 } 1481 1482 #if NATAPIBUS > 0 1483 static void 1484 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1485 { 1486 struct ata_channel *chp = ata_sc->sc_chan; 1487 struct atac_softc *atac = chp->ch_atac; 1488 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1489 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1490 /* 1491 * Fill in the scsipi_adapter. 1492 */ 1493 adapt->adapt_dev = atac->atac_dev; 1494 adapt->adapt_nchannels = atac->atac_nchannels; 1495 adapt->adapt_request = ahci_atapi_scsipi_request; 1496 adapt->adapt_minphys = ahci_atapi_minphys; 1497 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1498 1499 /* 1500 * Fill in the scsipi_channel. 1501 */ 1502 memset(chan, 0, sizeof(*chan)); 1503 chan->chan_adapter = adapt; 1504 chan->chan_bustype = &ahci_atapi_bustype; 1505 chan->chan_channel = chp->ch_channel; 1506 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1507 chan->chan_openings = 1; 1508 chan->chan_max_periph = 1; 1509 chan->chan_ntargets = 1; 1510 chan->chan_nluns = 1; 1511 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1512 atapiprint); 1513 } 1514 1515 static void 1516 ahci_atapi_minphys(struct buf *bp) 1517 { 1518 if (bp->b_bcount > MACHINE_MAXPHYS) 1519 bp->b_bcount = MACHINE_MAXPHYS; 1520 minphys(bp); 1521 } 1522 1523 /* 1524 * Kill off all pending xfers for a periph. 1525 * 1526 * Must be called at splbio(). 1527 */ 1528 static void 1529 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1530 { 1531 struct atac_softc *atac = 1532 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1533 struct ata_channel *chp = 1534 atac->atac_channels[periph->periph_channel->chan_channel]; 1535 1536 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1537 } 1538 1539 static void 1540 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1541 scsipi_adapter_req_t req, void *arg) 1542 { 1543 struct scsipi_adapter *adapt = chan->chan_adapter; 1544 struct scsipi_periph *periph; 1545 struct scsipi_xfer *sc_xfer; 1546 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1547 struct atac_softc *atac = &sc->sc_atac; 1548 struct ata_xfer *xfer; 1549 int channel = chan->chan_channel; 1550 int drive, s; 1551 1552 switch (req) { 1553 case ADAPTER_REQ_RUN_XFER: 1554 sc_xfer = arg; 1555 periph = sc_xfer->xs_periph; 1556 drive = periph->periph_target; 1557 if (!device_is_active(atac->atac_dev)) { 1558 sc_xfer->error = XS_DRIVER_STUFFUP; 1559 scsipi_done(sc_xfer); 1560 return; 1561 } 1562 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1563 if (xfer == NULL) { 1564 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1565 scsipi_done(sc_xfer); 1566 return; 1567 } 1568 1569 if (sc_xfer->xs_control & XS_CTL_POLL) 1570 xfer->c_flags |= C_POLL; 1571 xfer->c_drive = drive; 1572 xfer->c_flags |= C_ATAPI; 1573 xfer->c_cmd = sc_xfer; 1574 xfer->c_databuf = sc_xfer->data; 1575 xfer->c_bcount = sc_xfer->datalen; 1576 xfer->c_start = ahci_atapi_start; 1577 xfer->c_intr = ahci_atapi_complete; 1578 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1579 xfer->c_dscpoll = 0; 1580 s = splbio(); 1581 ata_exec_xfer(atac->atac_channels[channel], xfer); 1582 #ifdef DIAGNOSTIC 1583 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1584 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1585 panic("ahci_atapi_scsipi_request: polled command " 1586 "not done"); 1587 #endif 1588 splx(s); 1589 return; 1590 default: 1591 /* Not supported, nothing to do. */ 1592 ; 1593 } 1594 } 1595 1596 static void 1597 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1598 { 1599 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1600 struct ahci_channel *achp = (struct ahci_channel *)chp; 1601 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1602 int slot = 0 /* XXX slot */; 1603 struct ahci_cmd_tbl *cmd_tbl; 1604 struct ahci_cmd_header *cmd_h; 1605 int i; 1606 int channel = chp->ch_channel; 1607 1608 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1609 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1610 1611 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1612 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1613 cmd_tbl), DEBUG_XFERS); 1614 1615 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1616 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1617 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1618 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1619 1620 cmd_h = &achp->ahcic_cmdh[slot]; 1621 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1622 chp->ch_channel, cmd_h), DEBUG_XFERS); 1623 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1624 sc_xfer->datalen, 1625 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1626 BUS_DMA_READ : BUS_DMA_WRITE)) { 1627 sc_xfer->error = XS_DRIVER_STUFFUP; 1628 ahci_atapi_complete(chp, xfer, slot); 1629 return; 1630 } 1631 cmd_h->cmdh_flags = htole16( 1632 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1633 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1634 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1635 cmd_h->cmdh_prdbc = 0; 1636 AHCI_CMDH_SYNC(sc, achp, slot, 1637 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1638 1639 if (xfer->c_flags & C_POLL) { 1640 /* polled command, disable interrupts */ 1641 AHCI_WRITE(sc, AHCI_GHC, 1642 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1643 } 1644 chp->ch_flags |= ATACH_IRQ_WAIT; 1645 chp->ch_status = 0; 1646 /* start command */ 1647 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1648 /* and says we started this command */ 1649 achp->ahcic_cmds_active |= 1 << slot; 1650 1651 if ((xfer->c_flags & C_POLL) == 0) { 1652 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1653 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1654 ahci_timeout, chp); 1655 return; 1656 } 1657 /* 1658 * Polled command. 1659 */ 1660 for (i = 0; i < ATA_DELAY / 10; i++) { 1661 if (sc_xfer->xs_status & XS_STS_DONE) 1662 break; 1663 ahci_intr_port(sc, achp); 1664 delay(10000); 1665 } 1666 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1667 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1668 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1669 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1670 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1671 DEBUG_XFERS); 1672 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1673 sc_xfer->error = XS_TIMEOUT; 1674 ahci_atapi_complete(chp, xfer, slot); 1675 } 1676 /* reenable interrupts */ 1677 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1678 } 1679 1680 static int 1681 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1682 { 1683 int slot = 0; /* XXX slot */ 1684 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1685 int drive = xfer->c_drive; 1686 struct ahci_channel *achp = (struct ahci_channel *)chp; 1687 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1688 1689 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1690 DEBUG_FUNCS); 1691 1692 achp->ahcic_cmds_active &= ~(1 << slot); 1693 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1694 if (xfer->c_flags & C_TIMEOU) { 1695 sc_xfer->error = XS_TIMEOUT; 1696 } else { 1697 callout_stop(&chp->ch_callout); 1698 sc_xfer->error = 0; 1699 } 1700 1701 chp->ch_queue->active_xfer = NULL; 1702 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1703 achp->ahcic_datad[slot]->dm_mapsize, 1704 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1705 BUS_DMASYNC_POSTWRITE); 1706 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1707 1708 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1709 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1710 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1711 wakeup(&chp->ch_queue->active_xfer); 1712 return 0; 1713 } 1714 ata_free_xfer(chp, xfer); 1715 1716 AHCI_CMDH_SYNC(sc, achp, slot, 1717 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1718 sc_xfer->resid = sc_xfer->datalen; 1719 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1720 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1721 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1722 if (chp->ch_status & WDCS_ERR && 1723 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1724 sc_xfer->resid == sc_xfer->datalen)) { 1725 sc_xfer->error = XS_SHORTSENSE; 1726 sc_xfer->sense.atapi_sense = chp->ch_error; 1727 if ((sc_xfer->xs_periph->periph_quirks & 1728 PQUIRK_NOSENSE) == 0) { 1729 /* ask scsipi to send a REQUEST_SENSE */ 1730 sc_xfer->error = XS_BUSY; 1731 sc_xfer->status = SCSI_CHECK; 1732 } 1733 } 1734 scsipi_done(sc_xfer); 1735 atastart(chp); 1736 return 0; 1737 } 1738 1739 static void 1740 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1741 { 1742 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1743 struct ahci_channel *achp = (struct ahci_channel *)chp; 1744 int slot = 0; /* XXX slot */ 1745 1746 achp->ahcic_cmds_active &= ~(1 << slot); 1747 1748 /* remove this command from xfer queue */ 1749 switch (reason) { 1750 case KILL_GONE: 1751 sc_xfer->error = XS_DRIVER_STUFFUP; 1752 break; 1753 case KILL_RESET: 1754 sc_xfer->error = XS_RESET; 1755 break; 1756 default: 1757 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1758 panic("ahci_ata_atapi_kill_xfer"); 1759 } 1760 ata_free_xfer(chp, xfer); 1761 scsipi_done(sc_xfer); 1762 } 1763 1764 static void 1765 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1766 { 1767 struct scsipi_channel *chan = sc->sc_channel; 1768 struct scsipi_periph *periph; 1769 struct ataparams ids; 1770 struct ataparams *id = &ids; 1771 struct ahci_softc *ahcic = 1772 device_private(chan->chan_adapter->adapt_dev); 1773 struct atac_softc *atac = &ahcic->sc_atac; 1774 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1775 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1776 struct scsipibus_attach_args sa; 1777 char serial_number[21], model[41], firmware_revision[9]; 1778 int s; 1779 1780 /* skip if already attached */ 1781 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1782 return; 1783 1784 /* if no ATAPI device detected at attach time, skip */ 1785 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1786 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1787 "not present\n", target), DEBUG_PROBE); 1788 return; 1789 } 1790 1791 /* Some ATAPI devices need a bit more time after software reset. */ 1792 delay(5000); 1793 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1794 #ifdef ATAPI_DEBUG_PROBE 1795 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1796 AHCINAME(ahcic), target, 1797 id->atap_config & ATAPI_CFG_CMD_MASK, 1798 id->atap_config & ATAPI_CFG_DRQ_MASK); 1799 #endif 1800 periph = scsipi_alloc_periph(M_NOWAIT); 1801 if (periph == NULL) { 1802 aprint_error_dev(sc->sc_dev, 1803 "unable to allocate periph for drive %d\n", 1804 target); 1805 return; 1806 } 1807 periph->periph_dev = NULL; 1808 periph->periph_channel = chan; 1809 periph->periph_switch = &atapi_probe_periphsw; 1810 periph->periph_target = target; 1811 periph->periph_lun = 0; 1812 periph->periph_quirks = PQUIRK_ONLYBIG; 1813 1814 #ifdef SCSIPI_DEBUG 1815 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1816 SCSIPI_DEBUG_TARGET == target) 1817 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1818 #endif 1819 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1820 if (id->atap_config & ATAPI_CFG_REMOV) 1821 periph->periph_flags |= PERIPH_REMOVABLE; 1822 if (periph->periph_type == T_SEQUENTIAL) { 1823 s = splbio(); 1824 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1825 splx(s); 1826 } 1827 1828 sa.sa_periph = periph; 1829 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1830 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1831 T_REMOV : T_FIXED; 1832 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1833 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1834 20); 1835 scsipi_strvis((u_char *)firmware_revision, 8, 1836 id->atap_revision, 8); 1837 sa.sa_inqbuf.vendor = model; 1838 sa.sa_inqbuf.product = serial_number; 1839 sa.sa_inqbuf.revision = firmware_revision; 1840 1841 /* 1842 * Determine the operating mode capabilities of the device. 1843 */ 1844 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1845 periph->periph_cap |= PERIPH_CAP_CMD16; 1846 /* XXX This is gross. */ 1847 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1848 1849 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1850 1851 if (drvp->drv_softc) 1852 ata_probe_caps(drvp); 1853 else { 1854 s = splbio(); 1855 drvp->drive_type = ATA_DRIVET_NONE; 1856 splx(s); 1857 } 1858 } else { 1859 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1860 "failed for drive %s:%d:%d: error 0x%x\n", 1861 AHCINAME(ahcic), chp->ch_channel, target, 1862 chp->ch_error), DEBUG_PROBE); 1863 s = splbio(); 1864 drvp->drive_type = ATA_DRIVET_NONE; 1865 splx(s); 1866 } 1867 } 1868 #endif /* NATAPIBUS */ 1869
Indexes created Fri Oct 17 00:09:41 GMT 2025