ahcisata_core.c revision 1.43.2.6
1 /* $NetBSD: ahcisata_core.c,v 1.43.2.6 2017/12/03 11:37:02 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.43.2.6 2017/12/03 11:37:02 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 struct ata_xfer *xfer); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 void ahci_channel_recover(struct ahci_softc *, struct ata_channel *, int); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending 125 }; 126 127 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 return 0; 170 } 171 172 static void 173 ahci_setup_ports(struct ahci_softc *sc) 174 { 175 int i, port; 176 177 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 178 if ((sc->sc_ahci_ports & (1 << i)) == 0) 179 continue; 180 if (port >= sc->sc_atac.atac_nchannels) { 181 aprint_error("%s: more ports than announced\n", 182 AHCINAME(sc)); 183 break; 184 } 185 ahci_setup_port(sc, i); 186 } 187 } 188 189 static void 190 ahci_reprobe_drives(struct ahci_softc *sc) 191 { 192 int i, port; 193 struct ahci_channel *achp; 194 struct ata_channel *chp; 195 196 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 197 if ((sc->sc_ahci_ports & (1 << i)) == 0) 198 continue; 199 if (port >= sc->sc_atac.atac_nchannels) { 200 aprint_error("%s: more ports than announced\n", 201 AHCINAME(sc)); 202 break; 203 } 204 achp = &sc->sc_channels[i]; 205 chp = &achp->ata_channel; 206 207 ahci_probe_drive(chp); 208 } 209 } 210 211 static void 212 ahci_setup_port(struct ahci_softc *sc, int i) 213 { 214 struct ahci_channel *achp; 215 216 achp = &sc->sc_channels[i]; 217 218 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 219 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 220 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 221 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 222 } 223 224 static void 225 ahci_enable_intrs(struct ahci_softc *sc) 226 { 227 228 /* clear interrupts */ 229 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 230 /* enable interrupts */ 231 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 232 } 233 234 void 235 ahci_attach(struct ahci_softc *sc) 236 { 237 uint32_t ahci_rev; 238 int i, j, port; 239 struct ahci_channel *achp; 240 struct ata_channel *chp; 241 int error; 242 int dmasize; 243 char buf[128]; 244 void *cmdhp; 245 void *cmdtblp; 246 247 if (sc->sc_save_init_data) { 248 ahci_enable(sc); 249 250 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 251 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 252 253 ahci_rev = AHCI_READ(sc, AHCI_VS); 254 if (AHCI_VS_MJR(ahci_rev) > 1 || 255 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 256 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 257 } else { 258 sc->sc_init_data.cap2 = 0; 259 } 260 if (sc->sc_init_data.ports == 0) { 261 sc->sc_init_data.ports = sc->sc_ahci_ports; 262 } 263 } 264 265 if (ahci_reset(sc) != 0) 266 return; 267 268 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 269 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 270 aprint_verbose_dev(sc->sc_atac.atac_dev, 271 "ignoring broken port multiplier support\n"); 272 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 273 } 274 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 275 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 276 ahci_rev = AHCI_READ(sc, AHCI_VS); 277 snprintb(buf, sizeof(buf), "\177\020" 278 /* "f\000\005NP\0" */ 279 "b\005SXS\0" 280 "b\006EMS\0" 281 "b\007CCCS\0" 282 /* "f\010\005NCS\0" */ 283 "b\015PSC\0" 284 "b\016SSC\0" 285 "b\017PMD\0" 286 "b\020FBSS\0" 287 "b\021SPM\0" 288 "b\022SAM\0" 289 "b\023SNZO\0" 290 "f\024\003ISS\0" 291 "=\001Gen1\0" 292 "=\002Gen2\0" 293 "=\003Gen3\0" 294 "b\030SCLO\0" 295 "b\031SAL\0" 296 "b\032SALP\0" 297 "b\033SSS\0" 298 "b\034SMPS\0" 299 "b\035SSNTF\0" 300 "b\036SNCQ\0" 301 "b\037S64A\0" 302 "\0", sc->sc_ahci_cap); 303 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 304 ", %d port%s, %d slot%s, CAP %s\n", 305 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 306 sc->sc_atac.atac_nchannels, 307 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 308 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 309 310 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 311 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 312 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 313 sc->sc_atac.atac_pio_cap = 4; 314 sc->sc_atac.atac_dma_cap = 2; 315 sc->sc_atac.atac_udma_cap = 6; 316 sc->sc_atac.atac_channels = sc->sc_chanarray; 317 sc->sc_atac.atac_probe = ahci_probe_drive; 318 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 319 sc->sc_atac.atac_set_modes = ahci_setup_channel; 320 #if NATAPIBUS > 0 321 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 322 #endif 323 324 dmasize = 325 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 326 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 327 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 328 if (error) { 329 aprint_error("%s: unable to allocate command header memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 return; 332 } 333 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 334 sc->sc_cmd_hdr_nseg, dmasize, 335 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 336 if (error) { 337 aprint_error("%s: unable to map command header memory" 338 ", error=%d\n", AHCINAME(sc), error); 339 return; 340 } 341 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 342 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 343 if (error) { 344 aprint_error("%s: unable to create command header map" 345 ", error=%d\n", AHCINAME(sc), error); 346 return; 347 } 348 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 349 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 350 if (error) { 351 aprint_error("%s: unable to load command header map" 352 ", error=%d\n", AHCINAME(sc), error); 353 return; 354 } 355 sc->sc_cmd_hdr = cmdhp; 356 357 ahci_enable_intrs(sc); 358 359 if (sc->sc_ahci_ports == 0) { 360 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 361 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 362 DEBUG_PROBE); 363 } 364 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 365 if ((sc->sc_ahci_ports & (1 << i)) == 0) 366 continue; 367 if (port >= sc->sc_atac.atac_nchannels) { 368 aprint_error("%s: more ports than announced\n", 369 AHCINAME(sc)); 370 break; 371 } 372 achp = &sc->sc_channels[i]; 373 chp = &achp->ata_channel; 374 sc->sc_chanarray[i] = chp; 375 chp->ch_channel = i; 376 chp->ch_atac = &sc->sc_atac; 377 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 378 if (chp->ch_queue == NULL) { 379 aprint_error("%s port %d: can't allocate memory for " 380 "command queue", AHCINAME(sc), i); 381 break; 382 } 383 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 384 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 385 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 386 BUS_DMA_NOWAIT); 387 if (error) { 388 aprint_error("%s: unable to allocate command table " 389 "memory, error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 393 achp->ahcic_cmd_tbl_nseg, dmasize, 394 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 395 if (error) { 396 aprint_error("%s: unable to map command table memory" 397 ", error=%d\n", AHCINAME(sc), error); 398 break; 399 } 400 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 401 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 402 if (error) { 403 aprint_error("%s: unable to create command table map" 404 ", error=%d\n", AHCINAME(sc), error); 405 break; 406 } 407 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 408 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 409 if (error) { 410 aprint_error("%s: unable to load command table map" 411 ", error=%d\n", AHCINAME(sc), error); 412 break; 413 } 414 achp->ahcic_cmdh = (struct ahci_cmd_header *) 415 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 416 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 417 AHCI_CMDH_SIZE * port; 418 achp->ahcic_rfis = (struct ahci_r_fis *) 419 ((char *)cmdhp + 420 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 421 AHCI_RFIS_SIZE * port); 422 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port; 425 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 426 "rfis %p (0x%" PRIx64 ")\n", i, 427 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 428 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 429 DEBUG_PROBE); 430 431 for (j = 0; j < sc->sc_ncmds; j++) { 432 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 433 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 434 achp->ahcic_bus_cmd_tbl[j] = 435 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 436 AHCI_CMDTBL_SIZE * j; 437 achp->ahcic_cmdh[j].cmdh_cmdtba = 438 htole64(achp->ahcic_bus_cmd_tbl[j]); 439 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 440 achp->ahcic_cmd_tbl[j], 441 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 442 /* The xfer DMA map */ 443 error = bus_dmamap_create(sc->sc_dmat, 444 sc->sc_atac.atac_dev->dv_maxphys, 445 AHCI_NPRD, 0x400000 /* 4MB */, 0, 446 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 447 &achp->ahcic_datad[j]); 448 if (error) { 449 aprint_error("%s: couldn't alloc xfer DMA map, " 450 "error=%d\n", AHCINAME(sc), error); 451 goto end; 452 } 453 } 454 ahci_setup_port(sc, i); 455 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 456 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 457 aprint_error("%s: couldn't map channel %d " 458 "sata_status regs\n", AHCINAME(sc), i); 459 break; 460 } 461 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 462 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 463 aprint_error("%s: couldn't map channel %d " 464 "sata_control regs\n", AHCINAME(sc), i); 465 break; 466 } 467 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 468 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 469 aprint_error("%s: couldn't map channel %d " 470 "sata_error regs\n", AHCINAME(sc), i); 471 break; 472 } 473 ata_channel_attach(chp); 474 port++; 475 end: 476 continue; 477 } 478 } 479 480 int 481 ahci_detach(struct ahci_softc *sc, int flags) 482 { 483 struct atac_softc *atac; 484 struct ahci_channel *achp; 485 struct ata_channel *chp; 486 struct scsipi_adapter *adapt; 487 int i, j; 488 int error; 489 490 atac = &sc->sc_atac; 491 adapt = &atac->atac_atapi_adapter._generic; 492 493 for (i = 0; i < AHCI_MAX_PORTS; i++) { 494 achp = &sc->sc_channels[i]; 495 chp = &achp->ata_channel; 496 497 if ((sc->sc_ahci_ports & (1 << i)) == 0) 498 continue; 499 if (i >= sc->sc_atac.atac_nchannels) { 500 aprint_error("%s: more ports than announced\n", 501 AHCINAME(sc)); 502 break; 503 } 504 505 if (chp->atabus == NULL) 506 continue; 507 if ((error = config_detach(chp->atabus, flags)) != 0) 508 return error; 509 510 for (j = 0; j < sc->sc_ncmds; j++) 511 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 512 513 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 514 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 515 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 516 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 517 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 518 achp->ahcic_cmd_tbl_nseg); 519 520 chp->atabus = NULL; 521 522 ata_channel_detach(chp); 523 } 524 525 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 526 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 527 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 528 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 529 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 530 531 if (adapt->adapt_refcnt != 0) 532 return EBUSY; 533 534 return 0; 535 } 536 537 void 538 ahci_resume(struct ahci_softc *sc) 539 { 540 ahci_reset(sc); 541 ahci_setup_ports(sc); 542 ahci_reprobe_drives(sc); 543 ahci_enable_intrs(sc); 544 } 545 546 int 547 ahci_intr(void *v) 548 { 549 struct ahci_softc *sc = v; 550 uint32_t is; 551 int i, r = 0; 552 553 while ((is = AHCI_READ(sc, AHCI_IS))) { 554 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 555 DEBUG_INTR); 556 r = 1; 557 AHCI_WRITE(sc, AHCI_IS, is); 558 for (i = 0; i < AHCI_MAX_PORTS; i++) 559 if (is & (1 << i)) 560 ahci_intr_port(sc, &sc->sc_channels[i]); 561 } 562 return r; 563 } 564 565 static void 566 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 567 { 568 uint32_t is, tfd, sact; 569 struct ata_channel *chp = &achp->ata_channel; 570 struct ata_xfer *xfer; 571 int slot = -1; 572 bool recover = false; 573 574 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 575 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 576 577 AHCIDEBUG_PRINT(( 578 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 579 AHCINAME(sc), 580 chp->ch_channel, is, 581 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 582 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 583 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 584 DEBUG_INTR); 585 586 if ((chp->ch_flags & ATACH_NCQ) == 0) { 587 /* Non-NCQ operation */ 588 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 589 } else { 590 /* NCQ operation */ 591 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 592 } 593 594 /* Handle errors */ 595 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 596 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 597 /* Fatal errors */ 598 if (is & AHCI_P_IX_TFES) { 599 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 600 601 if ((chp->ch_flags & ATACH_NCQ) == 0) { 602 /* Slot valid only for Non-NCQ operation */ 603 slot = (AHCI_READ(sc, 604 AHCI_P_CMD(chp->ch_channel)) 605 & AHCI_P_CMD_CCS_MASK) 606 >> AHCI_P_CMD_CCS_SHIFT; 607 } 608 609 AHCIDEBUG_PRINT(( 610 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 611 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 612 DEBUG_INTR); 613 } else { 614 /* mark an error, and set BSY */ 615 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 616 WDCS_ERR | WDCS_BSY; 617 } 618 619 if (is & AHCI_P_IX_IFS) { 620 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 621 AHCINAME(sc), chp->ch_channel, 622 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 623 DEBUG_INTR); 624 } 625 626 if (!achp->ahcic_recovering) 627 recover = true; 628 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 629 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 630 631 /* D2H Register FIS or Set Device Bits */ 632 if ((tfd & WDCS_ERR) != 0) { 633 if (!achp->ahcic_recovering) 634 recover = true; 635 636 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 637 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 638 639 } 640 } else { 641 tfd = 0; 642 } 643 644 if (__predict_false(recover)) 645 ata_channel_freeze(chp); 646 647 if (slot >= 0) { 648 if ((achp->ahcic_cmds_active & __BIT(slot)) != 0 && 649 (sact & __BIT(slot)) == 0) { 650 xfer = ata_queue_hwslot_to_xfer(chp, slot); 651 xfer->c_intr(chp, xfer, tfd); 652 } 653 } else { 654 /* 655 * For NCQ, HBA halts processing when error is notified, 656 * and any further D2H FISes are ignored until the error 657 * condition is cleared. Hence if a command is inactive, 658 * it means it actually already finished successfully. 659 * Note: active slots can change as c_intr() callback 660 * can activate another command(s), so must only process 661 * commands active before we start processing. 662 */ 663 uint32_t aslots = achp->ahcic_cmds_active; 664 665 for (slot=0; slot < sc->sc_ncmds; slot++) { 666 if ((aslots & __BIT(slot)) != 0 && 667 (sact & __BIT(slot)) == 0) { 668 xfer = ata_queue_hwslot_to_xfer(chp, slot); 669 xfer->c_intr(chp, xfer, tfd); 670 } 671 } 672 } 673 674 if (__predict_false(recover)) { 675 ata_channel_thaw(chp); 676 ahci_channel_recover(sc, chp, tfd); 677 } 678 } 679 680 static void 681 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 682 { 683 struct ata_channel *chp = drvp->chnl_softc; 684 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 685 struct ata_xfer *xfer; 686 687 xfer = ata_get_xfer_ext(chp, C_RECOVERY, 0); 688 689 ata_channel_lock(chp); 690 691 AHCI_WRITE(sc, AHCI_GHC, 692 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 693 ahci_channel_stop(sc, chp, flags); 694 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp, xfer) != 0) 695 ata_reset_channel(chp, flags); 696 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 697 698 ata_channel_unlock(chp); 699 700 ata_free_xfer(chp, xfer); 701 702 return; 703 } 704 705 /* return error code from ata_bio */ 706 static int 707 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 708 { 709 struct ahci_channel *achp = (struct ahci_channel *)chp; 710 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 711 int i; 712 uint32_t is; 713 714 /* 715 * Base timeout is specified in ms. 716 * If we are allowed to sleep, wait a tick each round. 717 * Otherwise delay for 10ms on each round. 718 */ 719 if (flags & AT_WAIT) 720 timeout = MAX(1, mstohz(timeout)); 721 else 722 timeout = timeout / 10; 723 724 AHCI_CMDH_SYNC(sc, achp, slot, 725 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 726 /* start command */ 727 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 728 for (i = 0; i < timeout; i++) { 729 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) == 730 0) 731 return 0; 732 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 733 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 734 AHCI_P_IX_IFS | 735 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 736 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 737 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 738 /* 739 * we got the D2H FIS anyway, 740 * assume sig is valid. 741 * channel is restarted later 742 */ 743 return ERROR; 744 } 745 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 746 AHCINAME(sc), chp->ch_channel, is); 747 return ERR_DF; 748 } 749 ata_delay(chp, 10, "ahcifis", flags); 750 } 751 752 aprint_debug("%s channel %d: timeout sending FIS\n", 753 AHCINAME(sc), chp->ch_channel); 754 return TIMEOUT; 755 } 756 757 static int 758 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 759 uint32_t *sigp, struct ata_xfer *xfer) 760 { 761 struct ahci_channel *achp = (struct ahci_channel *)chp; 762 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 763 struct ahci_cmd_tbl *cmd_tbl; 764 struct ahci_cmd_header *cmd_h; 765 int i; 766 uint32_t sig; 767 768 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 769 ata_channel_lock_owned(chp); 770 771 again: 772 /* clear port interrupt register */ 773 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 774 /* clear SErrors and start operations */ 775 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 776 /* 777 * issue a command list override to clear BSY. 778 * This is needed if there's a PMP with no drive 779 * on port 0 780 */ 781 ahci_channel_start(sc, chp, flags, 1); 782 } else { 783 ahci_channel_start(sc, chp, flags, 0); 784 } 785 if (drive > 0) { 786 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 787 } 788 789 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 790 goto skip_reset; 791 792 /* polled command, assume interrupts are disabled */ 793 794 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 795 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 796 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 797 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 798 cmd_h->cmdh_prdbc = 0; 799 memset(cmd_tbl->cmdt_cfis, 0, 64); 800 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 801 cmd_tbl->cmdt_cfis[rhd_c] = drive; 802 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 803 switch(ahci_exec_fis(chp, 100, flags, xfer->c_slot)) { 804 case ERR_DF: 805 case TIMEOUT: 806 aprint_error("%s channel %d: setting WDCTL_RST failed " 807 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 808 if (sigp) 809 *sigp = 0xffffffff; 810 goto end; 811 default: 812 break; 813 } 814 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 815 (drive << AHCI_CMDH_F_PMP_SHIFT)); 816 cmd_h->cmdh_prdbc = 0; 817 memset(cmd_tbl->cmdt_cfis, 0, 64); 818 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 819 cmd_tbl->cmdt_cfis[rhd_c] = drive; 820 cmd_tbl->cmdt_cfis[rhd_control] = 0; 821 switch(ahci_exec_fis(chp, 310, flags, xfer->c_slot)) { 822 case ERR_DF: 823 case TIMEOUT: 824 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 825 drive == PMP_PORT_CTL) { 826 /* 827 * some controllers fails to reset when 828 * targeting a PMP but a single drive is attached. 829 * try again with port 0 830 */ 831 drive = 0; 832 ahci_channel_stop(sc, chp, flags); 833 goto again; 834 } 835 aprint_error("%s channel %d: clearing WDCTL_RST failed " 836 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 837 if (sigp) 838 *sigp = 0xffffffff; 839 goto end; 840 default: 841 break; 842 } 843 844 skip_reset: 845 /* 846 * wait 31s for BSY to clear 847 * This should not be needed, but some controllers clear the 848 * command slot before receiving the D2H FIS ... 849 */ 850 for (i = 0; i < AHCI_RST_WAIT; i++) { 851 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 852 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 853 break; 854 ata_delay(chp, 10, "ahcid2h", flags); 855 } 856 if (i == AHCI_RST_WAIT) { 857 aprint_error("%s: BSY never cleared, TD 0x%x\n", 858 AHCINAME(sc), sig); 859 if (sigp) 860 *sigp = 0xffffffff; 861 goto end; 862 } 863 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 864 DEBUG_PROBE); 865 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 866 if (sigp) 867 *sigp = sig; 868 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 869 AHCINAME(sc), chp->ch_channel, sig, 870 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 871 end: 872 ahci_channel_stop(sc, chp, flags); 873 ata_delay(chp, 500, "ahcirst", flags); 874 /* clear port interrupt register */ 875 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 876 ahci_channel_start(sc, chp, flags, 877 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 878 return 0; 879 } 880 881 static void 882 ahci_reset_channel(struct ata_channel *chp, int flags) 883 { 884 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 885 struct ahci_channel *achp = (struct ahci_channel *)chp; 886 int i, tfd; 887 888 ata_channel_lock(chp); 889 890 ahci_channel_stop(sc, chp, flags); 891 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 892 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 893 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 894 /* XXX and then ? */ 895 } 896 ata_kill_active(chp, KILL_RESET, flags); 897 ata_delay(chp, 500, "ahcirst", flags); 898 /* clear port interrupt register */ 899 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 900 /* clear SErrors and start operations */ 901 ahci_channel_start(sc, chp, flags, 902 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 903 /* wait 31s for BSY to clear */ 904 for (i = 0; i <AHCI_RST_WAIT; i++) { 905 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 906 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 907 break; 908 ata_delay(chp, 10, "ahcid2h", flags); 909 } 910 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 911 aprint_error("%s: BSY never cleared, TD 0x%x\n", 912 AHCINAME(sc), tfd); 913 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 914 DEBUG_PROBE); 915 /* clear port interrupt register */ 916 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 917 918 ata_channel_unlock(chp); 919 920 return; 921 } 922 923 static int 924 ahci_ata_addref(struct ata_drive_datas *drvp) 925 { 926 return 0; 927 } 928 929 static void 930 ahci_ata_delref(struct ata_drive_datas *drvp) 931 { 932 return; 933 } 934 935 static void 936 ahci_killpending(struct ata_drive_datas *drvp) 937 { 938 return; 939 } 940 941 static void 942 ahci_probe_drive(struct ata_channel *chp) 943 { 944 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 945 struct ahci_channel *achp = (struct ahci_channel *)chp; 946 uint32_t sig; 947 struct ata_xfer *xfer; 948 949 xfer = ata_get_xfer_ext(chp, 0, 0); 950 if (xfer == NULL) { 951 aprint_error_dev(sc->sc_atac.atac_dev, 952 "%s: failed to get xfer port %d\n", 953 __func__, chp->ch_channel); 954 return; 955 } 956 957 ata_channel_lock(chp); 958 959 /* bring interface up, accept FISs, power up and spin up device */ 960 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 961 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 962 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 963 /* reset the PHY and bring online */ 964 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 965 achp->ahcic_sstatus, AT_WAIT)) { 966 case SStatus_DET_DEV: 967 ata_delay(chp, 500, "ahcidv", AT_WAIT); 968 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 969 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig, 970 xfer); 971 } else { 972 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, xfer); 973 } 974 sata_interpret_sig(chp, 0, sig); 975 /* if we have a PMP attached, inform the controller */ 976 if (chp->ch_ndrives > PMP_PORT_CTL && 977 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 978 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 979 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 980 AHCI_P_CMD_PMA); 981 } 982 /* clear port interrupt register */ 983 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 984 985 /* and enable interrupts */ 986 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 987 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 988 AHCI_P_IX_IFS | 989 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 990 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 991 /* wait 500ms before actually starting operations */ 992 ata_delay(chp, 500, "ahciprb", AT_WAIT); 993 break; 994 995 default: 996 break; 997 } 998 ata_channel_unlock(chp); 999 } 1000 1001 static void 1002 ahci_setup_channel(struct ata_channel *chp) 1003 { 1004 return; 1005 } 1006 1007 static int 1008 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1009 { 1010 struct ata_channel *chp = drvp->chnl_softc; 1011 struct ata_command *ata_c = &xfer->c_ata_c; 1012 int ret; 1013 int s; 1014 1015 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1016 chp->ch_channel, 1017 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1018 DEBUG_XFERS); 1019 if (ata_c->flags & AT_POLL) 1020 xfer->c_flags |= C_POLL; 1021 if (ata_c->flags & AT_WAIT) 1022 xfer->c_flags |= C_WAIT; 1023 xfer->c_drive = drvp->drive; 1024 xfer->c_databuf = ata_c->data; 1025 xfer->c_bcount = ata_c->bcount; 1026 xfer->c_start = ahci_cmd_start; 1027 xfer->c_poll = ahci_cmd_poll; 1028 xfer->c_abort = ahci_cmd_abort; 1029 xfer->c_intr = ahci_cmd_complete; 1030 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 1031 s = splbio(); 1032 ata_exec_xfer(chp, xfer); 1033 #ifdef DIAGNOSTIC 1034 if ((ata_c->flags & AT_POLL) != 0 && 1035 (ata_c->flags & AT_DONE) == 0) 1036 panic("ahci_exec_command: polled command not done"); 1037 #endif 1038 if (ata_c->flags & AT_DONE) { 1039 ret = ATACMD_COMPLETE; 1040 } else { 1041 if (ata_c->flags & AT_WAIT) { 1042 ata_channel_lock(chp); 1043 if ((ata_c->flags & AT_DONE) == 0) { 1044 ata_wait_xfer(chp, xfer); 1045 KASSERT((ata_c->flags & AT_DONE) != 0); 1046 } 1047 ata_channel_unlock(chp); 1048 ret = ATACMD_COMPLETE; 1049 } else { 1050 ret = ATACMD_QUEUED; 1051 } 1052 } 1053 splx(s); 1054 return ret; 1055 } 1056 1057 static int 1058 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1059 { 1060 struct ahci_softc *sc = AHCI_CH2SC(chp); 1061 struct ahci_channel *achp = (struct ahci_channel *)chp; 1062 struct ata_command *ata_c = &xfer->c_ata_c; 1063 int slot = xfer->c_slot; 1064 struct ahci_cmd_tbl *cmd_tbl; 1065 struct ahci_cmd_header *cmd_h; 1066 1067 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1068 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1069 ata_c->timeout, slot), 1070 DEBUG_XFERS); 1071 1072 ata_channel_lock_owned(chp); 1073 KASSERT((achp->ahcic_cmds_active & (1 << slot)) == 0); 1074 1075 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1076 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1077 cmd_tbl), DEBUG_XFERS); 1078 1079 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1080 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1081 1082 cmd_h = &achp->ahcic_cmdh[slot]; 1083 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1084 chp->ch_channel, cmd_h), DEBUG_XFERS); 1085 if (ahci_dma_setup(chp, slot, 1086 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1087 ata_c->data : NULL, 1088 ata_c->bcount, 1089 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1090 ata_c->flags |= AT_DF; 1091 return ATASTART_ABORT; 1092 } 1093 cmd_h->cmdh_flags = htole16( 1094 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1095 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1096 cmd_h->cmdh_prdbc = 0; 1097 AHCI_CMDH_SYNC(sc, achp, slot, 1098 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1099 1100 if (ata_c->flags & AT_POLL) { 1101 /* polled command, disable interrupts */ 1102 AHCI_WRITE(sc, AHCI_GHC, 1103 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1104 } 1105 /* start command */ 1106 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1107 /* and says we started this command */ 1108 achp->ahcic_cmds_active |= 1 << slot; 1109 1110 if ((ata_c->flags & AT_POLL) == 0) { 1111 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 1112 ata_timeout, xfer); 1113 return ATASTART_STARTED; 1114 } else 1115 return ATASTART_POLL; 1116 } 1117 1118 static void 1119 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1120 { 1121 struct ahci_softc *sc = AHCI_CH2SC(chp); 1122 struct ahci_channel *achp = (struct ahci_channel *)chp; 1123 1124 ata_channel_lock(chp); 1125 1126 /* 1127 * Polled command. 1128 */ 1129 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1130 if (xfer->c_ata_c.flags & AT_DONE) 1131 break; 1132 ata_channel_unlock(chp); 1133 ahci_intr_port(sc, achp); 1134 ata_channel_lock(chp); 1135 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1136 } 1137 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1138 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1139 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1140 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1141 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1142 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1143 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1144 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1145 DEBUG_XFERS); 1146 1147 ata_channel_unlock(chp); 1148 1149 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1150 xfer->c_ata_c.flags |= AT_TIMEOU; 1151 xfer->c_intr(chp, xfer, 0); 1152 } 1153 /* reenable interrupts */ 1154 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1155 } 1156 1157 static void 1158 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1159 { 1160 ahci_cmd_complete(chp, xfer, 0); 1161 } 1162 1163 static void 1164 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1165 { 1166 struct ahci_channel *achp = (struct ahci_channel *)chp; 1167 struct ata_command *ata_c = &xfer->c_ata_c; 1168 bool deactivate = true; 1169 1170 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1171 DEBUG_FUNCS); 1172 1173 switch (reason) { 1174 case KILL_GONE_INACTIVE: 1175 deactivate = false; 1176 /* FALLTHROUGH */ 1177 case KILL_GONE: 1178 ata_c->flags |= AT_GONE; 1179 break; 1180 case KILL_RESET: 1181 ata_c->flags |= AT_RESET; 1182 break; 1183 case KILL_REQUEUE: 1184 panic("%s: not supposed to be requeued\n", __func__); 1185 break; 1186 default: 1187 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1188 panic("ahci_cmd_kill_xfer"); 1189 } 1190 1191 if (deactivate) { 1192 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1193 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1194 ata_deactivate_xfer(chp, xfer); 1195 } 1196 1197 ahci_cmd_done_end(chp, xfer); 1198 } 1199 1200 static int 1201 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1202 { 1203 struct ata_command *ata_c = &xfer->c_ata_c; 1204 struct ahci_channel *achp = (struct ahci_channel *)chp; 1205 1206 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1207 chp->ch_channel, 1208 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1209 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1210 DEBUG_FUNCS); 1211 1212 if (ata_waitdrain_xfer_check(chp, xfer)) 1213 return 0; 1214 1215 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1216 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1217 ata_deactivate_xfer(chp, xfer); 1218 1219 if (xfer->c_flags & C_TIMEOU) { 1220 ata_c->flags |= AT_TIMEOU; 1221 } 1222 1223 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1224 ata_c->flags |= AT_TIMEOU; 1225 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1226 ata_c->r_error = AHCI_TFD_ERR(tfd); 1227 ata_c->flags |= AT_ERROR; 1228 } 1229 1230 if (ata_c->flags & AT_READREG) 1231 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1232 1233 ahci_cmd_done(chp, xfer); 1234 return 0; 1235 } 1236 1237 static void 1238 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1239 { 1240 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1241 struct ahci_channel *achp = (struct ahci_channel *)chp; 1242 struct ata_command *ata_c = &xfer->c_ata_c; 1243 uint16_t *idwordbuf; 1244 int flags = ata_c->flags; 1245 int i; 1246 1247 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n", 1248 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1249 1250 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1251 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1252 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1253 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1254 BUS_DMASYNC_POSTWRITE); 1255 bus_dmamap_unload(sc->sc_dmat, map); 1256 } 1257 1258 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1259 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1260 1261 /* ata(4) expects IDENTIFY data to be in host endianess */ 1262 if (ata_c->r_command == WDCC_IDENTIFY || 1263 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1264 idwordbuf = xfer->c_databuf; 1265 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1266 idwordbuf[i] = le16toh(idwordbuf[i]); 1267 } 1268 } 1269 1270 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1271 ata_c->flags |= AT_XFDONE; 1272 ahci_cmd_done_end(chp, xfer); 1273 if ((flags & (AT_TIMEOU|AT_ERROR)) == 0) 1274 atastart(chp); 1275 } 1276 1277 static void 1278 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1279 { 1280 struct ata_command *ata_c = &xfer->c_ata_c; 1281 1282 ata_channel_lock(chp); 1283 1284 ata_c->flags |= AT_DONE; 1285 1286 if (ata_c->flags & AT_WAIT) 1287 ata_wake_xfer(chp, xfer); 1288 1289 ata_channel_unlock(chp); 1290 return; 1291 } 1292 1293 static int 1294 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1295 { 1296 struct ata_channel *chp = drvp->chnl_softc; 1297 struct ata_bio *ata_bio = &xfer->c_bio; 1298 1299 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1300 chp->ch_channel, 1301 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1302 DEBUG_XFERS); 1303 if (ata_bio->flags & ATA_POLL) 1304 xfer->c_flags |= C_POLL; 1305 xfer->c_drive = drvp->drive; 1306 xfer->c_databuf = ata_bio->databuf; 1307 xfer->c_bcount = ata_bio->bcount; 1308 xfer->c_start = ahci_bio_start; 1309 xfer->c_poll = ahci_bio_poll; 1310 xfer->c_abort = ahci_bio_abort; 1311 xfer->c_intr = ahci_bio_complete; 1312 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1313 ata_exec_xfer(chp, xfer); 1314 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1315 } 1316 1317 static int 1318 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1319 { 1320 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1321 struct ahci_channel *achp = (struct ahci_channel *)chp; 1322 struct ata_bio *ata_bio = &xfer->c_bio; 1323 struct ahci_cmd_tbl *cmd_tbl; 1324 struct ahci_cmd_header *cmd_h; 1325 1326 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1327 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1328 1329 ata_channel_lock_owned(chp); 1330 1331 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1332 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1333 cmd_tbl), DEBUG_XFERS); 1334 1335 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1336 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1337 1338 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1339 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1340 chp->ch_channel, cmd_h), DEBUG_XFERS); 1341 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1342 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1343 ata_bio->error = ERR_DMA; 1344 ata_bio->r_error = 0; 1345 return ATASTART_ABORT; 1346 } 1347 cmd_h->cmdh_flags = htole16( 1348 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1349 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1350 cmd_h->cmdh_prdbc = 0; 1351 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1353 1354 if (xfer->c_flags & C_POLL) { 1355 /* polled command, disable interrupts */ 1356 AHCI_WRITE(sc, AHCI_GHC, 1357 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1358 } 1359 if (xfer->c_flags & C_NCQ) 1360 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1 << xfer->c_slot); 1361 /* start command */ 1362 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << xfer->c_slot); 1363 /* and says we started this command */ 1364 achp->ahcic_cmds_active |= 1 << xfer->c_slot; 1365 1366 if ((xfer->c_flags & C_POLL) == 0) { 1367 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1368 ata_timeout, xfer); 1369 return ATASTART_STARTED; 1370 } else 1371 return ATASTART_POLL; 1372 } 1373 1374 static void 1375 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1376 { 1377 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1378 struct ahci_channel *achp = (struct ahci_channel *)chp; 1379 1380 /* 1381 * Polled command. 1382 */ 1383 for (int i = 0; i < ATA_DELAY * 10; i++) { 1384 if (xfer->c_bio.flags & ATA_ITSDONE) 1385 break; 1386 ahci_intr_port(sc, achp); 1387 delay(100); 1388 } 1389 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1390 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1391 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1392 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1393 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1394 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1395 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1396 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1397 DEBUG_XFERS); 1398 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1399 xfer->c_bio.error = TIMEOUT; 1400 xfer->c_intr(chp, xfer, 0); 1401 } 1402 /* reenable interrupts */ 1403 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1404 } 1405 1406 static void 1407 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1408 { 1409 ahci_bio_complete(chp, xfer, 0); 1410 } 1411 1412 static void 1413 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1414 { 1415 int drive = xfer->c_drive; 1416 struct ata_bio *ata_bio = &xfer->c_bio; 1417 struct ahci_channel *achp = (struct ahci_channel *)chp; 1418 bool deactivate = true; 1419 1420 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1421 DEBUG_FUNCS); 1422 1423 ata_bio->flags |= ATA_ITSDONE; 1424 switch (reason) { 1425 case KILL_GONE_INACTIVE: 1426 deactivate = false; 1427 /* FALLTHROUGH */ 1428 case KILL_GONE: 1429 ata_bio->error = ERR_NODEV; 1430 break; 1431 case KILL_RESET: 1432 ata_bio->error = ERR_RESET; 1433 break; 1434 case KILL_REQUEUE: 1435 ata_bio->error = REQUEUE; 1436 break; 1437 default: 1438 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1439 panic("ahci_bio_kill_xfer"); 1440 } 1441 ata_bio->r_error = WDCE_ABRT; 1442 1443 if (deactivate) { 1444 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1445 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1446 ata_deactivate_xfer(chp, xfer); 1447 } 1448 1449 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1450 } 1451 1452 static int 1453 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1454 { 1455 struct ata_bio *ata_bio = &xfer->c_bio; 1456 int drive = xfer->c_drive; 1457 struct ahci_channel *achp = (struct ahci_channel *)chp; 1458 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1459 1460 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1461 DEBUG_FUNCS); 1462 1463 if (ata_waitdrain_xfer_check(chp, xfer)) 1464 return 0; 1465 1466 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1467 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1468 ata_deactivate_xfer(chp, xfer); 1469 1470 if (xfer->c_flags & C_TIMEOU) { 1471 ata_bio->error = TIMEOUT; 1472 } 1473 1474 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1475 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1476 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1477 BUS_DMASYNC_POSTWRITE); 1478 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1479 1480 ata_bio->flags |= ATA_ITSDONE; 1481 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1482 ata_bio->error = ERR_DF; 1483 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1484 ata_bio->error = ERROR; 1485 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1486 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1487 ata_bio->flags |= ATA_CORR; 1488 1489 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1490 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1491 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1492 ata_bio->bcount), DEBUG_XFERS); 1493 /* 1494 * If it was a write, complete data buffer may have been transfered 1495 * before error detection; in this case don't use cmdh_prdbc 1496 * as it won't reflect what was written to media. Assume nothing 1497 * was transfered and leave bcount as-is. 1498 * For queued commands, PRD Byte Count should not be used, and is 1499 * not required to be valid; in that case underflow is always illegal. 1500 */ 1501 if ((xfer->c_flags & C_NCQ) != 0) { 1502 if (ata_bio->error == NOERROR) 1503 ata_bio->bcount = 0; 1504 } else { 1505 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1506 ata_bio->bcount -= 1507 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1508 } 1509 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1510 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1511 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1512 atastart(chp); 1513 return 0; 1514 } 1515 1516 static void 1517 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1518 { 1519 int i; 1520 /* stop channel */ 1521 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1522 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1523 /* wait 1s for channel to stop */ 1524 for (i = 0; i <100; i++) { 1525 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1526 == 0) 1527 break; 1528 ata_delay(chp, 10, "ahcistop", flags); 1529 } 1530 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1531 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1532 /* XXX controller reset ? */ 1533 return; 1534 } 1535 1536 if (sc->sc_channel_stop) 1537 sc->sc_channel_stop(sc, chp); 1538 } 1539 1540 static void 1541 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1542 int flags, int clo) 1543 { 1544 int i; 1545 uint32_t p_cmd; 1546 /* clear error */ 1547 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1548 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1549 1550 if (clo) { 1551 /* issue command list override */ 1552 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1553 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1554 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1555 /* wait 1s for AHCI_CAP_CLO to clear */ 1556 for (i = 0; i <100; i++) { 1557 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1558 AHCI_P_CMD_CLO) == 0) 1559 break; 1560 ata_delay(chp, 10, "ahciclo", flags); 1561 } 1562 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1563 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1564 /* XXX controller reset ? */ 1565 return; 1566 } 1567 } 1568 1569 if (sc->sc_channel_start) 1570 sc->sc_channel_start(sc, chp); 1571 1572 /* and start controller */ 1573 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1574 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1575 if (chp->ch_ndrives > PMP_PORT_CTL && 1576 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1577 p_cmd |= AHCI_P_CMD_PMA; 1578 } 1579 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1580 } 1581 1582 static void 1583 ahci_hold(struct ahci_channel *achp) 1584 { 1585 achp->ahcic_cmds_hold |= achp->ahcic_cmds_active; 1586 achp->ahcic_cmds_active = 0; 1587 } 1588 1589 static void 1590 ahci_unhold(struct ahci_channel *achp) 1591 { 1592 achp->ahcic_cmds_active = achp->ahcic_cmds_hold; 1593 achp->ahcic_cmds_hold = 0; 1594 } 1595 1596 /* Recover channel after command failure */ 1597 void 1598 ahci_channel_recover(struct ahci_softc *sc, struct ata_channel *chp, int tfd) 1599 { 1600 struct ahci_channel *achp = (struct ahci_channel *)chp; 1601 struct ata_drive_datas *drvp; 1602 uint8_t slot, eslot, st, err; 1603 int drive = -1, error; 1604 struct ata_xfer *xfer; 1605 bool reset = false; 1606 1607 KASSERT(!achp->ahcic_recovering); 1608 1609 achp->ahcic_recovering = true; 1610 1611 /* 1612 * Read FBS to get the drive which caused the error, if PM is in use. 1613 * According to AHCI 1.3 spec, this register is available regardless 1614 * if FIS-based switching (FBSS) feature is supported, or disabled. 1615 * If FIS-based switching is not in use, it merely maintains single 1616 * pair of DRQ/BSY state, but it is enough since in that case we 1617 * never issue commands for more than one device at the time anyway. 1618 * XXX untested 1619 */ 1620 if (chp->ch_ndrives > PMP_PORT_CTL) { 1621 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1622 if (fbs & AHCI_P_FBS_SDE) { 1623 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1624 1625 /* 1626 * Tell HBA to reset PM port X (value in DWE) state, 1627 * and resume processing commands for other ports. 1628 */ 1629 fbs |= AHCI_P_FBS_DEC; 1630 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1631 for (int i = 0; i < 1000; i++) { 1632 fbs = AHCI_READ(sc, 1633 AHCI_P_FBS(chp->ch_channel)); 1634 if ((fbs & AHCI_P_FBS_DEC) == 0) 1635 break; 1636 DELAY(1000); 1637 } 1638 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1639 /* follow non-device specific recovery */ 1640 drive = -1; 1641 reset = true; 1642 } 1643 } else { 1644 /* not device specific, reset channel */ 1645 drive = -1; 1646 reset = true; 1647 } 1648 } else 1649 drive = 0; 1650 1651 drvp = &chp->ch_drive[drive]; 1652 1653 /* 1654 * If BSY or DRQ bits are set, must execute COMRESET to return 1655 * device to idle state. If drive is idle, it's enough to just 1656 * reset CMD.ST, it's not necessary to do software reset. 1657 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1658 * to unblock device processing if COMRESET was not done. 1659 */ 1660 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 1661 goto reset; 1662 1663 KASSERT(drive >= 0); 1664 ahci_channel_stop(sc, chp, AT_POLL); 1665 ahci_channel_start(sc, chp, AT_POLL, 1666 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1667 1668 ahci_hold(achp); 1669 1670 /* 1671 * When running NCQ commands, READ LOG EXT is necessary to clear the 1672 * error condition and unblock the device. 1673 */ 1674 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 1675 1676 ahci_unhold(achp); 1677 1678 switch (error) { 1679 case 0: 1680 /* Error out the particular NCQ xfer, then requeue the others */ 1681 if ((achp->ahcic_cmds_active & (1 << eslot)) != 0) { 1682 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 1683 xfer->c_flags |= C_RECOVERED; 1684 xfer->c_intr(chp, xfer, 1685 (err << AHCI_P_TFD_ERR_SHIFT) | st); 1686 } 1687 break; 1688 1689 case EOPNOTSUPP: 1690 /* 1691 * Non-NCQ command error, just find the slot and end with 1692 * the error. 1693 */ 1694 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1695 if ((achp->ahcic_cmds_active & (1 << slot)) != 0) { 1696 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1697 xfer->c_intr(chp, xfer, tfd); 1698 } 1699 } 1700 break; 1701 1702 case EAGAIN: 1703 /* 1704 * Failed to get resources to run the recovery command, must 1705 * reset the drive. This will also kill all still outstanding 1706 * transfers. 1707 */ 1708 reset: 1709 ahci_reset_channel(chp, AT_POLL); 1710 goto out; 1711 /* NOTREACHED */ 1712 1713 default: 1714 /* 1715 * The command to get the slot failed. Kill outstanding 1716 * commands for the same drive only. No need to reset 1717 * the drive, it's unblocked nevertheless. 1718 */ 1719 break; 1720 } 1721 1722 /* Requeue all unfinished commands for same drive as failed command */ 1723 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1724 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 1725 continue; 1726 1727 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1728 if (drive != xfer->c_drive) 1729 continue; 1730 1731 xfer->c_kill_xfer(chp, xfer, 1732 (error == 0) ? KILL_REQUEUE : KILL_RESET); 1733 } 1734 1735 out: 1736 /* Drive unblocked, back to normal operation */ 1737 achp->ahcic_recovering = false; 1738 atastart(chp); 1739 } 1740 1741 static int 1742 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1743 size_t count, int op) 1744 { 1745 int error, seg; 1746 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1747 struct ahci_channel *achp = (struct ahci_channel *)chp; 1748 struct ahci_cmd_tbl *cmd_tbl; 1749 struct ahci_cmd_header *cmd_h; 1750 1751 cmd_h = &achp->ahcic_cmdh[slot]; 1752 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1753 1754 if (data == NULL) { 1755 cmd_h->cmdh_prdtl = 0; 1756 goto end; 1757 } 1758 1759 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1760 data, count, NULL, 1761 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1762 if (error) { 1763 printf("%s port %d: failed to load xfer: %d\n", 1764 AHCINAME(sc), chp->ch_channel, error); 1765 return error; 1766 } 1767 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1768 achp->ahcic_datad[slot]->dm_mapsize, 1769 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1770 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1771 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1772 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1773 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1774 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1775 } 1776 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1777 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1778 end: 1779 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1780 return 0; 1781 } 1782 1783 #if NATAPIBUS > 0 1784 static void 1785 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1786 { 1787 struct ata_channel *chp = ata_sc->sc_chan; 1788 struct atac_softc *atac = chp->ch_atac; 1789 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1790 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1791 /* 1792 * Fill in the scsipi_adapter. 1793 */ 1794 adapt->adapt_dev = atac->atac_dev; 1795 adapt->adapt_nchannels = atac->atac_nchannels; 1796 adapt->adapt_request = ahci_atapi_scsipi_request; 1797 adapt->adapt_minphys = ahci_atapi_minphys; 1798 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1799 1800 /* 1801 * Fill in the scsipi_channel. 1802 */ 1803 memset(chan, 0, sizeof(*chan)); 1804 chan->chan_adapter = adapt; 1805 chan->chan_bustype = &ahci_atapi_bustype; 1806 chan->chan_channel = chp->ch_channel; 1807 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1808 chan->chan_openings = 1; 1809 chan->chan_max_periph = 1; 1810 chan->chan_ntargets = 1; 1811 chan->chan_nluns = 1; 1812 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1813 atapiprint); 1814 } 1815 1816 static void 1817 ahci_atapi_minphys(struct buf *bp) 1818 { 1819 if (bp->b_bcount > MACHINE_MAXPHYS) 1820 bp->b_bcount = MACHINE_MAXPHYS; 1821 minphys(bp); 1822 } 1823 1824 /* 1825 * Kill off all pending xfers for a periph. 1826 * 1827 * Must be called at splbio(). 1828 */ 1829 static void 1830 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1831 { 1832 struct atac_softc *atac = 1833 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1834 struct ata_channel *chp = 1835 atac->atac_channels[periph->periph_channel->chan_channel]; 1836 1837 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1838 } 1839 1840 static void 1841 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1842 scsipi_adapter_req_t req, void *arg) 1843 { 1844 struct scsipi_adapter *adapt = chan->chan_adapter; 1845 struct scsipi_periph *periph; 1846 struct scsipi_xfer *sc_xfer; 1847 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1848 struct atac_softc *atac = &sc->sc_atac; 1849 struct ata_xfer *xfer; 1850 int channel = chan->chan_channel; 1851 int drive, s; 1852 1853 switch (req) { 1854 case ADAPTER_REQ_RUN_XFER: 1855 sc_xfer = arg; 1856 periph = sc_xfer->xs_periph; 1857 drive = periph->periph_target; 1858 if (!device_is_active(atac->atac_dev)) { 1859 sc_xfer->error = XS_DRIVER_STUFFUP; 1860 scsipi_done(sc_xfer); 1861 return; 1862 } 1863 xfer = ata_get_xfer_ext(atac->atac_channels[channel], 0, 0); 1864 if (xfer == NULL) { 1865 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1866 scsipi_done(sc_xfer); 1867 return; 1868 } 1869 1870 if (sc_xfer->xs_control & XS_CTL_POLL) 1871 xfer->c_flags |= C_POLL; 1872 xfer->c_drive = drive; 1873 xfer->c_flags |= C_ATAPI; 1874 xfer->c_scsipi = sc_xfer; 1875 xfer->c_databuf = sc_xfer->data; 1876 xfer->c_bcount = sc_xfer->datalen; 1877 xfer->c_start = ahci_atapi_start; 1878 xfer->c_poll = ahci_atapi_poll; 1879 xfer->c_abort = ahci_atapi_abort; 1880 xfer->c_intr = ahci_atapi_complete; 1881 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1882 xfer->c_dscpoll = 0; 1883 s = splbio(); 1884 ata_exec_xfer(atac->atac_channels[channel], xfer); 1885 #ifdef DIAGNOSTIC 1886 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1887 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1888 panic("ahci_atapi_scsipi_request: polled command " 1889 "not done"); 1890 #endif 1891 splx(s); 1892 return; 1893 default: 1894 /* Not supported, nothing to do. */ 1895 ; 1896 } 1897 } 1898 1899 static int 1900 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1901 { 1902 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1903 struct ahci_channel *achp = (struct ahci_channel *)chp; 1904 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1905 struct ahci_cmd_tbl *cmd_tbl; 1906 struct ahci_cmd_header *cmd_h; 1907 1908 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1909 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1910 1911 ata_channel_lock_owned(chp); 1912 1913 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1914 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1915 cmd_tbl), DEBUG_XFERS); 1916 1917 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1918 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1919 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1920 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1921 1922 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1923 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1924 chp->ch_channel, cmd_h), DEBUG_XFERS); 1925 if (ahci_dma_setup(chp, xfer->c_slot, 1926 sc_xfer->datalen ? sc_xfer->data : NULL, 1927 sc_xfer->datalen, 1928 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1929 BUS_DMA_READ : BUS_DMA_WRITE)) { 1930 sc_xfer->error = XS_DRIVER_STUFFUP; 1931 return ATASTART_ABORT; 1932 } 1933 cmd_h->cmdh_flags = htole16( 1934 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1935 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1936 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1937 cmd_h->cmdh_prdbc = 0; 1938 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1939 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1940 1941 if (xfer->c_flags & C_POLL) { 1942 /* polled command, disable interrupts */ 1943 AHCI_WRITE(sc, AHCI_GHC, 1944 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1945 } 1946 /* start command */ 1947 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << xfer->c_slot); 1948 /* and says we started this command */ 1949 achp->ahcic_cmds_active |= 1 << xfer->c_slot; 1950 1951 if ((xfer->c_flags & C_POLL) == 0) { 1952 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1953 ata_timeout, xfer); 1954 return ATASTART_STARTED; 1955 } else 1956 return ATASTART_POLL; 1957 } 1958 1959 static void 1960 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1961 { 1962 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1963 struct ahci_channel *achp = (struct ahci_channel *)chp; 1964 1965 /* 1966 * Polled command. 1967 */ 1968 for (int i = 0; i < ATA_DELAY / 10; i++) { 1969 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1970 break; 1971 ahci_intr_port(sc, achp); 1972 delay(10000); 1973 } 1974 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1975 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1976 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1977 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1978 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1979 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1980 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1981 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1982 DEBUG_XFERS); 1983 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1984 xfer->c_scsipi->error = XS_TIMEOUT; 1985 xfer->c_intr(chp, xfer, 0); 1986 } 1987 /* reenable interrupts */ 1988 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1989 } 1990 1991 static void 1992 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1993 { 1994 ahci_atapi_complete(chp, xfer, 0); 1995 } 1996 1997 static int 1998 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1999 { 2000 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2001 struct ahci_channel *achp = (struct ahci_channel *)chp; 2002 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 2003 2004 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 2005 DEBUG_FUNCS); 2006 2007 if (ata_waitdrain_xfer_check(chp, xfer)) 2008 return 0; 2009 2010 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 2011 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 2012 ata_deactivate_xfer(chp, xfer); 2013 2014 if (xfer->c_flags & C_TIMEOU) { 2015 sc_xfer->error = XS_TIMEOUT; 2016 } 2017 2018 if (xfer->c_bcount > 0) { 2019 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2020 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2021 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2022 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2023 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2024 } 2025 2026 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2028 sc_xfer->resid = sc_xfer->datalen; 2029 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2030 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2031 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2032 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2033 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2034 sc_xfer->resid == sc_xfer->datalen)) { 2035 sc_xfer->error = XS_SHORTSENSE; 2036 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2037 if ((sc_xfer->xs_periph->periph_quirks & 2038 PQUIRK_NOSENSE) == 0) { 2039 /* ask scsipi to send a REQUEST_SENSE */ 2040 sc_xfer->error = XS_BUSY; 2041 sc_xfer->status = SCSI_CHECK; 2042 } 2043 } 2044 ata_free_xfer(chp, xfer); 2045 scsipi_done(sc_xfer); 2046 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2047 atastart(chp); 2048 return 0; 2049 } 2050 2051 static void 2052 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2053 { 2054 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2055 struct ahci_channel *achp = (struct ahci_channel *)chp; 2056 bool deactivate = true; 2057 2058 /* remove this command from xfer queue */ 2059 switch (reason) { 2060 case KILL_GONE_INACTIVE: 2061 deactivate = false; 2062 /* FALLTHROUGH */ 2063 case KILL_GONE: 2064 sc_xfer->error = XS_DRIVER_STUFFUP; 2065 break; 2066 case KILL_RESET: 2067 sc_xfer->error = XS_RESET; 2068 break; 2069 case KILL_REQUEUE: 2070 sc_xfer->error = XS_REQUEUE; 2071 break; 2072 default: 2073 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2074 panic("ahci_ata_atapi_kill_xfer"); 2075 } 2076 2077 if (deactivate) { 2078 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 2079 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 2080 ata_deactivate_xfer(chp, xfer); 2081 } 2082 2083 ata_free_xfer(chp, xfer); 2084 scsipi_done(sc_xfer); 2085 } 2086 2087 static void 2088 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2089 { 2090 struct scsipi_channel *chan = sc->sc_channel; 2091 struct scsipi_periph *periph; 2092 struct ataparams ids; 2093 struct ataparams *id = &ids; 2094 struct ahci_softc *ahcic = 2095 device_private(chan->chan_adapter->adapt_dev); 2096 struct atac_softc *atac = &ahcic->sc_atac; 2097 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2098 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2099 struct scsipibus_attach_args sa; 2100 char serial_number[21], model[41], firmware_revision[9]; 2101 int s; 2102 2103 /* skip if already attached */ 2104 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2105 return; 2106 2107 /* if no ATAPI device detected at attach time, skip */ 2108 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2109 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2110 "not present\n", target), DEBUG_PROBE); 2111 return; 2112 } 2113 2114 /* Some ATAPI devices need a bit more time after software reset. */ 2115 delay(5000); 2116 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2117 #ifdef ATAPI_DEBUG_PROBE 2118 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2119 AHCINAME(ahcic), target, 2120 id->atap_config & ATAPI_CFG_CMD_MASK, 2121 id->atap_config & ATAPI_CFG_DRQ_MASK); 2122 #endif 2123 periph = scsipi_alloc_periph(M_NOWAIT); 2124 if (periph == NULL) { 2125 aprint_error_dev(sc->sc_dev, 2126 "unable to allocate periph for drive %d\n", 2127 target); 2128 return; 2129 } 2130 periph->periph_dev = NULL; 2131 periph->periph_channel = chan; 2132 periph->periph_switch = &atapi_probe_periphsw; 2133 periph->periph_target = target; 2134 periph->periph_lun = 0; 2135 periph->periph_quirks = PQUIRK_ONLYBIG; 2136 2137 #ifdef SCSIPI_DEBUG 2138 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2139 SCSIPI_DEBUG_TARGET == target) 2140 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2141 #endif 2142 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2143 if (id->atap_config & ATAPI_CFG_REMOV) 2144 periph->periph_flags |= PERIPH_REMOVABLE; 2145 if (periph->periph_type == T_SEQUENTIAL) { 2146 s = splbio(); 2147 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2148 splx(s); 2149 } 2150 2151 sa.sa_periph = periph; 2152 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2153 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2154 T_REMOV : T_FIXED; 2155 strnvisx(model, sizeof(model), id->atap_model, 40, 2156 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2157 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2158 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2159 strnvisx(firmware_revision, sizeof(firmware_revision), 2160 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2161 sa.sa_inqbuf.vendor = model; 2162 sa.sa_inqbuf.product = serial_number; 2163 sa.sa_inqbuf.revision = firmware_revision; 2164 2165 /* 2166 * Determine the operating mode capabilities of the device. 2167 */ 2168 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2169 periph->periph_cap |= PERIPH_CAP_CMD16; 2170 /* XXX This is gross. */ 2171 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2172 2173 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2174 2175 if (drvp->drv_softc) 2176 ata_probe_caps(drvp); 2177 else { 2178 s = splbio(); 2179 drvp->drive_type = ATA_DRIVET_NONE; 2180 splx(s); 2181 } 2182 } else { 2183 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2184 "failed for drive %s:%d:%d\n", 2185 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2186 s = splbio(); 2187 drvp->drive_type = ATA_DRIVET_NONE; 2188 splx(s); 2189 } 2190 } 2191 #endif /* NATAPIBUS */ 2192
Indexes created Fri Oct 17 00:09:41 GMT 2025