ahcisata_core.c revision 1.46
1 /* $NetBSD: ahcisata_core.c,v 1.46 2013/02/02 14:11:37 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.46 2013/02/02 14:11:37 matt Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 62 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 63 static void ahci_reset_channel(struct ata_channel *, int); 64 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 65 static int ahci_ata_addref(struct ata_drive_datas *); 66 static void ahci_ata_delref(struct ata_drive_datas *); 67 static void ahci_killpending(struct ata_drive_datas *); 68 69 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 70 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 74 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 75 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 77 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 78 int, int); 79 static void ahci_timeout(void *); 80 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 static void ahci_atapibus_attach(struct atabus_softc *); 84 static void ahci_atapi_kill_pending(struct scsipi_periph *); 85 static void ahci_atapi_minphys(struct buf *); 86 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 NULL, 100 }; 101 #endif /* NATAPIBUS */ 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 105 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 106 107 const struct ata_bustype ahci_ata_bustype = { 108 SCSIPI_BUSTYPE_ATA, 109 ahci_ata_bio, 110 ahci_reset_drive, 111 ahci_reset_channel, 112 ahci_exec_command, 113 ata_get_params, 114 ahci_ata_addref, 115 ahci_ata_delref, 116 ahci_killpending 117 }; 118 119 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 static int 123 ahci_reset(struct ahci_softc *sc) 124 { 125 int i; 126 127 /* reset controller */ 128 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 129 /* wait up to 1s for reset to complete */ 130 for (i = 0; i < 1000; i++) { 131 delay(1000); 132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 133 break; 134 } 135 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 136 aprint_error("%s: reset failed\n", AHCINAME(sc)); 137 return -1; 138 } 139 /* enable ahci mode */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 141 return 0; 142 } 143 144 static void 145 ahci_setup_ports(struct ahci_softc *sc) 146 { 147 uint32_t ahci_ports; 148 int i, port; 149 150 ahci_ports = AHCI_READ(sc, AHCI_PI); 151 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 152 if ((ahci_ports & (1 << i)) == 0) 153 continue; 154 if (port >= sc->sc_atac.atac_nchannels) { 155 aprint_error("%s: more ports than announced\n", 156 AHCINAME(sc)); 157 break; 158 } 159 ahci_setup_port(sc, i); 160 } 161 } 162 163 static void 164 ahci_reprobe_drives(struct ahci_softc *sc) 165 { 166 uint32_t ahci_ports; 167 int i, port; 168 struct ahci_channel *achp; 169 struct ata_channel *chp; 170 171 ahci_ports = AHCI_READ(sc, AHCI_PI); 172 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 173 if ((ahci_ports & (1 << i)) == 0) 174 continue; 175 if (port >= sc->sc_atac.atac_nchannels) { 176 aprint_error("%s: more ports than announced\n", 177 AHCINAME(sc)); 178 break; 179 } 180 achp = &sc->sc_channels[i]; 181 chp = &achp->ata_channel; 182 183 ahci_probe_drive(chp); 184 } 185 } 186 187 static void 188 ahci_setup_port(struct ahci_softc *sc, int i) 189 { 190 struct ahci_channel *achp; 191 192 achp = &sc->sc_channels[i]; 193 194 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 195 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 196 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 197 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 198 } 199 200 static void 201 ahci_enable_intrs(struct ahci_softc *sc) 202 { 203 204 /* clear interrupts */ 205 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 206 /* enable interrupts */ 207 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 208 } 209 210 void 211 ahci_attach(struct ahci_softc *sc) 212 { 213 uint32_t ahci_rev, ahci_ports; 214 int i, j, port; 215 struct ahci_channel *achp; 216 struct ata_channel *chp; 217 int error; 218 int dmasize; 219 char buf[128]; 220 void *cmdhp; 221 void *cmdtblp; 222 223 if (ahci_reset(sc) != 0) 224 return; 225 226 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 227 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 228 aprint_verbose_dev(sc->sc_atac.atac_dev, 229 "ignoring broken port multiplier support\n"); 230 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 231 } 232 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 233 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 234 ahci_rev = AHCI_READ(sc, AHCI_VS); 235 snprintb(buf, sizeof(buf), "\177\020" 236 /* "f\000\005NP\0" */ 237 "b\005SXS\0" 238 "b\006EMS\0" 239 "b\007CCCS\0" 240 /* "f\010\005NCS\0" */ 241 "b\015PSC\0" 242 "b\016SSC\0" 243 "b\017PMD\0" 244 "b\020FBSS\0" 245 "b\021SPM\0" 246 "b\022SAM\0" 247 "b\023SNZO\0" 248 "f\024\003ISS\0" 249 "=\001Gen1\0" 250 "=\002Gen2\0" 251 "=\003Gen3\0" 252 "b\030SCLO\0" 253 "b\031SAL\0" 254 "b\032SALP\0" 255 "b\033SSS\0" 256 "b\034SMPS\0" 257 "b\035SSNTF\0" 258 "b\036SNCQ\0" 259 "b\037S64A\0" 260 "\0", sc->sc_ahci_cap); 261 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 262 ", %d ports, %d slots, CAP %s\n", 263 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 264 sc->sc_atac.atac_nchannels, sc->sc_ncmds, buf); 265 266 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 267 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 268 sc->sc_atac.atac_pio_cap = 4; 269 sc->sc_atac.atac_dma_cap = 2; 270 sc->sc_atac.atac_udma_cap = 6; 271 sc->sc_atac.atac_channels = sc->sc_chanarray; 272 sc->sc_atac.atac_probe = ahci_probe_drive; 273 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 274 sc->sc_atac.atac_set_modes = ahci_setup_channel; 275 #if NATAPIBUS > 0 276 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 277 #endif 278 279 dmasize = 280 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 281 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 282 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 283 if (error) { 284 aprint_error("%s: unable to allocate command header memory" 285 ", error=%d\n", AHCINAME(sc), error); 286 return; 287 } 288 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 289 sc->sc_cmd_hdr_nseg, dmasize, 290 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 291 if (error) { 292 aprint_error("%s: unable to map command header memory" 293 ", error=%d\n", AHCINAME(sc), error); 294 return; 295 } 296 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 297 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 298 if (error) { 299 aprint_error("%s: unable to create command header map" 300 ", error=%d\n", AHCINAME(sc), error); 301 return; 302 } 303 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 304 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 305 if (error) { 306 aprint_error("%s: unable to load command header map" 307 ", error=%d\n", AHCINAME(sc), error); 308 return; 309 } 310 sc->sc_cmd_hdr = cmdhp; 311 312 ahci_enable_intrs(sc); 313 314 ahci_ports = AHCI_READ(sc, AHCI_PI); 315 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 316 if ((ahci_ports & (1 << i)) == 0) 317 continue; 318 if (port >= sc->sc_atac.atac_nchannels) { 319 aprint_error("%s: more ports than announced\n", 320 AHCINAME(sc)); 321 break; 322 } 323 achp = &sc->sc_channels[i]; 324 chp = &achp->ata_channel; 325 sc->sc_chanarray[i] = chp; 326 chp->ch_channel = i; 327 chp->ch_atac = &sc->sc_atac; 328 chp->ch_queue = malloc(sizeof(struct ata_queue), 329 M_DEVBUF, M_NOWAIT); 330 if (chp->ch_queue == NULL) { 331 aprint_error("%s port %d: can't allocate memory for " 332 "command queue", AHCINAME(sc), i); 333 break; 334 } 335 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 338 BUS_DMA_NOWAIT); 339 if (error) { 340 aprint_error("%s: unable to allocate command table " 341 "memory, error=%d\n", AHCINAME(sc), error); 342 break; 343 } 344 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 345 achp->ahcic_cmd_tbl_nseg, dmasize, 346 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 347 if (error) { 348 aprint_error("%s: unable to map command table memory" 349 ", error=%d\n", AHCINAME(sc), error); 350 break; 351 } 352 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 353 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 354 if (error) { 355 aprint_error("%s: unable to create command table map" 356 ", error=%d\n", AHCINAME(sc), error); 357 break; 358 } 359 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 360 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 361 if (error) { 362 aprint_error("%s: unable to load command table map" 363 ", error=%d\n", AHCINAME(sc), error); 364 break; 365 } 366 achp->ahcic_cmdh = (struct ahci_cmd_header *) 367 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 368 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 369 AHCI_CMDH_SIZE * port; 370 achp->ahcic_rfis = (struct ahci_r_fis *) 371 ((char *)cmdhp + 372 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 373 AHCI_RFIS_SIZE * port); 374 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 375 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 376 AHCI_RFIS_SIZE * port; 377 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 378 "rfis %p (0x%" PRIx64 ")\n", i, 379 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 380 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 381 DEBUG_PROBE); 382 383 for (j = 0; j < sc->sc_ncmds; j++) { 384 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 385 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 386 achp->ahcic_bus_cmd_tbl[j] = 387 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 388 AHCI_CMDTBL_SIZE * j; 389 achp->ahcic_cmdh[j].cmdh_cmdtba = 390 htole64(achp->ahcic_bus_cmd_tbl[j]); 391 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 392 achp->ahcic_cmd_tbl[j], 393 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 394 /* The xfer DMA map */ 395 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 396 AHCI_NPRD, 0x400000 /* 4MB */, 0, 397 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 398 &achp->ahcic_datad[j]); 399 if (error) { 400 aprint_error("%s: couldn't alloc xfer DMA map, " 401 "error=%d\n", AHCINAME(sc), error); 402 goto end; 403 } 404 } 405 ahci_setup_port(sc, i); 406 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 407 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 408 aprint_error("%s: couldn't map channel %d " 409 "sata_status regs\n", AHCINAME(sc), i); 410 break; 411 } 412 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 413 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 414 aprint_error("%s: couldn't map channel %d " 415 "sata_control regs\n", AHCINAME(sc), i); 416 break; 417 } 418 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 419 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 420 aprint_error("%s: couldn't map channel %d " 421 "sata_error regs\n", AHCINAME(sc), i); 422 break; 423 } 424 ata_channel_attach(chp); 425 port++; 426 end: 427 continue; 428 } 429 } 430 431 int 432 ahci_detach(struct ahci_softc *sc, int flags) 433 { 434 struct atac_softc *atac; 435 struct ahci_channel *achp; 436 struct ata_channel *chp; 437 struct scsipi_adapter *adapt; 438 uint32_t ahci_ports; 439 int i, j; 440 int error; 441 442 atac = &sc->sc_atac; 443 adapt = &atac->atac_atapi_adapter._generic; 444 445 ahci_ports = AHCI_READ(sc, AHCI_PI); 446 for (i = 0; i < AHCI_MAX_PORTS; i++) { 447 achp = &sc->sc_channels[i]; 448 chp = &achp->ata_channel; 449 450 if ((ahci_ports & (1 << i)) == 0) 451 continue; 452 if (i >= sc->sc_atac.atac_nchannels) { 453 aprint_error("%s: more ports than announced\n", 454 AHCINAME(sc)); 455 break; 456 } 457 458 if (chp->atabus == NULL) 459 continue; 460 if ((error = config_detach(chp->atabus, flags)) != 0) 461 return error; 462 463 for (j = 0; j < sc->sc_ncmds; j++) 464 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 465 466 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 467 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 468 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 469 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 470 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 471 achp->ahcic_cmd_tbl_nseg); 472 473 free(chp->ch_queue, M_DEVBUF); 474 chp->atabus = NULL; 475 } 476 477 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 478 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 479 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 480 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 481 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 482 483 if (adapt->adapt_refcnt != 0) 484 return EBUSY; 485 486 return 0; 487 } 488 489 void 490 ahci_resume(struct ahci_softc *sc) 491 { 492 ahci_reset(sc); 493 ahci_setup_ports(sc); 494 ahci_reprobe_drives(sc); 495 ahci_enable_intrs(sc); 496 } 497 498 int 499 ahci_intr(void *v) 500 { 501 struct ahci_softc *sc = v; 502 uint32_t is; 503 int i, r = 0; 504 505 while ((is = AHCI_READ(sc, AHCI_IS))) { 506 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 507 DEBUG_INTR); 508 r = 1; 509 AHCI_WRITE(sc, AHCI_IS, is); 510 for (i = 0; i < AHCI_MAX_PORTS; i++) 511 if (is & (1 << i)) 512 ahci_intr_port(sc, &sc->sc_channels[i]); 513 } 514 return r; 515 } 516 517 static void 518 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 519 { 520 uint32_t is, tfd; 521 struct ata_channel *chp = &achp->ata_channel; 522 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 523 int slot; 524 525 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 526 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 527 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 528 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 529 DEBUG_INTR); 530 531 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 532 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 533 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 534 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 535 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 536 return; 537 /* stop channel */ 538 ahci_channel_stop(sc, chp, 0); 539 if (slot != 0) { 540 printf("ahci_intr_port: slot %d\n", slot); 541 panic("ahci_intr_port"); 542 } 543 if (is & AHCI_P_IX_TFES) { 544 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 545 chp->ch_error = 546 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 547 chp->ch_status = (tfd & 0xff); 548 } else { 549 /* emulate a CRC error */ 550 chp->ch_error = WDCE_CRC; 551 chp->ch_status = WDCS_ERR; 552 } 553 if (is & AHCI_P_IX_IFS) { 554 aprint_error("%s port %d: SERR 0x%x\n", 555 AHCINAME(sc), chp->ch_channel, 556 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 557 } 558 xfer->c_intr(chp, xfer, is); 559 /* if channel has not been restarted, do it now */ 560 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 561 == 0) 562 ahci_channel_start(sc, chp, 0, 0); 563 } else { 564 slot = 0; /* XXX */ 565 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 566 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 567 chp->ch_channel, is, achp->ahcic_cmds_active, 568 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 569 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 570 return; 571 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 572 == 0) { 573 xfer->c_intr(chp, xfer, 0); 574 } 575 } 576 } 577 578 static void 579 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 580 { 581 struct ata_channel *chp = drvp->chnl_softc; 582 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 583 AHCI_WRITE(sc, AHCI_GHC, 584 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 585 ahci_channel_stop(sc, chp, flags); 586 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 587 ata_reset_channel(chp, flags); 588 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 589 return; 590 } 591 592 /* return error code from ata_bio */ 593 static int 594 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 595 { 596 struct ahci_channel *achp = (struct ahci_channel *)chp; 597 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 598 int i; 599 uint32_t is; 600 601 timeout = timeout * 10; /* wait is 10ms */ 602 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 603 /* start command */ 604 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 605 for (i = 0; i < timeout; i++) { 606 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 607 return 0; 608 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 609 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 610 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 611 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 612 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 613 /* 614 * we got the D2H FIS anyway, 615 * assume sig is valid. 616 * channel is restarted later 617 */ 618 return ERROR; 619 } 620 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 621 AHCINAME(sc), chp->ch_channel, is); 622 return ERR_DF; 623 } 624 if (flags & AT_WAIT) 625 tsleep(&sc, PRIBIO, "ahcifis", mstohz(10)); 626 else 627 delay(10000); 628 } 629 aprint_debug("%s channel %d: timeout sending FIS\n", 630 AHCINAME(sc), chp->ch_channel); 631 return TIMEOUT; 632 } 633 634 static int 635 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 636 uint32_t *sigp) 637 { 638 struct ahci_channel *achp = (struct ahci_channel *)chp; 639 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 640 struct ahci_cmd_tbl *cmd_tbl; 641 struct ahci_cmd_header *cmd_h; 642 int i; 643 uint32_t sig; 644 645 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 646 again: 647 /* clear port interrupt register */ 648 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 649 /* clear SErrors and start operations */ 650 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 651 /* 652 * issue a command list override to clear BSY. 653 * This is needed if there's a PMP with no drive 654 * on port 0 655 */ 656 ahci_channel_start(sc, chp, flags, 1); 657 } else { 658 ahci_channel_start(sc, chp, flags, 0); 659 } 660 if (drive > 0) { 661 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 662 } 663 /* polled command, assume interrupts are disabled */ 664 /* use slot 0 to send reset, the channel is idle */ 665 cmd_h = &achp->ahcic_cmdh[0]; 666 cmd_tbl = achp->ahcic_cmd_tbl[0]; 667 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 668 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 669 cmd_h->cmdh_prdbc = 0; 670 memset(cmd_tbl->cmdt_cfis, 0, 64); 671 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 672 cmd_tbl->cmdt_cfis[rhd_c] = drive; 673 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 674 switch(ahci_exec_fis(chp, 1, flags)) { 675 case ERR_DF: 676 case TIMEOUT: 677 aprint_error("%s channel %d: setting WDCTL_RST failed " 678 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 679 if (sigp) 680 *sigp = 0xffffffff; 681 goto end; 682 default: 683 break; 684 } 685 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 686 (drive << AHCI_CMDH_F_PMP_SHIFT)); 687 cmd_h->cmdh_prdbc = 0; 688 memset(cmd_tbl->cmdt_cfis, 0, 64); 689 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 690 cmd_tbl->cmdt_cfis[rhd_c] = drive; 691 cmd_tbl->cmdt_cfis[rhd_control] = 0; 692 switch(ahci_exec_fis(chp, 31, flags)) { 693 case ERR_DF: 694 case TIMEOUT: 695 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 696 drive == PMP_PORT_CTL) { 697 /* 698 * some controllers fails to reset when 699 * targeting a PMP but a single drive is attached. 700 * try again with port 0 701 */ 702 drive = 0; 703 ahci_channel_stop(sc, chp, flags); 704 goto again; 705 } 706 aprint_error("%s channel %d: clearing WDCTL_RST failed " 707 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 708 if (sigp) 709 *sigp = 0xffffffff; 710 goto end; 711 default: 712 break; 713 } 714 /* 715 * wait 31s for BSY to clear 716 * This should not be needed, but some controllers clear the 717 * command slot before receiving the D2H FIS ... 718 */ 719 for (i = 0; i < AHCI_RST_WAIT; i++) { 720 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 721 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 722 break; 723 if (flags & AT_WAIT) 724 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 725 else 726 delay(10000); 727 } 728 if (i == AHCI_RST_WAIT) { 729 aprint_error("%s: BSY never cleared, TD 0x%x\n", 730 AHCINAME(sc), sig); 731 if (sigp) 732 *sigp = 0xffffffff; 733 goto end; 734 } 735 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 736 DEBUG_PROBE); 737 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 738 if (sigp) 739 *sigp = sig; 740 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 741 AHCINAME(sc), chp->ch_channel, sig, 742 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 743 end: 744 ahci_channel_stop(sc, chp, flags); 745 if (flags & AT_WAIT) 746 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 747 else 748 delay(500000); 749 /* clear port interrupt register */ 750 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 751 ahci_channel_start(sc, chp, AT_WAIT, 752 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 753 return 0; 754 } 755 756 static void 757 ahci_reset_channel(struct ata_channel *chp, int flags) 758 { 759 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 760 struct ahci_channel *achp = (struct ahci_channel *)chp; 761 int i, tfd; 762 763 ahci_channel_stop(sc, chp, flags); 764 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 765 achp->ahcic_sstatus) != SStatus_DET_DEV) { 766 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 767 /* XXX and then ? */ 768 } 769 if (chp->ch_queue->active_xfer) { 770 chp->ch_queue->active_xfer->c_kill_xfer(chp, 771 chp->ch_queue->active_xfer, KILL_RESET); 772 } 773 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 774 /* clear port interrupt register */ 775 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 776 /* clear SErrors and start operations */ 777 ahci_channel_start(sc, chp, flags, 1); 778 /* wait 31s for BSY to clear */ 779 for (i = 0; i <AHCI_RST_WAIT; i++) { 780 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 781 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 782 & WDCS_BSY) == 0) 783 break; 784 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 785 } 786 if (i == AHCI_RST_WAIT) 787 aprint_error("%s: BSY never cleared, TD 0x%x\n", 788 AHCINAME(sc), tfd); 789 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 790 DEBUG_PROBE); 791 /* clear port interrupt register */ 792 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 793 794 return; 795 } 796 797 static int 798 ahci_ata_addref(struct ata_drive_datas *drvp) 799 { 800 return 0; 801 } 802 803 static void 804 ahci_ata_delref(struct ata_drive_datas *drvp) 805 { 806 return; 807 } 808 809 static void 810 ahci_killpending(struct ata_drive_datas *drvp) 811 { 812 return; 813 } 814 815 static void 816 ahci_probe_drive(struct ata_channel *chp) 817 { 818 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 819 struct ahci_channel *achp = (struct ahci_channel *)chp; 820 uint32_t sig; 821 822 /* bring interface up, accept FISs, power up and spin up device */ 823 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 824 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 825 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 826 /* reset the PHY and bring online */ 827 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 828 achp->ahcic_sstatus)) { 829 case SStatus_DET_DEV: 830 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 831 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 832 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 833 } else { 834 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 835 } 836 sata_interpret_sig(chp, 0, sig); 837 /* if we have a PMP attached, inform the controller */ 838 if (chp->ch_ndrives > PMP_PORT_CTL && 839 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 840 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 841 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 842 AHCI_P_CMD_PMA); 843 } 844 /* clear port interrupt register */ 845 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 846 847 /* and enable interrupts */ 848 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 849 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 850 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 851 AHCI_P_IX_PSS | AHCI_P_IX_DHRS); 852 /* wait 500ms before actually starting operations */ 853 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 854 break; 855 856 default: 857 break; 858 } 859 } 860 861 static void 862 ahci_setup_channel(struct ata_channel *chp) 863 { 864 return; 865 } 866 867 static int 868 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 869 { 870 struct ata_channel *chp = drvp->chnl_softc; 871 struct ata_xfer *xfer; 872 int ret; 873 int s; 874 875 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 876 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 877 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 878 DEBUG_XFERS); 879 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 880 ATAXF_NOSLEEP); 881 if (xfer == NULL) { 882 return ATACMD_TRY_AGAIN; 883 } 884 if (ata_c->flags & AT_POLL) 885 xfer->c_flags |= C_POLL; 886 if (ata_c->flags & AT_WAIT) 887 xfer->c_flags |= C_WAIT; 888 xfer->c_drive = drvp->drive; 889 xfer->c_databuf = ata_c->data; 890 xfer->c_bcount = ata_c->bcount; 891 xfer->c_cmd = ata_c; 892 xfer->c_start = ahci_cmd_start; 893 xfer->c_intr = ahci_cmd_complete; 894 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 895 s = splbio(); 896 ata_exec_xfer(chp, xfer); 897 #ifdef DIAGNOSTIC 898 if ((ata_c->flags & AT_POLL) != 0 && 899 (ata_c->flags & AT_DONE) == 0) 900 panic("ahci_exec_command: polled command not done"); 901 #endif 902 if (ata_c->flags & AT_DONE) { 903 ret = ATACMD_COMPLETE; 904 } else { 905 if (ata_c->flags & AT_WAIT) { 906 while ((ata_c->flags & AT_DONE) == 0) { 907 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 908 } 909 ret = ATACMD_COMPLETE; 910 } else { 911 ret = ATACMD_QUEUED; 912 } 913 } 914 splx(s); 915 return ret; 916 } 917 918 static void 919 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 920 { 921 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 922 struct ahci_channel *achp = (struct ahci_channel *)chp; 923 struct ata_command *ata_c = xfer->c_cmd; 924 int slot = 0 /* XXX slot */; 925 struct ahci_cmd_tbl *cmd_tbl; 926 struct ahci_cmd_header *cmd_h; 927 int i; 928 int channel = chp->ch_channel; 929 930 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n", 931 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout), 932 DEBUG_XFERS); 933 934 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 935 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 936 cmd_tbl), DEBUG_XFERS); 937 938 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 939 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 940 941 cmd_h = &achp->ahcic_cmdh[slot]; 942 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 943 chp->ch_channel, cmd_h), DEBUG_XFERS); 944 if (ahci_dma_setup(chp, slot, 945 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 946 ata_c->data : NULL, 947 ata_c->bcount, 948 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 949 ata_c->flags |= AT_DF; 950 ahci_cmd_complete(chp, xfer, slot); 951 return; 952 } 953 cmd_h->cmdh_flags = htole16( 954 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 955 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 956 cmd_h->cmdh_prdbc = 0; 957 AHCI_CMDH_SYNC(sc, achp, slot, 958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 959 960 if (ata_c->flags & AT_POLL) { 961 /* polled command, disable interrupts */ 962 AHCI_WRITE(sc, AHCI_GHC, 963 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 964 } 965 chp->ch_flags |= ATACH_IRQ_WAIT; 966 chp->ch_status = 0; 967 /* start command */ 968 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 969 /* and says we started this command */ 970 achp->ahcic_cmds_active |= 1 << slot; 971 972 if ((ata_c->flags & AT_POLL) == 0) { 973 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 974 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 975 ahci_timeout, chp); 976 return; 977 } 978 /* 979 * Polled command. 980 */ 981 for (i = 0; i < ata_c->timeout / 10; i++) { 982 if (ata_c->flags & AT_DONE) 983 break; 984 ahci_intr_port(sc, achp); 985 if (ata_c->flags & AT_WAIT) 986 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 987 else 988 delay(10000); 989 } 990 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 991 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 992 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 993 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 994 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 995 DEBUG_XFERS); 996 if ((ata_c->flags & AT_DONE) == 0) { 997 ata_c->flags |= AT_TIMEOU; 998 ahci_cmd_complete(chp, xfer, slot); 999 } 1000 /* reenable interrupts */ 1001 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1002 } 1003 1004 static void 1005 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1006 { 1007 struct ata_command *ata_c = xfer->c_cmd; 1008 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1009 DEBUG_FUNCS); 1010 1011 switch (reason) { 1012 case KILL_GONE: 1013 ata_c->flags |= AT_GONE; 1014 break; 1015 case KILL_RESET: 1016 ata_c->flags |= AT_RESET; 1017 break; 1018 default: 1019 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1020 panic("ahci_cmd_kill_xfer"); 1021 } 1022 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1023 } 1024 1025 static int 1026 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1027 { 1028 int slot = 0; /* XXX slot */ 1029 struct ata_command *ata_c = xfer->c_cmd; 1030 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1031 struct ahci_channel *achp = (struct ahci_channel *)chp; 1032 1033 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1034 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1035 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1036 DEBUG_FUNCS); 1037 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1038 if (xfer->c_flags & C_TIMEOU) { 1039 ata_c->flags |= AT_TIMEOU; 1040 } else 1041 callout_stop(&chp->ch_callout); 1042 1043 chp->ch_queue->active_xfer = NULL; 1044 1045 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1046 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1047 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1048 wakeup(&chp->ch_queue->active_xfer); 1049 return 0; 1050 } 1051 1052 if (chp->ch_status & WDCS_BSY) { 1053 ata_c->flags |= AT_TIMEOU; 1054 } else if (chp->ch_status & WDCS_ERR) { 1055 ata_c->r_error = chp->ch_error; 1056 ata_c->flags |= AT_ERROR; 1057 } 1058 1059 if (ata_c->flags & AT_READREG) 1060 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1061 1062 ahci_cmd_done(chp, xfer, slot); 1063 return 0; 1064 } 1065 1066 static void 1067 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1068 { 1069 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1070 struct ahci_channel *achp = (struct ahci_channel *)chp; 1071 struct ata_command *ata_c = xfer->c_cmd; 1072 uint16_t *idwordbuf; 1073 int i; 1074 1075 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n", 1076 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1077 1078 /* this comamnd is not active any more */ 1079 achp->ahcic_cmds_active &= ~(1 << slot); 1080 1081 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1082 bus_dmamap_t map = achp->ahcic_datad[slot]; 1083 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1084 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1085 BUS_DMASYNC_POSTWRITE); 1086 bus_dmamap_unload(sc->sc_dmat, map); 1087 } 1088 1089 AHCI_CMDH_SYNC(sc, achp, slot, 1090 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1091 1092 /* ata(4) expects IDENTIFY data to be in host endianess */ 1093 if (ata_c->r_command == WDCC_IDENTIFY || 1094 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1095 idwordbuf = xfer->c_databuf; 1096 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1097 idwordbuf[i] = le16toh(idwordbuf[i]); 1098 } 1099 } 1100 1101 ata_c->flags |= AT_DONE; 1102 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1103 ata_c->flags |= AT_XFDONE; 1104 1105 ata_free_xfer(chp, xfer); 1106 if (ata_c->flags & AT_WAIT) 1107 wakeup(ata_c); 1108 else if (ata_c->callback) 1109 ata_c->callback(ata_c->callback_arg); 1110 atastart(chp); 1111 return; 1112 } 1113 1114 static int 1115 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1116 { 1117 struct ata_channel *chp = drvp->chnl_softc; 1118 struct ata_xfer *xfer; 1119 1120 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1121 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1122 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1123 DEBUG_XFERS); 1124 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1125 if (xfer == NULL) { 1126 return ATACMD_TRY_AGAIN; 1127 } 1128 if (ata_bio->flags & ATA_POLL) 1129 xfer->c_flags |= C_POLL; 1130 xfer->c_drive = drvp->drive; 1131 xfer->c_cmd = ata_bio; 1132 xfer->c_databuf = ata_bio->databuf; 1133 xfer->c_bcount = ata_bio->bcount; 1134 xfer->c_start = ahci_bio_start; 1135 xfer->c_intr = ahci_bio_complete; 1136 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1137 ata_exec_xfer(chp, xfer); 1138 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1139 } 1140 1141 static void 1142 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1143 { 1144 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1145 struct ahci_channel *achp = (struct ahci_channel *)chp; 1146 struct ata_bio *ata_bio = xfer->c_cmd; 1147 int slot = 0 /* XXX slot */; 1148 struct ahci_cmd_tbl *cmd_tbl; 1149 struct ahci_cmd_header *cmd_h; 1150 int i; 1151 int channel = chp->ch_channel; 1152 1153 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1154 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1155 1156 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1157 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1158 cmd_tbl), DEBUG_XFERS); 1159 1160 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1161 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1162 1163 cmd_h = &achp->ahcic_cmdh[slot]; 1164 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1165 chp->ch_channel, cmd_h), DEBUG_XFERS); 1166 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1167 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1168 ata_bio->error = ERR_DMA; 1169 ata_bio->r_error = 0; 1170 ahci_bio_complete(chp, xfer, slot); 1171 return; 1172 } 1173 cmd_h->cmdh_flags = htole16( 1174 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1175 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1176 cmd_h->cmdh_prdbc = 0; 1177 AHCI_CMDH_SYNC(sc, achp, slot, 1178 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1179 1180 if (xfer->c_flags & C_POLL) { 1181 /* polled command, disable interrupts */ 1182 AHCI_WRITE(sc, AHCI_GHC, 1183 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1184 } 1185 chp->ch_flags |= ATACH_IRQ_WAIT; 1186 chp->ch_status = 0; 1187 /* start command */ 1188 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1189 /* and says we started this command */ 1190 achp->ahcic_cmds_active |= 1 << slot; 1191 1192 if ((xfer->c_flags & C_POLL) == 0) { 1193 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1194 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1195 ahci_timeout, chp); 1196 return; 1197 } 1198 /* 1199 * Polled command. 1200 */ 1201 for (i = 0; i < ATA_DELAY / 10; i++) { 1202 if (ata_bio->flags & ATA_ITSDONE) 1203 break; 1204 ahci_intr_port(sc, achp); 1205 if (ata_bio->flags & ATA_NOSLEEP) 1206 delay(10000); 1207 else 1208 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1209 } 1210 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1211 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1212 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1213 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1214 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1215 DEBUG_XFERS); 1216 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1217 ata_bio->error = TIMEOUT; 1218 ahci_bio_complete(chp, xfer, slot); 1219 } 1220 /* reenable interrupts */ 1221 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1222 } 1223 1224 static void 1225 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1226 { 1227 int slot = 0; /* XXX slot */ 1228 int drive = xfer->c_drive; 1229 struct ata_bio *ata_bio = xfer->c_cmd; 1230 struct ahci_channel *achp = (struct ahci_channel *)chp; 1231 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1232 DEBUG_FUNCS); 1233 1234 achp->ahcic_cmds_active &= ~(1 << slot); 1235 ata_free_xfer(chp, xfer); 1236 ata_bio->flags |= ATA_ITSDONE; 1237 switch (reason) { 1238 case KILL_GONE: 1239 ata_bio->error = ERR_NODEV; 1240 break; 1241 case KILL_RESET: 1242 ata_bio->error = ERR_RESET; 1243 break; 1244 default: 1245 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1246 panic("ahci_bio_kill_xfer"); 1247 } 1248 ata_bio->r_error = WDCE_ABRT; 1249 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1250 } 1251 1252 static int 1253 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1254 { 1255 int slot = 0; /* XXX slot */ 1256 struct ata_bio *ata_bio = xfer->c_cmd; 1257 int drive = xfer->c_drive; 1258 struct ahci_channel *achp = (struct ahci_channel *)chp; 1259 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1260 1261 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1262 DEBUG_FUNCS); 1263 1264 achp->ahcic_cmds_active &= ~(1 << slot); 1265 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1266 if (xfer->c_flags & C_TIMEOU) { 1267 ata_bio->error = TIMEOUT; 1268 } else { 1269 callout_stop(&chp->ch_callout); 1270 ata_bio->error = NOERROR; 1271 } 1272 1273 chp->ch_queue->active_xfer = NULL; 1274 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1275 achp->ahcic_datad[slot]->dm_mapsize, 1276 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1277 BUS_DMASYNC_POSTWRITE); 1278 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1279 1280 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1281 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1282 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1283 wakeup(&chp->ch_queue->active_xfer); 1284 return 0; 1285 } 1286 ata_free_xfer(chp, xfer); 1287 ata_bio->flags |= ATA_ITSDONE; 1288 if (chp->ch_status & WDCS_DWF) { 1289 ata_bio->error = ERR_DF; 1290 } else if (chp->ch_status & WDCS_ERR) { 1291 ata_bio->error = ERROR; 1292 ata_bio->r_error = chp->ch_error; 1293 } else if (chp->ch_status & WDCS_CORR) 1294 ata_bio->flags |= ATA_CORR; 1295 1296 AHCI_CMDH_SYNC(sc, achp, slot, 1297 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1298 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1299 ata_bio->bcount), DEBUG_XFERS); 1300 /* 1301 * if it was a write, complete data buffer may have been transfered 1302 * before error detection; in this case don't use cmdh_prdbc 1303 * as it won't reflect what was written to media. Assume nothing 1304 * was transfered and leave bcount as-is. 1305 */ 1306 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1307 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1308 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1309 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1310 atastart(chp); 1311 return 0; 1312 } 1313 1314 static void 1315 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1316 { 1317 int i; 1318 /* stop channel */ 1319 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1320 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1321 /* wait 1s for channel to stop */ 1322 for (i = 0; i <100; i++) { 1323 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1324 == 0) 1325 break; 1326 if (flags & AT_WAIT) 1327 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1328 else 1329 delay(10000); 1330 } 1331 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1332 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1333 /* XXX controller reset ? */ 1334 return; 1335 } 1336 } 1337 1338 static void 1339 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1340 int flags, int clo) 1341 { 1342 int i; 1343 uint32_t p_cmd; 1344 /* clear error */ 1345 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1346 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1347 1348 if (clo) { 1349 /* issue command list override */ 1350 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1351 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1352 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1353 /* wait 1s for AHCI_CAP_CLO to clear */ 1354 for (i = 0; i <100; i++) { 1355 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1356 AHCI_P_CMD_CLO) == 0) 1357 break; 1358 if (flags & AT_WAIT) 1359 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1360 else 1361 delay(10000); 1362 } 1363 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1364 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1365 /* XXX controller reset ? */ 1366 return; 1367 } 1368 } 1369 /* and start controller */ 1370 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1371 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1372 if (chp->ch_ndrives > PMP_PORT_CTL && 1373 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1374 p_cmd |= AHCI_P_CMD_PMA; 1375 } 1376 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1377 } 1378 1379 static void 1380 ahci_timeout(void *v) 1381 { 1382 struct ata_channel *chp = (struct ata_channel *)v; 1383 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1384 #ifdef AHCI_DEBUG 1385 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1386 #endif 1387 int s = splbio(); 1388 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel))), DEBUG_INTR); 1389 1390 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1391 xfer->c_flags |= C_TIMEOU; 1392 xfer->c_intr(chp, xfer, 0); 1393 } 1394 splx(s); 1395 } 1396 1397 static int 1398 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1399 size_t count, int op) 1400 { 1401 int error, seg; 1402 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1403 struct ahci_channel *achp = (struct ahci_channel *)chp; 1404 struct ahci_cmd_tbl *cmd_tbl; 1405 struct ahci_cmd_header *cmd_h; 1406 1407 cmd_h = &achp->ahcic_cmdh[slot]; 1408 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1409 1410 if (data == NULL) { 1411 cmd_h->cmdh_prdtl = 0; 1412 goto end; 1413 } 1414 1415 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1416 data, count, NULL, 1417 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1418 if (error) { 1419 printf("%s port %d: failed to load xfer: %d\n", 1420 AHCINAME(sc), chp->ch_channel, error); 1421 return error; 1422 } 1423 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1424 achp->ahcic_datad[slot]->dm_mapsize, 1425 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1426 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1427 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1428 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1429 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1430 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1431 } 1432 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1433 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1434 end: 1435 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1436 return 0; 1437 } 1438 1439 #if NATAPIBUS > 0 1440 static void 1441 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1442 { 1443 struct ata_channel *chp = ata_sc->sc_chan; 1444 struct atac_softc *atac = chp->ch_atac; 1445 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1446 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1447 /* 1448 * Fill in the scsipi_adapter. 1449 */ 1450 adapt->adapt_dev = atac->atac_dev; 1451 adapt->adapt_nchannels = atac->atac_nchannels; 1452 adapt->adapt_request = ahci_atapi_scsipi_request; 1453 adapt->adapt_minphys = ahci_atapi_minphys; 1454 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1455 1456 /* 1457 * Fill in the scsipi_channel. 1458 */ 1459 memset(chan, 0, sizeof(*chan)); 1460 chan->chan_adapter = adapt; 1461 chan->chan_bustype = &ahci_atapi_bustype; 1462 chan->chan_channel = chp->ch_channel; 1463 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1464 chan->chan_openings = 1; 1465 chan->chan_max_periph = 1; 1466 chan->chan_ntargets = 1; 1467 chan->chan_nluns = 1; 1468 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1469 atapiprint); 1470 } 1471 1472 static void 1473 ahci_atapi_minphys(struct buf *bp) 1474 { 1475 if (bp->b_bcount > MAXPHYS) 1476 bp->b_bcount = MAXPHYS; 1477 minphys(bp); 1478 } 1479 1480 /* 1481 * Kill off all pending xfers for a periph. 1482 * 1483 * Must be called at splbio(). 1484 */ 1485 static void 1486 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1487 { 1488 struct atac_softc *atac = 1489 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1490 struct ata_channel *chp = 1491 atac->atac_channels[periph->periph_channel->chan_channel]; 1492 1493 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1494 } 1495 1496 static void 1497 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1498 scsipi_adapter_req_t req, void *arg) 1499 { 1500 struct scsipi_adapter *adapt = chan->chan_adapter; 1501 struct scsipi_periph *periph; 1502 struct scsipi_xfer *sc_xfer; 1503 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1504 struct atac_softc *atac = &sc->sc_atac; 1505 struct ata_xfer *xfer; 1506 int channel = chan->chan_channel; 1507 int drive, s; 1508 1509 switch (req) { 1510 case ADAPTER_REQ_RUN_XFER: 1511 sc_xfer = arg; 1512 periph = sc_xfer->xs_periph; 1513 drive = periph->periph_target; 1514 if (!device_is_active(atac->atac_dev)) { 1515 sc_xfer->error = XS_DRIVER_STUFFUP; 1516 scsipi_done(sc_xfer); 1517 return; 1518 } 1519 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1520 if (xfer == NULL) { 1521 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1522 scsipi_done(sc_xfer); 1523 return; 1524 } 1525 1526 if (sc_xfer->xs_control & XS_CTL_POLL) 1527 xfer->c_flags |= C_POLL; 1528 xfer->c_drive = drive; 1529 xfer->c_flags |= C_ATAPI; 1530 xfer->c_cmd = sc_xfer; 1531 xfer->c_databuf = sc_xfer->data; 1532 xfer->c_bcount = sc_xfer->datalen; 1533 xfer->c_start = ahci_atapi_start; 1534 xfer->c_intr = ahci_atapi_complete; 1535 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1536 xfer->c_dscpoll = 0; 1537 s = splbio(); 1538 ata_exec_xfer(atac->atac_channels[channel], xfer); 1539 #ifdef DIAGNOSTIC 1540 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1541 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1542 panic("ahci_atapi_scsipi_request: polled command " 1543 "not done"); 1544 #endif 1545 splx(s); 1546 return; 1547 default: 1548 /* Not supported, nothing to do. */ 1549 ; 1550 } 1551 } 1552 1553 static void 1554 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1555 { 1556 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1557 struct ahci_channel *achp = (struct ahci_channel *)chp; 1558 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1559 int slot = 0 /* XXX slot */; 1560 struct ahci_cmd_tbl *cmd_tbl; 1561 struct ahci_cmd_header *cmd_h; 1562 int i; 1563 int channel = chp->ch_channel; 1564 1565 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1566 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1567 1568 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1569 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1570 cmd_tbl), DEBUG_XFERS); 1571 1572 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1573 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1574 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1575 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1576 1577 cmd_h = &achp->ahcic_cmdh[slot]; 1578 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1579 chp->ch_channel, cmd_h), DEBUG_XFERS); 1580 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1581 sc_xfer->datalen, 1582 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1583 BUS_DMA_READ : BUS_DMA_WRITE)) { 1584 sc_xfer->error = XS_DRIVER_STUFFUP; 1585 ahci_atapi_complete(chp, xfer, slot); 1586 return; 1587 } 1588 cmd_h->cmdh_flags = htole16( 1589 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1590 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1591 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1592 cmd_h->cmdh_prdbc = 0; 1593 AHCI_CMDH_SYNC(sc, achp, slot, 1594 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1595 1596 if (xfer->c_flags & C_POLL) { 1597 /* polled command, disable interrupts */ 1598 AHCI_WRITE(sc, AHCI_GHC, 1599 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1600 } 1601 chp->ch_flags |= ATACH_IRQ_WAIT; 1602 chp->ch_status = 0; 1603 /* start command */ 1604 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1605 /* and says we started this command */ 1606 achp->ahcic_cmds_active |= 1 << slot; 1607 1608 if ((xfer->c_flags & C_POLL) == 0) { 1609 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1610 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1611 ahci_timeout, chp); 1612 return; 1613 } 1614 /* 1615 * Polled command. 1616 */ 1617 for (i = 0; i < ATA_DELAY / 10; i++) { 1618 if (sc_xfer->xs_status & XS_STS_DONE) 1619 break; 1620 ahci_intr_port(sc, achp); 1621 delay(10000); 1622 } 1623 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1624 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1625 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1626 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1627 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1628 DEBUG_XFERS); 1629 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1630 sc_xfer->error = XS_TIMEOUT; 1631 ahci_atapi_complete(chp, xfer, slot); 1632 } 1633 /* reenable interrupts */ 1634 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1635 } 1636 1637 static int 1638 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1639 { 1640 int slot = 0; /* XXX slot */ 1641 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1642 int drive = xfer->c_drive; 1643 struct ahci_channel *achp = (struct ahci_channel *)chp; 1644 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1645 1646 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1647 DEBUG_FUNCS); 1648 1649 achp->ahcic_cmds_active &= ~(1 << slot); 1650 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1651 if (xfer->c_flags & C_TIMEOU) { 1652 sc_xfer->error = XS_TIMEOUT; 1653 } else { 1654 callout_stop(&chp->ch_callout); 1655 sc_xfer->error = 0; 1656 } 1657 1658 chp->ch_queue->active_xfer = NULL; 1659 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1660 achp->ahcic_datad[slot]->dm_mapsize, 1661 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1662 BUS_DMASYNC_POSTWRITE); 1663 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1664 1665 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1666 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1667 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1668 wakeup(&chp->ch_queue->active_xfer); 1669 return 0; 1670 } 1671 ata_free_xfer(chp, xfer); 1672 1673 AHCI_CMDH_SYNC(sc, achp, slot, 1674 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1675 sc_xfer->resid = sc_xfer->datalen; 1676 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1677 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1678 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1679 if (chp->ch_status & WDCS_ERR && 1680 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1681 sc_xfer->resid == sc_xfer->datalen)) { 1682 sc_xfer->error = XS_SHORTSENSE; 1683 sc_xfer->sense.atapi_sense = chp->ch_error; 1684 if ((sc_xfer->xs_periph->periph_quirks & 1685 PQUIRK_NOSENSE) == 0) { 1686 /* ask scsipi to send a REQUEST_SENSE */ 1687 sc_xfer->error = XS_BUSY; 1688 sc_xfer->status = SCSI_CHECK; 1689 } 1690 } 1691 scsipi_done(sc_xfer); 1692 atastart(chp); 1693 return 0; 1694 } 1695 1696 static void 1697 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1698 { 1699 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1700 struct ahci_channel *achp = (struct ahci_channel *)chp; 1701 int slot = 0; /* XXX slot */ 1702 1703 achp->ahcic_cmds_active &= ~(1 << slot); 1704 1705 /* remove this command from xfer queue */ 1706 switch (reason) { 1707 case KILL_GONE: 1708 sc_xfer->error = XS_DRIVER_STUFFUP; 1709 break; 1710 case KILL_RESET: 1711 sc_xfer->error = XS_RESET; 1712 break; 1713 default: 1714 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1715 panic("ahci_ata_atapi_kill_xfer"); 1716 } 1717 ata_free_xfer(chp, xfer); 1718 scsipi_done(sc_xfer); 1719 } 1720 1721 static void 1722 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1723 { 1724 struct scsipi_channel *chan = sc->sc_channel; 1725 struct scsipi_periph *periph; 1726 struct ataparams ids; 1727 struct ataparams *id = &ids; 1728 struct ahci_softc *ahcic = 1729 device_private(chan->chan_adapter->adapt_dev); 1730 struct atac_softc *atac = &ahcic->sc_atac; 1731 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1732 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1733 struct scsipibus_attach_args sa; 1734 char serial_number[21], model[41], firmware_revision[9]; 1735 int s; 1736 1737 /* skip if already attached */ 1738 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1739 return; 1740 1741 /* if no ATAPI device detected at attach time, skip */ 1742 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1743 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1744 "not present\n", target), DEBUG_PROBE); 1745 return; 1746 } 1747 1748 /* Some ATAPI devices need a bit more time after software reset. */ 1749 delay(5000); 1750 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1751 #ifdef ATAPI_DEBUG_PROBE 1752 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1753 AHCINAME(ahcic), target, 1754 id->atap_config & ATAPI_CFG_CMD_MASK, 1755 id->atap_config & ATAPI_CFG_DRQ_MASK); 1756 #endif 1757 periph = scsipi_alloc_periph(M_NOWAIT); 1758 if (periph == NULL) { 1759 aprint_error_dev(sc->sc_dev, 1760 "unable to allocate periph for drive %d\n", 1761 target); 1762 return; 1763 } 1764 periph->periph_dev = NULL; 1765 periph->periph_channel = chan; 1766 periph->periph_switch = &atapi_probe_periphsw; 1767 periph->periph_target = target; 1768 periph->periph_lun = 0; 1769 periph->periph_quirks = PQUIRK_ONLYBIG; 1770 1771 #ifdef SCSIPI_DEBUG 1772 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1773 SCSIPI_DEBUG_TARGET == target) 1774 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1775 #endif 1776 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1777 if (id->atap_config & ATAPI_CFG_REMOV) 1778 periph->periph_flags |= PERIPH_REMOVABLE; 1779 if (periph->periph_type == T_SEQUENTIAL) { 1780 s = splbio(); 1781 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1782 splx(s); 1783 } 1784 1785 sa.sa_periph = periph; 1786 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1787 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1788 T_REMOV : T_FIXED; 1789 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1790 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1791 20); 1792 scsipi_strvis((u_char *)firmware_revision, 8, 1793 id->atap_revision, 8); 1794 sa.sa_inqbuf.vendor = model; 1795 sa.sa_inqbuf.product = serial_number; 1796 sa.sa_inqbuf.revision = firmware_revision; 1797 1798 /* 1799 * Determine the operating mode capabilities of the device. 1800 */ 1801 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1802 periph->periph_cap |= PERIPH_CAP_CMD16; 1803 /* XXX This is gross. */ 1804 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1805 1806 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1807 1808 if (drvp->drv_softc) 1809 ata_probe_caps(drvp); 1810 else { 1811 s = splbio(); 1812 drvp->drive_type = ATA_DRIVET_NONE; 1813 splx(s); 1814 } 1815 } else { 1816 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1817 "failed for drive %s:%d:%d: error 0x%x\n", 1818 AHCINAME(ahcic), chp->ch_channel, target, 1819 chp->ch_error), DEBUG_PROBE); 1820 s = splbio(); 1821 drvp->drive_type = ATA_DRIVET_NONE; 1822 splx(s); 1823 } 1824 } 1825 #endif /* NATAPIBUS */ 1826
Indexes created Fri Sep 26 08:10:20 GMT 2025