ahcisata_core.c revision 1.52
1 /* $NetBSD: ahcisata_core.c,v 1.52 2014/11/23 01:38:49 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.52 2014/11/23 01:38:49 joerg Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 62 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 63 static void ahci_reset_channel(struct ata_channel *, int); 64 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 65 static int ahci_ata_addref(struct ata_drive_datas *); 66 static void ahci_ata_delref(struct ata_drive_datas *); 67 static void ahci_killpending(struct ata_drive_datas *); 68 69 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 70 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 74 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 75 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 77 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 78 int, int); 79 static void ahci_timeout(void *); 80 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 static void ahci_atapibus_attach(struct atabus_softc *); 84 static void ahci_atapi_kill_pending(struct scsipi_periph *); 85 static void ahci_atapi_minphys(struct buf *); 86 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 NULL, 100 }; 101 #endif /* NATAPIBUS */ 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 105 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 106 107 const struct ata_bustype ahci_ata_bustype = { 108 SCSIPI_BUSTYPE_ATA, 109 ahci_ata_bio, 110 ahci_reset_drive, 111 ahci_reset_channel, 112 ahci_exec_command, 113 ata_get_params, 114 ahci_ata_addref, 115 ahci_ata_delref, 116 ahci_killpending 117 }; 118 119 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 static void 123 ahci_enable(struct ahci_softc *sc) 124 { 125 uint32_t ghc; 126 127 ghc = AHCI_READ(sc, AHCI_GHC); 128 if (!(ghc & AHCI_GHC_AE)) { 129 ghc |= AHCI_GHC_AE; 130 AHCI_WRITE(sc, AHCI_GHC, ghc); 131 } 132 } 133 134 static int 135 ahci_reset(struct ahci_softc *sc) 136 { 137 int i; 138 139 /* reset controller */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 141 /* wait up to 1s for reset to complete */ 142 for (i = 0; i < 1000; i++) { 143 delay(1000); 144 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 145 break; 146 } 147 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 148 aprint_error("%s: reset failed\n", AHCINAME(sc)); 149 return -1; 150 } 151 /* enable ahci mode */ 152 ahci_enable(sc); 153 154 if (sc->sc_save_init_data) { 155 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 156 if (sc->sc_init_data.cap2) 157 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 158 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 159 } 160 161 return 0; 162 } 163 164 static void 165 ahci_setup_ports(struct ahci_softc *sc) 166 { 167 int i, port; 168 169 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 170 if ((sc->sc_ahci_ports & (1 << i)) == 0) 171 continue; 172 if (port >= sc->sc_atac.atac_nchannels) { 173 aprint_error("%s: more ports than announced\n", 174 AHCINAME(sc)); 175 break; 176 } 177 ahci_setup_port(sc, i); 178 } 179 } 180 181 static void 182 ahci_reprobe_drives(struct ahci_softc *sc) 183 { 184 int i, port; 185 struct ahci_channel *achp; 186 struct ata_channel *chp; 187 188 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 189 if ((sc->sc_ahci_ports & (1 << i)) == 0) 190 continue; 191 if (port >= sc->sc_atac.atac_nchannels) { 192 aprint_error("%s: more ports than announced\n", 193 AHCINAME(sc)); 194 break; 195 } 196 achp = &sc->sc_channels[i]; 197 chp = &achp->ata_channel; 198 199 ahci_probe_drive(chp); 200 } 201 } 202 203 static void 204 ahci_setup_port(struct ahci_softc *sc, int i) 205 { 206 struct ahci_channel *achp; 207 208 achp = &sc->sc_channels[i]; 209 210 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 211 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 212 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 213 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 214 } 215 216 static void 217 ahci_enable_intrs(struct ahci_softc *sc) 218 { 219 220 /* clear interrupts */ 221 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 222 /* enable interrupts */ 223 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 224 } 225 226 void 227 ahci_attach(struct ahci_softc *sc) 228 { 229 uint32_t ahci_rev; 230 int i, j, port; 231 struct ahci_channel *achp; 232 struct ata_channel *chp; 233 int error; 234 int dmasize; 235 char buf[128]; 236 void *cmdhp; 237 void *cmdtblp; 238 239 if (sc->sc_save_init_data) { 240 ahci_enable(sc); 241 242 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 243 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 244 245 ahci_rev = AHCI_READ(sc, AHCI_VS); 246 if (AHCI_VS_MJR(ahci_rev) > 1 || 247 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 248 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 249 } else { 250 sc->sc_init_data.cap2 = 0; 251 } 252 if (sc->sc_init_data.ports == 0) { 253 sc->sc_init_data.ports = sc->sc_ahci_ports; 254 } 255 } 256 257 if (ahci_reset(sc) != 0) 258 return; 259 260 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 261 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 262 aprint_verbose_dev(sc->sc_atac.atac_dev, 263 "ignoring broken port multiplier support\n"); 264 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 265 } 266 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 267 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 268 ahci_rev = AHCI_READ(sc, AHCI_VS); 269 snprintb(buf, sizeof(buf), "\177\020" 270 /* "f\000\005NP\0" */ 271 "b\005SXS\0" 272 "b\006EMS\0" 273 "b\007CCCS\0" 274 /* "f\010\005NCS\0" */ 275 "b\015PSC\0" 276 "b\016SSC\0" 277 "b\017PMD\0" 278 "b\020FBSS\0" 279 "b\021SPM\0" 280 "b\022SAM\0" 281 "b\023SNZO\0" 282 "f\024\003ISS\0" 283 "=\001Gen1\0" 284 "=\002Gen2\0" 285 "=\003Gen3\0" 286 "b\030SCLO\0" 287 "b\031SAL\0" 288 "b\032SALP\0" 289 "b\033SSS\0" 290 "b\034SMPS\0" 291 "b\035SSNTF\0" 292 "b\036SNCQ\0" 293 "b\037S64A\0" 294 "\0", sc->sc_ahci_cap); 295 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 296 ", %d port%s, %d slot%s, CAP %s\n", 297 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 298 sc->sc_atac.atac_nchannels, 299 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 300 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 301 302 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 303 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 304 sc->sc_atac.atac_pio_cap = 4; 305 sc->sc_atac.atac_dma_cap = 2; 306 sc->sc_atac.atac_udma_cap = 6; 307 sc->sc_atac.atac_channels = sc->sc_chanarray; 308 sc->sc_atac.atac_probe = ahci_probe_drive; 309 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 310 sc->sc_atac.atac_set_modes = ahci_setup_channel; 311 #if NATAPIBUS > 0 312 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 313 #endif 314 315 dmasize = 316 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 318 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 319 if (error) { 320 aprint_error("%s: unable to allocate command header memory" 321 ", error=%d\n", AHCINAME(sc), error); 322 return; 323 } 324 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 325 sc->sc_cmd_hdr_nseg, dmasize, 326 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 327 if (error) { 328 aprint_error("%s: unable to map command header memory" 329 ", error=%d\n", AHCINAME(sc), error); 330 return; 331 } 332 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 333 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 334 if (error) { 335 aprint_error("%s: unable to create command header map" 336 ", error=%d\n", AHCINAME(sc), error); 337 return; 338 } 339 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 340 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error("%s: unable to load command header map" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 sc->sc_cmd_hdr = cmdhp; 347 348 ahci_enable_intrs(sc); 349 350 if (sc->sc_ahci_ports == 0) { 351 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 352 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 353 DEBUG_PROBE); 354 } 355 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 356 if ((sc->sc_ahci_ports & (1 << i)) == 0) 357 continue; 358 if (port >= sc->sc_atac.atac_nchannels) { 359 aprint_error("%s: more ports than announced\n", 360 AHCINAME(sc)); 361 break; 362 } 363 achp = &sc->sc_channels[i]; 364 chp = &achp->ata_channel; 365 sc->sc_chanarray[i] = chp; 366 chp->ch_channel = i; 367 chp->ch_atac = &sc->sc_atac; 368 chp->ch_queue = malloc(sizeof(struct ata_queue), 369 M_DEVBUF, M_NOWAIT|M_ZERO); 370 if (chp->ch_queue == NULL) { 371 aprint_error("%s port %d: can't allocate memory for " 372 "command queue", AHCINAME(sc), i); 373 break; 374 } 375 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 376 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 377 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 378 BUS_DMA_NOWAIT); 379 if (error) { 380 aprint_error("%s: unable to allocate command table " 381 "memory, error=%d\n", AHCINAME(sc), error); 382 break; 383 } 384 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 385 achp->ahcic_cmd_tbl_nseg, dmasize, 386 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 387 if (error) { 388 aprint_error("%s: unable to map command table memory" 389 ", error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 393 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 394 if (error) { 395 aprint_error("%s: unable to create command table map" 396 ", error=%d\n", AHCINAME(sc), error); 397 break; 398 } 399 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 400 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 401 if (error) { 402 aprint_error("%s: unable to load command table map" 403 ", error=%d\n", AHCINAME(sc), error); 404 break; 405 } 406 achp->ahcic_cmdh = (struct ahci_cmd_header *) 407 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 408 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 409 AHCI_CMDH_SIZE * port; 410 achp->ahcic_rfis = (struct ahci_r_fis *) 411 ((char *)cmdhp + 412 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 413 AHCI_RFIS_SIZE * port); 414 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 415 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 416 AHCI_RFIS_SIZE * port; 417 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 418 "rfis %p (0x%" PRIx64 ")\n", i, 419 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 420 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 421 DEBUG_PROBE); 422 423 for (j = 0; j < sc->sc_ncmds; j++) { 424 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 425 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 426 achp->ahcic_bus_cmd_tbl[j] = 427 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 428 AHCI_CMDTBL_SIZE * j; 429 achp->ahcic_cmdh[j].cmdh_cmdtba = 430 htole64(achp->ahcic_bus_cmd_tbl[j]); 431 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 432 achp->ahcic_cmd_tbl[j], 433 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 434 /* The xfer DMA map */ 435 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 436 AHCI_NPRD, 0x400000 /* 4MB */, 0, 437 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 438 &achp->ahcic_datad[j]); 439 if (error) { 440 aprint_error("%s: couldn't alloc xfer DMA map, " 441 "error=%d\n", AHCINAME(sc), error); 442 goto end; 443 } 444 } 445 ahci_setup_port(sc, i); 446 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 447 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 448 aprint_error("%s: couldn't map channel %d " 449 "sata_status regs\n", AHCINAME(sc), i); 450 break; 451 } 452 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 453 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 454 aprint_error("%s: couldn't map channel %d " 455 "sata_control regs\n", AHCINAME(sc), i); 456 break; 457 } 458 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 459 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 460 aprint_error("%s: couldn't map channel %d " 461 "sata_error regs\n", AHCINAME(sc), i); 462 break; 463 } 464 ata_channel_attach(chp); 465 port++; 466 end: 467 continue; 468 } 469 } 470 471 int 472 ahci_detach(struct ahci_softc *sc, int flags) 473 { 474 struct atac_softc *atac; 475 struct ahci_channel *achp; 476 struct ata_channel *chp; 477 struct scsipi_adapter *adapt; 478 int i, j; 479 int error; 480 481 atac = &sc->sc_atac; 482 adapt = &atac->atac_atapi_adapter._generic; 483 484 for (i = 0; i < AHCI_MAX_PORTS; i++) { 485 achp = &sc->sc_channels[i]; 486 chp = &achp->ata_channel; 487 488 if ((sc->sc_ahci_ports & (1 << i)) == 0) 489 continue; 490 if (i >= sc->sc_atac.atac_nchannels) { 491 aprint_error("%s: more ports than announced\n", 492 AHCINAME(sc)); 493 break; 494 } 495 496 if (chp->atabus == NULL) 497 continue; 498 if ((error = config_detach(chp->atabus, flags)) != 0) 499 return error; 500 501 for (j = 0; j < sc->sc_ncmds; j++) 502 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 503 504 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 505 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 506 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 507 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 508 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 509 achp->ahcic_cmd_tbl_nseg); 510 511 free(chp->ch_queue, M_DEVBUF); 512 chp->atabus = NULL; 513 } 514 515 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 516 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 517 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 518 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 519 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 520 521 if (adapt->adapt_refcnt != 0) 522 return EBUSY; 523 524 return 0; 525 } 526 527 void 528 ahci_resume(struct ahci_softc *sc) 529 { 530 ahci_reset(sc); 531 ahci_setup_ports(sc); 532 ahci_reprobe_drives(sc); 533 ahci_enable_intrs(sc); 534 } 535 536 int 537 ahci_intr(void *v) 538 { 539 struct ahci_softc *sc = v; 540 uint32_t is; 541 int i, r = 0; 542 543 while ((is = AHCI_READ(sc, AHCI_IS))) { 544 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 545 DEBUG_INTR); 546 r = 1; 547 AHCI_WRITE(sc, AHCI_IS, is); 548 for (i = 0; i < AHCI_MAX_PORTS; i++) 549 if (is & (1 << i)) 550 ahci_intr_port(sc, &sc->sc_channels[i]); 551 } 552 return r; 553 } 554 555 static void 556 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 557 { 558 uint32_t is, tfd; 559 struct ata_channel *chp = &achp->ata_channel; 560 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 561 int slot; 562 563 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 564 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 565 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 566 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 567 DEBUG_INTR); 568 569 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 570 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 571 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 572 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 573 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 574 return; 575 /* stop channel */ 576 ahci_channel_stop(sc, chp, 0); 577 if (slot != 0) { 578 printf("ahci_intr_port: slot %d\n", slot); 579 panic("ahci_intr_port"); 580 } 581 if (is & AHCI_P_IX_TFES) { 582 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 583 chp->ch_error = 584 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 585 chp->ch_status = (tfd & 0xff); 586 } else { 587 /* emulate a CRC error */ 588 chp->ch_error = WDCE_CRC; 589 chp->ch_status = WDCS_ERR; 590 } 591 if (is & AHCI_P_IX_IFS) { 592 aprint_error("%s port %d: SERR 0x%x\n", 593 AHCINAME(sc), chp->ch_channel, 594 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 595 } 596 xfer->c_intr(chp, xfer, is); 597 /* if channel has not been restarted, do it now */ 598 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 599 == 0) 600 ahci_channel_start(sc, chp, 0, 0); 601 } else { 602 slot = 0; /* XXX */ 603 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 604 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 605 chp->ch_channel, is, achp->ahcic_cmds_active, 606 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 607 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 608 return; 609 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 610 == 0) { 611 xfer->c_intr(chp, xfer, 0); 612 } 613 } 614 } 615 616 static void 617 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 618 { 619 struct ata_channel *chp = drvp->chnl_softc; 620 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 621 AHCI_WRITE(sc, AHCI_GHC, 622 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 623 ahci_channel_stop(sc, chp, flags); 624 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 625 ata_reset_channel(chp, flags); 626 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 627 return; 628 } 629 630 /* return error code from ata_bio */ 631 static int 632 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 633 { 634 struct ahci_channel *achp = (struct ahci_channel *)chp; 635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 636 int i; 637 uint32_t is; 638 639 /* 640 * Base timeout is specified in ms. 641 * If we are allowed to sleep, wait a tick each round. 642 * Otherwise delay for 1ms on each round. 643 */ 644 if (flags & AT_WAIT) 645 timeout = MAX(1, mstohz(timeout)); 646 647 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 648 /* start command */ 649 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 650 for (i = 0; i < timeout; i++) { 651 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 652 return 0; 653 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 654 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 655 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 656 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 657 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 658 /* 659 * we got the D2H FIS anyway, 660 * assume sig is valid. 661 * channel is restarted later 662 */ 663 return ERROR; 664 } 665 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 666 AHCINAME(sc), chp->ch_channel, is); 667 return ERR_DF; 668 } 669 if (flags & AT_WAIT) 670 tsleep(&sc, PRIBIO, "ahcifis", 1); 671 else 672 delay(1000); 673 } 674 675 aprint_debug("%s channel %d: timeout sending FIS\n", 676 AHCINAME(sc), chp->ch_channel); 677 return TIMEOUT; 678 } 679 680 static int 681 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 682 uint32_t *sigp) 683 { 684 struct ahci_channel *achp = (struct ahci_channel *)chp; 685 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 686 struct ahci_cmd_tbl *cmd_tbl; 687 struct ahci_cmd_header *cmd_h; 688 int i; 689 uint32_t sig; 690 691 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 692 again: 693 /* clear port interrupt register */ 694 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 695 /* clear SErrors and start operations */ 696 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 697 /* 698 * issue a command list override to clear BSY. 699 * This is needed if there's a PMP with no drive 700 * on port 0 701 */ 702 ahci_channel_start(sc, chp, flags, 1); 703 } else { 704 ahci_channel_start(sc, chp, flags, 0); 705 } 706 if (drive > 0) { 707 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 708 } 709 /* polled command, assume interrupts are disabled */ 710 /* use slot 0 to send reset, the channel is idle */ 711 cmd_h = &achp->ahcic_cmdh[0]; 712 cmd_tbl = achp->ahcic_cmd_tbl[0]; 713 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 714 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 715 cmd_h->cmdh_prdbc = 0; 716 memset(cmd_tbl->cmdt_cfis, 0, 64); 717 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 718 cmd_tbl->cmdt_cfis[rhd_c] = drive; 719 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 720 switch(ahci_exec_fis(chp, 100, flags)) { 721 case ERR_DF: 722 case TIMEOUT: 723 aprint_error("%s channel %d: setting WDCTL_RST failed " 724 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 725 if (sigp) 726 *sigp = 0xffffffff; 727 goto end; 728 default: 729 break; 730 } 731 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 732 (drive << AHCI_CMDH_F_PMP_SHIFT)); 733 cmd_h->cmdh_prdbc = 0; 734 memset(cmd_tbl->cmdt_cfis, 0, 64); 735 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 736 cmd_tbl->cmdt_cfis[rhd_c] = drive; 737 cmd_tbl->cmdt_cfis[rhd_control] = 0; 738 switch(ahci_exec_fis(chp, 310, flags)) { 739 case ERR_DF: 740 case TIMEOUT: 741 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 742 drive == PMP_PORT_CTL) { 743 /* 744 * some controllers fails to reset when 745 * targeting a PMP but a single drive is attached. 746 * try again with port 0 747 */ 748 drive = 0; 749 ahci_channel_stop(sc, chp, flags); 750 goto again; 751 } 752 aprint_error("%s channel %d: clearing WDCTL_RST failed " 753 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 754 if (sigp) 755 *sigp = 0xffffffff; 756 goto end; 757 default: 758 break; 759 } 760 /* 761 * wait 31s for BSY to clear 762 * This should not be needed, but some controllers clear the 763 * command slot before receiving the D2H FIS ... 764 */ 765 for (i = 0; i < AHCI_RST_WAIT; i++) { 766 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 767 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 768 break; 769 if (flags & AT_WAIT) 770 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 771 else 772 delay(10000); 773 } 774 if (i == AHCI_RST_WAIT) { 775 aprint_error("%s: BSY never cleared, TD 0x%x\n", 776 AHCINAME(sc), sig); 777 if (sigp) 778 *sigp = 0xffffffff; 779 goto end; 780 } 781 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 782 DEBUG_PROBE); 783 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 784 if (sigp) 785 *sigp = sig; 786 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 787 AHCINAME(sc), chp->ch_channel, sig, 788 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 789 end: 790 ahci_channel_stop(sc, chp, flags); 791 if (flags & AT_WAIT) 792 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 793 else 794 delay(500000); 795 /* clear port interrupt register */ 796 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 797 ahci_channel_start(sc, chp, flags, 798 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 799 return 0; 800 } 801 802 static void 803 ahci_reset_channel(struct ata_channel *chp, int flags) 804 { 805 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 806 struct ahci_channel *achp = (struct ahci_channel *)chp; 807 int i, tfd; 808 809 ahci_channel_stop(sc, chp, flags); 810 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 811 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 812 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 813 /* XXX and then ? */ 814 } 815 if (chp->ch_queue->active_xfer) { 816 chp->ch_queue->active_xfer->c_kill_xfer(chp, 817 chp->ch_queue->active_xfer, KILL_RESET); 818 } 819 ata_delay(500, "ahcirst", flags); 820 /* clear port interrupt register */ 821 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 822 /* clear SErrors and start operations */ 823 ahci_channel_start(sc, chp, flags, 1); 824 /* wait 31s for BSY to clear */ 825 for (i = 0; i <AHCI_RST_WAIT; i++) { 826 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 827 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 828 & WDCS_BSY) == 0) 829 break; 830 ata_delay(10, "ahcid2h", flags); 831 } 832 if (i == AHCI_RST_WAIT) 833 aprint_error("%s: BSY never cleared, TD 0x%x\n", 834 AHCINAME(sc), tfd); 835 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 836 DEBUG_PROBE); 837 /* clear port interrupt register */ 838 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 839 840 return; 841 } 842 843 static int 844 ahci_ata_addref(struct ata_drive_datas *drvp) 845 { 846 return 0; 847 } 848 849 static void 850 ahci_ata_delref(struct ata_drive_datas *drvp) 851 { 852 return; 853 } 854 855 static void 856 ahci_killpending(struct ata_drive_datas *drvp) 857 { 858 return; 859 } 860 861 static void 862 ahci_probe_drive(struct ata_channel *chp) 863 { 864 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 865 struct ahci_channel *achp = (struct ahci_channel *)chp; 866 uint32_t sig; 867 868 /* bring interface up, accept FISs, power up and spin up device */ 869 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 870 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 871 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 872 /* reset the PHY and bring online */ 873 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 874 achp->ahcic_sstatus, AT_WAIT)) { 875 case SStatus_DET_DEV: 876 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 877 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 878 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 879 } else { 880 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 881 } 882 sata_interpret_sig(chp, 0, sig); 883 /* if we have a PMP attached, inform the controller */ 884 if (chp->ch_ndrives > PMP_PORT_CTL && 885 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 886 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 887 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 888 AHCI_P_CMD_PMA); 889 } 890 /* clear port interrupt register */ 891 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 892 893 /* and enable interrupts */ 894 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 895 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 896 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 897 AHCI_P_IX_PSS | AHCI_P_IX_DHRS); 898 /* wait 500ms before actually starting operations */ 899 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 900 break; 901 902 default: 903 break; 904 } 905 } 906 907 static void 908 ahci_setup_channel(struct ata_channel *chp) 909 { 910 return; 911 } 912 913 static int 914 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 915 { 916 struct ata_channel *chp = drvp->chnl_softc; 917 struct ata_xfer *xfer; 918 int ret; 919 int s; 920 921 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 922 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 923 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 924 DEBUG_XFERS); 925 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 926 ATAXF_NOSLEEP); 927 if (xfer == NULL) { 928 return ATACMD_TRY_AGAIN; 929 } 930 if (ata_c->flags & AT_POLL) 931 xfer->c_flags |= C_POLL; 932 if (ata_c->flags & AT_WAIT) 933 xfer->c_flags |= C_WAIT; 934 xfer->c_drive = drvp->drive; 935 xfer->c_databuf = ata_c->data; 936 xfer->c_bcount = ata_c->bcount; 937 xfer->c_cmd = ata_c; 938 xfer->c_start = ahci_cmd_start; 939 xfer->c_intr = ahci_cmd_complete; 940 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 941 s = splbio(); 942 ata_exec_xfer(chp, xfer); 943 #ifdef DIAGNOSTIC 944 if ((ata_c->flags & AT_POLL) != 0 && 945 (ata_c->flags & AT_DONE) == 0) 946 panic("ahci_exec_command: polled command not done"); 947 #endif 948 if (ata_c->flags & AT_DONE) { 949 ret = ATACMD_COMPLETE; 950 } else { 951 if (ata_c->flags & AT_WAIT) { 952 while ((ata_c->flags & AT_DONE) == 0) { 953 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 954 } 955 ret = ATACMD_COMPLETE; 956 } else { 957 ret = ATACMD_QUEUED; 958 } 959 } 960 splx(s); 961 return ret; 962 } 963 964 static void 965 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 966 { 967 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 968 struct ahci_channel *achp = (struct ahci_channel *)chp; 969 struct ata_command *ata_c = xfer->c_cmd; 970 int slot = 0 /* XXX slot */; 971 struct ahci_cmd_tbl *cmd_tbl; 972 struct ahci_cmd_header *cmd_h; 973 int i; 974 int channel = chp->ch_channel; 975 976 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n", 977 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout), 978 DEBUG_XFERS); 979 980 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 981 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 982 cmd_tbl), DEBUG_XFERS); 983 984 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 985 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 986 987 cmd_h = &achp->ahcic_cmdh[slot]; 988 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 989 chp->ch_channel, cmd_h), DEBUG_XFERS); 990 if (ahci_dma_setup(chp, slot, 991 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 992 ata_c->data : NULL, 993 ata_c->bcount, 994 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 995 ata_c->flags |= AT_DF; 996 ahci_cmd_complete(chp, xfer, slot); 997 return; 998 } 999 cmd_h->cmdh_flags = htole16( 1000 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1001 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1002 cmd_h->cmdh_prdbc = 0; 1003 AHCI_CMDH_SYNC(sc, achp, slot, 1004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1005 1006 if (ata_c->flags & AT_POLL) { 1007 /* polled command, disable interrupts */ 1008 AHCI_WRITE(sc, AHCI_GHC, 1009 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1010 } 1011 chp->ch_flags |= ATACH_IRQ_WAIT; 1012 chp->ch_status = 0; 1013 /* start command */ 1014 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1015 /* and says we started this command */ 1016 achp->ahcic_cmds_active |= 1 << slot; 1017 1018 if ((ata_c->flags & AT_POLL) == 0) { 1019 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1020 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 1021 ahci_timeout, chp); 1022 return; 1023 } 1024 /* 1025 * Polled command. 1026 */ 1027 for (i = 0; i < ata_c->timeout / 10; i++) { 1028 if (ata_c->flags & AT_DONE) 1029 break; 1030 ahci_intr_port(sc, achp); 1031 if (ata_c->flags & AT_WAIT) 1032 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1033 else 1034 delay(10000); 1035 } 1036 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1037 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1038 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1039 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1040 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1041 DEBUG_XFERS); 1042 if ((ata_c->flags & AT_DONE) == 0) { 1043 ata_c->flags |= AT_TIMEOU; 1044 ahci_cmd_complete(chp, xfer, slot); 1045 } 1046 /* reenable interrupts */ 1047 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1048 } 1049 1050 static void 1051 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1052 { 1053 struct ata_command *ata_c = xfer->c_cmd; 1054 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1055 DEBUG_FUNCS); 1056 1057 switch (reason) { 1058 case KILL_GONE: 1059 ata_c->flags |= AT_GONE; 1060 break; 1061 case KILL_RESET: 1062 ata_c->flags |= AT_RESET; 1063 break; 1064 default: 1065 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1066 panic("ahci_cmd_kill_xfer"); 1067 } 1068 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1069 } 1070 1071 static int 1072 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1073 { 1074 int slot = 0; /* XXX slot */ 1075 struct ata_command *ata_c = xfer->c_cmd; 1076 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1077 struct ahci_channel *achp = (struct ahci_channel *)chp; 1078 1079 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1080 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1081 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1082 DEBUG_FUNCS); 1083 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1084 if (xfer->c_flags & C_TIMEOU) { 1085 ata_c->flags |= AT_TIMEOU; 1086 } else 1087 callout_stop(&chp->ch_callout); 1088 1089 chp->ch_queue->active_xfer = NULL; 1090 1091 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1092 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1093 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1094 wakeup(&chp->ch_queue->active_xfer); 1095 return 0; 1096 } 1097 1098 if (chp->ch_status & WDCS_BSY) { 1099 ata_c->flags |= AT_TIMEOU; 1100 } else if (chp->ch_status & WDCS_ERR) { 1101 ata_c->r_error = chp->ch_error; 1102 ata_c->flags |= AT_ERROR; 1103 } 1104 1105 if (ata_c->flags & AT_READREG) 1106 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1107 1108 ahci_cmd_done(chp, xfer, slot); 1109 return 0; 1110 } 1111 1112 static void 1113 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1114 { 1115 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1116 struct ahci_channel *achp = (struct ahci_channel *)chp; 1117 struct ata_command *ata_c = xfer->c_cmd; 1118 uint16_t *idwordbuf; 1119 int i; 1120 1121 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n", 1122 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1123 1124 /* this comamnd is not active any more */ 1125 achp->ahcic_cmds_active &= ~(1 << slot); 1126 1127 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1128 bus_dmamap_t map = achp->ahcic_datad[slot]; 1129 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1130 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1131 BUS_DMASYNC_POSTWRITE); 1132 bus_dmamap_unload(sc->sc_dmat, map); 1133 } 1134 1135 AHCI_CMDH_SYNC(sc, achp, slot, 1136 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1137 1138 /* ata(4) expects IDENTIFY data to be in host endianess */ 1139 if (ata_c->r_command == WDCC_IDENTIFY || 1140 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1141 idwordbuf = xfer->c_databuf; 1142 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1143 idwordbuf[i] = le16toh(idwordbuf[i]); 1144 } 1145 } 1146 1147 ata_c->flags |= AT_DONE; 1148 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1149 ata_c->flags |= AT_XFDONE; 1150 1151 ata_free_xfer(chp, xfer); 1152 if (ata_c->flags & AT_WAIT) 1153 wakeup(ata_c); 1154 else if (ata_c->callback) 1155 ata_c->callback(ata_c->callback_arg); 1156 atastart(chp); 1157 return; 1158 } 1159 1160 static int 1161 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1162 { 1163 struct ata_channel *chp = drvp->chnl_softc; 1164 struct ata_xfer *xfer; 1165 1166 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1167 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1168 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1169 DEBUG_XFERS); 1170 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1171 if (xfer == NULL) { 1172 return ATACMD_TRY_AGAIN; 1173 } 1174 if (ata_bio->flags & ATA_POLL) 1175 xfer->c_flags |= C_POLL; 1176 xfer->c_drive = drvp->drive; 1177 xfer->c_cmd = ata_bio; 1178 xfer->c_databuf = ata_bio->databuf; 1179 xfer->c_bcount = ata_bio->bcount; 1180 xfer->c_start = ahci_bio_start; 1181 xfer->c_intr = ahci_bio_complete; 1182 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1183 ata_exec_xfer(chp, xfer); 1184 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1185 } 1186 1187 static void 1188 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1189 { 1190 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1191 struct ahci_channel *achp = (struct ahci_channel *)chp; 1192 struct ata_bio *ata_bio = xfer->c_cmd; 1193 int slot = 0 /* XXX slot */; 1194 struct ahci_cmd_tbl *cmd_tbl; 1195 struct ahci_cmd_header *cmd_h; 1196 int i; 1197 int channel = chp->ch_channel; 1198 1199 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1200 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1201 1202 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1203 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1204 cmd_tbl), DEBUG_XFERS); 1205 1206 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1207 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1208 1209 cmd_h = &achp->ahcic_cmdh[slot]; 1210 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1211 chp->ch_channel, cmd_h), DEBUG_XFERS); 1212 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1213 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1214 ata_bio->error = ERR_DMA; 1215 ata_bio->r_error = 0; 1216 ahci_bio_complete(chp, xfer, slot); 1217 return; 1218 } 1219 cmd_h->cmdh_flags = htole16( 1220 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1221 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1222 cmd_h->cmdh_prdbc = 0; 1223 AHCI_CMDH_SYNC(sc, achp, slot, 1224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1225 1226 if (xfer->c_flags & C_POLL) { 1227 /* polled command, disable interrupts */ 1228 AHCI_WRITE(sc, AHCI_GHC, 1229 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1230 } 1231 chp->ch_flags |= ATACH_IRQ_WAIT; 1232 chp->ch_status = 0; 1233 /* start command */ 1234 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1235 /* and says we started this command */ 1236 achp->ahcic_cmds_active |= 1 << slot; 1237 1238 if ((xfer->c_flags & C_POLL) == 0) { 1239 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1240 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1241 ahci_timeout, chp); 1242 return; 1243 } 1244 /* 1245 * Polled command. 1246 */ 1247 for (i = 0; i < ATA_DELAY * 10; i++) { 1248 if (ata_bio->flags & ATA_ITSDONE) 1249 break; 1250 ahci_intr_port(sc, achp); 1251 delay(100); 1252 } 1253 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1254 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1255 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1256 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1257 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1258 DEBUG_XFERS); 1259 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1260 ata_bio->error = TIMEOUT; 1261 ahci_bio_complete(chp, xfer, slot); 1262 } 1263 /* reenable interrupts */ 1264 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1265 } 1266 1267 static void 1268 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1269 { 1270 int slot = 0; /* XXX slot */ 1271 int drive = xfer->c_drive; 1272 struct ata_bio *ata_bio = xfer->c_cmd; 1273 struct ahci_channel *achp = (struct ahci_channel *)chp; 1274 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1275 DEBUG_FUNCS); 1276 1277 achp->ahcic_cmds_active &= ~(1 << slot); 1278 ata_free_xfer(chp, xfer); 1279 ata_bio->flags |= ATA_ITSDONE; 1280 switch (reason) { 1281 case KILL_GONE: 1282 ata_bio->error = ERR_NODEV; 1283 break; 1284 case KILL_RESET: 1285 ata_bio->error = ERR_RESET; 1286 break; 1287 default: 1288 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1289 panic("ahci_bio_kill_xfer"); 1290 } 1291 ata_bio->r_error = WDCE_ABRT; 1292 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1293 } 1294 1295 static int 1296 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1297 { 1298 int slot = 0; /* XXX slot */ 1299 struct ata_bio *ata_bio = xfer->c_cmd; 1300 int drive = xfer->c_drive; 1301 struct ahci_channel *achp = (struct ahci_channel *)chp; 1302 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1303 1304 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1305 DEBUG_FUNCS); 1306 1307 achp->ahcic_cmds_active &= ~(1 << slot); 1308 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1309 if (xfer->c_flags & C_TIMEOU) { 1310 ata_bio->error = TIMEOUT; 1311 } else { 1312 callout_stop(&chp->ch_callout); 1313 ata_bio->error = NOERROR; 1314 } 1315 1316 chp->ch_queue->active_xfer = NULL; 1317 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1318 achp->ahcic_datad[slot]->dm_mapsize, 1319 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1320 BUS_DMASYNC_POSTWRITE); 1321 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1322 1323 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1324 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1325 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1326 wakeup(&chp->ch_queue->active_xfer); 1327 return 0; 1328 } 1329 ata_free_xfer(chp, xfer); 1330 ata_bio->flags |= ATA_ITSDONE; 1331 if (chp->ch_status & WDCS_DWF) { 1332 ata_bio->error = ERR_DF; 1333 } else if (chp->ch_status & WDCS_ERR) { 1334 ata_bio->error = ERROR; 1335 ata_bio->r_error = chp->ch_error; 1336 } else if (chp->ch_status & WDCS_CORR) 1337 ata_bio->flags |= ATA_CORR; 1338 1339 AHCI_CMDH_SYNC(sc, achp, slot, 1340 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1341 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1342 ata_bio->bcount), DEBUG_XFERS); 1343 /* 1344 * if it was a write, complete data buffer may have been transfered 1345 * before error detection; in this case don't use cmdh_prdbc 1346 * as it won't reflect what was written to media. Assume nothing 1347 * was transfered and leave bcount as-is. 1348 */ 1349 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1350 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1351 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1352 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1353 atastart(chp); 1354 return 0; 1355 } 1356 1357 static void 1358 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1359 { 1360 int i; 1361 /* stop channel */ 1362 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1363 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1364 /* wait 1s for channel to stop */ 1365 for (i = 0; i <100; i++) { 1366 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1367 == 0) 1368 break; 1369 if (flags & AT_WAIT) 1370 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1371 else 1372 delay(10000); 1373 } 1374 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1375 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1376 /* XXX controller reset ? */ 1377 return; 1378 } 1379 1380 if (sc->sc_channel_stop) 1381 sc->sc_channel_stop(sc, chp); 1382 } 1383 1384 static void 1385 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1386 int flags, int clo) 1387 { 1388 int i; 1389 uint32_t p_cmd; 1390 /* clear error */ 1391 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1392 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1393 1394 if (clo) { 1395 /* issue command list override */ 1396 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1397 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1398 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1399 /* wait 1s for AHCI_CAP_CLO to clear */ 1400 for (i = 0; i <100; i++) { 1401 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1402 AHCI_P_CMD_CLO) == 0) 1403 break; 1404 if (flags & AT_WAIT) 1405 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1406 else 1407 delay(10000); 1408 } 1409 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1410 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1411 /* XXX controller reset ? */ 1412 return; 1413 } 1414 } 1415 1416 if (sc->sc_channel_start) 1417 sc->sc_channel_start(sc, chp); 1418 1419 /* and start controller */ 1420 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1421 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1422 if (chp->ch_ndrives > PMP_PORT_CTL && 1423 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1424 p_cmd |= AHCI_P_CMD_PMA; 1425 } 1426 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1427 } 1428 1429 static void 1430 ahci_timeout(void *v) 1431 { 1432 struct ata_channel *chp = (struct ata_channel *)v; 1433 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1434 #ifdef AHCI_DEBUG 1435 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1436 #endif 1437 int s = splbio(); 1438 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x ghc %08x is %08x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)), AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS)), DEBUG_INTR); 1439 1440 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1441 xfer->c_flags |= C_TIMEOU; 1442 xfer->c_intr(chp, xfer, 0); 1443 } 1444 splx(s); 1445 } 1446 1447 static int 1448 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1449 size_t count, int op) 1450 { 1451 int error, seg; 1452 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1453 struct ahci_channel *achp = (struct ahci_channel *)chp; 1454 struct ahci_cmd_tbl *cmd_tbl; 1455 struct ahci_cmd_header *cmd_h; 1456 1457 cmd_h = &achp->ahcic_cmdh[slot]; 1458 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1459 1460 if (data == NULL) { 1461 cmd_h->cmdh_prdtl = 0; 1462 goto end; 1463 } 1464 1465 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1466 data, count, NULL, 1467 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1468 if (error) { 1469 printf("%s port %d: failed to load xfer: %d\n", 1470 AHCINAME(sc), chp->ch_channel, error); 1471 return error; 1472 } 1473 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1474 achp->ahcic_datad[slot]->dm_mapsize, 1475 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1476 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1477 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1478 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1479 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1480 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1481 } 1482 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1483 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1484 end: 1485 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1486 return 0; 1487 } 1488 1489 #if NATAPIBUS > 0 1490 static void 1491 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1492 { 1493 struct ata_channel *chp = ata_sc->sc_chan; 1494 struct atac_softc *atac = chp->ch_atac; 1495 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1496 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1497 /* 1498 * Fill in the scsipi_adapter. 1499 */ 1500 adapt->adapt_dev = atac->atac_dev; 1501 adapt->adapt_nchannels = atac->atac_nchannels; 1502 adapt->adapt_request = ahci_atapi_scsipi_request; 1503 adapt->adapt_minphys = ahci_atapi_minphys; 1504 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1505 1506 /* 1507 * Fill in the scsipi_channel. 1508 */ 1509 memset(chan, 0, sizeof(*chan)); 1510 chan->chan_adapter = adapt; 1511 chan->chan_bustype = &ahci_atapi_bustype; 1512 chan->chan_channel = chp->ch_channel; 1513 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1514 chan->chan_openings = 1; 1515 chan->chan_max_periph = 1; 1516 chan->chan_ntargets = 1; 1517 chan->chan_nluns = 1; 1518 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1519 atapiprint); 1520 } 1521 1522 static void 1523 ahci_atapi_minphys(struct buf *bp) 1524 { 1525 if (bp->b_bcount > MAXPHYS) 1526 bp->b_bcount = MAXPHYS; 1527 minphys(bp); 1528 } 1529 1530 /* 1531 * Kill off all pending xfers for a periph. 1532 * 1533 * Must be called at splbio(). 1534 */ 1535 static void 1536 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1537 { 1538 struct atac_softc *atac = 1539 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1540 struct ata_channel *chp = 1541 atac->atac_channels[periph->periph_channel->chan_channel]; 1542 1543 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1544 } 1545 1546 static void 1547 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1548 scsipi_adapter_req_t req, void *arg) 1549 { 1550 struct scsipi_adapter *adapt = chan->chan_adapter; 1551 struct scsipi_periph *periph; 1552 struct scsipi_xfer *sc_xfer; 1553 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1554 struct atac_softc *atac = &sc->sc_atac; 1555 struct ata_xfer *xfer; 1556 int channel = chan->chan_channel; 1557 int drive, s; 1558 1559 switch (req) { 1560 case ADAPTER_REQ_RUN_XFER: 1561 sc_xfer = arg; 1562 periph = sc_xfer->xs_periph; 1563 drive = periph->periph_target; 1564 if (!device_is_active(atac->atac_dev)) { 1565 sc_xfer->error = XS_DRIVER_STUFFUP; 1566 scsipi_done(sc_xfer); 1567 return; 1568 } 1569 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1570 if (xfer == NULL) { 1571 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1572 scsipi_done(sc_xfer); 1573 return; 1574 } 1575 1576 if (sc_xfer->xs_control & XS_CTL_POLL) 1577 xfer->c_flags |= C_POLL; 1578 xfer->c_drive = drive; 1579 xfer->c_flags |= C_ATAPI; 1580 xfer->c_cmd = sc_xfer; 1581 xfer->c_databuf = sc_xfer->data; 1582 xfer->c_bcount = sc_xfer->datalen; 1583 xfer->c_start = ahci_atapi_start; 1584 xfer->c_intr = ahci_atapi_complete; 1585 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1586 xfer->c_dscpoll = 0; 1587 s = splbio(); 1588 ata_exec_xfer(atac->atac_channels[channel], xfer); 1589 #ifdef DIAGNOSTIC 1590 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1591 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1592 panic("ahci_atapi_scsipi_request: polled command " 1593 "not done"); 1594 #endif 1595 splx(s); 1596 return; 1597 default: 1598 /* Not supported, nothing to do. */ 1599 ; 1600 } 1601 } 1602 1603 static void 1604 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1605 { 1606 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1607 struct ahci_channel *achp = (struct ahci_channel *)chp; 1608 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1609 int slot = 0 /* XXX slot */; 1610 struct ahci_cmd_tbl *cmd_tbl; 1611 struct ahci_cmd_header *cmd_h; 1612 int i; 1613 int channel = chp->ch_channel; 1614 1615 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1616 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1617 1618 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1619 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1620 cmd_tbl), DEBUG_XFERS); 1621 1622 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1623 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1624 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1625 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1626 1627 cmd_h = &achp->ahcic_cmdh[slot]; 1628 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1629 chp->ch_channel, cmd_h), DEBUG_XFERS); 1630 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1631 sc_xfer->datalen, 1632 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1633 BUS_DMA_READ : BUS_DMA_WRITE)) { 1634 sc_xfer->error = XS_DRIVER_STUFFUP; 1635 ahci_atapi_complete(chp, xfer, slot); 1636 return; 1637 } 1638 cmd_h->cmdh_flags = htole16( 1639 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1640 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1641 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1642 cmd_h->cmdh_prdbc = 0; 1643 AHCI_CMDH_SYNC(sc, achp, slot, 1644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1645 1646 if (xfer->c_flags & C_POLL) { 1647 /* polled command, disable interrupts */ 1648 AHCI_WRITE(sc, AHCI_GHC, 1649 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1650 } 1651 chp->ch_flags |= ATACH_IRQ_WAIT; 1652 chp->ch_status = 0; 1653 /* start command */ 1654 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1655 /* and says we started this command */ 1656 achp->ahcic_cmds_active |= 1 << slot; 1657 1658 if ((xfer->c_flags & C_POLL) == 0) { 1659 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1660 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1661 ahci_timeout, chp); 1662 return; 1663 } 1664 /* 1665 * Polled command. 1666 */ 1667 for (i = 0; i < ATA_DELAY / 10; i++) { 1668 if (sc_xfer->xs_status & XS_STS_DONE) 1669 break; 1670 ahci_intr_port(sc, achp); 1671 delay(10000); 1672 } 1673 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1674 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1675 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1676 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1677 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1678 DEBUG_XFERS); 1679 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1680 sc_xfer->error = XS_TIMEOUT; 1681 ahci_atapi_complete(chp, xfer, slot); 1682 } 1683 /* reenable interrupts */ 1684 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1685 } 1686 1687 static int 1688 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1689 { 1690 int slot = 0; /* XXX slot */ 1691 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1692 int drive = xfer->c_drive; 1693 struct ahci_channel *achp = (struct ahci_channel *)chp; 1694 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1695 1696 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1697 DEBUG_FUNCS); 1698 1699 achp->ahcic_cmds_active &= ~(1 << slot); 1700 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1701 if (xfer->c_flags & C_TIMEOU) { 1702 sc_xfer->error = XS_TIMEOUT; 1703 } else { 1704 callout_stop(&chp->ch_callout); 1705 sc_xfer->error = 0; 1706 } 1707 1708 chp->ch_queue->active_xfer = NULL; 1709 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1710 achp->ahcic_datad[slot]->dm_mapsize, 1711 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1712 BUS_DMASYNC_POSTWRITE); 1713 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1714 1715 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1716 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1717 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1718 wakeup(&chp->ch_queue->active_xfer); 1719 return 0; 1720 } 1721 ata_free_xfer(chp, xfer); 1722 1723 AHCI_CMDH_SYNC(sc, achp, slot, 1724 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1725 sc_xfer->resid = sc_xfer->datalen; 1726 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1727 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1728 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1729 if (chp->ch_status & WDCS_ERR && 1730 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1731 sc_xfer->resid == sc_xfer->datalen)) { 1732 sc_xfer->error = XS_SHORTSENSE; 1733 sc_xfer->sense.atapi_sense = chp->ch_error; 1734 if ((sc_xfer->xs_periph->periph_quirks & 1735 PQUIRK_NOSENSE) == 0) { 1736 /* ask scsipi to send a REQUEST_SENSE */ 1737 sc_xfer->error = XS_BUSY; 1738 sc_xfer->status = SCSI_CHECK; 1739 } 1740 } 1741 scsipi_done(sc_xfer); 1742 atastart(chp); 1743 return 0; 1744 } 1745 1746 static void 1747 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1748 { 1749 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1750 struct ahci_channel *achp = (struct ahci_channel *)chp; 1751 int slot = 0; /* XXX slot */ 1752 1753 achp->ahcic_cmds_active &= ~(1 << slot); 1754 1755 /* remove this command from xfer queue */ 1756 switch (reason) { 1757 case KILL_GONE: 1758 sc_xfer->error = XS_DRIVER_STUFFUP; 1759 break; 1760 case KILL_RESET: 1761 sc_xfer->error = XS_RESET; 1762 break; 1763 default: 1764 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1765 panic("ahci_ata_atapi_kill_xfer"); 1766 } 1767 ata_free_xfer(chp, xfer); 1768 scsipi_done(sc_xfer); 1769 } 1770 1771 static void 1772 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1773 { 1774 struct scsipi_channel *chan = sc->sc_channel; 1775 struct scsipi_periph *periph; 1776 struct ataparams ids; 1777 struct ataparams *id = &ids; 1778 struct ahci_softc *ahcic = 1779 device_private(chan->chan_adapter->adapt_dev); 1780 struct atac_softc *atac = &ahcic->sc_atac; 1781 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1782 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1783 struct scsipibus_attach_args sa; 1784 char serial_number[21], model[41], firmware_revision[9]; 1785 int s; 1786 1787 /* skip if already attached */ 1788 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1789 return; 1790 1791 /* if no ATAPI device detected at attach time, skip */ 1792 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1793 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1794 "not present\n", target), DEBUG_PROBE); 1795 return; 1796 } 1797 1798 /* Some ATAPI devices need a bit more time after software reset. */ 1799 delay(5000); 1800 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1801 #ifdef ATAPI_DEBUG_PROBE 1802 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1803 AHCINAME(ahcic), target, 1804 id->atap_config & ATAPI_CFG_CMD_MASK, 1805 id->atap_config & ATAPI_CFG_DRQ_MASK); 1806 #endif 1807 periph = scsipi_alloc_periph(M_NOWAIT); 1808 if (periph == NULL) { 1809 aprint_error_dev(sc->sc_dev, 1810 "unable to allocate periph for drive %d\n", 1811 target); 1812 return; 1813 } 1814 periph->periph_dev = NULL; 1815 periph->periph_channel = chan; 1816 periph->periph_switch = &atapi_probe_periphsw; 1817 periph->periph_target = target; 1818 periph->periph_lun = 0; 1819 periph->periph_quirks = PQUIRK_ONLYBIG; 1820 1821 #ifdef SCSIPI_DEBUG 1822 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1823 SCSIPI_DEBUG_TARGET == target) 1824 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1825 #endif 1826 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1827 if (id->atap_config & ATAPI_CFG_REMOV) 1828 periph->periph_flags |= PERIPH_REMOVABLE; 1829 if (periph->periph_type == T_SEQUENTIAL) { 1830 s = splbio(); 1831 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1832 splx(s); 1833 } 1834 1835 sa.sa_periph = periph; 1836 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1837 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1838 T_REMOV : T_FIXED; 1839 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1840 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1841 20); 1842 scsipi_strvis((u_char *)firmware_revision, 8, 1843 id->atap_revision, 8); 1844 sa.sa_inqbuf.vendor = model; 1845 sa.sa_inqbuf.product = serial_number; 1846 sa.sa_inqbuf.revision = firmware_revision; 1847 1848 /* 1849 * Determine the operating mode capabilities of the device. 1850 */ 1851 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1852 periph->periph_cap |= PERIPH_CAP_CMD16; 1853 /* XXX This is gross. */ 1854 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1855 1856 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1857 1858 if (drvp->drv_softc) 1859 ata_probe_caps(drvp); 1860 else { 1861 s = splbio(); 1862 drvp->drive_type = ATA_DRIVET_NONE; 1863 splx(s); 1864 } 1865 } else { 1866 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1867 "failed for drive %s:%d:%d: error 0x%x\n", 1868 AHCINAME(ahcic), chp->ch_channel, target, 1869 chp->ch_error), DEBUG_PROBE); 1870 s = splbio(); 1871 drvp->drive_type = ATA_DRIVET_NONE; 1872 splx(s); 1873 } 1874 } 1875 #endif /* NATAPIBUS */ 1876
Indexes created Thu Sep 25 06:09:39 GMT 2025