ahcisata_core.c revision 1.53
1 /* $NetBSD: ahcisata_core.c,v 1.53 2014/12/04 21:50:29 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.53 2014/12/04 21:50:29 joerg Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *); 62 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 63 static void ahci_reset_channel(struct ata_channel *, int); 64 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 65 static int ahci_ata_addref(struct ata_drive_datas *); 66 static void ahci_ata_delref(struct ata_drive_datas *); 67 static void ahci_killpending(struct ata_drive_datas *); 68 69 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 70 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 71 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 74 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 75 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 77 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 78 int, int); 79 static void ahci_timeout(void *); 80 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 static void ahci_atapibus_attach(struct atabus_softc *); 84 static void ahci_atapi_kill_pending(struct scsipi_periph *); 85 static void ahci_atapi_minphys(struct buf *); 86 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 NULL, 100 }; 101 #endif /* NATAPIBUS */ 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 105 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 106 107 const struct ata_bustype ahci_ata_bustype = { 108 SCSIPI_BUSTYPE_ATA, 109 ahci_ata_bio, 110 ahci_reset_drive, 111 ahci_reset_channel, 112 ahci_exec_command, 113 ata_get_params, 114 ahci_ata_addref, 115 ahci_ata_delref, 116 ahci_killpending 117 }; 118 119 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 120 static void ahci_setup_port(struct ahci_softc *sc, int i); 121 122 static void 123 ahci_enable(struct ahci_softc *sc) 124 { 125 uint32_t ghc; 126 127 ghc = AHCI_READ(sc, AHCI_GHC); 128 if (!(ghc & AHCI_GHC_AE)) { 129 ghc |= AHCI_GHC_AE; 130 AHCI_WRITE(sc, AHCI_GHC, ghc); 131 } 132 } 133 134 static int 135 ahci_reset(struct ahci_softc *sc) 136 { 137 int i; 138 139 /* reset controller */ 140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 141 /* wait up to 1s for reset to complete */ 142 for (i = 0; i < 1000; i++) { 143 delay(1000); 144 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 145 break; 146 } 147 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 148 aprint_error("%s: reset failed\n", AHCINAME(sc)); 149 return -1; 150 } 151 /* enable ahci mode */ 152 ahci_enable(sc); 153 154 if (sc->sc_save_init_data) { 155 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 156 if (sc->sc_init_data.cap2) 157 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 158 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 159 } 160 161 return 0; 162 } 163 164 static void 165 ahci_setup_ports(struct ahci_softc *sc) 166 { 167 int i, port; 168 169 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 170 if ((sc->sc_ahci_ports & (1 << i)) == 0) 171 continue; 172 if (port >= sc->sc_atac.atac_nchannels) { 173 aprint_error("%s: more ports than announced\n", 174 AHCINAME(sc)); 175 break; 176 } 177 ahci_setup_port(sc, i); 178 } 179 } 180 181 static void 182 ahci_reprobe_drives(struct ahci_softc *sc) 183 { 184 int i, port; 185 struct ahci_channel *achp; 186 struct ata_channel *chp; 187 188 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 189 if ((sc->sc_ahci_ports & (1 << i)) == 0) 190 continue; 191 if (port >= sc->sc_atac.atac_nchannels) { 192 aprint_error("%s: more ports than announced\n", 193 AHCINAME(sc)); 194 break; 195 } 196 achp = &sc->sc_channels[i]; 197 chp = &achp->ata_channel; 198 199 ahci_probe_drive(chp); 200 } 201 } 202 203 static void 204 ahci_setup_port(struct ahci_softc *sc, int i) 205 { 206 struct ahci_channel *achp; 207 208 achp = &sc->sc_channels[i]; 209 210 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 211 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 212 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 213 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 214 } 215 216 static void 217 ahci_enable_intrs(struct ahci_softc *sc) 218 { 219 220 /* clear interrupts */ 221 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 222 /* enable interrupts */ 223 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 224 } 225 226 void 227 ahci_attach(struct ahci_softc *sc) 228 { 229 uint32_t ahci_rev; 230 int i, j, port; 231 struct ahci_channel *achp; 232 struct ata_channel *chp; 233 int error; 234 int dmasize; 235 char buf[128]; 236 void *cmdhp; 237 void *cmdtblp; 238 239 if (sc->sc_save_init_data) { 240 ahci_enable(sc); 241 242 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 243 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 244 245 ahci_rev = AHCI_READ(sc, AHCI_VS); 246 if (AHCI_VS_MJR(ahci_rev) > 1 || 247 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 248 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 249 } else { 250 sc->sc_init_data.cap2 = 0; 251 } 252 if (sc->sc_init_data.ports == 0) { 253 sc->sc_init_data.ports = sc->sc_ahci_ports; 254 } 255 } 256 257 if (ahci_reset(sc) != 0) 258 return; 259 260 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 261 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 262 aprint_verbose_dev(sc->sc_atac.atac_dev, 263 "ignoring broken port multiplier support\n"); 264 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 265 } 266 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 267 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 268 ahci_rev = AHCI_READ(sc, AHCI_VS); 269 snprintb(buf, sizeof(buf), "\177\020" 270 /* "f\000\005NP\0" */ 271 "b\005SXS\0" 272 "b\006EMS\0" 273 "b\007CCCS\0" 274 /* "f\010\005NCS\0" */ 275 "b\015PSC\0" 276 "b\016SSC\0" 277 "b\017PMD\0" 278 "b\020FBSS\0" 279 "b\021SPM\0" 280 "b\022SAM\0" 281 "b\023SNZO\0" 282 "f\024\003ISS\0" 283 "=\001Gen1\0" 284 "=\002Gen2\0" 285 "=\003Gen3\0" 286 "b\030SCLO\0" 287 "b\031SAL\0" 288 "b\032SALP\0" 289 "b\033SSS\0" 290 "b\034SMPS\0" 291 "b\035SSNTF\0" 292 "b\036SNCQ\0" 293 "b\037S64A\0" 294 "\0", sc->sc_ahci_cap); 295 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 296 ", %d port%s, %d slot%s, CAP %s\n", 297 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 298 sc->sc_atac.atac_nchannels, 299 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 300 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 301 302 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 303 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 304 sc->sc_atac.atac_pio_cap = 4; 305 sc->sc_atac.atac_dma_cap = 2; 306 sc->sc_atac.atac_udma_cap = 6; 307 sc->sc_atac.atac_channels = sc->sc_chanarray; 308 sc->sc_atac.atac_probe = ahci_probe_drive; 309 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 310 sc->sc_atac.atac_set_modes = ahci_setup_channel; 311 #if NATAPIBUS > 0 312 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 313 #endif 314 315 dmasize = 316 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 318 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 319 if (error) { 320 aprint_error("%s: unable to allocate command header memory" 321 ", error=%d\n", AHCINAME(sc), error); 322 return; 323 } 324 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 325 sc->sc_cmd_hdr_nseg, dmasize, 326 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 327 if (error) { 328 aprint_error("%s: unable to map command header memory" 329 ", error=%d\n", AHCINAME(sc), error); 330 return; 331 } 332 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 333 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 334 if (error) { 335 aprint_error("%s: unable to create command header map" 336 ", error=%d\n", AHCINAME(sc), error); 337 return; 338 } 339 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 340 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error("%s: unable to load command header map" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 sc->sc_cmd_hdr = cmdhp; 347 348 ahci_enable_intrs(sc); 349 350 if (sc->sc_ahci_ports == 0) { 351 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 352 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 353 DEBUG_PROBE); 354 } 355 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 356 if ((sc->sc_ahci_ports & (1 << i)) == 0) 357 continue; 358 if (port >= sc->sc_atac.atac_nchannels) { 359 aprint_error("%s: more ports than announced\n", 360 AHCINAME(sc)); 361 break; 362 } 363 achp = &sc->sc_channels[i]; 364 chp = &achp->ata_channel; 365 sc->sc_chanarray[i] = chp; 366 chp->ch_channel = i; 367 chp->ch_atac = &sc->sc_atac; 368 chp->ch_queue = malloc(sizeof(struct ata_queue), 369 M_DEVBUF, M_NOWAIT|M_ZERO); 370 if (chp->ch_queue == NULL) { 371 aprint_error("%s port %d: can't allocate memory for " 372 "command queue", AHCINAME(sc), i); 373 break; 374 } 375 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 376 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 377 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 378 BUS_DMA_NOWAIT); 379 if (error) { 380 aprint_error("%s: unable to allocate command table " 381 "memory, error=%d\n", AHCINAME(sc), error); 382 break; 383 } 384 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 385 achp->ahcic_cmd_tbl_nseg, dmasize, 386 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 387 if (error) { 388 aprint_error("%s: unable to map command table memory" 389 ", error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 393 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 394 if (error) { 395 aprint_error("%s: unable to create command table map" 396 ", error=%d\n", AHCINAME(sc), error); 397 break; 398 } 399 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 400 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 401 if (error) { 402 aprint_error("%s: unable to load command table map" 403 ", error=%d\n", AHCINAME(sc), error); 404 break; 405 } 406 achp->ahcic_cmdh = (struct ahci_cmd_header *) 407 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 408 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 409 AHCI_CMDH_SIZE * port; 410 achp->ahcic_rfis = (struct ahci_r_fis *) 411 ((char *)cmdhp + 412 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 413 AHCI_RFIS_SIZE * port); 414 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 415 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 416 AHCI_RFIS_SIZE * port; 417 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 418 "rfis %p (0x%" PRIx64 ")\n", i, 419 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 420 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 421 DEBUG_PROBE); 422 423 for (j = 0; j < sc->sc_ncmds; j++) { 424 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 425 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 426 achp->ahcic_bus_cmd_tbl[j] = 427 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 428 AHCI_CMDTBL_SIZE * j; 429 achp->ahcic_cmdh[j].cmdh_cmdtba = 430 htole64(achp->ahcic_bus_cmd_tbl[j]); 431 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 432 achp->ahcic_cmd_tbl[j], 433 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 434 /* The xfer DMA map */ 435 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 436 AHCI_NPRD, 0x400000 /* 4MB */, 0, 437 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 438 &achp->ahcic_datad[j]); 439 if (error) { 440 aprint_error("%s: couldn't alloc xfer DMA map, " 441 "error=%d\n", AHCINAME(sc), error); 442 goto end; 443 } 444 } 445 ahci_setup_port(sc, i); 446 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 447 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 448 aprint_error("%s: couldn't map channel %d " 449 "sata_status regs\n", AHCINAME(sc), i); 450 break; 451 } 452 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 453 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 454 aprint_error("%s: couldn't map channel %d " 455 "sata_control regs\n", AHCINAME(sc), i); 456 break; 457 } 458 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 459 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 460 aprint_error("%s: couldn't map channel %d " 461 "sata_error regs\n", AHCINAME(sc), i); 462 break; 463 } 464 ata_channel_attach(chp); 465 port++; 466 end: 467 continue; 468 } 469 } 470 471 int 472 ahci_detach(struct ahci_softc *sc, int flags) 473 { 474 struct atac_softc *atac; 475 struct ahci_channel *achp; 476 struct ata_channel *chp; 477 struct scsipi_adapter *adapt; 478 int i, j; 479 int error; 480 481 atac = &sc->sc_atac; 482 adapt = &atac->atac_atapi_adapter._generic; 483 484 for (i = 0; i < AHCI_MAX_PORTS; i++) { 485 achp = &sc->sc_channels[i]; 486 chp = &achp->ata_channel; 487 488 if ((sc->sc_ahci_ports & (1 << i)) == 0) 489 continue; 490 if (i >= sc->sc_atac.atac_nchannels) { 491 aprint_error("%s: more ports than announced\n", 492 AHCINAME(sc)); 493 break; 494 } 495 496 if (chp->atabus == NULL) 497 continue; 498 if ((error = config_detach(chp->atabus, flags)) != 0) 499 return error; 500 501 for (j = 0; j < sc->sc_ncmds; j++) 502 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 503 504 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 505 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 506 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 507 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 508 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 509 achp->ahcic_cmd_tbl_nseg); 510 511 free(chp->ch_queue, M_DEVBUF); 512 chp->atabus = NULL; 513 } 514 515 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 516 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 517 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 518 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 519 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 520 521 if (adapt->adapt_refcnt != 0) 522 return EBUSY; 523 524 return 0; 525 } 526 527 void 528 ahci_resume(struct ahci_softc *sc) 529 { 530 ahci_reset(sc); 531 ahci_setup_ports(sc); 532 ahci_reprobe_drives(sc); 533 ahci_enable_intrs(sc); 534 } 535 536 int 537 ahci_intr(void *v) 538 { 539 struct ahci_softc *sc = v; 540 uint32_t is; 541 int i, r = 0; 542 543 while ((is = AHCI_READ(sc, AHCI_IS))) { 544 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 545 DEBUG_INTR); 546 r = 1; 547 AHCI_WRITE(sc, AHCI_IS, is); 548 for (i = 0; i < AHCI_MAX_PORTS; i++) 549 if (is & (1 << i)) 550 ahci_intr_port(sc, &sc->sc_channels[i]); 551 } 552 return r; 553 } 554 555 static void 556 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 557 { 558 uint32_t is, tfd; 559 struct ata_channel *chp = &achp->ata_channel; 560 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 561 int slot; 562 563 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 564 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 565 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 566 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 567 DEBUG_INTR); 568 569 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 570 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 571 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 572 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 573 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 574 return; 575 /* stop channel */ 576 ahci_channel_stop(sc, chp, 0); 577 if (slot != 0) { 578 printf("ahci_intr_port: slot %d\n", slot); 579 panic("ahci_intr_port"); 580 } 581 if (is & AHCI_P_IX_TFES) { 582 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 583 chp->ch_error = 584 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 585 chp->ch_status = (tfd & 0xff); 586 } else { 587 /* emulate a CRC error */ 588 chp->ch_error = WDCE_CRC; 589 chp->ch_status = WDCS_ERR; 590 } 591 if (is & AHCI_P_IX_IFS) { 592 aprint_error("%s port %d: SERR 0x%x\n", 593 AHCINAME(sc), chp->ch_channel, 594 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 595 } 596 xfer->c_intr(chp, xfer, is); 597 /* if channel has not been restarted, do it now */ 598 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 599 == 0) 600 ahci_channel_start(sc, chp, 0, 0); 601 } else { 602 slot = 0; /* XXX */ 603 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 604 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 605 chp->ch_channel, is, achp->ahcic_cmds_active, 606 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 607 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 608 return; 609 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 610 == 0) { 611 xfer->c_intr(chp, xfer, 0); 612 } 613 } 614 } 615 616 static void 617 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 618 { 619 struct ata_channel *chp = drvp->chnl_softc; 620 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 621 AHCI_WRITE(sc, AHCI_GHC, 622 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 623 ahci_channel_stop(sc, chp, flags); 624 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0) 625 ata_reset_channel(chp, flags); 626 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 627 return; 628 } 629 630 /* return error code from ata_bio */ 631 static int 632 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags) 633 { 634 struct ahci_channel *achp = (struct ahci_channel *)chp; 635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 636 int i; 637 uint32_t is; 638 639 /* 640 * Base timeout is specified in ms. 641 * If we are allowed to sleep, wait a tick each round. 642 * Otherwise delay for 10ms on each round. 643 */ 644 if (flags & AT_WAIT) 645 timeout = MAX(1, mstohz(timeout)); 646 else 647 timeout = timeout / 10; 648 649 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 650 /* start command */ 651 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0); 652 for (i = 0; i < timeout; i++) { 653 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0) 654 return 0; 655 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 656 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 657 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 658 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 659 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 660 /* 661 * we got the D2H FIS anyway, 662 * assume sig is valid. 663 * channel is restarted later 664 */ 665 return ERROR; 666 } 667 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 668 AHCINAME(sc), chp->ch_channel, is); 669 return ERR_DF; 670 } 671 if (flags & AT_WAIT) 672 tsleep(&sc, PRIBIO, "ahcifis", 1); 673 else 674 delay(10000); 675 } 676 677 aprint_debug("%s channel %d: timeout sending FIS\n", 678 AHCINAME(sc), chp->ch_channel); 679 return TIMEOUT; 680 } 681 682 static int 683 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 684 uint32_t *sigp) 685 { 686 struct ahci_channel *achp = (struct ahci_channel *)chp; 687 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 688 struct ahci_cmd_tbl *cmd_tbl; 689 struct ahci_cmd_header *cmd_h; 690 int i; 691 uint32_t sig; 692 693 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 694 again: 695 /* clear port interrupt register */ 696 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 697 /* clear SErrors and start operations */ 698 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 699 /* 700 * issue a command list override to clear BSY. 701 * This is needed if there's a PMP with no drive 702 * on port 0 703 */ 704 ahci_channel_start(sc, chp, flags, 1); 705 } else { 706 ahci_channel_start(sc, chp, flags, 0); 707 } 708 if (drive > 0) { 709 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 710 } 711 /* polled command, assume interrupts are disabled */ 712 /* use slot 0 to send reset, the channel is idle */ 713 cmd_h = &achp->ahcic_cmdh[0]; 714 cmd_tbl = achp->ahcic_cmd_tbl[0]; 715 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 716 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 717 cmd_h->cmdh_prdbc = 0; 718 memset(cmd_tbl->cmdt_cfis, 0, 64); 719 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 720 cmd_tbl->cmdt_cfis[rhd_c] = drive; 721 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 722 switch(ahci_exec_fis(chp, 100, flags)) { 723 case ERR_DF: 724 case TIMEOUT: 725 aprint_error("%s channel %d: setting WDCTL_RST failed " 726 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 727 if (sigp) 728 *sigp = 0xffffffff; 729 goto end; 730 default: 731 break; 732 } 733 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 734 (drive << AHCI_CMDH_F_PMP_SHIFT)); 735 cmd_h->cmdh_prdbc = 0; 736 memset(cmd_tbl->cmdt_cfis, 0, 64); 737 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 738 cmd_tbl->cmdt_cfis[rhd_c] = drive; 739 cmd_tbl->cmdt_cfis[rhd_control] = 0; 740 switch(ahci_exec_fis(chp, 310, flags)) { 741 case ERR_DF: 742 case TIMEOUT: 743 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 744 drive == PMP_PORT_CTL) { 745 /* 746 * some controllers fails to reset when 747 * targeting a PMP but a single drive is attached. 748 * try again with port 0 749 */ 750 drive = 0; 751 ahci_channel_stop(sc, chp, flags); 752 goto again; 753 } 754 aprint_error("%s channel %d: clearing WDCTL_RST failed " 755 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 756 if (sigp) 757 *sigp = 0xffffffff; 758 goto end; 759 default: 760 break; 761 } 762 /* 763 * wait 31s for BSY to clear 764 * This should not be needed, but some controllers clear the 765 * command slot before receiving the D2H FIS ... 766 */ 767 for (i = 0; i < AHCI_RST_WAIT; i++) { 768 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 769 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 770 break; 771 if (flags & AT_WAIT) 772 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 773 else 774 delay(10000); 775 } 776 if (i == AHCI_RST_WAIT) { 777 aprint_error("%s: BSY never cleared, TD 0x%x\n", 778 AHCINAME(sc), sig); 779 if (sigp) 780 *sigp = 0xffffffff; 781 goto end; 782 } 783 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 784 DEBUG_PROBE); 785 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 786 if (sigp) 787 *sigp = sig; 788 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 789 AHCINAME(sc), chp->ch_channel, sig, 790 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 791 end: 792 ahci_channel_stop(sc, chp, flags); 793 if (flags & AT_WAIT) 794 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 795 else 796 delay(500000); 797 /* clear port interrupt register */ 798 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 799 ahci_channel_start(sc, chp, flags, 800 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 801 return 0; 802 } 803 804 static void 805 ahci_reset_channel(struct ata_channel *chp, int flags) 806 { 807 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 808 struct ahci_channel *achp = (struct ahci_channel *)chp; 809 int i, tfd; 810 811 ahci_channel_stop(sc, chp, flags); 812 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 813 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 814 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 815 /* XXX and then ? */ 816 } 817 if (chp->ch_queue->active_xfer) { 818 chp->ch_queue->active_xfer->c_kill_xfer(chp, 819 chp->ch_queue->active_xfer, KILL_RESET); 820 } 821 ata_delay(500, "ahcirst", flags); 822 /* clear port interrupt register */ 823 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 824 /* clear SErrors and start operations */ 825 ahci_channel_start(sc, chp, flags, 1); 826 /* wait 31s for BSY to clear */ 827 for (i = 0; i <AHCI_RST_WAIT; i++) { 828 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 829 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 830 & WDCS_BSY) == 0) 831 break; 832 ata_delay(10, "ahcid2h", flags); 833 } 834 if (i == AHCI_RST_WAIT) 835 aprint_error("%s: BSY never cleared, TD 0x%x\n", 836 AHCINAME(sc), tfd); 837 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 838 DEBUG_PROBE); 839 /* clear port interrupt register */ 840 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 841 842 return; 843 } 844 845 static int 846 ahci_ata_addref(struct ata_drive_datas *drvp) 847 { 848 return 0; 849 } 850 851 static void 852 ahci_ata_delref(struct ata_drive_datas *drvp) 853 { 854 return; 855 } 856 857 static void 858 ahci_killpending(struct ata_drive_datas *drvp) 859 { 860 return; 861 } 862 863 static void 864 ahci_probe_drive(struct ata_channel *chp) 865 { 866 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 867 struct ahci_channel *achp = (struct ahci_channel *)chp; 868 uint32_t sig; 869 870 /* bring interface up, accept FISs, power up and spin up device */ 871 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 872 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 873 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 874 /* reset the PHY and bring online */ 875 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 876 achp->ahcic_sstatus, AT_WAIT)) { 877 case SStatus_DET_DEV: 878 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 879 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 880 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig); 881 } else { 882 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig); 883 } 884 sata_interpret_sig(chp, 0, sig); 885 /* if we have a PMP attached, inform the controller */ 886 if (chp->ch_ndrives > PMP_PORT_CTL && 887 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 888 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 889 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 890 AHCI_P_CMD_PMA); 891 } 892 /* clear port interrupt register */ 893 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 894 895 /* and enable interrupts */ 896 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 897 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 898 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 899 AHCI_P_IX_PSS | AHCI_P_IX_DHRS); 900 /* wait 500ms before actually starting operations */ 901 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 902 break; 903 904 default: 905 break; 906 } 907 } 908 909 static void 910 ahci_setup_channel(struct ata_channel *chp) 911 { 912 return; 913 } 914 915 static int 916 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 917 { 918 struct ata_channel *chp = drvp->chnl_softc; 919 struct ata_xfer *xfer; 920 int ret; 921 int s; 922 923 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 924 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 925 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 926 DEBUG_XFERS); 927 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 928 ATAXF_NOSLEEP); 929 if (xfer == NULL) { 930 return ATACMD_TRY_AGAIN; 931 } 932 if (ata_c->flags & AT_POLL) 933 xfer->c_flags |= C_POLL; 934 if (ata_c->flags & AT_WAIT) 935 xfer->c_flags |= C_WAIT; 936 xfer->c_drive = drvp->drive; 937 xfer->c_databuf = ata_c->data; 938 xfer->c_bcount = ata_c->bcount; 939 xfer->c_cmd = ata_c; 940 xfer->c_start = ahci_cmd_start; 941 xfer->c_intr = ahci_cmd_complete; 942 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 943 s = splbio(); 944 ata_exec_xfer(chp, xfer); 945 #ifdef DIAGNOSTIC 946 if ((ata_c->flags & AT_POLL) != 0 && 947 (ata_c->flags & AT_DONE) == 0) 948 panic("ahci_exec_command: polled command not done"); 949 #endif 950 if (ata_c->flags & AT_DONE) { 951 ret = ATACMD_COMPLETE; 952 } else { 953 if (ata_c->flags & AT_WAIT) { 954 while ((ata_c->flags & AT_DONE) == 0) { 955 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 956 } 957 ret = ATACMD_COMPLETE; 958 } else { 959 ret = ATACMD_QUEUED; 960 } 961 } 962 splx(s); 963 return ret; 964 } 965 966 static void 967 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 968 { 969 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 970 struct ahci_channel *achp = (struct ahci_channel *)chp; 971 struct ata_command *ata_c = xfer->c_cmd; 972 int slot = 0 /* XXX slot */; 973 struct ahci_cmd_tbl *cmd_tbl; 974 struct ahci_cmd_header *cmd_h; 975 int i; 976 int channel = chp->ch_channel; 977 978 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n", 979 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout), 980 DEBUG_XFERS); 981 982 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 983 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 984 cmd_tbl), DEBUG_XFERS); 985 986 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 987 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 988 989 cmd_h = &achp->ahcic_cmdh[slot]; 990 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 991 chp->ch_channel, cmd_h), DEBUG_XFERS); 992 if (ahci_dma_setup(chp, slot, 993 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 994 ata_c->data : NULL, 995 ata_c->bcount, 996 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 997 ata_c->flags |= AT_DF; 998 ahci_cmd_complete(chp, xfer, slot); 999 return; 1000 } 1001 cmd_h->cmdh_flags = htole16( 1002 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1003 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1004 cmd_h->cmdh_prdbc = 0; 1005 AHCI_CMDH_SYNC(sc, achp, slot, 1006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1007 1008 if (ata_c->flags & AT_POLL) { 1009 /* polled command, disable interrupts */ 1010 AHCI_WRITE(sc, AHCI_GHC, 1011 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1012 } 1013 chp->ch_flags |= ATACH_IRQ_WAIT; 1014 chp->ch_status = 0; 1015 /* start command */ 1016 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1017 /* and says we started this command */ 1018 achp->ahcic_cmds_active |= 1 << slot; 1019 1020 if ((ata_c->flags & AT_POLL) == 0) { 1021 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1022 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 1023 ahci_timeout, chp); 1024 return; 1025 } 1026 /* 1027 * Polled command. 1028 */ 1029 for (i = 0; i < ata_c->timeout / 10; i++) { 1030 if (ata_c->flags & AT_DONE) 1031 break; 1032 ahci_intr_port(sc, achp); 1033 if (ata_c->flags & AT_WAIT) 1034 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1035 else 1036 delay(10000); 1037 } 1038 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1039 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1040 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1041 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1042 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1043 DEBUG_XFERS); 1044 if ((ata_c->flags & AT_DONE) == 0) { 1045 ata_c->flags |= AT_TIMEOU; 1046 ahci_cmd_complete(chp, xfer, slot); 1047 } 1048 /* reenable interrupts */ 1049 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1050 } 1051 1052 static void 1053 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1054 { 1055 struct ata_command *ata_c = xfer->c_cmd; 1056 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1057 DEBUG_FUNCS); 1058 1059 switch (reason) { 1060 case KILL_GONE: 1061 ata_c->flags |= AT_GONE; 1062 break; 1063 case KILL_RESET: 1064 ata_c->flags |= AT_RESET; 1065 break; 1066 default: 1067 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1068 panic("ahci_cmd_kill_xfer"); 1069 } 1070 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 1071 } 1072 1073 static int 1074 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1075 { 1076 int slot = 0; /* XXX slot */ 1077 struct ata_command *ata_c = xfer->c_cmd; 1078 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1079 struct ahci_channel *achp = (struct ahci_channel *)chp; 1080 1081 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1082 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1083 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1084 DEBUG_FUNCS); 1085 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1086 if (xfer->c_flags & C_TIMEOU) { 1087 ata_c->flags |= AT_TIMEOU; 1088 } else 1089 callout_stop(&chp->ch_callout); 1090 1091 chp->ch_queue->active_xfer = NULL; 1092 1093 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1094 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 1095 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1096 wakeup(&chp->ch_queue->active_xfer); 1097 return 0; 1098 } 1099 1100 if (chp->ch_status & WDCS_BSY) { 1101 ata_c->flags |= AT_TIMEOU; 1102 } else if (chp->ch_status & WDCS_ERR) { 1103 ata_c->r_error = chp->ch_error; 1104 ata_c->flags |= AT_ERROR; 1105 } 1106 1107 if (ata_c->flags & AT_READREG) 1108 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1109 1110 ahci_cmd_done(chp, xfer, slot); 1111 return 0; 1112 } 1113 1114 static void 1115 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1116 { 1117 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1118 struct ahci_channel *achp = (struct ahci_channel *)chp; 1119 struct ata_command *ata_c = xfer->c_cmd; 1120 uint16_t *idwordbuf; 1121 int i; 1122 1123 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n", 1124 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1125 1126 /* this comamnd is not active any more */ 1127 achp->ahcic_cmds_active &= ~(1 << slot); 1128 1129 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1130 bus_dmamap_t map = achp->ahcic_datad[slot]; 1131 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1132 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1133 BUS_DMASYNC_POSTWRITE); 1134 bus_dmamap_unload(sc->sc_dmat, map); 1135 } 1136 1137 AHCI_CMDH_SYNC(sc, achp, slot, 1138 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1139 1140 /* ata(4) expects IDENTIFY data to be in host endianess */ 1141 if (ata_c->r_command == WDCC_IDENTIFY || 1142 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1143 idwordbuf = xfer->c_databuf; 1144 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1145 idwordbuf[i] = le16toh(idwordbuf[i]); 1146 } 1147 } 1148 1149 ata_c->flags |= AT_DONE; 1150 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 1151 ata_c->flags |= AT_XFDONE; 1152 1153 ata_free_xfer(chp, xfer); 1154 if (ata_c->flags & AT_WAIT) 1155 wakeup(ata_c); 1156 else if (ata_c->callback) 1157 ata_c->callback(ata_c->callback_arg); 1158 atastart(chp); 1159 return; 1160 } 1161 1162 static int 1163 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1164 { 1165 struct ata_channel *chp = drvp->chnl_softc; 1166 struct ata_xfer *xfer; 1167 1168 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1169 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1170 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1171 DEBUG_XFERS); 1172 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1173 if (xfer == NULL) { 1174 return ATACMD_TRY_AGAIN; 1175 } 1176 if (ata_bio->flags & ATA_POLL) 1177 xfer->c_flags |= C_POLL; 1178 xfer->c_drive = drvp->drive; 1179 xfer->c_cmd = ata_bio; 1180 xfer->c_databuf = ata_bio->databuf; 1181 xfer->c_bcount = ata_bio->bcount; 1182 xfer->c_start = ahci_bio_start; 1183 xfer->c_intr = ahci_bio_complete; 1184 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1185 ata_exec_xfer(chp, xfer); 1186 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1187 } 1188 1189 static void 1190 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1191 { 1192 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1193 struct ahci_channel *achp = (struct ahci_channel *)chp; 1194 struct ata_bio *ata_bio = xfer->c_cmd; 1195 int slot = 0 /* XXX slot */; 1196 struct ahci_cmd_tbl *cmd_tbl; 1197 struct ahci_cmd_header *cmd_h; 1198 int i; 1199 int channel = chp->ch_channel; 1200 1201 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1202 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1203 1204 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1205 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1206 cmd_tbl), DEBUG_XFERS); 1207 1208 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1209 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1210 1211 cmd_h = &achp->ahcic_cmdh[slot]; 1212 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1213 chp->ch_channel, cmd_h), DEBUG_XFERS); 1214 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1215 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1216 ata_bio->error = ERR_DMA; 1217 ata_bio->r_error = 0; 1218 ahci_bio_complete(chp, xfer, slot); 1219 return; 1220 } 1221 cmd_h->cmdh_flags = htole16( 1222 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1223 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1224 cmd_h->cmdh_prdbc = 0; 1225 AHCI_CMDH_SYNC(sc, achp, slot, 1226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1227 1228 if (xfer->c_flags & C_POLL) { 1229 /* polled command, disable interrupts */ 1230 AHCI_WRITE(sc, AHCI_GHC, 1231 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1232 } 1233 chp->ch_flags |= ATACH_IRQ_WAIT; 1234 chp->ch_status = 0; 1235 /* start command */ 1236 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1237 /* and says we started this command */ 1238 achp->ahcic_cmds_active |= 1 << slot; 1239 1240 if ((xfer->c_flags & C_POLL) == 0) { 1241 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1242 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1243 ahci_timeout, chp); 1244 return; 1245 } 1246 /* 1247 * Polled command. 1248 */ 1249 for (i = 0; i < ATA_DELAY * 10; i++) { 1250 if (ata_bio->flags & ATA_ITSDONE) 1251 break; 1252 ahci_intr_port(sc, achp); 1253 delay(100); 1254 } 1255 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1256 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1257 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1258 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1259 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1260 DEBUG_XFERS); 1261 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1262 ata_bio->error = TIMEOUT; 1263 ahci_bio_complete(chp, xfer, slot); 1264 } 1265 /* reenable interrupts */ 1266 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1267 } 1268 1269 static void 1270 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1271 { 1272 int slot = 0; /* XXX slot */ 1273 int drive = xfer->c_drive; 1274 struct ata_bio *ata_bio = xfer->c_cmd; 1275 struct ahci_channel *achp = (struct ahci_channel *)chp; 1276 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1277 DEBUG_FUNCS); 1278 1279 achp->ahcic_cmds_active &= ~(1 << slot); 1280 ata_free_xfer(chp, xfer); 1281 ata_bio->flags |= ATA_ITSDONE; 1282 switch (reason) { 1283 case KILL_GONE: 1284 ata_bio->error = ERR_NODEV; 1285 break; 1286 case KILL_RESET: 1287 ata_bio->error = ERR_RESET; 1288 break; 1289 default: 1290 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1291 panic("ahci_bio_kill_xfer"); 1292 } 1293 ata_bio->r_error = WDCE_ABRT; 1294 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1295 } 1296 1297 static int 1298 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1299 { 1300 int slot = 0; /* XXX slot */ 1301 struct ata_bio *ata_bio = xfer->c_cmd; 1302 int drive = xfer->c_drive; 1303 struct ahci_channel *achp = (struct ahci_channel *)chp; 1304 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1305 1306 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1307 DEBUG_FUNCS); 1308 1309 achp->ahcic_cmds_active &= ~(1 << slot); 1310 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1311 if (xfer->c_flags & C_TIMEOU) { 1312 ata_bio->error = TIMEOUT; 1313 } else { 1314 callout_stop(&chp->ch_callout); 1315 ata_bio->error = NOERROR; 1316 } 1317 1318 chp->ch_queue->active_xfer = NULL; 1319 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1320 achp->ahcic_datad[slot]->dm_mapsize, 1321 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1322 BUS_DMASYNC_POSTWRITE); 1323 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1324 1325 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1326 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1327 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1328 wakeup(&chp->ch_queue->active_xfer); 1329 return 0; 1330 } 1331 ata_free_xfer(chp, xfer); 1332 ata_bio->flags |= ATA_ITSDONE; 1333 if (chp->ch_status & WDCS_DWF) { 1334 ata_bio->error = ERR_DF; 1335 } else if (chp->ch_status & WDCS_ERR) { 1336 ata_bio->error = ERROR; 1337 ata_bio->r_error = chp->ch_error; 1338 } else if (chp->ch_status & WDCS_CORR) 1339 ata_bio->flags |= ATA_CORR; 1340 1341 AHCI_CMDH_SYNC(sc, achp, slot, 1342 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1343 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1344 ata_bio->bcount), DEBUG_XFERS); 1345 /* 1346 * if it was a write, complete data buffer may have been transfered 1347 * before error detection; in this case don't use cmdh_prdbc 1348 * as it won't reflect what was written to media. Assume nothing 1349 * was transfered and leave bcount as-is. 1350 */ 1351 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1352 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1353 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1354 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1355 atastart(chp); 1356 return 0; 1357 } 1358 1359 static void 1360 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1361 { 1362 int i; 1363 /* stop channel */ 1364 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1365 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1366 /* wait 1s for channel to stop */ 1367 for (i = 0; i <100; i++) { 1368 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1369 == 0) 1370 break; 1371 if (flags & AT_WAIT) 1372 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10)); 1373 else 1374 delay(10000); 1375 } 1376 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1377 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1378 /* XXX controller reset ? */ 1379 return; 1380 } 1381 1382 if (sc->sc_channel_stop) 1383 sc->sc_channel_stop(sc, chp); 1384 } 1385 1386 static void 1387 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1388 int flags, int clo) 1389 { 1390 int i; 1391 uint32_t p_cmd; 1392 /* clear error */ 1393 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1394 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1395 1396 if (clo) { 1397 /* issue command list override */ 1398 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1399 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1400 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1401 /* wait 1s for AHCI_CAP_CLO to clear */ 1402 for (i = 0; i <100; i++) { 1403 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1404 AHCI_P_CMD_CLO) == 0) 1405 break; 1406 if (flags & AT_WAIT) 1407 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10)); 1408 else 1409 delay(10000); 1410 } 1411 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1412 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1413 /* XXX controller reset ? */ 1414 return; 1415 } 1416 } 1417 1418 if (sc->sc_channel_start) 1419 sc->sc_channel_start(sc, chp); 1420 1421 /* and start controller */ 1422 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1423 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1424 if (chp->ch_ndrives > PMP_PORT_CTL && 1425 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1426 p_cmd |= AHCI_P_CMD_PMA; 1427 } 1428 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1429 } 1430 1431 static void 1432 ahci_timeout(void *v) 1433 { 1434 struct ata_channel *chp = (struct ata_channel *)v; 1435 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1436 #ifdef AHCI_DEBUG 1437 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1438 #endif 1439 int s = splbio(); 1440 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x ghc %08x is %08x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)), AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS)), DEBUG_INTR); 1441 1442 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1443 xfer->c_flags |= C_TIMEOU; 1444 xfer->c_intr(chp, xfer, 0); 1445 } 1446 splx(s); 1447 } 1448 1449 static int 1450 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1451 size_t count, int op) 1452 { 1453 int error, seg; 1454 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1455 struct ahci_channel *achp = (struct ahci_channel *)chp; 1456 struct ahci_cmd_tbl *cmd_tbl; 1457 struct ahci_cmd_header *cmd_h; 1458 1459 cmd_h = &achp->ahcic_cmdh[slot]; 1460 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1461 1462 if (data == NULL) { 1463 cmd_h->cmdh_prdtl = 0; 1464 goto end; 1465 } 1466 1467 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1468 data, count, NULL, 1469 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1470 if (error) { 1471 printf("%s port %d: failed to load xfer: %d\n", 1472 AHCINAME(sc), chp->ch_channel, error); 1473 return error; 1474 } 1475 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1476 achp->ahcic_datad[slot]->dm_mapsize, 1477 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1478 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1479 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1480 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1481 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1482 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1483 } 1484 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1485 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1486 end: 1487 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1488 return 0; 1489 } 1490 1491 #if NATAPIBUS > 0 1492 static void 1493 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1494 { 1495 struct ata_channel *chp = ata_sc->sc_chan; 1496 struct atac_softc *atac = chp->ch_atac; 1497 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1498 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1499 /* 1500 * Fill in the scsipi_adapter. 1501 */ 1502 adapt->adapt_dev = atac->atac_dev; 1503 adapt->adapt_nchannels = atac->atac_nchannels; 1504 adapt->adapt_request = ahci_atapi_scsipi_request; 1505 adapt->adapt_minphys = ahci_atapi_minphys; 1506 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1507 1508 /* 1509 * Fill in the scsipi_channel. 1510 */ 1511 memset(chan, 0, sizeof(*chan)); 1512 chan->chan_adapter = adapt; 1513 chan->chan_bustype = &ahci_atapi_bustype; 1514 chan->chan_channel = chp->ch_channel; 1515 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1516 chan->chan_openings = 1; 1517 chan->chan_max_periph = 1; 1518 chan->chan_ntargets = 1; 1519 chan->chan_nluns = 1; 1520 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1521 atapiprint); 1522 } 1523 1524 static void 1525 ahci_atapi_minphys(struct buf *bp) 1526 { 1527 if (bp->b_bcount > MAXPHYS) 1528 bp->b_bcount = MAXPHYS; 1529 minphys(bp); 1530 } 1531 1532 /* 1533 * Kill off all pending xfers for a periph. 1534 * 1535 * Must be called at splbio(). 1536 */ 1537 static void 1538 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1539 { 1540 struct atac_softc *atac = 1541 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1542 struct ata_channel *chp = 1543 atac->atac_channels[periph->periph_channel->chan_channel]; 1544 1545 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1546 } 1547 1548 static void 1549 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1550 scsipi_adapter_req_t req, void *arg) 1551 { 1552 struct scsipi_adapter *adapt = chan->chan_adapter; 1553 struct scsipi_periph *periph; 1554 struct scsipi_xfer *sc_xfer; 1555 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1556 struct atac_softc *atac = &sc->sc_atac; 1557 struct ata_xfer *xfer; 1558 int channel = chan->chan_channel; 1559 int drive, s; 1560 1561 switch (req) { 1562 case ADAPTER_REQ_RUN_XFER: 1563 sc_xfer = arg; 1564 periph = sc_xfer->xs_periph; 1565 drive = periph->periph_target; 1566 if (!device_is_active(atac->atac_dev)) { 1567 sc_xfer->error = XS_DRIVER_STUFFUP; 1568 scsipi_done(sc_xfer); 1569 return; 1570 } 1571 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1572 if (xfer == NULL) { 1573 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1574 scsipi_done(sc_xfer); 1575 return; 1576 } 1577 1578 if (sc_xfer->xs_control & XS_CTL_POLL) 1579 xfer->c_flags |= C_POLL; 1580 xfer->c_drive = drive; 1581 xfer->c_flags |= C_ATAPI; 1582 xfer->c_cmd = sc_xfer; 1583 xfer->c_databuf = sc_xfer->data; 1584 xfer->c_bcount = sc_xfer->datalen; 1585 xfer->c_start = ahci_atapi_start; 1586 xfer->c_intr = ahci_atapi_complete; 1587 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1588 xfer->c_dscpoll = 0; 1589 s = splbio(); 1590 ata_exec_xfer(atac->atac_channels[channel], xfer); 1591 #ifdef DIAGNOSTIC 1592 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1593 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1594 panic("ahci_atapi_scsipi_request: polled command " 1595 "not done"); 1596 #endif 1597 splx(s); 1598 return; 1599 default: 1600 /* Not supported, nothing to do. */ 1601 ; 1602 } 1603 } 1604 1605 static void 1606 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1607 { 1608 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1609 struct ahci_channel *achp = (struct ahci_channel *)chp; 1610 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1611 int slot = 0 /* XXX slot */; 1612 struct ahci_cmd_tbl *cmd_tbl; 1613 struct ahci_cmd_header *cmd_h; 1614 int i; 1615 int channel = chp->ch_channel; 1616 1617 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1618 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1619 1620 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1621 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1622 cmd_tbl), DEBUG_XFERS); 1623 1624 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1625 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1626 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1627 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1628 1629 cmd_h = &achp->ahcic_cmdh[slot]; 1630 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1631 chp->ch_channel, cmd_h), DEBUG_XFERS); 1632 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1633 sc_xfer->datalen, 1634 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1635 BUS_DMA_READ : BUS_DMA_WRITE)) { 1636 sc_xfer->error = XS_DRIVER_STUFFUP; 1637 ahci_atapi_complete(chp, xfer, slot); 1638 return; 1639 } 1640 cmd_h->cmdh_flags = htole16( 1641 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1642 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1643 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1644 cmd_h->cmdh_prdbc = 0; 1645 AHCI_CMDH_SYNC(sc, achp, slot, 1646 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1647 1648 if (xfer->c_flags & C_POLL) { 1649 /* polled command, disable interrupts */ 1650 AHCI_WRITE(sc, AHCI_GHC, 1651 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1652 } 1653 chp->ch_flags |= ATACH_IRQ_WAIT; 1654 chp->ch_status = 0; 1655 /* start command */ 1656 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1657 /* and says we started this command */ 1658 achp->ahcic_cmds_active |= 1 << slot; 1659 1660 if ((xfer->c_flags & C_POLL) == 0) { 1661 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1662 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1663 ahci_timeout, chp); 1664 return; 1665 } 1666 /* 1667 * Polled command. 1668 */ 1669 for (i = 0; i < ATA_DELAY / 10; i++) { 1670 if (sc_xfer->xs_status & XS_STS_DONE) 1671 break; 1672 ahci_intr_port(sc, achp); 1673 delay(10000); 1674 } 1675 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1676 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1677 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1678 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1679 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1680 DEBUG_XFERS); 1681 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1682 sc_xfer->error = XS_TIMEOUT; 1683 ahci_atapi_complete(chp, xfer, slot); 1684 } 1685 /* reenable interrupts */ 1686 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1687 } 1688 1689 static int 1690 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1691 { 1692 int slot = 0; /* XXX slot */ 1693 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1694 int drive = xfer->c_drive; 1695 struct ahci_channel *achp = (struct ahci_channel *)chp; 1696 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1697 1698 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1699 DEBUG_FUNCS); 1700 1701 achp->ahcic_cmds_active &= ~(1 << slot); 1702 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1703 if (xfer->c_flags & C_TIMEOU) { 1704 sc_xfer->error = XS_TIMEOUT; 1705 } else { 1706 callout_stop(&chp->ch_callout); 1707 sc_xfer->error = 0; 1708 } 1709 1710 chp->ch_queue->active_xfer = NULL; 1711 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1712 achp->ahcic_datad[slot]->dm_mapsize, 1713 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1716 1717 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1718 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1719 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1720 wakeup(&chp->ch_queue->active_xfer); 1721 return 0; 1722 } 1723 ata_free_xfer(chp, xfer); 1724 1725 AHCI_CMDH_SYNC(sc, achp, slot, 1726 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1727 sc_xfer->resid = sc_xfer->datalen; 1728 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1729 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1730 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1731 if (chp->ch_status & WDCS_ERR && 1732 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1733 sc_xfer->resid == sc_xfer->datalen)) { 1734 sc_xfer->error = XS_SHORTSENSE; 1735 sc_xfer->sense.atapi_sense = chp->ch_error; 1736 if ((sc_xfer->xs_periph->periph_quirks & 1737 PQUIRK_NOSENSE) == 0) { 1738 /* ask scsipi to send a REQUEST_SENSE */ 1739 sc_xfer->error = XS_BUSY; 1740 sc_xfer->status = SCSI_CHECK; 1741 } 1742 } 1743 scsipi_done(sc_xfer); 1744 atastart(chp); 1745 return 0; 1746 } 1747 1748 static void 1749 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1750 { 1751 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1752 struct ahci_channel *achp = (struct ahci_channel *)chp; 1753 int slot = 0; /* XXX slot */ 1754 1755 achp->ahcic_cmds_active &= ~(1 << slot); 1756 1757 /* remove this command from xfer queue */ 1758 switch (reason) { 1759 case KILL_GONE: 1760 sc_xfer->error = XS_DRIVER_STUFFUP; 1761 break; 1762 case KILL_RESET: 1763 sc_xfer->error = XS_RESET; 1764 break; 1765 default: 1766 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1767 panic("ahci_ata_atapi_kill_xfer"); 1768 } 1769 ata_free_xfer(chp, xfer); 1770 scsipi_done(sc_xfer); 1771 } 1772 1773 static void 1774 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1775 { 1776 struct scsipi_channel *chan = sc->sc_channel; 1777 struct scsipi_periph *periph; 1778 struct ataparams ids; 1779 struct ataparams *id = &ids; 1780 struct ahci_softc *ahcic = 1781 device_private(chan->chan_adapter->adapt_dev); 1782 struct atac_softc *atac = &ahcic->sc_atac; 1783 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1784 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1785 struct scsipibus_attach_args sa; 1786 char serial_number[21], model[41], firmware_revision[9]; 1787 int s; 1788 1789 /* skip if already attached */ 1790 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1791 return; 1792 1793 /* if no ATAPI device detected at attach time, skip */ 1794 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1795 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1796 "not present\n", target), DEBUG_PROBE); 1797 return; 1798 } 1799 1800 /* Some ATAPI devices need a bit more time after software reset. */ 1801 delay(5000); 1802 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1803 #ifdef ATAPI_DEBUG_PROBE 1804 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1805 AHCINAME(ahcic), target, 1806 id->atap_config & ATAPI_CFG_CMD_MASK, 1807 id->atap_config & ATAPI_CFG_DRQ_MASK); 1808 #endif 1809 periph = scsipi_alloc_periph(M_NOWAIT); 1810 if (periph == NULL) { 1811 aprint_error_dev(sc->sc_dev, 1812 "unable to allocate periph for drive %d\n", 1813 target); 1814 return; 1815 } 1816 periph->periph_dev = NULL; 1817 periph->periph_channel = chan; 1818 periph->periph_switch = &atapi_probe_periphsw; 1819 periph->periph_target = target; 1820 periph->periph_lun = 0; 1821 periph->periph_quirks = PQUIRK_ONLYBIG; 1822 1823 #ifdef SCSIPI_DEBUG 1824 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1825 SCSIPI_DEBUG_TARGET == target) 1826 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1827 #endif 1828 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1829 if (id->atap_config & ATAPI_CFG_REMOV) 1830 periph->periph_flags |= PERIPH_REMOVABLE; 1831 if (periph->periph_type == T_SEQUENTIAL) { 1832 s = splbio(); 1833 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 1834 splx(s); 1835 } 1836 1837 sa.sa_periph = periph; 1838 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1839 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1840 T_REMOV : T_FIXED; 1841 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1842 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1843 20); 1844 scsipi_strvis((u_char *)firmware_revision, 8, 1845 id->atap_revision, 8); 1846 sa.sa_inqbuf.vendor = model; 1847 sa.sa_inqbuf.product = serial_number; 1848 sa.sa_inqbuf.revision = firmware_revision; 1849 1850 /* 1851 * Determine the operating mode capabilities of the device. 1852 */ 1853 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1854 periph->periph_cap |= PERIPH_CAP_CMD16; 1855 /* XXX This is gross. */ 1856 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1857 1858 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1859 1860 if (drvp->drv_softc) 1861 ata_probe_caps(drvp); 1862 else { 1863 s = splbio(); 1864 drvp->drive_type = ATA_DRIVET_NONE; 1865 splx(s); 1866 } 1867 } else { 1868 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1869 "failed for drive %s:%d:%d: error 0x%x\n", 1870 AHCINAME(ahcic), chp->ch_channel, target, 1871 chp->ch_error), DEBUG_PROBE); 1872 s = splbio(); 1873 drvp->drive_type = ATA_DRIVET_NONE; 1874 splx(s); 1875 } 1876 } 1877 #endif /* NATAPIBUS */ 1878
Indexes created Thu Sep 25 16:09:42 GMT 2025