ahcisata_core.c revision 1.58
1 /* $NetBSD: ahcisata_core.c,v 1.58 2017/10/07 16:05:32 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.58 2017/10/07 16:05:32 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 struct ata_xfer *xfer); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 void ahci_channel_recover(struct ahci_softc *, struct ata_channel *, int); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending 125 }; 126 127 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 return 0; 170 } 171 172 static void 173 ahci_setup_ports(struct ahci_softc *sc) 174 { 175 int i, port; 176 177 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 178 if ((sc->sc_ahci_ports & (1 << i)) == 0) 179 continue; 180 if (port >= sc->sc_atac.atac_nchannels) { 181 aprint_error("%s: more ports than announced\n", 182 AHCINAME(sc)); 183 break; 184 } 185 ahci_setup_port(sc, i); 186 } 187 } 188 189 static void 190 ahci_reprobe_drives(struct ahci_softc *sc) 191 { 192 int i, port; 193 struct ahci_channel *achp; 194 struct ata_channel *chp; 195 196 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 197 if ((sc->sc_ahci_ports & (1 << i)) == 0) 198 continue; 199 if (port >= sc->sc_atac.atac_nchannels) { 200 aprint_error("%s: more ports than announced\n", 201 AHCINAME(sc)); 202 break; 203 } 204 achp = &sc->sc_channels[i]; 205 chp = &achp->ata_channel; 206 207 ahci_probe_drive(chp); 208 } 209 } 210 211 static void 212 ahci_setup_port(struct ahci_softc *sc, int i) 213 { 214 struct ahci_channel *achp; 215 216 achp = &sc->sc_channels[i]; 217 218 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 219 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 220 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 221 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 222 } 223 224 static void 225 ahci_enable_intrs(struct ahci_softc *sc) 226 { 227 228 /* clear interrupts */ 229 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 230 /* enable interrupts */ 231 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 232 } 233 234 void 235 ahci_attach(struct ahci_softc *sc) 236 { 237 uint32_t ahci_rev; 238 int i, j, port; 239 struct ahci_channel *achp; 240 struct ata_channel *chp; 241 int error; 242 int dmasize; 243 char buf[128]; 244 void *cmdhp; 245 void *cmdtblp; 246 247 if (sc->sc_save_init_data) { 248 ahci_enable(sc); 249 250 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 251 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 252 253 ahci_rev = AHCI_READ(sc, AHCI_VS); 254 if (AHCI_VS_MJR(ahci_rev) > 1 || 255 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 256 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 257 } else { 258 sc->sc_init_data.cap2 = 0; 259 } 260 if (sc->sc_init_data.ports == 0) { 261 sc->sc_init_data.ports = sc->sc_ahci_ports; 262 } 263 } 264 265 if (ahci_reset(sc) != 0) 266 return; 267 268 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 269 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 270 aprint_verbose_dev(sc->sc_atac.atac_dev, 271 "ignoring broken port multiplier support\n"); 272 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 273 } 274 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 275 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 276 ahci_rev = AHCI_READ(sc, AHCI_VS); 277 snprintb(buf, sizeof(buf), "\177\020" 278 /* "f\000\005NP\0" */ 279 "b\005SXS\0" 280 "b\006EMS\0" 281 "b\007CCCS\0" 282 /* "f\010\005NCS\0" */ 283 "b\015PSC\0" 284 "b\016SSC\0" 285 "b\017PMD\0" 286 "b\020FBSS\0" 287 "b\021SPM\0" 288 "b\022SAM\0" 289 "b\023SNZO\0" 290 "f\024\003ISS\0" 291 "=\001Gen1\0" 292 "=\002Gen2\0" 293 "=\003Gen3\0" 294 "b\030SCLO\0" 295 "b\031SAL\0" 296 "b\032SALP\0" 297 "b\033SSS\0" 298 "b\034SMPS\0" 299 "b\035SSNTF\0" 300 "b\036SNCQ\0" 301 "b\037S64A\0" 302 "\0", sc->sc_ahci_cap); 303 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 304 ", %d port%s, %d slot%s, CAP %s\n", 305 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 306 sc->sc_atac.atac_nchannels, 307 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 308 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 309 310 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 311 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 312 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 313 sc->sc_atac.atac_pio_cap = 4; 314 sc->sc_atac.atac_dma_cap = 2; 315 sc->sc_atac.atac_udma_cap = 6; 316 sc->sc_atac.atac_channels = sc->sc_chanarray; 317 sc->sc_atac.atac_probe = ahci_probe_drive; 318 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 319 sc->sc_atac.atac_set_modes = ahci_setup_channel; 320 #if NATAPIBUS > 0 321 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 322 #endif 323 324 dmasize = 325 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 326 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 327 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 328 if (error) { 329 aprint_error("%s: unable to allocate command header memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 return; 332 } 333 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 334 sc->sc_cmd_hdr_nseg, dmasize, 335 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 336 if (error) { 337 aprint_error("%s: unable to map command header memory" 338 ", error=%d\n", AHCINAME(sc), error); 339 return; 340 } 341 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 342 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 343 if (error) { 344 aprint_error("%s: unable to create command header map" 345 ", error=%d\n", AHCINAME(sc), error); 346 return; 347 } 348 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 349 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 350 if (error) { 351 aprint_error("%s: unable to load command header map" 352 ", error=%d\n", AHCINAME(sc), error); 353 return; 354 } 355 sc->sc_cmd_hdr = cmdhp; 356 357 ahci_enable_intrs(sc); 358 359 if (sc->sc_ahci_ports == 0) { 360 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 361 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 362 DEBUG_PROBE); 363 } 364 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 365 if ((sc->sc_ahci_ports & (1 << i)) == 0) 366 continue; 367 if (port >= sc->sc_atac.atac_nchannels) { 368 aprint_error("%s: more ports than announced\n", 369 AHCINAME(sc)); 370 break; 371 } 372 achp = &sc->sc_channels[i]; 373 chp = &achp->ata_channel; 374 sc->sc_chanarray[i] = chp; 375 chp->ch_channel = i; 376 chp->ch_atac = &sc->sc_atac; 377 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 378 if (chp->ch_queue == NULL) { 379 aprint_error("%s port %d: can't allocate memory for " 380 "command queue", AHCINAME(sc), i); 381 break; 382 } 383 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 384 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 385 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 386 BUS_DMA_NOWAIT); 387 if (error) { 388 aprint_error("%s: unable to allocate command table " 389 "memory, error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 393 achp->ahcic_cmd_tbl_nseg, dmasize, 394 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 395 if (error) { 396 aprint_error("%s: unable to map command table memory" 397 ", error=%d\n", AHCINAME(sc), error); 398 break; 399 } 400 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 401 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 402 if (error) { 403 aprint_error("%s: unable to create command table map" 404 ", error=%d\n", AHCINAME(sc), error); 405 break; 406 } 407 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 408 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 409 if (error) { 410 aprint_error("%s: unable to load command table map" 411 ", error=%d\n", AHCINAME(sc), error); 412 break; 413 } 414 achp->ahcic_cmdh = (struct ahci_cmd_header *) 415 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 416 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 417 AHCI_CMDH_SIZE * port; 418 achp->ahcic_rfis = (struct ahci_r_fis *) 419 ((char *)cmdhp + 420 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 421 AHCI_RFIS_SIZE * port); 422 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port; 425 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 426 "rfis %p (0x%" PRIx64 ")\n", i, 427 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 428 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 429 DEBUG_PROBE); 430 431 for (j = 0; j < sc->sc_ncmds; j++) { 432 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 433 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 434 achp->ahcic_bus_cmd_tbl[j] = 435 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 436 AHCI_CMDTBL_SIZE * j; 437 achp->ahcic_cmdh[j].cmdh_cmdtba = 438 htole64(achp->ahcic_bus_cmd_tbl[j]); 439 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 440 achp->ahcic_cmd_tbl[j], 441 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 442 /* The xfer DMA map */ 443 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 444 AHCI_NPRD, 0x400000 /* 4MB */, 0, 445 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 446 &achp->ahcic_datad[j]); 447 if (error) { 448 aprint_error("%s: couldn't alloc xfer DMA map, " 449 "error=%d\n", AHCINAME(sc), error); 450 goto end; 451 } 452 } 453 ahci_setup_port(sc, i); 454 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 455 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 456 aprint_error("%s: couldn't map channel %d " 457 "sata_status regs\n", AHCINAME(sc), i); 458 break; 459 } 460 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 461 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 462 aprint_error("%s: couldn't map channel %d " 463 "sata_control regs\n", AHCINAME(sc), i); 464 break; 465 } 466 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 467 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 468 aprint_error("%s: couldn't map channel %d " 469 "sata_error regs\n", AHCINAME(sc), i); 470 break; 471 } 472 ata_channel_attach(chp); 473 port++; 474 end: 475 continue; 476 } 477 } 478 479 int 480 ahci_detach(struct ahci_softc *sc, int flags) 481 { 482 struct atac_softc *atac; 483 struct ahci_channel *achp; 484 struct ata_channel *chp; 485 struct scsipi_adapter *adapt; 486 int i, j; 487 int error; 488 489 atac = &sc->sc_atac; 490 adapt = &atac->atac_atapi_adapter._generic; 491 492 for (i = 0; i < AHCI_MAX_PORTS; i++) { 493 achp = &sc->sc_channels[i]; 494 chp = &achp->ata_channel; 495 496 if ((sc->sc_ahci_ports & (1 << i)) == 0) 497 continue; 498 if (i >= sc->sc_atac.atac_nchannels) { 499 aprint_error("%s: more ports than announced\n", 500 AHCINAME(sc)); 501 break; 502 } 503 504 if (chp->atabus == NULL) 505 continue; 506 if ((error = config_detach(chp->atabus, flags)) != 0) 507 return error; 508 509 for (j = 0; j < sc->sc_ncmds; j++) 510 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 511 512 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 513 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 514 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 515 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 516 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 517 achp->ahcic_cmd_tbl_nseg); 518 519 ata_queue_free(chp->ch_queue); 520 chp->ch_queue = NULL; 521 chp->atabus = NULL; 522 523 ata_channel_detach(chp); 524 } 525 526 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 527 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 528 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 529 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 530 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 531 532 if (adapt->adapt_refcnt != 0) 533 return EBUSY; 534 535 return 0; 536 } 537 538 void 539 ahci_resume(struct ahci_softc *sc) 540 { 541 ahci_reset(sc); 542 ahci_setup_ports(sc); 543 ahci_reprobe_drives(sc); 544 ahci_enable_intrs(sc); 545 } 546 547 int 548 ahci_intr(void *v) 549 { 550 struct ahci_softc *sc = v; 551 uint32_t is; 552 int i, r = 0; 553 554 while ((is = AHCI_READ(sc, AHCI_IS))) { 555 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 556 DEBUG_INTR); 557 r = 1; 558 AHCI_WRITE(sc, AHCI_IS, is); 559 for (i = 0; i < AHCI_MAX_PORTS; i++) 560 if (is & (1 << i)) 561 ahci_intr_port(sc, &sc->sc_channels[i]); 562 } 563 return r; 564 } 565 566 static void 567 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 568 { 569 uint32_t is, tfd, sact; 570 struct ata_channel *chp = &achp->ata_channel; 571 struct ata_xfer *xfer; 572 int slot = -1; 573 bool recover = false; 574 575 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 576 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 577 AHCIDEBUG_PRINT(( 578 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 579 AHCINAME(sc), 580 chp->ch_channel, is, 581 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 582 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 583 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 584 DEBUG_INTR); 585 586 if ((chp->ch_flags & ATACH_NCQ) == 0) { 587 /* Non-NCQ operation */ 588 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 589 } else { 590 /* NCQ operation */ 591 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 592 } 593 594 /* Handle errors */ 595 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 596 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 597 /* Fatal errors */ 598 if (is & AHCI_P_IX_TFES) { 599 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 600 601 if ((chp->ch_flags & ATACH_NCQ) == 0) { 602 /* Slot valid only for Non-NCQ operation */ 603 slot = (AHCI_READ(sc, 604 AHCI_P_CMD(chp->ch_channel)) 605 & AHCI_P_CMD_CCS_MASK) 606 >> AHCI_P_CMD_CCS_SHIFT; 607 } 608 609 aprint_error("%s port %d: active %x is 0x%x tfd 0x%x\n", 610 AHCINAME(sc), chp->ch_channel, sact, is, tfd); 611 } else { 612 /* mark an error, and set BSY */ 613 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 614 WDCS_ERR | WDCS_BSY; 615 } 616 617 if (is & AHCI_P_IX_IFS) { 618 aprint_error("%s port %d: SERR 0x%x\n", 619 AHCINAME(sc), chp->ch_channel, 620 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 621 } 622 623 if (!achp->ahcic_recovering) 624 recover = true; 625 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 626 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 627 628 /* D2H Register FIS or Set Device Bits */ 629 if ((tfd & WDCS_ERR) != 0) { 630 if (!achp->ahcic_recovering) 631 recover = true; 632 633 aprint_error("%s port %d: transfer aborted 0x%x\n", 634 AHCINAME(sc), chp->ch_channel, tfd); 635 636 } 637 } else { 638 tfd = 0; 639 } 640 641 if (__predict_false(recover)) 642 ata_channel_freeze(chp); 643 644 if (slot >= 0) { 645 if ((achp->ahcic_cmds_active & __BIT(slot)) != 0 && 646 (sact & __BIT(slot)) == 0) { 647 xfer = ata_queue_hwslot_to_xfer(chp, slot); 648 xfer->c_intr(chp, xfer, tfd); 649 } 650 } else { 651 /* 652 * For NCQ, HBA halts processing when error is notified, 653 * and any further D2H FISes are ignored until the error 654 * condition is cleared. Hence if a command is inactive, 655 * it means it actually already finished successfully. 656 * Note: active slots can change as c_intr() callback 657 * can activate another command(s), so must only process 658 * commands active before we start processing. 659 */ 660 uint32_t aslots = achp->ahcic_cmds_active; 661 662 for (slot=0; slot < sc->sc_ncmds; slot++) { 663 if ((aslots & __BIT(slot)) != 0 && 664 (sact & __BIT(slot)) == 0) { 665 xfer = ata_queue_hwslot_to_xfer(chp, slot); 666 xfer->c_intr(chp, xfer, tfd); 667 } 668 } 669 } 670 671 if (__predict_false(recover)) { 672 ata_channel_thaw(chp); 673 ahci_channel_recover(sc, chp, tfd); 674 } 675 } 676 677 static void 678 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 679 { 680 struct ata_channel *chp = drvp->chnl_softc; 681 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 682 struct ata_xfer *xfer; 683 684 xfer = ata_get_xfer_ext(chp, C_RECOVERY, 0); 685 686 ata_channel_lock(chp); 687 688 AHCI_WRITE(sc, AHCI_GHC, 689 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 690 ahci_channel_stop(sc, chp, flags); 691 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp, xfer) != 0) 692 ata_reset_channel(chp, flags); 693 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 694 695 ata_channel_unlock(chp); 696 697 ata_free_xfer(chp, xfer); 698 699 return; 700 } 701 702 /* return error code from ata_bio */ 703 static int 704 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 705 { 706 struct ahci_channel *achp = (struct ahci_channel *)chp; 707 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 708 int i; 709 uint32_t is; 710 711 /* 712 * Base timeout is specified in ms. 713 * If we are allowed to sleep, wait a tick each round. 714 * Otherwise delay for 10ms on each round. 715 */ 716 if (flags & AT_WAIT) 717 timeout = MAX(1, mstohz(timeout)); 718 else 719 timeout = timeout / 10; 720 721 AHCI_CMDH_SYNC(sc, achp, slot, 722 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 723 /* start command */ 724 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 725 for (i = 0; i < timeout; i++) { 726 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) == 727 0) 728 return 0; 729 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 730 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 731 AHCI_P_IX_IFS | 732 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 733 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 734 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 735 /* 736 * we got the D2H FIS anyway, 737 * assume sig is valid. 738 * channel is restarted later 739 */ 740 return ERROR; 741 } 742 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 743 AHCINAME(sc), chp->ch_channel, is); 744 return ERR_DF; 745 } 746 ata_delay(chp, 10, "ahcifis", flags); 747 } 748 749 aprint_debug("%s channel %d: timeout sending FIS\n", 750 AHCINAME(sc), chp->ch_channel); 751 return TIMEOUT; 752 } 753 754 static int 755 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 756 uint32_t *sigp, struct ata_xfer *xfer) 757 { 758 struct ahci_channel *achp = (struct ahci_channel *)chp; 759 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 760 struct ahci_cmd_tbl *cmd_tbl; 761 struct ahci_cmd_header *cmd_h; 762 int i; 763 uint32_t sig; 764 765 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 766 ata_channel_lock_owned(chp); 767 768 again: 769 /* clear port interrupt register */ 770 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 771 /* clear SErrors and start operations */ 772 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 773 /* 774 * issue a command list override to clear BSY. 775 * This is needed if there's a PMP with no drive 776 * on port 0 777 */ 778 ahci_channel_start(sc, chp, flags, 1); 779 } else { 780 ahci_channel_start(sc, chp, flags, 0); 781 } 782 if (drive > 0) { 783 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 784 } 785 786 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 787 goto skip_reset; 788 789 /* polled command, assume interrupts are disabled */ 790 791 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 792 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 793 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 794 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 795 cmd_h->cmdh_prdbc = 0; 796 memset(cmd_tbl->cmdt_cfis, 0, 64); 797 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 798 cmd_tbl->cmdt_cfis[rhd_c] = drive; 799 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 800 switch(ahci_exec_fis(chp, 100, flags, xfer->c_slot)) { 801 case ERR_DF: 802 case TIMEOUT: 803 aprint_error("%s channel %d: setting WDCTL_RST failed " 804 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 805 if (sigp) 806 *sigp = 0xffffffff; 807 goto end; 808 default: 809 break; 810 } 811 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 812 (drive << AHCI_CMDH_F_PMP_SHIFT)); 813 cmd_h->cmdh_prdbc = 0; 814 memset(cmd_tbl->cmdt_cfis, 0, 64); 815 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 816 cmd_tbl->cmdt_cfis[rhd_c] = drive; 817 cmd_tbl->cmdt_cfis[rhd_control] = 0; 818 switch(ahci_exec_fis(chp, 310, flags, xfer->c_slot)) { 819 case ERR_DF: 820 case TIMEOUT: 821 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 822 drive == PMP_PORT_CTL) { 823 /* 824 * some controllers fails to reset when 825 * targeting a PMP but a single drive is attached. 826 * try again with port 0 827 */ 828 drive = 0; 829 ahci_channel_stop(sc, chp, flags); 830 goto again; 831 } 832 aprint_error("%s channel %d: clearing WDCTL_RST failed " 833 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 834 if (sigp) 835 *sigp = 0xffffffff; 836 goto end; 837 default: 838 break; 839 } 840 841 skip_reset: 842 /* 843 * wait 31s for BSY to clear 844 * This should not be needed, but some controllers clear the 845 * command slot before receiving the D2H FIS ... 846 */ 847 for (i = 0; i < AHCI_RST_WAIT; i++) { 848 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 849 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 850 break; 851 ata_delay(chp, 10, "ahcid2h", flags); 852 } 853 if (i == AHCI_RST_WAIT) { 854 aprint_error("%s: BSY never cleared, TD 0x%x\n", 855 AHCINAME(sc), sig); 856 if (sigp) 857 *sigp = 0xffffffff; 858 goto end; 859 } 860 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 861 DEBUG_PROBE); 862 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 863 if (sigp) 864 *sigp = sig; 865 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 866 AHCINAME(sc), chp->ch_channel, sig, 867 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 868 end: 869 ahci_channel_stop(sc, chp, flags); 870 ata_delay(chp, 500, "ahcirst", flags); 871 /* clear port interrupt register */ 872 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 873 ahci_channel_start(sc, chp, flags, 874 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 875 return 0; 876 } 877 878 static void 879 ahci_reset_channel(struct ata_channel *chp, int flags) 880 { 881 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 882 struct ahci_channel *achp = (struct ahci_channel *)chp; 883 int i, tfd; 884 885 ata_channel_lock(chp); 886 887 ahci_channel_stop(sc, chp, flags); 888 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 889 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 890 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 891 /* XXX and then ? */ 892 } 893 ata_kill_active(chp, KILL_RESET, flags); 894 ata_delay(chp, 500, "ahcirst", flags); 895 /* clear port interrupt register */ 896 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 897 /* clear SErrors and start operations */ 898 ahci_channel_start(sc, chp, flags, 899 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 900 /* wait 31s for BSY to clear */ 901 for (i = 0; i <AHCI_RST_WAIT; i++) { 902 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 903 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 904 break; 905 ata_delay(chp, 10, "ahcid2h", flags); 906 } 907 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 908 aprint_error("%s: BSY never cleared, TD 0x%x\n", 909 AHCINAME(sc), tfd); 910 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 911 DEBUG_PROBE); 912 /* clear port interrupt register */ 913 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 914 915 ata_channel_unlock(chp); 916 917 return; 918 } 919 920 static int 921 ahci_ata_addref(struct ata_drive_datas *drvp) 922 { 923 return 0; 924 } 925 926 static void 927 ahci_ata_delref(struct ata_drive_datas *drvp) 928 { 929 return; 930 } 931 932 static void 933 ahci_killpending(struct ata_drive_datas *drvp) 934 { 935 return; 936 } 937 938 static void 939 ahci_probe_drive(struct ata_channel *chp) 940 { 941 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 942 struct ahci_channel *achp = (struct ahci_channel *)chp; 943 uint32_t sig; 944 struct ata_xfer *xfer; 945 946 xfer = ata_get_xfer_ext(chp, 0, 0); 947 if (xfer == NULL) { 948 aprint_error_dev(sc->sc_atac.atac_dev, 949 "%s: failed to get xfer port %d\n", 950 __func__, chp->ch_channel); 951 return; 952 } 953 954 ata_channel_lock(chp); 955 956 /* bring interface up, accept FISs, power up and spin up device */ 957 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 958 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 959 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 960 /* reset the PHY and bring online */ 961 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 962 achp->ahcic_sstatus, AT_WAIT)) { 963 case SStatus_DET_DEV: 964 ata_delay(chp, 500, "ahcidv", AT_WAIT); 965 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 966 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig, 967 xfer); 968 } else { 969 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, xfer); 970 } 971 sata_interpret_sig(chp, 0, sig); 972 /* if we have a PMP attached, inform the controller */ 973 if (chp->ch_ndrives > PMP_PORT_CTL && 974 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 975 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 976 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 977 AHCI_P_CMD_PMA); 978 } 979 /* clear port interrupt register */ 980 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 981 982 /* and enable interrupts */ 983 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 984 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 985 AHCI_P_IX_IFS | 986 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 987 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 988 /* wait 500ms before actually starting operations */ 989 ata_delay(chp, 500, "ahciprb", AT_WAIT); 990 break; 991 992 default: 993 break; 994 } 995 ata_channel_unlock(chp); 996 } 997 998 static void 999 ahci_setup_channel(struct ata_channel *chp) 1000 { 1001 return; 1002 } 1003 1004 static int 1005 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1006 { 1007 struct ata_channel *chp = drvp->chnl_softc; 1008 struct ata_command *ata_c = &xfer->c_ata_c; 1009 int ret; 1010 int s; 1011 1012 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1013 chp->ch_channel, 1014 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1015 DEBUG_XFERS); 1016 if (ata_c->flags & AT_POLL) 1017 xfer->c_flags |= C_POLL; 1018 if (ata_c->flags & AT_WAIT) 1019 xfer->c_flags |= C_WAIT; 1020 xfer->c_drive = drvp->drive; 1021 xfer->c_databuf = ata_c->data; 1022 xfer->c_bcount = ata_c->bcount; 1023 xfer->c_start = ahci_cmd_start; 1024 xfer->c_poll = ahci_cmd_poll; 1025 xfer->c_abort = ahci_cmd_abort; 1026 xfer->c_intr = ahci_cmd_complete; 1027 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 1028 s = splbio(); 1029 ata_exec_xfer(chp, xfer); 1030 #ifdef DIAGNOSTIC 1031 if ((ata_c->flags & AT_POLL) != 0 && 1032 (ata_c->flags & AT_DONE) == 0) 1033 panic("ahci_exec_command: polled command not done"); 1034 #endif 1035 if (ata_c->flags & AT_DONE) { 1036 ret = ATACMD_COMPLETE; 1037 } else { 1038 if (ata_c->flags & AT_WAIT) { 1039 ata_channel_lock(chp); 1040 if ((ata_c->flags & AT_DONE) == 0) { 1041 ata_wait_xfer(chp, xfer); 1042 KASSERT((ata_c->flags & AT_DONE) != 0); 1043 } 1044 ata_channel_unlock(chp); 1045 ret = ATACMD_COMPLETE; 1046 } else { 1047 ret = ATACMD_QUEUED; 1048 } 1049 } 1050 splx(s); 1051 return ret; 1052 } 1053 1054 static int 1055 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1056 { 1057 struct ahci_softc *sc = AHCI_CH2SC(chp); 1058 struct ahci_channel *achp = (struct ahci_channel *)chp; 1059 struct ata_command *ata_c = &xfer->c_ata_c; 1060 int slot = xfer->c_slot; 1061 struct ahci_cmd_tbl *cmd_tbl; 1062 struct ahci_cmd_header *cmd_h; 1063 1064 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1065 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1066 ata_c->timeout, slot), 1067 DEBUG_XFERS); 1068 1069 ata_channel_lock_owned(chp); 1070 KASSERT((achp->ahcic_cmds_active & (1 << slot)) == 0); 1071 1072 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1073 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1074 cmd_tbl), DEBUG_XFERS); 1075 1076 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1077 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1078 1079 cmd_h = &achp->ahcic_cmdh[slot]; 1080 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1081 chp->ch_channel, cmd_h), DEBUG_XFERS); 1082 if (ahci_dma_setup(chp, slot, 1083 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1084 ata_c->data : NULL, 1085 ata_c->bcount, 1086 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1087 ata_c->flags |= AT_DF; 1088 return ATASTART_ABORT; 1089 } 1090 cmd_h->cmdh_flags = htole16( 1091 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1092 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1093 cmd_h->cmdh_prdbc = 0; 1094 AHCI_CMDH_SYNC(sc, achp, slot, 1095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1096 1097 if (ata_c->flags & AT_POLL) { 1098 /* polled command, disable interrupts */ 1099 AHCI_WRITE(sc, AHCI_GHC, 1100 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1101 } 1102 /* start command */ 1103 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1104 /* and says we started this command */ 1105 achp->ahcic_cmds_active |= 1 << slot; 1106 1107 if ((ata_c->flags & AT_POLL) == 0) { 1108 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 1109 ata_timeout, xfer); 1110 return ATASTART_STARTED; 1111 } else 1112 return ATASTART_POLL; 1113 } 1114 1115 static void 1116 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1117 { 1118 struct ahci_softc *sc = AHCI_CH2SC(chp); 1119 struct ahci_channel *achp = (struct ahci_channel *)chp; 1120 1121 ata_channel_lock(chp); 1122 1123 /* 1124 * Polled command. 1125 */ 1126 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1127 if (xfer->c_ata_c.flags & AT_DONE) 1128 break; 1129 ata_channel_unlock(chp); 1130 ahci_intr_port(sc, achp); 1131 ata_channel_lock(chp); 1132 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1133 } 1134 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1135 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1136 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1137 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1138 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1139 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1140 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1141 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1142 DEBUG_XFERS); 1143 1144 ata_channel_unlock(chp); 1145 1146 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1147 xfer->c_ata_c.flags |= AT_TIMEOU; 1148 xfer->c_intr(chp, xfer, 0); 1149 } 1150 /* reenable interrupts */ 1151 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1152 } 1153 1154 static void 1155 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1156 { 1157 ahci_cmd_complete(chp, xfer, 0); 1158 } 1159 1160 static void 1161 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1162 { 1163 struct ahci_channel *achp = (struct ahci_channel *)chp; 1164 struct ata_command *ata_c = &xfer->c_ata_c; 1165 bool deactivate = true; 1166 1167 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1168 DEBUG_FUNCS); 1169 1170 switch (reason) { 1171 case KILL_GONE_INACTIVE: 1172 deactivate = false; 1173 /* FALLTHROUGH */ 1174 case KILL_GONE: 1175 ata_c->flags |= AT_GONE; 1176 break; 1177 case KILL_RESET: 1178 ata_c->flags |= AT_RESET; 1179 break; 1180 case KILL_REQUEUE: 1181 panic("%s: not supposed to be requeued\n", __func__); 1182 break; 1183 default: 1184 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1185 panic("ahci_cmd_kill_xfer"); 1186 } 1187 1188 if (deactivate) { 1189 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1190 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1191 ata_deactivate_xfer(chp, xfer); 1192 } 1193 1194 ahci_cmd_done_end(chp, xfer); 1195 } 1196 1197 static int 1198 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1199 { 1200 struct ata_command *ata_c = &xfer->c_ata_c; 1201 struct ahci_channel *achp = (struct ahci_channel *)chp; 1202 1203 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1204 chp->ch_channel, 1205 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1206 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1207 DEBUG_FUNCS); 1208 1209 if (ata_waitdrain_xfer_check(chp, xfer)) 1210 return 0; 1211 1212 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1213 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1214 ata_deactivate_xfer(chp, xfer); 1215 1216 if (xfer->c_flags & C_TIMEOU) { 1217 ata_c->flags |= AT_TIMEOU; 1218 } 1219 1220 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1221 ata_c->flags |= AT_TIMEOU; 1222 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1223 ata_c->r_error = AHCI_TFD_ERR(tfd); 1224 ata_c->flags |= AT_ERROR; 1225 } 1226 1227 if (ata_c->flags & AT_READREG) 1228 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1229 1230 ahci_cmd_done(chp, xfer); 1231 return 0; 1232 } 1233 1234 static void 1235 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1236 { 1237 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1238 struct ahci_channel *achp = (struct ahci_channel *)chp; 1239 struct ata_command *ata_c = &xfer->c_ata_c; 1240 uint16_t *idwordbuf; 1241 int flags = ata_c->flags; 1242 int i; 1243 1244 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n", 1245 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1246 1247 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1248 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1249 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1250 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1251 BUS_DMASYNC_POSTWRITE); 1252 bus_dmamap_unload(sc->sc_dmat, map); 1253 } 1254 1255 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1256 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1257 1258 /* ata(4) expects IDENTIFY data to be in host endianess */ 1259 if (ata_c->r_command == WDCC_IDENTIFY || 1260 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1261 idwordbuf = xfer->c_databuf; 1262 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1263 idwordbuf[i] = le16toh(idwordbuf[i]); 1264 } 1265 } 1266 1267 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1268 ata_c->flags |= AT_XFDONE; 1269 ahci_cmd_done_end(chp, xfer); 1270 if ((flags & (AT_TIMEOU|AT_ERROR)) == 0) 1271 atastart(chp); 1272 } 1273 1274 static void 1275 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1276 { 1277 struct ata_command *ata_c = &xfer->c_ata_c; 1278 1279 ata_channel_lock(chp); 1280 1281 ata_c->flags |= AT_DONE; 1282 1283 if (ata_c->flags & AT_WAIT) 1284 ata_wake_xfer(chp, xfer); 1285 1286 ata_channel_unlock(chp); 1287 return; 1288 } 1289 1290 static int 1291 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1292 { 1293 struct ata_channel *chp = drvp->chnl_softc; 1294 struct ata_bio *ata_bio = &xfer->c_bio; 1295 1296 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1297 chp->ch_channel, 1298 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1299 DEBUG_XFERS); 1300 if (ata_bio->flags & ATA_POLL) 1301 xfer->c_flags |= C_POLL; 1302 xfer->c_drive = drvp->drive; 1303 xfer->c_databuf = ata_bio->databuf; 1304 xfer->c_bcount = ata_bio->bcount; 1305 xfer->c_start = ahci_bio_start; 1306 xfer->c_poll = ahci_bio_poll; 1307 xfer->c_abort = ahci_bio_abort; 1308 xfer->c_intr = ahci_bio_complete; 1309 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1310 ata_exec_xfer(chp, xfer); 1311 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1312 } 1313 1314 static int 1315 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1316 { 1317 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1318 struct ahci_channel *achp = (struct ahci_channel *)chp; 1319 struct ata_bio *ata_bio = &xfer->c_bio; 1320 struct ahci_cmd_tbl *cmd_tbl; 1321 struct ahci_cmd_header *cmd_h; 1322 1323 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1324 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1325 1326 ata_channel_lock_owned(chp); 1327 1328 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1329 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1330 cmd_tbl), DEBUG_XFERS); 1331 1332 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1333 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1334 1335 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1336 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1337 chp->ch_channel, cmd_h), DEBUG_XFERS); 1338 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1339 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1340 ata_bio->error = ERR_DMA; 1341 ata_bio->r_error = 0; 1342 return ATASTART_ABORT; 1343 } 1344 cmd_h->cmdh_flags = htole16( 1345 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1346 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1347 cmd_h->cmdh_prdbc = 0; 1348 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1349 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1350 1351 if (xfer->c_flags & C_POLL) { 1352 /* polled command, disable interrupts */ 1353 AHCI_WRITE(sc, AHCI_GHC, 1354 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1355 } 1356 if (xfer->c_flags & C_NCQ) 1357 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1 << xfer->c_slot); 1358 /* start command */ 1359 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << xfer->c_slot); 1360 /* and says we started this command */ 1361 achp->ahcic_cmds_active |= 1 << xfer->c_slot; 1362 1363 if ((xfer->c_flags & C_POLL) == 0) { 1364 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1365 ata_timeout, xfer); 1366 return ATASTART_STARTED; 1367 } else 1368 return ATASTART_POLL; 1369 } 1370 1371 static void 1372 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1373 { 1374 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1375 struct ahci_channel *achp = (struct ahci_channel *)chp; 1376 1377 /* 1378 * Polled command. 1379 */ 1380 for (int i = 0; i < ATA_DELAY * 10; i++) { 1381 if (xfer->c_bio.flags & ATA_ITSDONE) 1382 break; 1383 ahci_intr_port(sc, achp); 1384 delay(100); 1385 } 1386 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1387 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1388 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1389 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1390 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1391 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1392 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1393 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1394 DEBUG_XFERS); 1395 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1396 xfer->c_bio.error = TIMEOUT; 1397 xfer->c_intr(chp, xfer, 0); 1398 } 1399 /* reenable interrupts */ 1400 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1401 } 1402 1403 static void 1404 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1405 { 1406 ahci_bio_complete(chp, xfer, 0); 1407 } 1408 1409 static void 1410 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1411 { 1412 int drive = xfer->c_drive; 1413 struct ata_bio *ata_bio = &xfer->c_bio; 1414 struct ahci_channel *achp = (struct ahci_channel *)chp; 1415 bool deactivate = true; 1416 1417 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1418 DEBUG_FUNCS); 1419 1420 ata_bio->flags |= ATA_ITSDONE; 1421 switch (reason) { 1422 case KILL_GONE_INACTIVE: 1423 deactivate = false; 1424 /* FALLTHROUGH */ 1425 case KILL_GONE: 1426 ata_bio->error = ERR_NODEV; 1427 break; 1428 case KILL_RESET: 1429 ata_bio->error = ERR_RESET; 1430 break; 1431 case KILL_REQUEUE: 1432 ata_bio->error = REQUEUE; 1433 break; 1434 default: 1435 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1436 panic("ahci_bio_kill_xfer"); 1437 } 1438 ata_bio->r_error = WDCE_ABRT; 1439 1440 if (deactivate) { 1441 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1442 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1443 ata_deactivate_xfer(chp, xfer); 1444 } 1445 1446 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1447 } 1448 1449 static int 1450 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1451 { 1452 struct ata_bio *ata_bio = &xfer->c_bio; 1453 int drive = xfer->c_drive; 1454 struct ahci_channel *achp = (struct ahci_channel *)chp; 1455 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1456 1457 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1458 DEBUG_FUNCS); 1459 1460 if (ata_waitdrain_xfer_check(chp, xfer)) 1461 return 0; 1462 1463 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 1464 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 1465 ata_deactivate_xfer(chp, xfer); 1466 1467 if (xfer->c_flags & C_TIMEOU) { 1468 ata_bio->error = TIMEOUT; 1469 } 1470 1471 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1472 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1473 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1474 BUS_DMASYNC_POSTWRITE); 1475 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1476 1477 ata_bio->flags |= ATA_ITSDONE; 1478 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1479 ata_bio->error = ERR_DF; 1480 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1481 ata_bio->error = ERROR; 1482 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1483 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1484 ata_bio->flags |= ATA_CORR; 1485 1486 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1488 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1489 ata_bio->bcount), DEBUG_XFERS); 1490 /* 1491 * If it was a write, complete data buffer may have been transfered 1492 * before error detection; in this case don't use cmdh_prdbc 1493 * as it won't reflect what was written to media. Assume nothing 1494 * was transfered and leave bcount as-is. 1495 * For queued commands, PRD Byte Count should not be used, and is 1496 * not required to be valid; in that case underflow is always illegal. 1497 */ 1498 if ((xfer->c_flags & C_NCQ) != 0) { 1499 if (ata_bio->error == NOERROR) 1500 ata_bio->bcount = 0; 1501 } else { 1502 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1503 ata_bio->bcount -= 1504 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1505 } 1506 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1507 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1508 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1509 atastart(chp); 1510 return 0; 1511 } 1512 1513 static void 1514 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1515 { 1516 int i; 1517 /* stop channel */ 1518 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1519 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1520 /* wait 1s for channel to stop */ 1521 for (i = 0; i <100; i++) { 1522 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1523 == 0) 1524 break; 1525 ata_delay(chp, 10, "ahcistop", flags); 1526 } 1527 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1528 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1529 /* XXX controller reset ? */ 1530 return; 1531 } 1532 1533 if (sc->sc_channel_stop) 1534 sc->sc_channel_stop(sc, chp); 1535 } 1536 1537 static void 1538 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1539 int flags, int clo) 1540 { 1541 int i; 1542 uint32_t p_cmd; 1543 /* clear error */ 1544 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1545 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1546 1547 if (clo) { 1548 /* issue command list override */ 1549 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1550 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1551 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1552 /* wait 1s for AHCI_CAP_CLO to clear */ 1553 for (i = 0; i <100; i++) { 1554 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1555 AHCI_P_CMD_CLO) == 0) 1556 break; 1557 ata_delay(chp, 10, "ahciclo", flags); 1558 } 1559 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1560 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1561 /* XXX controller reset ? */ 1562 return; 1563 } 1564 } 1565 1566 if (sc->sc_channel_start) 1567 sc->sc_channel_start(sc, chp); 1568 1569 /* and start controller */ 1570 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1571 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1572 if (chp->ch_ndrives > PMP_PORT_CTL && 1573 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1574 p_cmd |= AHCI_P_CMD_PMA; 1575 } 1576 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1577 } 1578 1579 static void 1580 ahci_hold(struct ahci_channel *achp) 1581 { 1582 achp->ahcic_cmds_hold |= achp->ahcic_cmds_active; 1583 achp->ahcic_cmds_active = 0; 1584 } 1585 1586 static void 1587 ahci_unhold(struct ahci_channel *achp) 1588 { 1589 achp->ahcic_cmds_active = achp->ahcic_cmds_hold; 1590 achp->ahcic_cmds_hold = 0; 1591 } 1592 1593 /* Recover channel after command failure */ 1594 void 1595 ahci_channel_recover(struct ahci_softc *sc, struct ata_channel *chp, int tfd) 1596 { 1597 struct ahci_channel *achp = (struct ahci_channel *)chp; 1598 struct ata_drive_datas *drvp; 1599 uint8_t slot, eslot, st, err; 1600 int drive = -1, error; 1601 struct ata_xfer *xfer; 1602 bool reset = false; 1603 1604 KASSERT(!achp->ahcic_recovering); 1605 1606 achp->ahcic_recovering = true; 1607 1608 /* 1609 * Read FBS to get the drive which caused the error, if PM is in use. 1610 * According to AHCI 1.3 spec, this register is available regardless 1611 * if FIS-based switching (FBSS) feature is supported, or disabled. 1612 * If FIS-based switching is not in use, it merely maintains single 1613 * pair of DRQ/BSY state, but it is enough since in that case we 1614 * never issue commands for more than one device at the time anyway. 1615 * XXX untested 1616 */ 1617 if (chp->ch_ndrives > PMP_PORT_CTL) { 1618 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1619 if (fbs & AHCI_P_FBS_SDE) { 1620 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1621 1622 /* 1623 * Tell HBA to reset PM port X (value in DWE) state, 1624 * and resume processing commands for other ports. 1625 */ 1626 fbs |= AHCI_P_FBS_DEC; 1627 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1628 for (int i = 0; i < 1000; i++) { 1629 fbs = AHCI_READ(sc, 1630 AHCI_P_FBS(chp->ch_channel)); 1631 if ((fbs & AHCI_P_FBS_DEC) == 0) 1632 break; 1633 DELAY(1000); 1634 } 1635 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1636 /* follow non-device specific recovery */ 1637 drive = -1; 1638 reset = true; 1639 } 1640 } else { 1641 /* not device specific, reset channel */ 1642 drive = -1; 1643 reset = true; 1644 } 1645 } else 1646 drive = 0; 1647 1648 drvp = &chp->ch_drive[drive]; 1649 1650 /* 1651 * If BSY or DRQ bits are set, must execute COMRESET to return 1652 * device to idle state. If drive is idle, it's enough to just 1653 * reset CMD.ST, it's not necessary to do software reset. 1654 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1655 * to unblock device processing if COMRESET was not done. 1656 */ 1657 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 1658 goto reset; 1659 1660 KASSERT(drive >= 0); 1661 ahci_channel_stop(sc, chp, AT_POLL); 1662 ahci_channel_start(sc, chp, AT_POLL, 1663 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1664 1665 ahci_hold(achp); 1666 1667 /* 1668 * When running NCQ commands, READ LOG EXT is necessary to clear the 1669 * error condition and unblock the device. 1670 */ 1671 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 1672 1673 ahci_unhold(achp); 1674 1675 switch (error) { 1676 case 0: 1677 /* Error out the particular NCQ xfer, then requeue the others */ 1678 if ((achp->ahcic_cmds_active & (1 << eslot)) != 0) { 1679 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 1680 xfer->c_flags |= C_RECOVERED; 1681 xfer->c_intr(chp, xfer, 1682 (err << AHCI_P_TFD_ERR_SHIFT) | st); 1683 } 1684 break; 1685 1686 case EOPNOTSUPP: 1687 /* 1688 * Non-NCQ command error, just find the slot and end with 1689 * the error. 1690 */ 1691 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1692 if ((achp->ahcic_cmds_active & (1 << slot)) != 0) { 1693 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1694 xfer->c_intr(chp, xfer, tfd); 1695 } 1696 } 1697 break; 1698 1699 case EAGAIN: 1700 /* 1701 * Failed to get resources to run the recovery command, must 1702 * reset the drive. This will also kill all still outstanding 1703 * transfers. 1704 */ 1705 reset: 1706 ahci_reset_channel(chp, AT_POLL); 1707 goto out; 1708 /* NOTREACHED */ 1709 1710 default: 1711 /* 1712 * The command to get the slot failed. Kill outstanding 1713 * commands for the same drive only. No need to reset 1714 * the drive, it's unblocked nevertheless. 1715 */ 1716 break; 1717 } 1718 1719 /* Requeue all unfinished commands for same drive as failed command */ 1720 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1721 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 1722 continue; 1723 1724 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1725 if (drive != xfer->c_drive) 1726 continue; 1727 1728 xfer->c_kill_xfer(chp, xfer, 1729 (error == 0) ? KILL_REQUEUE : KILL_RESET); 1730 } 1731 1732 out: 1733 /* Drive unblocked, back to normal operation */ 1734 achp->ahcic_recovering = false; 1735 atastart(chp); 1736 } 1737 1738 static int 1739 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1740 size_t count, int op) 1741 { 1742 int error, seg; 1743 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1744 struct ahci_channel *achp = (struct ahci_channel *)chp; 1745 struct ahci_cmd_tbl *cmd_tbl; 1746 struct ahci_cmd_header *cmd_h; 1747 1748 cmd_h = &achp->ahcic_cmdh[slot]; 1749 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1750 1751 if (data == NULL) { 1752 cmd_h->cmdh_prdtl = 0; 1753 goto end; 1754 } 1755 1756 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1757 data, count, NULL, 1758 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1759 if (error) { 1760 printf("%s port %d: failed to load xfer: %d\n", 1761 AHCINAME(sc), chp->ch_channel, error); 1762 return error; 1763 } 1764 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1765 achp->ahcic_datad[slot]->dm_mapsize, 1766 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1767 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1768 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1769 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1770 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1771 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1772 } 1773 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1774 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1775 end: 1776 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1777 return 0; 1778 } 1779 1780 #if NATAPIBUS > 0 1781 static void 1782 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1783 { 1784 struct ata_channel *chp = ata_sc->sc_chan; 1785 struct atac_softc *atac = chp->ch_atac; 1786 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1787 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1788 /* 1789 * Fill in the scsipi_adapter. 1790 */ 1791 adapt->adapt_dev = atac->atac_dev; 1792 adapt->adapt_nchannels = atac->atac_nchannels; 1793 adapt->adapt_request = ahci_atapi_scsipi_request; 1794 adapt->adapt_minphys = ahci_atapi_minphys; 1795 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1796 1797 /* 1798 * Fill in the scsipi_channel. 1799 */ 1800 memset(chan, 0, sizeof(*chan)); 1801 chan->chan_adapter = adapt; 1802 chan->chan_bustype = &ahci_atapi_bustype; 1803 chan->chan_channel = chp->ch_channel; 1804 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1805 chan->chan_openings = 1; 1806 chan->chan_max_periph = 1; 1807 chan->chan_ntargets = 1; 1808 chan->chan_nluns = 1; 1809 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1810 atapiprint); 1811 } 1812 1813 static void 1814 ahci_atapi_minphys(struct buf *bp) 1815 { 1816 if (bp->b_bcount > MAXPHYS) 1817 bp->b_bcount = MAXPHYS; 1818 minphys(bp); 1819 } 1820 1821 /* 1822 * Kill off all pending xfers for a periph. 1823 * 1824 * Must be called at splbio(). 1825 */ 1826 static void 1827 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1828 { 1829 struct atac_softc *atac = 1830 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1831 struct ata_channel *chp = 1832 atac->atac_channels[periph->periph_channel->chan_channel]; 1833 1834 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1835 } 1836 1837 static void 1838 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1839 scsipi_adapter_req_t req, void *arg) 1840 { 1841 struct scsipi_adapter *adapt = chan->chan_adapter; 1842 struct scsipi_periph *periph; 1843 struct scsipi_xfer *sc_xfer; 1844 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1845 struct atac_softc *atac = &sc->sc_atac; 1846 struct ata_xfer *xfer; 1847 int channel = chan->chan_channel; 1848 int drive, s; 1849 1850 switch (req) { 1851 case ADAPTER_REQ_RUN_XFER: 1852 sc_xfer = arg; 1853 periph = sc_xfer->xs_periph; 1854 drive = periph->periph_target; 1855 if (!device_is_active(atac->atac_dev)) { 1856 sc_xfer->error = XS_DRIVER_STUFFUP; 1857 scsipi_done(sc_xfer); 1858 return; 1859 } 1860 xfer = ata_get_xfer_ext(atac->atac_channels[channel], 0, 0); 1861 if (xfer == NULL) { 1862 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1863 scsipi_done(sc_xfer); 1864 return; 1865 } 1866 1867 if (sc_xfer->xs_control & XS_CTL_POLL) 1868 xfer->c_flags |= C_POLL; 1869 xfer->c_drive = drive; 1870 xfer->c_flags |= C_ATAPI; 1871 xfer->c_scsipi = sc_xfer; 1872 xfer->c_databuf = sc_xfer->data; 1873 xfer->c_bcount = sc_xfer->datalen; 1874 xfer->c_start = ahci_atapi_start; 1875 xfer->c_poll = ahci_atapi_poll; 1876 xfer->c_abort = ahci_atapi_abort; 1877 xfer->c_intr = ahci_atapi_complete; 1878 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1879 xfer->c_dscpoll = 0; 1880 s = splbio(); 1881 ata_exec_xfer(atac->atac_channels[channel], xfer); 1882 #ifdef DIAGNOSTIC 1883 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1884 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1885 panic("ahci_atapi_scsipi_request: polled command " 1886 "not done"); 1887 #endif 1888 splx(s); 1889 return; 1890 default: 1891 /* Not supported, nothing to do. */ 1892 ; 1893 } 1894 } 1895 1896 static int 1897 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1898 { 1899 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1900 struct ahci_channel *achp = (struct ahci_channel *)chp; 1901 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1902 struct ahci_cmd_tbl *cmd_tbl; 1903 struct ahci_cmd_header *cmd_h; 1904 1905 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1906 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1907 1908 ata_channel_lock_owned(chp); 1909 1910 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1911 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1912 cmd_tbl), DEBUG_XFERS); 1913 1914 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1915 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1916 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1917 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1918 1919 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1920 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1921 chp->ch_channel, cmd_h), DEBUG_XFERS); 1922 if (ahci_dma_setup(chp, xfer->c_slot, 1923 sc_xfer->datalen ? sc_xfer->data : NULL, 1924 sc_xfer->datalen, 1925 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1926 BUS_DMA_READ : BUS_DMA_WRITE)) { 1927 sc_xfer->error = XS_DRIVER_STUFFUP; 1928 return ATASTART_ABORT; 1929 } 1930 cmd_h->cmdh_flags = htole16( 1931 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1932 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1933 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1934 cmd_h->cmdh_prdbc = 0; 1935 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1936 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1937 1938 if (xfer->c_flags & C_POLL) { 1939 /* polled command, disable interrupts */ 1940 AHCI_WRITE(sc, AHCI_GHC, 1941 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1942 } 1943 /* start command */ 1944 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << xfer->c_slot); 1945 /* and says we started this command */ 1946 achp->ahcic_cmds_active |= 1 << xfer->c_slot; 1947 1948 if ((xfer->c_flags & C_POLL) == 0) { 1949 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1950 ata_timeout, xfer); 1951 return ATASTART_STARTED; 1952 } else 1953 return ATASTART_POLL; 1954 } 1955 1956 static void 1957 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1958 { 1959 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1960 struct ahci_channel *achp = (struct ahci_channel *)chp; 1961 1962 /* 1963 * Polled command. 1964 */ 1965 for (int i = 0; i < ATA_DELAY / 10; i++) { 1966 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1967 break; 1968 ahci_intr_port(sc, achp); 1969 delay(10000); 1970 } 1971 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1972 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1973 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1974 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1975 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1976 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1977 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1978 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1979 DEBUG_XFERS); 1980 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1981 xfer->c_scsipi->error = XS_TIMEOUT; 1982 xfer->c_intr(chp, xfer, 0); 1983 } 1984 /* reenable interrupts */ 1985 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1986 } 1987 1988 static void 1989 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1990 { 1991 ahci_atapi_complete(chp, xfer, 0); 1992 } 1993 1994 static int 1995 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1996 { 1997 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1998 struct ahci_channel *achp = (struct ahci_channel *)chp; 1999 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 2000 2001 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 2002 DEBUG_FUNCS); 2003 2004 if (ata_waitdrain_xfer_check(chp, xfer)) 2005 return 0; 2006 2007 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 2008 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 2009 ata_deactivate_xfer(chp, xfer); 2010 2011 if (xfer->c_flags & C_TIMEOU) { 2012 sc_xfer->error = XS_TIMEOUT; 2013 } 2014 2015 if (xfer->c_bcount > 0) { 2016 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2017 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2018 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2019 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2020 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2021 } 2022 2023 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2024 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2025 sc_xfer->resid = sc_xfer->datalen; 2026 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2027 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2028 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2029 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2030 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2031 sc_xfer->resid == sc_xfer->datalen)) { 2032 sc_xfer->error = XS_SHORTSENSE; 2033 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2034 if ((sc_xfer->xs_periph->periph_quirks & 2035 PQUIRK_NOSENSE) == 0) { 2036 /* ask scsipi to send a REQUEST_SENSE */ 2037 sc_xfer->error = XS_BUSY; 2038 sc_xfer->status = SCSI_CHECK; 2039 } 2040 } 2041 ata_free_xfer(chp, xfer); 2042 scsipi_done(sc_xfer); 2043 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2044 atastart(chp); 2045 return 0; 2046 } 2047 2048 static void 2049 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2050 { 2051 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2052 struct ahci_channel *achp = (struct ahci_channel *)chp; 2053 bool deactivate = true; 2054 2055 /* remove this command from xfer queue */ 2056 switch (reason) { 2057 case KILL_GONE_INACTIVE: 2058 deactivate = false; 2059 /* FALLTHROUGH */ 2060 case KILL_GONE: 2061 sc_xfer->error = XS_DRIVER_STUFFUP; 2062 break; 2063 case KILL_RESET: 2064 sc_xfer->error = XS_RESET; 2065 break; 2066 case KILL_REQUEUE: 2067 sc_xfer->error = XS_REQUEUE; 2068 break; 2069 default: 2070 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2071 panic("ahci_ata_atapi_kill_xfer"); 2072 } 2073 2074 if (deactivate) { 2075 KASSERT((achp->ahcic_cmds_active & (1 << xfer->c_slot)) != 0); 2076 achp->ahcic_cmds_active &= ~(1 << xfer->c_slot); 2077 ata_deactivate_xfer(chp, xfer); 2078 } 2079 2080 ata_free_xfer(chp, xfer); 2081 scsipi_done(sc_xfer); 2082 } 2083 2084 static void 2085 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2086 { 2087 struct scsipi_channel *chan = sc->sc_channel; 2088 struct scsipi_periph *periph; 2089 struct ataparams ids; 2090 struct ataparams *id = &ids; 2091 struct ahci_softc *ahcic = 2092 device_private(chan->chan_adapter->adapt_dev); 2093 struct atac_softc *atac = &ahcic->sc_atac; 2094 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2095 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2096 struct scsipibus_attach_args sa; 2097 char serial_number[21], model[41], firmware_revision[9]; 2098 int s; 2099 2100 /* skip if already attached */ 2101 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2102 return; 2103 2104 /* if no ATAPI device detected at attach time, skip */ 2105 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2106 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2107 "not present\n", target), DEBUG_PROBE); 2108 return; 2109 } 2110 2111 /* Some ATAPI devices need a bit more time after software reset. */ 2112 delay(5000); 2113 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2114 #ifdef ATAPI_DEBUG_PROBE 2115 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2116 AHCINAME(ahcic), target, 2117 id->atap_config & ATAPI_CFG_CMD_MASK, 2118 id->atap_config & ATAPI_CFG_DRQ_MASK); 2119 #endif 2120 periph = scsipi_alloc_periph(M_NOWAIT); 2121 if (periph == NULL) { 2122 aprint_error_dev(sc->sc_dev, 2123 "unable to allocate periph for drive %d\n", 2124 target); 2125 return; 2126 } 2127 periph->periph_dev = NULL; 2128 periph->periph_channel = chan; 2129 periph->periph_switch = &atapi_probe_periphsw; 2130 periph->periph_target = target; 2131 periph->periph_lun = 0; 2132 periph->periph_quirks = PQUIRK_ONLYBIG; 2133 2134 #ifdef SCSIPI_DEBUG 2135 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2136 SCSIPI_DEBUG_TARGET == target) 2137 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2138 #endif 2139 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2140 if (id->atap_config & ATAPI_CFG_REMOV) 2141 periph->periph_flags |= PERIPH_REMOVABLE; 2142 if (periph->periph_type == T_SEQUENTIAL) { 2143 s = splbio(); 2144 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2145 splx(s); 2146 } 2147 2148 sa.sa_periph = periph; 2149 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2150 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2151 T_REMOV : T_FIXED; 2152 strnvisx(model, sizeof(model), id->atap_model, 40, 2153 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2154 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2155 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2156 strnvisx(firmware_revision, sizeof(firmware_revision), 2157 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2158 sa.sa_inqbuf.vendor = model; 2159 sa.sa_inqbuf.product = serial_number; 2160 sa.sa_inqbuf.revision = firmware_revision; 2161 2162 /* 2163 * Determine the operating mode capabilities of the device. 2164 */ 2165 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2166 periph->periph_cap |= PERIPH_CAP_CMD16; 2167 /* XXX This is gross. */ 2168 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2169 2170 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2171 2172 if (drvp->drv_softc) 2173 ata_probe_caps(drvp); 2174 else { 2175 s = splbio(); 2176 drvp->drive_type = ATA_DRIVET_NONE; 2177 splx(s); 2178 } 2179 } else { 2180 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2181 "failed for drive %s:%d:%d\n", 2182 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2183 s = splbio(); 2184 drvp->drive_type = ATA_DRIVET_NONE; 2185 splx(s); 2186 } 2187 } 2188 #endif /* NATAPIBUS */ 2189
Indexes created Mon Sep 29 21:09:56 GMT 2025