ahcisata_core.c revision 1.60.2.5
1 /* $NetBSD: ahcisata_core.c,v 1.60.2.5 2019/01/18 08:50:26 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.60.2.5 2019/01/18 08:50:26 pgoyette Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 280 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 281 ahci_rev = AHCI_READ(sc, AHCI_VS); 282 snprintb(buf, sizeof(buf), "\177\020" 283 /* "f\000\005NP\0" */ 284 "b\005SXS\0" 285 "b\006EMS\0" 286 "b\007CCCS\0" 287 /* "f\010\005NCS\0" */ 288 "b\015PSC\0" 289 "b\016SSC\0" 290 "b\017PMD\0" 291 "b\020FBSS\0" 292 "b\021SPM\0" 293 "b\022SAM\0" 294 "b\023SNZO\0" 295 "f\024\003ISS\0" 296 "=\001Gen1\0" 297 "=\002Gen2\0" 298 "=\003Gen3\0" 299 "b\030SCLO\0" 300 "b\031SAL\0" 301 "b\032SALP\0" 302 "b\033SSS\0" 303 "b\034SMPS\0" 304 "b\035SSNTF\0" 305 "b\036SNCQ\0" 306 "b\037S64A\0" 307 "\0", sc->sc_ahci_cap); 308 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 309 ", %d port%s, %d slot%s, CAP %s\n", 310 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 311 sc->sc_atac.atac_nchannels, 312 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 313 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 314 315 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 316 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 317 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 318 sc->sc_atac.atac_pio_cap = 4; 319 sc->sc_atac.atac_dma_cap = 2; 320 sc->sc_atac.atac_udma_cap = 6; 321 sc->sc_atac.atac_channels = sc->sc_chanarray; 322 sc->sc_atac.atac_probe = ahci_probe_drive; 323 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 324 sc->sc_atac.atac_set_modes = ahci_setup_channel; 325 #if NATAPIBUS > 0 326 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 327 #endif 328 329 dmasize = 330 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 331 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 332 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 333 if (error) { 334 aprint_error("%s: unable to allocate command header memory" 335 ", error=%d\n", AHCINAME(sc), error); 336 return; 337 } 338 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 339 sc->sc_cmd_hdr_nseg, dmasize, 340 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 341 if (error) { 342 aprint_error("%s: unable to map command header memory" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 347 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 348 if (error) { 349 aprint_error("%s: unable to create command header map" 350 ", error=%d\n", AHCINAME(sc), error); 351 return; 352 } 353 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 354 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 355 if (error) { 356 aprint_error("%s: unable to load command header map" 357 ", error=%d\n", AHCINAME(sc), error); 358 return; 359 } 360 sc->sc_cmd_hdr = cmdhp; 361 362 ahci_enable_intrs(sc); 363 364 if (sc->sc_ahci_ports == 0) { 365 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 366 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 367 DEBUG_PROBE); 368 } 369 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 370 if ((sc->sc_ahci_ports & (1U << i)) == 0) 371 continue; 372 if (port >= sc->sc_atac.atac_nchannels) { 373 aprint_error("%s: more ports than announced\n", 374 AHCINAME(sc)); 375 break; 376 } 377 378 /* Optional intr establish per active port */ 379 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 380 aprint_error("%s: intr establish hook failed\n", 381 AHCINAME(sc)); 382 break; 383 } 384 385 achp = &sc->sc_channels[i]; 386 chp = &achp->ata_channel; 387 sc->sc_chanarray[i] = chp; 388 chp->ch_channel = i; 389 chp->ch_atac = &sc->sc_atac; 390 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 391 if (chp->ch_queue == NULL) { 392 aprint_error("%s port %d: can't allocate memory for " 393 "command queue", AHCINAME(sc), i); 394 break; 395 } 396 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 397 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 398 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 399 BUS_DMA_NOWAIT); 400 if (error) { 401 aprint_error("%s: unable to allocate command table " 402 "memory, error=%d\n", AHCINAME(sc), error); 403 break; 404 } 405 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 406 achp->ahcic_cmd_tbl_nseg, dmasize, 407 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 408 if (error) { 409 aprint_error("%s: unable to map command table memory" 410 ", error=%d\n", AHCINAME(sc), error); 411 break; 412 } 413 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 414 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 415 if (error) { 416 aprint_error("%s: unable to create command table map" 417 ", error=%d\n", AHCINAME(sc), error); 418 break; 419 } 420 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 421 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 422 if (error) { 423 aprint_error("%s: unable to load command table map" 424 ", error=%d\n", AHCINAME(sc), error); 425 break; 426 } 427 achp->ahcic_cmdh = (struct ahci_cmd_header *) 428 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 429 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 430 AHCI_CMDH_SIZE * port; 431 achp->ahcic_rfis = (struct ahci_r_fis *) 432 ((char *)cmdhp + 433 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 434 AHCI_RFIS_SIZE * port); 435 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 436 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 437 AHCI_RFIS_SIZE * port; 438 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 439 "rfis %p (0x%" PRIx64 ")\n", i, 440 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 441 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 442 DEBUG_PROBE); 443 444 for (j = 0; j < sc->sc_ncmds; j++) { 445 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 446 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 447 achp->ahcic_bus_cmd_tbl[j] = 448 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 449 AHCI_CMDTBL_SIZE * j; 450 achp->ahcic_cmdh[j].cmdh_cmdtba = 451 htole64(achp->ahcic_bus_cmd_tbl[j]); 452 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 453 achp->ahcic_cmd_tbl[j], 454 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 455 /* The xfer DMA map */ 456 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 457 AHCI_NPRD, 0x400000 /* 4MB */, 0, 458 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 459 &achp->ahcic_datad[j]); 460 if (error) { 461 aprint_error("%s: couldn't alloc xfer DMA map, " 462 "error=%d\n", AHCINAME(sc), error); 463 goto end; 464 } 465 } 466 ahci_setup_port(sc, i); 467 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 468 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 469 aprint_error("%s: couldn't map port %d " 470 "sata_status regs\n", AHCINAME(sc), i); 471 break; 472 } 473 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 474 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 475 aprint_error("%s: couldn't map port %d " 476 "sata_control regs\n", AHCINAME(sc), i); 477 break; 478 } 479 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 480 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 481 aprint_error("%s: couldn't map port %d " 482 "sata_error regs\n", AHCINAME(sc), i); 483 break; 484 } 485 ata_channel_attach(chp); 486 port++; 487 end: 488 continue; 489 } 490 } 491 492 void 493 ahci_childdetached(struct ahci_softc *sc, device_t child) 494 { 495 struct ahci_channel *achp; 496 struct ata_channel *chp; 497 498 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 499 achp = &sc->sc_channels[i]; 500 chp = &achp->ata_channel; 501 502 if ((sc->sc_ahci_ports & (1U << i)) == 0) 503 continue; 504 505 if (child == chp->atabus) 506 chp->atabus = NULL; 507 } 508 } 509 510 int 511 ahci_detach(struct ahci_softc *sc, int flags) 512 { 513 struct atac_softc *atac; 514 struct ahci_channel *achp; 515 struct ata_channel *chp; 516 struct scsipi_adapter *adapt; 517 int i, j, port; 518 int error; 519 520 atac = &sc->sc_atac; 521 adapt = &atac->atac_atapi_adapter._generic; 522 523 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 524 achp = &sc->sc_channels[i]; 525 chp = &achp->ata_channel; 526 527 if ((sc->sc_ahci_ports & (1U << i)) == 0) 528 continue; 529 if (port >= sc->sc_atac.atac_nchannels) { 530 aprint_error("%s: more ports than announced\n", 531 AHCINAME(sc)); 532 break; 533 } 534 535 if (chp->atabus != NULL) { 536 if ((error = config_detach(chp->atabus, flags)) != 0) 537 return error; 538 539 KASSERT(chp->atabus == NULL); 540 } 541 542 if (chp->ch_flags & ATACH_DETACHED) 543 continue; 544 545 for (j = 0; j < sc->sc_ncmds; j++) 546 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 547 548 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 549 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 550 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 551 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 552 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 553 achp->ahcic_cmd_tbl_nseg); 554 555 ata_channel_detach(chp); 556 port++; 557 } 558 559 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 560 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 561 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 562 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 563 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 564 565 if (adapt->adapt_refcnt != 0) 566 return EBUSY; 567 568 return 0; 569 } 570 571 void 572 ahci_resume(struct ahci_softc *sc) 573 { 574 ahci_reset(sc); 575 ahci_setup_ports(sc); 576 ahci_reprobe_drives(sc); 577 ahci_enable_intrs(sc); 578 } 579 580 int 581 ahci_intr(void *v) 582 { 583 struct ahci_softc *sc = v; 584 uint32_t is; 585 int i, r = 0; 586 587 while ((is = AHCI_READ(sc, AHCI_IS))) { 588 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 589 DEBUG_INTR); 590 r = 1; 591 AHCI_WRITE(sc, AHCI_IS, is); 592 for (i = 0; i < AHCI_MAX_PORTS; i++) 593 if (is & (1U << i)) 594 ahci_intr_port(&sc->sc_channels[i]); 595 } 596 597 return r; 598 } 599 600 int 601 ahci_intr_port(void *v) 602 { 603 struct ahci_channel *achp = v; 604 struct ata_channel *chp = &achp->ata_channel; 605 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 606 uint32_t is, tfd, sact; 607 struct ata_xfer *xfer; 608 int slot = -1; 609 bool recover = false; 610 uint32_t aslots; 611 612 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 613 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 614 615 AHCIDEBUG_PRINT(( 616 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 617 AHCINAME(sc), 618 chp->ch_channel, is, 619 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 620 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 621 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 622 DEBUG_INTR); 623 624 if ((chp->ch_flags & ATACH_NCQ) == 0) { 625 /* Non-NCQ operation */ 626 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 627 } else { 628 /* NCQ operation */ 629 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 630 } 631 632 /* Handle errors */ 633 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 634 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 635 /* Fatal errors */ 636 if (is & AHCI_P_IX_TFES) { 637 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 638 639 if ((chp->ch_flags & ATACH_NCQ) == 0) { 640 /* Slot valid only for Non-NCQ operation */ 641 slot = (AHCI_READ(sc, 642 AHCI_P_CMD(chp->ch_channel)) 643 & AHCI_P_CMD_CCS_MASK) 644 >> AHCI_P_CMD_CCS_SHIFT; 645 } 646 647 AHCIDEBUG_PRINT(( 648 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 649 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 650 DEBUG_INTR); 651 } else { 652 /* mark an error, and set BSY */ 653 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 654 WDCS_ERR | WDCS_BSY; 655 } 656 657 if (is & AHCI_P_IX_IFS) { 658 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 659 AHCINAME(sc), chp->ch_channel, 660 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 661 DEBUG_INTR); 662 } 663 664 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 665 recover = true; 666 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 667 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 668 669 /* D2H Register FIS or Set Device Bits */ 670 if ((tfd & WDCS_ERR) != 0) { 671 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 672 recover = true; 673 674 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 675 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 676 677 } 678 } else { 679 tfd = 0; 680 } 681 682 if (__predict_false(recover)) 683 ata_channel_freeze(chp); 684 685 aslots = ata_queue_active(chp); 686 687 if (slot >= 0) { 688 if ((aslots & __BIT(slot)) != 0 && 689 (sact & __BIT(slot)) == 0) { 690 xfer = ata_queue_hwslot_to_xfer(chp, slot); 691 xfer->ops->c_intr(chp, xfer, tfd); 692 } 693 } else { 694 /* 695 * For NCQ, HBA halts processing when error is notified, 696 * and any further D2H FISes are ignored until the error 697 * condition is cleared. Hence if a command is inactive, 698 * it means it actually already finished successfully. 699 * Note: active slots can change as c_intr() callback 700 * can activate another command(s), so must only process 701 * commands active before we start processing. 702 */ 703 704 for (slot=0; slot < sc->sc_ncmds; slot++) { 705 if ((aslots & __BIT(slot)) != 0 && 706 (sact & __BIT(slot)) == 0) { 707 xfer = ata_queue_hwslot_to_xfer(chp, slot); 708 xfer->ops->c_intr(chp, xfer, tfd); 709 } 710 } 711 } 712 713 if (__predict_false(recover)) { 714 ata_channel_lock(chp); 715 ata_channel_thaw_locked(chp); 716 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 717 ata_channel_unlock(chp); 718 } 719 720 return 1; 721 } 722 723 static void 724 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 725 { 726 struct ata_channel *chp = drvp->chnl_softc; 727 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 728 uint8_t c_slot; 729 730 ata_channel_lock_owned(chp); 731 732 /* get a slot for running the command on */ 733 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 734 panic("%s: %s: failed to get xfer for reset, port %d\n", 735 device_xname(sc->sc_atac.atac_dev), 736 __func__, chp->ch_channel); 737 /* NOTREACHED */ 738 } 739 740 AHCI_WRITE(sc, AHCI_GHC, 741 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 742 ahci_channel_stop(sc, chp, flags); 743 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 744 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 745 746 ata_queue_free_slot(chp, c_slot); 747 } 748 749 /* return error code from ata_bio */ 750 static int 751 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 752 { 753 struct ahci_channel *achp = (struct ahci_channel *)chp; 754 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 755 int i; 756 uint32_t is; 757 758 /* 759 * Base timeout is specified in ms. 760 * If we are allowed to sleep, wait a tick each round. 761 * Otherwise delay for 10ms on each round. 762 */ 763 if (flags & AT_WAIT) 764 timeout = MAX(1, mstohz(timeout)); 765 else 766 timeout = timeout / 10; 767 768 AHCI_CMDH_SYNC(sc, achp, slot, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 /* start command */ 771 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 772 for (i = 0; i < timeout; i++) { 773 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 774 0) 775 return 0; 776 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 777 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 778 AHCI_P_IX_IFS | 779 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 780 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 781 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 782 /* 783 * we got the D2H FIS anyway, 784 * assume sig is valid. 785 * channel is restarted later 786 */ 787 return ERROR; 788 } 789 aprint_debug("%s port %d: error 0x%x sending FIS\n", 790 AHCINAME(sc), chp->ch_channel, is); 791 return ERR_DF; 792 } 793 ata_delay(chp, 10, "ahcifis", flags); 794 } 795 796 aprint_debug("%s port %d: timeout sending FIS\n", 797 AHCINAME(sc), chp->ch_channel); 798 return TIMEOUT; 799 } 800 801 static int 802 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 803 uint32_t *sigp, uint8_t c_slot) 804 { 805 struct ahci_channel *achp = (struct ahci_channel *)chp; 806 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 807 struct ahci_cmd_tbl *cmd_tbl; 808 struct ahci_cmd_header *cmd_h; 809 int i, error = 0; 810 uint32_t sig; 811 812 ata_channel_lock_owned(chp); 813 814 /* clear port interrupt register */ 815 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 816 /* clear SErrors and start operations */ 817 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 818 /* 819 * issue a command list override to clear BSY. 820 * This is needed if there's a PMP with no drive 821 * on port 0 822 */ 823 ahci_channel_start(sc, chp, flags, 1); 824 } else { 825 /* Can't handle command still running without CLO */ 826 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 827 828 ahci_channel_start(sc, chp, flags, 0); 829 } 830 if (drive > 0) { 831 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 832 } 833 834 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 835 goto skip_reset; 836 837 /* polled command, assume interrupts are disabled */ 838 839 cmd_h = &achp->ahcic_cmdh[c_slot]; 840 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 841 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 842 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 843 cmd_h->cmdh_prdbc = 0; 844 memset(cmd_tbl->cmdt_cfis, 0, 64); 845 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 846 cmd_tbl->cmdt_cfis[rhd_c] = drive; 847 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 848 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 849 case ERR_DF: 850 case TIMEOUT: 851 aprint_error("%s port %d: setting WDCTL_RST failed " 852 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 853 if (sigp) 854 *sigp = 0xffffffff; 855 error = EBUSY; 856 goto end; 857 default: 858 break; 859 } 860 861 /* 862 * SATA specification has toggle period for SRST bit of 5 usec. Some 863 * controllers fail to process the SRST clear operation unless 864 * we wait for at least this period between the set and clear commands. 865 */ 866 ata_delay(chp, 10, "ahcirstw", flags); 867 868 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 869 (drive << AHCI_CMDH_F_PMP_SHIFT)); 870 cmd_h->cmdh_prdbc = 0; 871 memset(cmd_tbl->cmdt_cfis, 0, 64); 872 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 873 cmd_tbl->cmdt_cfis[rhd_c] = drive; 874 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 875 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 876 case ERR_DF: 877 case TIMEOUT: 878 aprint_error("%s port %d: clearing WDCTL_RST failed " 879 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 880 if (sigp) 881 *sigp = 0xffffffff; 882 error = EBUSY; 883 goto end; 884 default: 885 break; 886 } 887 888 skip_reset: 889 /* 890 * wait 31s for BSY to clear 891 * This should not be needed, but some controllers clear the 892 * command slot before receiving the D2H FIS ... 893 */ 894 for (i = 0; i < AHCI_RST_WAIT; i++) { 895 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 896 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 897 break; 898 ata_delay(chp, 10, "ahcid2h", flags); 899 } 900 if (i == AHCI_RST_WAIT) { 901 aprint_error("%s: BSY never cleared, TD 0x%x\n", 902 AHCINAME(sc), sig); 903 if (sigp) 904 *sigp = 0xffffffff; 905 goto end; 906 } 907 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 908 DEBUG_PROBE); 909 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 910 if (sigp) 911 *sigp = sig; 912 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 913 AHCINAME(sc), chp->ch_channel, sig, 914 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 915 end: 916 ahci_channel_stop(sc, chp, flags); 917 ata_delay(chp, 500, "ahcirst", flags); 918 /* clear port interrupt register */ 919 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 920 ahci_channel_start(sc, chp, flags, 921 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 922 return error; 923 } 924 925 static void 926 ahci_reset_channel(struct ata_channel *chp, int flags) 927 { 928 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 929 struct ahci_channel *achp = (struct ahci_channel *)chp; 930 int i, tfd; 931 932 ata_channel_lock_owned(chp); 933 934 ahci_channel_stop(sc, chp, flags); 935 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 936 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 937 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 938 /* XXX and then ? */ 939 } 940 ata_kill_active(chp, KILL_RESET, flags); 941 ata_delay(chp, 500, "ahcirst", flags); 942 /* clear port interrupt register */ 943 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 944 /* clear SErrors and start operations */ 945 ahci_channel_start(sc, chp, flags, 946 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 947 /* wait 31s for BSY to clear */ 948 for (i = 0; i < AHCI_RST_WAIT; i++) { 949 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 950 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 951 break; 952 ata_delay(chp, 10, "ahcid2h", flags); 953 } 954 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 955 aprint_error("%s: BSY never cleared, TD 0x%x\n", 956 AHCINAME(sc), tfd); 957 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 958 DEBUG_PROBE); 959 /* clear port interrupt register */ 960 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 961 962 return; 963 } 964 965 static int 966 ahci_ata_addref(struct ata_drive_datas *drvp) 967 { 968 return 0; 969 } 970 971 static void 972 ahci_ata_delref(struct ata_drive_datas *drvp) 973 { 974 return; 975 } 976 977 static void 978 ahci_killpending(struct ata_drive_datas *drvp) 979 { 980 return; 981 } 982 983 static void 984 ahci_probe_drive(struct ata_channel *chp) 985 { 986 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 987 struct ahci_channel *achp = (struct ahci_channel *)chp; 988 uint32_t sig; 989 uint8_t c_slot; 990 int error; 991 992 ata_channel_lock(chp); 993 994 /* get a slot for running the command on */ 995 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 996 aprint_error_dev(sc->sc_atac.atac_dev, 997 "%s: failed to get xfer port %d\n", 998 __func__, chp->ch_channel); 999 ata_channel_unlock(chp); 1000 return; 1001 } 1002 1003 again: 1004 /* bring interface up, accept FISs, power up and spin up device */ 1005 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1006 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1007 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1008 /* reset the PHY and bring online */ 1009 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1010 achp->ahcic_sstatus, AT_WAIT)) { 1011 case SStatus_DET_DEV: 1012 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1013 1014 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1015 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1016 &sig, c_slot); 1017 1018 /* If probe for PMP failed, just fallback to drive 0 */ 1019 if (error) { 1020 aprint_error("%s port %d: drive %d reset " 1021 "failed, disabling PMP\n", 1022 AHCINAME(sc), chp->ch_channel, 1023 PMP_PORT_CTL); 1024 1025 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1026 goto again; 1027 } 1028 } else { 1029 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1030 } 1031 sata_interpret_sig(chp, 0, sig); 1032 /* if we have a PMP attached, inform the controller */ 1033 if (chp->ch_ndrives > PMP_PORT_CTL && 1034 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1035 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1036 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1037 AHCI_P_CMD_PMA); 1038 } 1039 /* clear port interrupt register */ 1040 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1041 1042 /* and enable interrupts */ 1043 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1044 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1045 AHCI_P_IX_IFS | 1046 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1047 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1048 /* wait 500ms before actually starting operations */ 1049 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1050 break; 1051 1052 default: 1053 break; 1054 } 1055 1056 ata_queue_free_slot(chp, c_slot); 1057 1058 ata_channel_unlock(chp); 1059 } 1060 1061 static void 1062 ahci_setup_channel(struct ata_channel *chp) 1063 { 1064 return; 1065 } 1066 1067 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1068 .c_start = ahci_cmd_start, 1069 .c_poll = ahci_cmd_poll, 1070 .c_abort = ahci_cmd_abort, 1071 .c_intr = ahci_cmd_complete, 1072 .c_kill_xfer = ahci_cmd_kill_xfer, 1073 }; 1074 1075 static int 1076 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1077 { 1078 struct ata_channel *chp = drvp->chnl_softc; 1079 struct ata_command *ata_c = &xfer->c_ata_c; 1080 int ret; 1081 int s; 1082 1083 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1084 chp->ch_channel, 1085 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1086 DEBUG_XFERS); 1087 if (ata_c->flags & AT_POLL) 1088 xfer->c_flags |= C_POLL; 1089 if (ata_c->flags & AT_WAIT) 1090 xfer->c_flags |= C_WAIT; 1091 xfer->c_drive = drvp->drive; 1092 xfer->c_databuf = ata_c->data; 1093 xfer->c_bcount = ata_c->bcount; 1094 xfer->ops = &ahci_cmd_xfer_ops; 1095 s = splbio(); 1096 ata_exec_xfer(chp, xfer); 1097 #ifdef DIAGNOSTIC 1098 if ((ata_c->flags & AT_POLL) != 0 && 1099 (ata_c->flags & AT_DONE) == 0) 1100 panic("ahci_exec_command: polled command not done"); 1101 #endif 1102 if (ata_c->flags & AT_DONE) { 1103 ret = ATACMD_COMPLETE; 1104 } else { 1105 if (ata_c->flags & AT_WAIT) { 1106 ata_wait_cmd(chp, xfer); 1107 ret = ATACMD_COMPLETE; 1108 } else { 1109 ret = ATACMD_QUEUED; 1110 } 1111 } 1112 splx(s); 1113 return ret; 1114 } 1115 1116 static int 1117 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1118 { 1119 struct ahci_softc *sc = AHCI_CH2SC(chp); 1120 struct ahci_channel *achp = (struct ahci_channel *)chp; 1121 struct ata_command *ata_c = &xfer->c_ata_c; 1122 int slot = xfer->c_slot; 1123 struct ahci_cmd_tbl *cmd_tbl; 1124 struct ahci_cmd_header *cmd_h; 1125 1126 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1127 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1128 ata_c->timeout, slot), 1129 DEBUG_XFERS); 1130 1131 ata_channel_lock_owned(chp); 1132 1133 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1134 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1135 cmd_tbl), DEBUG_XFERS); 1136 1137 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1138 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1139 1140 cmd_h = &achp->ahcic_cmdh[slot]; 1141 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1142 chp->ch_channel, cmd_h), DEBUG_XFERS); 1143 if (ahci_dma_setup(chp, slot, 1144 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1145 ata_c->data : NULL, 1146 ata_c->bcount, 1147 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1148 ata_c->flags |= AT_DF; 1149 return ATASTART_ABORT; 1150 } 1151 cmd_h->cmdh_flags = htole16( 1152 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1153 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1154 cmd_h->cmdh_prdbc = 0; 1155 AHCI_CMDH_SYNC(sc, achp, slot, 1156 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1157 1158 if (ata_c->flags & AT_POLL) { 1159 /* polled command, disable interrupts */ 1160 AHCI_WRITE(sc, AHCI_GHC, 1161 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1162 } 1163 /* start command */ 1164 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1165 1166 if ((ata_c->flags & AT_POLL) == 0) { 1167 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1168 ata_timeout, chp); 1169 return ATASTART_STARTED; 1170 } else 1171 return ATASTART_POLL; 1172 } 1173 1174 static void 1175 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1176 { 1177 struct ahci_softc *sc = AHCI_CH2SC(chp); 1178 struct ahci_channel *achp = (struct ahci_channel *)chp; 1179 1180 ata_channel_lock(chp); 1181 1182 /* 1183 * Polled command. 1184 */ 1185 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1186 if (xfer->c_ata_c.flags & AT_DONE) 1187 break; 1188 ata_channel_unlock(chp); 1189 ahci_intr_port(achp); 1190 ata_channel_lock(chp); 1191 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1192 } 1193 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1194 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1195 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1196 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1197 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1198 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1199 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1200 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1201 DEBUG_XFERS); 1202 1203 ata_channel_unlock(chp); 1204 1205 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1206 xfer->c_ata_c.flags |= AT_TIMEOU; 1207 xfer->ops->c_intr(chp, xfer, 0); 1208 } 1209 /* reenable interrupts */ 1210 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1211 } 1212 1213 static void 1214 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1215 { 1216 ahci_cmd_complete(chp, xfer, 0); 1217 } 1218 1219 static void 1220 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1221 { 1222 struct ata_command *ata_c = &xfer->c_ata_c; 1223 bool deactivate = true; 1224 1225 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1226 DEBUG_FUNCS); 1227 1228 switch (reason) { 1229 case KILL_GONE_INACTIVE: 1230 deactivate = false; 1231 /* FALLTHROUGH */ 1232 case KILL_GONE: 1233 ata_c->flags |= AT_GONE; 1234 break; 1235 case KILL_RESET: 1236 ata_c->flags |= AT_RESET; 1237 break; 1238 case KILL_REQUEUE: 1239 panic("%s: not supposed to be requeued\n", __func__); 1240 break; 1241 default: 1242 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1243 panic("ahci_cmd_kill_xfer"); 1244 } 1245 1246 ahci_cmd_done_end(chp, xfer); 1247 1248 if (deactivate) 1249 ata_deactivate_xfer(chp, xfer); 1250 } 1251 1252 static int 1253 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1254 { 1255 struct ata_command *ata_c = &xfer->c_ata_c; 1256 struct ahci_channel *achp = (struct ahci_channel *)chp; 1257 1258 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1259 chp->ch_channel, 1260 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1261 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1262 DEBUG_FUNCS); 1263 1264 if (ata_waitdrain_xfer_check(chp, xfer)) 1265 return 0; 1266 1267 if (xfer->c_flags & C_TIMEOU) { 1268 ata_c->flags |= AT_TIMEOU; 1269 } 1270 1271 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1272 ata_c->flags |= AT_TIMEOU; 1273 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1274 ata_c->r_error = AHCI_TFD_ERR(tfd); 1275 ata_c->flags |= AT_ERROR; 1276 } 1277 1278 if (ata_c->flags & AT_READREG) 1279 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1280 1281 ahci_cmd_done(chp, xfer); 1282 1283 ata_deactivate_xfer(chp, xfer); 1284 1285 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1286 atastart(chp); 1287 1288 return 0; 1289 } 1290 1291 static void 1292 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1293 { 1294 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1295 struct ahci_channel *achp = (struct ahci_channel *)chp; 1296 struct ata_command *ata_c = &xfer->c_ata_c; 1297 uint16_t *idwordbuf; 1298 int i; 1299 1300 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1301 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1302 1303 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1304 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1305 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1306 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1307 BUS_DMASYNC_POSTWRITE); 1308 bus_dmamap_unload(sc->sc_dmat, map); 1309 } 1310 1311 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1312 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1313 1314 /* ata(4) expects IDENTIFY data to be in host endianess */ 1315 if (ata_c->r_command == WDCC_IDENTIFY || 1316 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1317 idwordbuf = xfer->c_databuf; 1318 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1319 idwordbuf[i] = le16toh(idwordbuf[i]); 1320 } 1321 } 1322 1323 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1324 ata_c->flags |= AT_XFDONE; 1325 1326 ahci_cmd_done_end(chp, xfer); 1327 } 1328 1329 static void 1330 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1331 { 1332 struct ata_command *ata_c = &xfer->c_ata_c; 1333 1334 ata_c->flags |= AT_DONE; 1335 } 1336 1337 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1338 .c_start = ahci_bio_start, 1339 .c_poll = ahci_bio_poll, 1340 .c_abort = ahci_bio_abort, 1341 .c_intr = ahci_bio_complete, 1342 .c_kill_xfer = ahci_bio_kill_xfer, 1343 }; 1344 1345 static int 1346 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1347 { 1348 struct ata_channel *chp = drvp->chnl_softc; 1349 struct ata_bio *ata_bio = &xfer->c_bio; 1350 1351 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1352 chp->ch_channel, 1353 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1354 DEBUG_XFERS); 1355 if (ata_bio->flags & ATA_POLL) 1356 xfer->c_flags |= C_POLL; 1357 xfer->c_drive = drvp->drive; 1358 xfer->c_databuf = ata_bio->databuf; 1359 xfer->c_bcount = ata_bio->bcount; 1360 xfer->ops = &ahci_bio_xfer_ops; 1361 ata_exec_xfer(chp, xfer); 1362 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1363 } 1364 1365 static int 1366 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1367 { 1368 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1369 struct ahci_channel *achp = (struct ahci_channel *)chp; 1370 struct ata_bio *ata_bio = &xfer->c_bio; 1371 struct ahci_cmd_tbl *cmd_tbl; 1372 struct ahci_cmd_header *cmd_h; 1373 1374 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1375 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1376 1377 ata_channel_lock_owned(chp); 1378 1379 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1380 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1381 cmd_tbl), DEBUG_XFERS); 1382 1383 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1384 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1385 1386 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1387 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1388 chp->ch_channel, cmd_h), DEBUG_XFERS); 1389 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1390 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1391 ata_bio->error = ERR_DMA; 1392 ata_bio->r_error = 0; 1393 return ATASTART_ABORT; 1394 } 1395 cmd_h->cmdh_flags = htole16( 1396 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1397 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1398 cmd_h->cmdh_prdbc = 0; 1399 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1400 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1401 1402 if (xfer->c_flags & C_POLL) { 1403 /* polled command, disable interrupts */ 1404 AHCI_WRITE(sc, AHCI_GHC, 1405 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1406 } 1407 if (xfer->c_flags & C_NCQ) 1408 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1409 /* start command */ 1410 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1411 1412 if ((xfer->c_flags & C_POLL) == 0) { 1413 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1414 ata_timeout, chp); 1415 return ATASTART_STARTED; 1416 } else 1417 return ATASTART_POLL; 1418 } 1419 1420 static void 1421 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1422 { 1423 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1424 struct ahci_channel *achp = (struct ahci_channel *)chp; 1425 1426 /* 1427 * Polled command. 1428 */ 1429 for (int i = 0; i < ATA_DELAY * 10; i++) { 1430 if (xfer->c_bio.flags & ATA_ITSDONE) 1431 break; 1432 ahci_intr_port(achp); 1433 delay(100); 1434 } 1435 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1436 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1437 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1438 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1439 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1440 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1441 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1442 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1443 DEBUG_XFERS); 1444 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1445 xfer->c_bio.error = TIMEOUT; 1446 xfer->ops->c_intr(chp, xfer, 0); 1447 } 1448 /* reenable interrupts */ 1449 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1450 } 1451 1452 static void 1453 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1454 { 1455 ahci_bio_complete(chp, xfer, 0); 1456 } 1457 1458 static void 1459 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1460 { 1461 int drive = xfer->c_drive; 1462 struct ata_bio *ata_bio = &xfer->c_bio; 1463 bool deactivate = true; 1464 1465 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1466 DEBUG_FUNCS); 1467 1468 ata_bio->flags |= ATA_ITSDONE; 1469 switch (reason) { 1470 case KILL_GONE_INACTIVE: 1471 deactivate = false; 1472 /* FALLTHROUGH */ 1473 case KILL_GONE: 1474 ata_bio->error = ERR_NODEV; 1475 break; 1476 case KILL_RESET: 1477 ata_bio->error = ERR_RESET; 1478 break; 1479 case KILL_REQUEUE: 1480 ata_bio->error = REQUEUE; 1481 break; 1482 default: 1483 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1484 panic("ahci_bio_kill_xfer"); 1485 } 1486 ata_bio->r_error = WDCE_ABRT; 1487 1488 if (deactivate) 1489 ata_deactivate_xfer(chp, xfer); 1490 1491 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1492 } 1493 1494 static int 1495 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1496 { 1497 struct ata_bio *ata_bio = &xfer->c_bio; 1498 int drive = xfer->c_drive; 1499 struct ahci_channel *achp = (struct ahci_channel *)chp; 1500 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1501 1502 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1503 DEBUG_FUNCS); 1504 1505 if (ata_waitdrain_xfer_check(chp, xfer)) 1506 return 0; 1507 1508 if (xfer->c_flags & C_TIMEOU) { 1509 ata_bio->error = TIMEOUT; 1510 } 1511 1512 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1513 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1514 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1515 BUS_DMASYNC_POSTWRITE); 1516 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1517 1518 ata_bio->flags |= ATA_ITSDONE; 1519 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1520 ata_bio->error = ERR_DF; 1521 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1522 ata_bio->error = ERROR; 1523 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1524 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1525 ata_bio->flags |= ATA_CORR; 1526 1527 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1528 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1529 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1530 ata_bio->bcount), DEBUG_XFERS); 1531 /* 1532 * If it was a write, complete data buffer may have been transfered 1533 * before error detection; in this case don't use cmdh_prdbc 1534 * as it won't reflect what was written to media. Assume nothing 1535 * was transfered and leave bcount as-is. 1536 * For queued commands, PRD Byte Count should not be used, and is 1537 * not required to be valid; in that case underflow is always illegal. 1538 */ 1539 if ((xfer->c_flags & C_NCQ) != 0) { 1540 if (ata_bio->error == NOERROR) 1541 ata_bio->bcount = 0; 1542 } else { 1543 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1544 ata_bio->bcount -= 1545 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1546 } 1547 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1548 1549 ata_deactivate_xfer(chp, xfer); 1550 1551 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1552 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1553 atastart(chp); 1554 return 0; 1555 } 1556 1557 static void 1558 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1559 { 1560 int i; 1561 /* stop channel */ 1562 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1563 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1564 /* wait 1s for channel to stop */ 1565 for (i = 0; i <100; i++) { 1566 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1567 == 0) 1568 break; 1569 ata_delay(chp, 10, "ahcistop", flags); 1570 } 1571 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1572 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1573 /* XXX controller reset ? */ 1574 return; 1575 } 1576 1577 if (sc->sc_channel_stop) 1578 sc->sc_channel_stop(sc, chp); 1579 } 1580 1581 static void 1582 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1583 int flags, int clo) 1584 { 1585 int i; 1586 uint32_t p_cmd; 1587 /* clear error */ 1588 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1589 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1590 1591 if (clo) { 1592 /* issue command list override */ 1593 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1594 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1595 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1596 /* wait 1s for AHCI_CAP_CLO to clear */ 1597 for (i = 0; i <100; i++) { 1598 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1599 AHCI_P_CMD_CLO) == 0) 1600 break; 1601 ata_delay(chp, 10, "ahciclo", flags); 1602 } 1603 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1604 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1605 /* XXX controller reset ? */ 1606 return; 1607 } 1608 } 1609 1610 if (sc->sc_channel_start) 1611 sc->sc_channel_start(sc, chp); 1612 1613 /* and start controller */ 1614 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1615 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1616 if (chp->ch_ndrives > PMP_PORT_CTL && 1617 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1618 p_cmd |= AHCI_P_CMD_PMA; 1619 } 1620 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1621 } 1622 1623 /* Recover channel after command failure */ 1624 static void 1625 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1626 { 1627 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1628 int drive = ATACH_NODRIVE; 1629 bool reset = false; 1630 1631 ata_channel_lock_owned(chp); 1632 1633 /* 1634 * Read FBS to get the drive which caused the error, if PM is in use. 1635 * According to AHCI 1.3 spec, this register is available regardless 1636 * if FIS-based switching (FBSS) feature is supported, or disabled. 1637 * If FIS-based switching is not in use, it merely maintains single 1638 * pair of DRQ/BSY state, but it is enough since in that case we 1639 * never issue commands for more than one device at the time anyway. 1640 * XXX untested 1641 */ 1642 if (chp->ch_ndrives > PMP_PORT_CTL) { 1643 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1644 if (fbs & AHCI_P_FBS_SDE) { 1645 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1646 1647 /* 1648 * Tell HBA to reset PM port X (value in DWE) state, 1649 * and resume processing commands for other ports. 1650 */ 1651 fbs |= AHCI_P_FBS_DEC; 1652 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1653 for (int i = 0; i < 1000; i++) { 1654 fbs = AHCI_READ(sc, 1655 AHCI_P_FBS(chp->ch_channel)); 1656 if ((fbs & AHCI_P_FBS_DEC) == 0) 1657 break; 1658 DELAY(1000); 1659 } 1660 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1661 /* follow non-device specific recovery */ 1662 drive = ATACH_NODRIVE; 1663 reset = true; 1664 } 1665 } else { 1666 /* not device specific, reset channel */ 1667 drive = ATACH_NODRIVE; 1668 reset = true; 1669 } 1670 } else 1671 drive = 0; 1672 1673 /* 1674 * If BSY or DRQ bits are set, must execute COMRESET to return 1675 * device to idle state. If drive is idle, it's enough to just 1676 * reset CMD.ST, it's not necessary to do software reset. 1677 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1678 * to unblock device processing if COMRESET was not done. 1679 */ 1680 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1681 ahci_reset_channel(chp, flags); 1682 goto out; 1683 } 1684 1685 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1686 ahci_channel_stop(sc, chp, flags); 1687 ahci_channel_start(sc, chp, flags, 1688 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1689 1690 ata_recovery_resume(chp, drive, tfd, flags); 1691 1692 out: 1693 /* Drive unblocked, back to normal operation */ 1694 return; 1695 } 1696 1697 static int 1698 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1699 size_t count, int op) 1700 { 1701 int error, seg; 1702 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1703 struct ahci_channel *achp = (struct ahci_channel *)chp; 1704 struct ahci_cmd_tbl *cmd_tbl; 1705 struct ahci_cmd_header *cmd_h; 1706 1707 cmd_h = &achp->ahcic_cmdh[slot]; 1708 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1709 1710 if (data == NULL) { 1711 cmd_h->cmdh_prdtl = 0; 1712 goto end; 1713 } 1714 1715 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1716 data, count, NULL, 1717 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1718 if (error) { 1719 printf("%s port %d: failed to load xfer: %d\n", 1720 AHCINAME(sc), chp->ch_channel, error); 1721 return error; 1722 } 1723 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1724 achp->ahcic_datad[slot]->dm_mapsize, 1725 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1726 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1727 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1728 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1729 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1730 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1731 } 1732 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1733 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1734 end: 1735 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1736 return 0; 1737 } 1738 1739 #if NATAPIBUS > 0 1740 static void 1741 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1742 { 1743 struct ata_channel *chp = ata_sc->sc_chan; 1744 struct atac_softc *atac = chp->ch_atac; 1745 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1746 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1747 /* 1748 * Fill in the scsipi_adapter. 1749 */ 1750 adapt->adapt_dev = atac->atac_dev; 1751 adapt->adapt_nchannels = atac->atac_nchannels; 1752 adapt->adapt_request = ahci_atapi_scsipi_request; 1753 adapt->adapt_minphys = ahci_atapi_minphys; 1754 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1755 1756 /* 1757 * Fill in the scsipi_channel. 1758 */ 1759 memset(chan, 0, sizeof(*chan)); 1760 chan->chan_adapter = adapt; 1761 chan->chan_bustype = &ahci_atapi_bustype; 1762 chan->chan_channel = chp->ch_channel; 1763 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1764 chan->chan_openings = 1; 1765 chan->chan_max_periph = 1; 1766 chan->chan_ntargets = 1; 1767 chan->chan_nluns = 1; 1768 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1769 atapiprint); 1770 } 1771 1772 static void 1773 ahci_atapi_minphys(struct buf *bp) 1774 { 1775 if (bp->b_bcount > MAXPHYS) 1776 bp->b_bcount = MAXPHYS; 1777 minphys(bp); 1778 } 1779 1780 /* 1781 * Kill off all pending xfers for a periph. 1782 * 1783 * Must be called at splbio(). 1784 */ 1785 static void 1786 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1787 { 1788 struct atac_softc *atac = 1789 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1790 struct ata_channel *chp = 1791 atac->atac_channels[periph->periph_channel->chan_channel]; 1792 1793 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1794 } 1795 1796 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1797 .c_start = ahci_atapi_start, 1798 .c_poll = ahci_atapi_poll, 1799 .c_abort = ahci_atapi_abort, 1800 .c_intr = ahci_atapi_complete, 1801 .c_kill_xfer = ahci_atapi_kill_xfer, 1802 }; 1803 1804 static void 1805 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1806 scsipi_adapter_req_t req, void *arg) 1807 { 1808 struct scsipi_adapter *adapt = chan->chan_adapter; 1809 struct scsipi_periph *periph; 1810 struct scsipi_xfer *sc_xfer; 1811 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1812 struct atac_softc *atac = &sc->sc_atac; 1813 struct ata_xfer *xfer; 1814 int channel = chan->chan_channel; 1815 int drive, s; 1816 1817 switch (req) { 1818 case ADAPTER_REQ_RUN_XFER: 1819 sc_xfer = arg; 1820 periph = sc_xfer->xs_periph; 1821 drive = periph->periph_target; 1822 if (!device_is_active(atac->atac_dev)) { 1823 sc_xfer->error = XS_DRIVER_STUFFUP; 1824 scsipi_done(sc_xfer); 1825 return; 1826 } 1827 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1828 if (xfer == NULL) { 1829 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1830 scsipi_done(sc_xfer); 1831 return; 1832 } 1833 1834 if (sc_xfer->xs_control & XS_CTL_POLL) 1835 xfer->c_flags |= C_POLL; 1836 xfer->c_drive = drive; 1837 xfer->c_flags |= C_ATAPI; 1838 xfer->c_databuf = sc_xfer->data; 1839 xfer->c_bcount = sc_xfer->datalen; 1840 xfer->ops = &ahci_atapi_xfer_ops; 1841 xfer->c_scsipi = sc_xfer; 1842 xfer->c_atapi.c_dscpoll = 0; 1843 s = splbio(); 1844 ata_exec_xfer(atac->atac_channels[channel], xfer); 1845 #ifdef DIAGNOSTIC 1846 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1847 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1848 panic("ahci_atapi_scsipi_request: polled command " 1849 "not done"); 1850 #endif 1851 splx(s); 1852 return; 1853 default: 1854 /* Not supported, nothing to do. */ 1855 ; 1856 } 1857 } 1858 1859 static int 1860 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1861 { 1862 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1863 struct ahci_channel *achp = (struct ahci_channel *)chp; 1864 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1865 struct ahci_cmd_tbl *cmd_tbl; 1866 struct ahci_cmd_header *cmd_h; 1867 1868 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1869 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1870 1871 ata_channel_lock_owned(chp); 1872 1873 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1874 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1875 cmd_tbl), DEBUG_XFERS); 1876 1877 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1878 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1879 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1880 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1881 1882 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1883 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1884 chp->ch_channel, cmd_h), DEBUG_XFERS); 1885 if (ahci_dma_setup(chp, xfer->c_slot, 1886 sc_xfer->datalen ? sc_xfer->data : NULL, 1887 sc_xfer->datalen, 1888 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1889 BUS_DMA_READ : BUS_DMA_WRITE)) { 1890 sc_xfer->error = XS_DRIVER_STUFFUP; 1891 return ATASTART_ABORT; 1892 } 1893 cmd_h->cmdh_flags = htole16( 1894 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1895 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1896 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1897 cmd_h->cmdh_prdbc = 0; 1898 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1899 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1900 1901 if (xfer->c_flags & C_POLL) { 1902 /* polled command, disable interrupts */ 1903 AHCI_WRITE(sc, AHCI_GHC, 1904 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1905 } 1906 /* start command */ 1907 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1908 1909 if ((xfer->c_flags & C_POLL) == 0) { 1910 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1911 ata_timeout, chp); 1912 return ATASTART_STARTED; 1913 } else 1914 return ATASTART_POLL; 1915 } 1916 1917 static void 1918 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1919 { 1920 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1921 struct ahci_channel *achp = (struct ahci_channel *)chp; 1922 1923 /* 1924 * Polled command. 1925 */ 1926 for (int i = 0; i < ATA_DELAY / 10; i++) { 1927 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1928 break; 1929 ahci_intr_port(achp); 1930 delay(10000); 1931 } 1932 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1933 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1934 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1935 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1936 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1937 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1938 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1939 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1940 DEBUG_XFERS); 1941 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1942 xfer->c_scsipi->error = XS_TIMEOUT; 1943 xfer->ops->c_intr(chp, xfer, 0); 1944 } 1945 /* reenable interrupts */ 1946 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1947 } 1948 1949 static void 1950 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1951 { 1952 ahci_atapi_complete(chp, xfer, 0); 1953 } 1954 1955 static int 1956 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1957 { 1958 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1959 struct ahci_channel *achp = (struct ahci_channel *)chp; 1960 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1961 1962 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1963 DEBUG_FUNCS); 1964 1965 if (ata_waitdrain_xfer_check(chp, xfer)) 1966 return 0; 1967 1968 if (xfer->c_flags & C_TIMEOU) { 1969 sc_xfer->error = XS_TIMEOUT; 1970 } 1971 1972 if (xfer->c_bcount > 0) { 1973 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1974 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1975 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1976 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1977 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1978 } 1979 1980 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1981 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1982 sc_xfer->resid = sc_xfer->datalen; 1983 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1984 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1985 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1986 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1987 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1988 sc_xfer->resid == sc_xfer->datalen)) { 1989 sc_xfer->error = XS_SHORTSENSE; 1990 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 1991 if ((sc_xfer->xs_periph->periph_quirks & 1992 PQUIRK_NOSENSE) == 0) { 1993 /* ask scsipi to send a REQUEST_SENSE */ 1994 sc_xfer->error = XS_BUSY; 1995 sc_xfer->status = SCSI_CHECK; 1996 } 1997 } 1998 1999 ata_deactivate_xfer(chp, xfer); 2000 2001 ata_free_xfer(chp, xfer); 2002 scsipi_done(sc_xfer); 2003 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2004 atastart(chp); 2005 return 0; 2006 } 2007 2008 static void 2009 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2010 { 2011 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2012 bool deactivate = true; 2013 2014 /* remove this command from xfer queue */ 2015 switch (reason) { 2016 case KILL_GONE_INACTIVE: 2017 deactivate = false; 2018 /* FALLTHROUGH */ 2019 case KILL_GONE: 2020 sc_xfer->error = XS_DRIVER_STUFFUP; 2021 break; 2022 case KILL_RESET: 2023 sc_xfer->error = XS_RESET; 2024 break; 2025 case KILL_REQUEUE: 2026 sc_xfer->error = XS_REQUEUE; 2027 break; 2028 default: 2029 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2030 panic("ahci_ata_atapi_kill_xfer"); 2031 } 2032 2033 if (deactivate) 2034 ata_deactivate_xfer(chp, xfer); 2035 2036 ata_free_xfer(chp, xfer); 2037 scsipi_done(sc_xfer); 2038 } 2039 2040 static void 2041 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2042 { 2043 struct scsipi_channel *chan = sc->sc_channel; 2044 struct scsipi_periph *periph; 2045 struct ataparams ids; 2046 struct ataparams *id = &ids; 2047 struct ahci_softc *ahcic = 2048 device_private(chan->chan_adapter->adapt_dev); 2049 struct atac_softc *atac = &ahcic->sc_atac; 2050 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2051 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2052 struct scsipibus_attach_args sa; 2053 char serial_number[21], model[41], firmware_revision[9]; 2054 int s; 2055 2056 /* skip if already attached */ 2057 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2058 return; 2059 2060 /* if no ATAPI device detected at attach time, skip */ 2061 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2062 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2063 "not present\n", target), DEBUG_PROBE); 2064 return; 2065 } 2066 2067 /* Some ATAPI devices need a bit more time after software reset. */ 2068 delay(5000); 2069 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2070 #ifdef ATAPI_DEBUG_PROBE 2071 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2072 AHCINAME(ahcic), target, 2073 id->atap_config & ATAPI_CFG_CMD_MASK, 2074 id->atap_config & ATAPI_CFG_DRQ_MASK); 2075 #endif 2076 periph = scsipi_alloc_periph(M_NOWAIT); 2077 if (periph == NULL) { 2078 aprint_error_dev(sc->sc_dev, 2079 "unable to allocate periph for drive %d\n", 2080 target); 2081 return; 2082 } 2083 periph->periph_dev = NULL; 2084 periph->periph_channel = chan; 2085 periph->periph_switch = &atapi_probe_periphsw; 2086 periph->periph_target = target; 2087 periph->periph_lun = 0; 2088 periph->periph_quirks = PQUIRK_ONLYBIG; 2089 2090 #ifdef SCSIPI_DEBUG 2091 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2092 SCSIPI_DEBUG_TARGET == target) 2093 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2094 #endif 2095 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2096 if (id->atap_config & ATAPI_CFG_REMOV) 2097 periph->periph_flags |= PERIPH_REMOVABLE; 2098 if (periph->periph_type == T_SEQUENTIAL) { 2099 s = splbio(); 2100 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2101 splx(s); 2102 } 2103 2104 sa.sa_periph = periph; 2105 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2106 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2107 T_REMOV : T_FIXED; 2108 strnvisx(model, sizeof(model), id->atap_model, 40, 2109 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2110 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2111 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2112 strnvisx(firmware_revision, sizeof(firmware_revision), 2113 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2114 sa.sa_inqbuf.vendor = model; 2115 sa.sa_inqbuf.product = serial_number; 2116 sa.sa_inqbuf.revision = firmware_revision; 2117 2118 /* 2119 * Determine the operating mode capabilities of the device. 2120 */ 2121 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2122 periph->periph_cap |= PERIPH_CAP_CMD16; 2123 /* XXX This is gross. */ 2124 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2125 2126 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2127 2128 if (drvp->drv_softc) 2129 ata_probe_caps(drvp); 2130 else { 2131 s = splbio(); 2132 drvp->drive_type = ATA_DRIVET_NONE; 2133 splx(s); 2134 } 2135 } else { 2136 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2137 "failed for drive %s:%d:%d\n", 2138 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2139 s = splbio(); 2140 drvp->drive_type = ATA_DRIVET_NONE; 2141 splx(s); 2142 } 2143 } 2144 #endif /* NATAPIBUS */ 2145
Indexes created Fri Oct 17 00:09:41 GMT 2025