ahcisata_core.c revision 1.60.4.2
1 /* $NetBSD: ahcisata_core.c,v 1.60.4.2 2020/04/08 14:08:05 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.60.4.2 2020/04/08 14:08:05 martin Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 103 .bustype_cmd = atapi_scsipi_cmd, 104 .bustype_interpret_sense = atapi_interpret_sense, 105 .bustype_printaddr = atapi_print_addr, 106 .bustype_kill_pending = ahci_atapi_kill_pending, 107 .bustype_async_event_xfer_mode = NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADNCQ) { 280 aprint_verbose_dev(sc->sc_atac.atac_dev, 281 "ignoring broken NCQ support\n"); 282 sc->sc_ahci_cap &= ~AHCI_CAP_NCQ; 283 } 284 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 285 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 286 ahci_rev = AHCI_READ(sc, AHCI_VS); 287 snprintb(buf, sizeof(buf), "\177\020" 288 /* "f\000\005NP\0" */ 289 "b\005SXS\0" 290 "b\006EMS\0" 291 "b\007CCCS\0" 292 /* "f\010\005NCS\0" */ 293 "b\015PSC\0" 294 "b\016SSC\0" 295 "b\017PMD\0" 296 "b\020FBSS\0" 297 "b\021SPM\0" 298 "b\022SAM\0" 299 "b\023SNZO\0" 300 "f\024\003ISS\0" 301 "=\001Gen1\0" 302 "=\002Gen2\0" 303 "=\003Gen3\0" 304 "b\030SCLO\0" 305 "b\031SAL\0" 306 "b\032SALP\0" 307 "b\033SSS\0" 308 "b\034SMPS\0" 309 "b\035SSNTF\0" 310 "b\036SNCQ\0" 311 "b\037S64A\0" 312 "\0", sc->sc_ahci_cap); 313 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 314 ", %d port%s, %d slot%s, CAP %s\n", 315 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 316 sc->sc_atac.atac_nchannels, 317 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 318 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 319 320 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 321 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 322 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 323 sc->sc_atac.atac_pio_cap = 4; 324 sc->sc_atac.atac_dma_cap = 2; 325 sc->sc_atac.atac_udma_cap = 6; 326 sc->sc_atac.atac_channels = sc->sc_chanarray; 327 sc->sc_atac.atac_probe = ahci_probe_drive; 328 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 329 sc->sc_atac.atac_set_modes = ahci_setup_channel; 330 #if NATAPIBUS > 0 331 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 332 #endif 333 334 dmasize = 335 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 338 if (error) { 339 aprint_error("%s: unable to allocate command header memory" 340 ", error=%d\n", AHCINAME(sc), error); 341 return; 342 } 343 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 344 sc->sc_cmd_hdr_nseg, dmasize, 345 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 346 if (error) { 347 aprint_error("%s: unable to map command header memory" 348 ", error=%d\n", AHCINAME(sc), error); 349 return; 350 } 351 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 352 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 353 if (error) { 354 aprint_error("%s: unable to create command header map" 355 ", error=%d\n", AHCINAME(sc), error); 356 return; 357 } 358 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 359 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 360 if (error) { 361 aprint_error("%s: unable to load command header map" 362 ", error=%d\n", AHCINAME(sc), error); 363 return; 364 } 365 sc->sc_cmd_hdr = cmdhp; 366 367 ahci_enable_intrs(sc); 368 369 if (sc->sc_ahci_ports == 0) { 370 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 371 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 372 DEBUG_PROBE); 373 } 374 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 375 if ((sc->sc_ahci_ports & (1U << i)) == 0) 376 continue; 377 if (port >= sc->sc_atac.atac_nchannels) { 378 aprint_error("%s: more ports than announced\n", 379 AHCINAME(sc)); 380 break; 381 } 382 383 /* Optional intr establish per active port */ 384 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 385 aprint_error("%s: intr establish hook failed\n", 386 AHCINAME(sc)); 387 break; 388 } 389 390 achp = &sc->sc_channels[i]; 391 chp = &achp->ata_channel; 392 sc->sc_chanarray[i] = chp; 393 chp->ch_channel = i; 394 chp->ch_atac = &sc->sc_atac; 395 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 396 if (chp->ch_queue == NULL) { 397 aprint_error("%s port %d: can't allocate memory for " 398 "command queue", AHCINAME(sc), i); 399 break; 400 } 401 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 402 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 403 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 404 BUS_DMA_NOWAIT); 405 if (error) { 406 aprint_error("%s: unable to allocate command table " 407 "memory, error=%d\n", AHCINAME(sc), error); 408 break; 409 } 410 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 411 achp->ahcic_cmd_tbl_nseg, dmasize, 412 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 413 if (error) { 414 aprint_error("%s: unable to map command table memory" 415 ", error=%d\n", AHCINAME(sc), error); 416 break; 417 } 418 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 419 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 420 if (error) { 421 aprint_error("%s: unable to create command table map" 422 ", error=%d\n", AHCINAME(sc), error); 423 break; 424 } 425 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 426 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 427 if (error) { 428 aprint_error("%s: unable to load command table map" 429 ", error=%d\n", AHCINAME(sc), error); 430 break; 431 } 432 achp->ahcic_cmdh = (struct ahci_cmd_header *) 433 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 434 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 435 AHCI_CMDH_SIZE * port; 436 achp->ahcic_rfis = (struct ahci_r_fis *) 437 ((char *)cmdhp + 438 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 439 AHCI_RFIS_SIZE * port); 440 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 441 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 442 AHCI_RFIS_SIZE * port; 443 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 444 "rfis %p (0x%" PRIx64 ")\n", i, 445 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 446 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 447 DEBUG_PROBE); 448 449 for (j = 0; j < sc->sc_ncmds; j++) { 450 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 451 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 452 achp->ahcic_bus_cmd_tbl[j] = 453 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 454 AHCI_CMDTBL_SIZE * j; 455 achp->ahcic_cmdh[j].cmdh_cmdtba = 456 htole64(achp->ahcic_bus_cmd_tbl[j]); 457 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 458 achp->ahcic_cmd_tbl[j], 459 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 460 /* The xfer DMA map */ 461 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 462 AHCI_NPRD, 0x400000 /* 4MB */, 0, 463 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 464 &achp->ahcic_datad[j]); 465 if (error) { 466 aprint_error("%s: couldn't alloc xfer DMA map, " 467 "error=%d\n", AHCINAME(sc), error); 468 goto end; 469 } 470 } 471 ahci_setup_port(sc, i); 472 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 473 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 474 aprint_error("%s: couldn't map port %d " 475 "sata_status regs\n", AHCINAME(sc), i); 476 break; 477 } 478 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 479 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 480 aprint_error("%s: couldn't map port %d " 481 "sata_control regs\n", AHCINAME(sc), i); 482 break; 483 } 484 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 485 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 486 aprint_error("%s: couldn't map port %d " 487 "sata_error regs\n", AHCINAME(sc), i); 488 break; 489 } 490 ata_channel_attach(chp); 491 port++; 492 end: 493 continue; 494 } 495 } 496 497 void 498 ahci_childdetached(struct ahci_softc *sc, device_t child) 499 { 500 struct ahci_channel *achp; 501 struct ata_channel *chp; 502 503 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 504 achp = &sc->sc_channels[i]; 505 chp = &achp->ata_channel; 506 507 if ((sc->sc_ahci_ports & (1U << i)) == 0) 508 continue; 509 510 if (child == chp->atabus) 511 chp->atabus = NULL; 512 } 513 } 514 515 int 516 ahci_detach(struct ahci_softc *sc, int flags) 517 { 518 struct atac_softc *atac; 519 struct ahci_channel *achp; 520 struct ata_channel *chp; 521 struct scsipi_adapter *adapt; 522 int i, j, port; 523 int error; 524 525 atac = &sc->sc_atac; 526 adapt = &atac->atac_atapi_adapter._generic; 527 528 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 529 achp = &sc->sc_channels[i]; 530 chp = &achp->ata_channel; 531 532 if ((sc->sc_ahci_ports & (1U << i)) == 0) 533 continue; 534 if (port >= sc->sc_atac.atac_nchannels) { 535 aprint_error("%s: more ports than announced\n", 536 AHCINAME(sc)); 537 break; 538 } 539 540 if (chp->atabus != NULL) { 541 if ((error = config_detach(chp->atabus, flags)) != 0) 542 return error; 543 544 KASSERT(chp->atabus == NULL); 545 } 546 547 if (chp->ch_flags & ATACH_DETACHED) 548 continue; 549 550 for (j = 0; j < sc->sc_ncmds; j++) 551 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 552 553 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 554 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 555 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 556 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 557 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 558 achp->ahcic_cmd_tbl_nseg); 559 560 ata_channel_detach(chp); 561 port++; 562 } 563 564 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 565 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 566 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 567 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 568 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 569 570 if (adapt->adapt_refcnt != 0) 571 return EBUSY; 572 573 return 0; 574 } 575 576 void 577 ahci_resume(struct ahci_softc *sc) 578 { 579 ahci_reset(sc); 580 ahci_setup_ports(sc); 581 ahci_reprobe_drives(sc); 582 ahci_enable_intrs(sc); 583 } 584 585 int 586 ahci_intr(void *v) 587 { 588 struct ahci_softc *sc = v; 589 uint32_t is; 590 int i, r = 0; 591 592 while ((is = AHCI_READ(sc, AHCI_IS))) { 593 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 594 DEBUG_INTR); 595 r = 1; 596 AHCI_WRITE(sc, AHCI_IS, is); 597 for (i = 0; i < AHCI_MAX_PORTS; i++) 598 if (is & (1U << i)) 599 ahci_intr_port(&sc->sc_channels[i]); 600 } 601 602 return r; 603 } 604 605 int 606 ahci_intr_port(void *v) 607 { 608 struct ahci_channel *achp = v; 609 struct ata_channel *chp = &achp->ata_channel; 610 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 611 uint32_t is, tfd, sact; 612 struct ata_xfer *xfer; 613 int slot = -1; 614 bool recover = false; 615 uint32_t aslots; 616 617 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 618 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 619 620 AHCIDEBUG_PRINT(( 621 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 622 AHCINAME(sc), 623 chp->ch_channel, is, 624 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 625 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 626 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 627 DEBUG_INTR); 628 629 if ((chp->ch_flags & ATACH_NCQ) == 0) { 630 /* Non-NCQ operation */ 631 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 632 } else { 633 /* NCQ operation */ 634 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 635 } 636 637 /* Handle errors */ 638 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 639 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 640 /* Fatal errors */ 641 if (is & AHCI_P_IX_TFES) { 642 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 643 644 if ((chp->ch_flags & ATACH_NCQ) == 0) { 645 /* Slot valid only for Non-NCQ operation */ 646 slot = (AHCI_READ(sc, 647 AHCI_P_CMD(chp->ch_channel)) 648 & AHCI_P_CMD_CCS_MASK) 649 >> AHCI_P_CMD_CCS_SHIFT; 650 } 651 652 AHCIDEBUG_PRINT(( 653 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 654 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 655 DEBUG_INTR); 656 } else { 657 /* mark an error, and set BSY */ 658 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 659 WDCS_ERR | WDCS_BSY; 660 } 661 662 if (is & AHCI_P_IX_IFS) { 663 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 664 AHCINAME(sc), chp->ch_channel, 665 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 666 DEBUG_INTR); 667 } 668 669 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 670 recover = true; 671 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 672 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 673 674 /* D2H Register FIS or Set Device Bits */ 675 if ((tfd & WDCS_ERR) != 0) { 676 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 677 recover = true; 678 679 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 680 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 681 682 } 683 } else { 684 tfd = 0; 685 } 686 687 if (__predict_false(recover)) 688 ata_channel_freeze(chp); 689 690 aslots = ata_queue_active(chp); 691 692 if (slot >= 0) { 693 if ((aslots & __BIT(slot)) != 0 && 694 (sact & __BIT(slot)) == 0) { 695 xfer = ata_queue_hwslot_to_xfer(chp, slot); 696 xfer->ops->c_intr(chp, xfer, tfd); 697 } 698 } else { 699 /* 700 * For NCQ, HBA halts processing when error is notified, 701 * and any further D2H FISes are ignored until the error 702 * condition is cleared. Hence if a command is inactive, 703 * it means it actually already finished successfully. 704 * Note: active slots can change as c_intr() callback 705 * can activate another command(s), so must only process 706 * commands active before we start processing. 707 */ 708 709 for (slot=0; slot < sc->sc_ncmds; slot++) { 710 if ((aslots & __BIT(slot)) != 0 && 711 (sact & __BIT(slot)) == 0) { 712 xfer = ata_queue_hwslot_to_xfer(chp, slot); 713 xfer->ops->c_intr(chp, xfer, tfd); 714 } 715 } 716 } 717 718 if (__predict_false(recover)) { 719 ata_channel_lock(chp); 720 ata_channel_thaw_locked(chp); 721 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 722 ata_channel_unlock(chp); 723 } 724 725 return 1; 726 } 727 728 static void 729 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 730 { 731 struct ata_channel *chp = drvp->chnl_softc; 732 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 733 uint8_t c_slot; 734 735 ata_channel_lock_owned(chp); 736 737 /* get a slot for running the command on */ 738 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 739 panic("%s: %s: failed to get xfer for reset, port %d\n", 740 device_xname(sc->sc_atac.atac_dev), 741 __func__, chp->ch_channel); 742 /* NOTREACHED */ 743 } 744 745 AHCI_WRITE(sc, AHCI_GHC, 746 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 747 ahci_channel_stop(sc, chp, flags); 748 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 749 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 750 751 ata_queue_free_slot(chp, c_slot); 752 } 753 754 /* return error code from ata_bio */ 755 static int 756 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 757 { 758 struct ahci_channel *achp = (struct ahci_channel *)chp; 759 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 760 int i; 761 uint32_t is; 762 763 /* 764 * Base timeout is specified in ms. 765 * If we are allowed to sleep, wait a tick each round. 766 * Otherwise delay for 10ms on each round. 767 */ 768 if (flags & AT_WAIT) 769 timeout = MAX(1, mstohz(timeout)); 770 else 771 timeout = timeout / 10; 772 773 AHCI_CMDH_SYNC(sc, achp, slot, 774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 775 /* start command */ 776 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 777 for (i = 0; i < timeout; i++) { 778 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 779 0) 780 return 0; 781 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 782 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 783 AHCI_P_IX_IFS | 784 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 785 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 786 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 787 /* 788 * we got the D2H FIS anyway, 789 * assume sig is valid. 790 * channel is restarted later 791 */ 792 return ERROR; 793 } 794 aprint_debug("%s port %d: error 0x%x sending FIS\n", 795 AHCINAME(sc), chp->ch_channel, is); 796 return ERR_DF; 797 } 798 ata_delay(chp, 10, "ahcifis", flags); 799 } 800 801 aprint_debug("%s port %d: timeout sending FIS\n", 802 AHCINAME(sc), chp->ch_channel); 803 return TIMEOUT; 804 } 805 806 static int 807 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 808 uint32_t *sigp, uint8_t c_slot) 809 { 810 struct ahci_channel *achp = (struct ahci_channel *)chp; 811 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 812 struct ahci_cmd_tbl *cmd_tbl; 813 struct ahci_cmd_header *cmd_h; 814 int i, error = 0; 815 uint32_t sig, cmd; 816 int noclo_retry = 0; 817 818 ata_channel_lock_owned(chp); 819 820 again: 821 /* clear port interrupt register */ 822 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 823 /* clear SErrors and start operations */ 824 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 825 /* 826 * issue a command list override to clear BSY. 827 * This is needed if there's a PMP with no drive 828 * on port 0 829 */ 830 ahci_channel_start(sc, chp, flags, 1); 831 } else { 832 /* Can't handle command still running without CLO */ 833 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 834 if ((cmd & AHCI_P_CMD_CR) != 0) { 835 ahci_channel_stop(sc, chp, flags); 836 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 837 if ((cmd & AHCI_P_CMD_CR) != 0) { 838 aprint_error("%s port %d: DMA engine busy " 839 "for drive %d\n", AHCINAME(sc), 840 chp->ch_channel, drive); 841 error = EBUSY; 842 goto end; 843 } 844 } 845 846 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 847 848 ahci_channel_start(sc, chp, flags, 0); 849 } 850 if (drive > 0) { 851 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 852 } 853 854 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 855 goto skip_reset; 856 857 /* polled command, assume interrupts are disabled */ 858 859 cmd_h = &achp->ahcic_cmdh[c_slot]; 860 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 861 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 862 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 863 cmd_h->cmdh_prdbc = 0; 864 memset(cmd_tbl->cmdt_cfis, 0, 64); 865 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 866 cmd_tbl->cmdt_cfis[rhd_c] = drive; 867 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 868 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 869 case ERR_DF: 870 case TIMEOUT: 871 /* 872 * without CLO we can't make sure a software reset will 873 * success, as the drive may still have BSY or DRQ set. 874 * in this case, reset the whole channel and retry the 875 * drive reset. The channel reset should clear BSY and DRQ 876 */ 877 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 878 noclo_retry++; 879 ahci_reset_channel(chp, flags); 880 goto again; 881 } 882 aprint_error("%s port %d: setting WDCTL_RST failed " 883 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 884 error = EBUSY; 885 goto end; 886 default: 887 break; 888 } 889 890 /* 891 * SATA specification has toggle period for SRST bit of 5 usec. Some 892 * controllers fail to process the SRST clear operation unless 893 * we wait for at least this period between the set and clear commands. 894 */ 895 ata_delay(chp, 10, "ahcirstw", flags); 896 897 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 898 (drive << AHCI_CMDH_F_PMP_SHIFT)); 899 cmd_h->cmdh_prdbc = 0; 900 memset(cmd_tbl->cmdt_cfis, 0, 64); 901 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 902 cmd_tbl->cmdt_cfis[rhd_c] = drive; 903 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 904 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 905 case ERR_DF: 906 case TIMEOUT: 907 aprint_error("%s port %d: clearing WDCTL_RST failed " 908 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 909 error = EBUSY; 910 goto end; 911 default: 912 break; 913 } 914 915 skip_reset: 916 /* 917 * wait 31s for BSY to clear 918 * This should not be needed, but some controllers clear the 919 * command slot before receiving the D2H FIS ... 920 */ 921 for (i = 0; i < AHCI_RST_WAIT; i++) { 922 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 923 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 924 break; 925 ata_delay(chp, 10, "ahcid2h", flags); 926 } 927 if (i == AHCI_RST_WAIT) { 928 aprint_error("%s: BSY never cleared, TD 0x%x\n", 929 AHCINAME(sc), sig); 930 goto end; 931 } 932 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 933 DEBUG_PROBE); 934 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 935 if (sigp) 936 *sigp = sig; 937 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 938 AHCINAME(sc), chp->ch_channel, sig, 939 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 940 end: 941 ahci_channel_stop(sc, chp, flags); 942 ata_delay(chp, 500, "ahcirst", flags); 943 /* clear port interrupt register */ 944 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 945 ahci_channel_start(sc, chp, flags, 946 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 947 return error; 948 } 949 950 static void 951 ahci_reset_channel(struct ata_channel *chp, int flags) 952 { 953 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 954 struct ahci_channel *achp = (struct ahci_channel *)chp; 955 int i, tfd; 956 957 ata_channel_lock_owned(chp); 958 959 ahci_channel_stop(sc, chp, flags); 960 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 961 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 962 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 963 /* XXX and then ? */ 964 } 965 ata_kill_active(chp, KILL_RESET, flags); 966 ata_delay(chp, 500, "ahcirst", flags); 967 /* clear port interrupt register */ 968 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 969 /* clear SErrors and start operations */ 970 ahci_channel_start(sc, chp, flags, 971 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 972 /* wait 31s for BSY to clear */ 973 for (i = 0; i < AHCI_RST_WAIT; i++) { 974 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 975 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 976 break; 977 ata_delay(chp, 10, "ahcid2h", flags); 978 } 979 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 980 aprint_error("%s: BSY never cleared, TD 0x%x\n", 981 AHCINAME(sc), tfd); 982 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 983 DEBUG_PROBE); 984 /* clear port interrupt register */ 985 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 986 987 return; 988 } 989 990 static int 991 ahci_ata_addref(struct ata_drive_datas *drvp) 992 { 993 return 0; 994 } 995 996 static void 997 ahci_ata_delref(struct ata_drive_datas *drvp) 998 { 999 return; 1000 } 1001 1002 static void 1003 ahci_killpending(struct ata_drive_datas *drvp) 1004 { 1005 return; 1006 } 1007 1008 static void 1009 ahci_probe_drive(struct ata_channel *chp) 1010 { 1011 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1012 struct ahci_channel *achp = (struct ahci_channel *)chp; 1013 uint32_t sig; 1014 uint8_t c_slot; 1015 int error; 1016 1017 ata_channel_lock(chp); 1018 1019 /* get a slot for running the command on */ 1020 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1021 aprint_error_dev(sc->sc_atac.atac_dev, 1022 "%s: failed to get xfer port %d\n", 1023 __func__, chp->ch_channel); 1024 ata_channel_unlock(chp); 1025 return; 1026 } 1027 1028 /* bring interface up, accept FISs, power up and spin up device */ 1029 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1030 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1031 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1032 /* reset the PHY and bring online */ 1033 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1034 achp->ahcic_sstatus, AT_WAIT)) { 1035 case SStatus_DET_DEV: 1036 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1037 1038 /* Initial value, used in case the soft reset fails */ 1039 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1040 1041 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1042 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1043 &sig, c_slot); 1044 1045 /* If probe for PMP failed, just fallback to drive 0 */ 1046 if (error) { 1047 aprint_error("%s port %d: drive %d reset " 1048 "failed, disabling PMP\n", 1049 AHCINAME(sc), chp->ch_channel, 1050 PMP_PORT_CTL); 1051 1052 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1053 ahci_reset_channel(chp, AT_WAIT); 1054 } 1055 } else { 1056 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1057 } 1058 sata_interpret_sig(chp, 0, sig); 1059 /* if we have a PMP attached, inform the controller */ 1060 if (chp->ch_ndrives > PMP_PORT_CTL && 1061 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1062 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1063 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1064 AHCI_P_CMD_PMA); 1065 } 1066 /* clear port interrupt register */ 1067 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1068 1069 /* and enable interrupts */ 1070 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1071 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1072 AHCI_P_IX_IFS | 1073 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1074 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1075 /* wait 500ms before actually starting operations */ 1076 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1077 break; 1078 1079 default: 1080 break; 1081 } 1082 1083 ata_queue_free_slot(chp, c_slot); 1084 1085 ata_channel_unlock(chp); 1086 } 1087 1088 static void 1089 ahci_setup_channel(struct ata_channel *chp) 1090 { 1091 return; 1092 } 1093 1094 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1095 .c_start = ahci_cmd_start, 1096 .c_poll = ahci_cmd_poll, 1097 .c_abort = ahci_cmd_abort, 1098 .c_intr = ahci_cmd_complete, 1099 .c_kill_xfer = ahci_cmd_kill_xfer, 1100 }; 1101 1102 static int 1103 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1104 { 1105 struct ata_channel *chp = drvp->chnl_softc; 1106 struct ata_command *ata_c = &xfer->c_ata_c; 1107 int ret; 1108 int s; 1109 1110 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1111 chp->ch_channel, 1112 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1113 DEBUG_XFERS); 1114 if (ata_c->flags & AT_POLL) 1115 xfer->c_flags |= C_POLL; 1116 if (ata_c->flags & AT_WAIT) 1117 xfer->c_flags |= C_WAIT; 1118 xfer->c_drive = drvp->drive; 1119 xfer->c_databuf = ata_c->data; 1120 xfer->c_bcount = ata_c->bcount; 1121 xfer->ops = &ahci_cmd_xfer_ops; 1122 s = splbio(); 1123 ata_exec_xfer(chp, xfer); 1124 #ifdef DIAGNOSTIC 1125 if ((ata_c->flags & AT_POLL) != 0 && 1126 (ata_c->flags & AT_DONE) == 0) 1127 panic("ahci_exec_command: polled command not done"); 1128 #endif 1129 if (ata_c->flags & AT_DONE) { 1130 ret = ATACMD_COMPLETE; 1131 } else { 1132 if (ata_c->flags & AT_WAIT) { 1133 ata_wait_cmd(chp, xfer); 1134 ret = ATACMD_COMPLETE; 1135 } else { 1136 ret = ATACMD_QUEUED; 1137 } 1138 } 1139 splx(s); 1140 return ret; 1141 } 1142 1143 static int 1144 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1145 { 1146 struct ahci_softc *sc = AHCI_CH2SC(chp); 1147 struct ahci_channel *achp = (struct ahci_channel *)chp; 1148 struct ata_command *ata_c = &xfer->c_ata_c; 1149 int slot = xfer->c_slot; 1150 struct ahci_cmd_tbl *cmd_tbl; 1151 struct ahci_cmd_header *cmd_h; 1152 1153 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1154 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1155 ata_c->timeout, slot), 1156 DEBUG_XFERS); 1157 1158 ata_channel_lock_owned(chp); 1159 1160 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1161 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1162 cmd_tbl), DEBUG_XFERS); 1163 1164 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1165 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1166 1167 cmd_h = &achp->ahcic_cmdh[slot]; 1168 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1169 chp->ch_channel, cmd_h), DEBUG_XFERS); 1170 if (ahci_dma_setup(chp, slot, 1171 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1172 ata_c->data : NULL, 1173 ata_c->bcount, 1174 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1175 ata_c->flags |= AT_DF; 1176 return ATASTART_ABORT; 1177 } 1178 cmd_h->cmdh_flags = htole16( 1179 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1180 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1181 cmd_h->cmdh_prdbc = 0; 1182 AHCI_CMDH_SYNC(sc, achp, slot, 1183 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1184 1185 if (ata_c->flags & AT_POLL) { 1186 /* polled command, disable interrupts */ 1187 AHCI_WRITE(sc, AHCI_GHC, 1188 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1189 } 1190 /* start command */ 1191 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1192 1193 if ((ata_c->flags & AT_POLL) == 0) { 1194 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1195 ata_timeout, chp); 1196 return ATASTART_STARTED; 1197 } else 1198 return ATASTART_POLL; 1199 } 1200 1201 static void 1202 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1203 { 1204 struct ahci_softc *sc = AHCI_CH2SC(chp); 1205 struct ahci_channel *achp = (struct ahci_channel *)chp; 1206 1207 ata_channel_lock(chp); 1208 1209 /* 1210 * Polled command. 1211 */ 1212 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1213 if (xfer->c_ata_c.flags & AT_DONE) 1214 break; 1215 ata_channel_unlock(chp); 1216 ahci_intr_port(achp); 1217 ata_channel_lock(chp); 1218 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1219 } 1220 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1221 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1222 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1223 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1224 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1225 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1226 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1227 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1228 DEBUG_XFERS); 1229 1230 ata_channel_unlock(chp); 1231 1232 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1233 xfer->c_ata_c.flags |= AT_TIMEOU; 1234 xfer->ops->c_intr(chp, xfer, 0); 1235 } 1236 /* reenable interrupts */ 1237 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1238 } 1239 1240 static void 1241 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1242 { 1243 ahci_cmd_complete(chp, xfer, 0); 1244 } 1245 1246 static void 1247 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1248 { 1249 struct ata_command *ata_c = &xfer->c_ata_c; 1250 bool deactivate = true; 1251 1252 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1253 DEBUG_FUNCS); 1254 1255 switch (reason) { 1256 case KILL_GONE_INACTIVE: 1257 deactivate = false; 1258 /* FALLTHROUGH */ 1259 case KILL_GONE: 1260 ata_c->flags |= AT_GONE; 1261 break; 1262 case KILL_RESET: 1263 ata_c->flags |= AT_RESET; 1264 break; 1265 case KILL_REQUEUE: 1266 panic("%s: not supposed to be requeued\n", __func__); 1267 break; 1268 default: 1269 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1270 panic("ahci_cmd_kill_xfer"); 1271 } 1272 1273 ahci_cmd_done_end(chp, xfer); 1274 1275 if (deactivate) 1276 ata_deactivate_xfer(chp, xfer); 1277 } 1278 1279 static int 1280 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1281 { 1282 struct ata_command *ata_c = &xfer->c_ata_c; 1283 struct ahci_channel *achp = (struct ahci_channel *)chp; 1284 1285 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1286 chp->ch_channel, 1287 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1288 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1289 DEBUG_FUNCS); 1290 1291 if (ata_waitdrain_xfer_check(chp, xfer)) 1292 return 0; 1293 1294 if (xfer->c_flags & C_TIMEOU) { 1295 ata_c->flags |= AT_TIMEOU; 1296 } 1297 1298 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1299 ata_c->flags |= AT_TIMEOU; 1300 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1301 ata_c->r_error = AHCI_TFD_ERR(tfd); 1302 ata_c->flags |= AT_ERROR; 1303 } 1304 1305 if (ata_c->flags & AT_READREG) 1306 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1307 1308 ahci_cmd_done(chp, xfer); 1309 1310 ata_deactivate_xfer(chp, xfer); 1311 1312 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1313 atastart(chp); 1314 1315 return 0; 1316 } 1317 1318 static void 1319 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1320 { 1321 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1322 struct ahci_channel *achp = (struct ahci_channel *)chp; 1323 struct ata_command *ata_c = &xfer->c_ata_c; 1324 uint16_t *idwordbuf; 1325 int i; 1326 1327 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1328 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1329 1330 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1331 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1332 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1333 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1334 BUS_DMASYNC_POSTWRITE); 1335 bus_dmamap_unload(sc->sc_dmat, map); 1336 } 1337 1338 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1339 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1340 1341 /* ata(4) expects IDENTIFY data to be in host endianess */ 1342 if (ata_c->r_command == WDCC_IDENTIFY || 1343 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1344 idwordbuf = xfer->c_databuf; 1345 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1346 idwordbuf[i] = le16toh(idwordbuf[i]); 1347 } 1348 } 1349 1350 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1351 ata_c->flags |= AT_XFDONE; 1352 1353 ahci_cmd_done_end(chp, xfer); 1354 } 1355 1356 static void 1357 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1358 { 1359 struct ata_command *ata_c = &xfer->c_ata_c; 1360 1361 ata_c->flags |= AT_DONE; 1362 } 1363 1364 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1365 .c_start = ahci_bio_start, 1366 .c_poll = ahci_bio_poll, 1367 .c_abort = ahci_bio_abort, 1368 .c_intr = ahci_bio_complete, 1369 .c_kill_xfer = ahci_bio_kill_xfer, 1370 }; 1371 1372 static int 1373 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1374 { 1375 struct ata_channel *chp = drvp->chnl_softc; 1376 struct ata_bio *ata_bio = &xfer->c_bio; 1377 1378 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1379 chp->ch_channel, 1380 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1381 DEBUG_XFERS); 1382 if (ata_bio->flags & ATA_POLL) 1383 xfer->c_flags |= C_POLL; 1384 xfer->c_drive = drvp->drive; 1385 xfer->c_databuf = ata_bio->databuf; 1386 xfer->c_bcount = ata_bio->bcount; 1387 xfer->ops = &ahci_bio_xfer_ops; 1388 ata_exec_xfer(chp, xfer); 1389 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1390 } 1391 1392 static int 1393 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1394 { 1395 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1396 struct ahci_channel *achp = (struct ahci_channel *)chp; 1397 struct ata_bio *ata_bio = &xfer->c_bio; 1398 struct ahci_cmd_tbl *cmd_tbl; 1399 struct ahci_cmd_header *cmd_h; 1400 1401 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1402 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1403 1404 ata_channel_lock_owned(chp); 1405 1406 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1407 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1408 cmd_tbl), DEBUG_XFERS); 1409 1410 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1411 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1412 1413 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1414 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1415 chp->ch_channel, cmd_h), DEBUG_XFERS); 1416 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1417 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1418 ata_bio->error = ERR_DMA; 1419 ata_bio->r_error = 0; 1420 return ATASTART_ABORT; 1421 } 1422 cmd_h->cmdh_flags = htole16( 1423 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1424 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1425 cmd_h->cmdh_prdbc = 0; 1426 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1427 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1428 1429 if (xfer->c_flags & C_POLL) { 1430 /* polled command, disable interrupts */ 1431 AHCI_WRITE(sc, AHCI_GHC, 1432 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1433 } 1434 if (xfer->c_flags & C_NCQ) 1435 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1436 /* start command */ 1437 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1438 1439 if ((xfer->c_flags & C_POLL) == 0) { 1440 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1441 ata_timeout, chp); 1442 return ATASTART_STARTED; 1443 } else 1444 return ATASTART_POLL; 1445 } 1446 1447 static void 1448 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1449 { 1450 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1451 struct ahci_channel *achp = (struct ahci_channel *)chp; 1452 1453 /* 1454 * Polled command. 1455 */ 1456 for (int i = 0; i < ATA_DELAY * 10; i++) { 1457 if (xfer->c_bio.flags & ATA_ITSDONE) 1458 break; 1459 ahci_intr_port(achp); 1460 delay(100); 1461 } 1462 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1463 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1464 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1465 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1466 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1467 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1468 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1469 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1470 DEBUG_XFERS); 1471 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1472 xfer->c_bio.error = TIMEOUT; 1473 xfer->ops->c_intr(chp, xfer, 0); 1474 } 1475 /* reenable interrupts */ 1476 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1477 } 1478 1479 static void 1480 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1481 { 1482 ahci_bio_complete(chp, xfer, 0); 1483 } 1484 1485 static void 1486 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1487 { 1488 int drive = xfer->c_drive; 1489 struct ata_bio *ata_bio = &xfer->c_bio; 1490 bool deactivate = true; 1491 1492 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1493 DEBUG_FUNCS); 1494 1495 ata_bio->flags |= ATA_ITSDONE; 1496 switch (reason) { 1497 case KILL_GONE_INACTIVE: 1498 deactivate = false; 1499 /* FALLTHROUGH */ 1500 case KILL_GONE: 1501 ata_bio->error = ERR_NODEV; 1502 break; 1503 case KILL_RESET: 1504 ata_bio->error = ERR_RESET; 1505 break; 1506 case KILL_REQUEUE: 1507 ata_bio->error = REQUEUE; 1508 break; 1509 default: 1510 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1511 panic("ahci_bio_kill_xfer"); 1512 } 1513 ata_bio->r_error = WDCE_ABRT; 1514 1515 if (deactivate) 1516 ata_deactivate_xfer(chp, xfer); 1517 1518 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1519 } 1520 1521 static int 1522 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1523 { 1524 struct ata_bio *ata_bio = &xfer->c_bio; 1525 int drive = xfer->c_drive; 1526 struct ahci_channel *achp = (struct ahci_channel *)chp; 1527 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1528 1529 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1530 DEBUG_FUNCS); 1531 1532 if (ata_waitdrain_xfer_check(chp, xfer)) 1533 return 0; 1534 1535 if (xfer->c_flags & C_TIMEOU) { 1536 ata_bio->error = TIMEOUT; 1537 } 1538 1539 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1540 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1541 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1542 BUS_DMASYNC_POSTWRITE); 1543 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1544 1545 ata_bio->flags |= ATA_ITSDONE; 1546 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1547 ata_bio->error = ERR_DF; 1548 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1549 ata_bio->error = ERROR; 1550 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1551 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1552 ata_bio->flags |= ATA_CORR; 1553 1554 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1555 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1556 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1557 ata_bio->bcount), DEBUG_XFERS); 1558 /* 1559 * If it was a write, complete data buffer may have been transferred 1560 * before error detection; in this case don't use cmdh_prdbc 1561 * as it won't reflect what was written to media. Assume nothing 1562 * was transferred and leave bcount as-is. 1563 * For queued commands, PRD Byte Count should not be used, and is 1564 * not required to be valid; in that case underflow is always illegal. 1565 */ 1566 if ((xfer->c_flags & C_NCQ) != 0) { 1567 if (ata_bio->error == NOERROR) 1568 ata_bio->bcount = 0; 1569 } else { 1570 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1571 ata_bio->bcount -= 1572 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1573 } 1574 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1575 1576 ata_deactivate_xfer(chp, xfer); 1577 1578 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1579 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1580 atastart(chp); 1581 return 0; 1582 } 1583 1584 static void 1585 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1586 { 1587 int i; 1588 /* stop channel */ 1589 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1590 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1591 /* wait 1s for channel to stop */ 1592 for (i = 0; i <100; i++) { 1593 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1594 == 0) 1595 break; 1596 ata_delay(chp, 10, "ahcistop", flags); 1597 } 1598 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1599 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1600 /* XXX controller reset ? */ 1601 return; 1602 } 1603 1604 if (sc->sc_channel_stop) 1605 sc->sc_channel_stop(sc, chp); 1606 } 1607 1608 static void 1609 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1610 int flags, int clo) 1611 { 1612 int i; 1613 uint32_t p_cmd; 1614 /* clear error */ 1615 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1616 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1617 1618 if (clo) { 1619 /* issue command list override */ 1620 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1621 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1622 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1623 /* wait 1s for AHCI_CAP_CLO to clear */ 1624 for (i = 0; i <100; i++) { 1625 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1626 AHCI_P_CMD_CLO) == 0) 1627 break; 1628 ata_delay(chp, 10, "ahciclo", flags); 1629 } 1630 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1631 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1632 /* XXX controller reset ? */ 1633 return; 1634 } 1635 } 1636 1637 if (sc->sc_channel_start) 1638 sc->sc_channel_start(sc, chp); 1639 1640 /* and start controller */ 1641 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1642 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1643 if (chp->ch_ndrives > PMP_PORT_CTL && 1644 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1645 p_cmd |= AHCI_P_CMD_PMA; 1646 } 1647 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1648 } 1649 1650 /* Recover channel after command failure */ 1651 static void 1652 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1653 { 1654 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1655 int drive = ATACH_NODRIVE; 1656 bool reset = false; 1657 1658 ata_channel_lock_owned(chp); 1659 1660 /* 1661 * Read FBS to get the drive which caused the error, if PM is in use. 1662 * According to AHCI 1.3 spec, this register is available regardless 1663 * if FIS-based switching (FBSS) feature is supported, or disabled. 1664 * If FIS-based switching is not in use, it merely maintains single 1665 * pair of DRQ/BSY state, but it is enough since in that case we 1666 * never issue commands for more than one device at the time anyway. 1667 * XXX untested 1668 */ 1669 if (chp->ch_ndrives > PMP_PORT_CTL) { 1670 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1671 if (fbs & AHCI_P_FBS_SDE) { 1672 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1673 1674 /* 1675 * Tell HBA to reset PM port X (value in DWE) state, 1676 * and resume processing commands for other ports. 1677 */ 1678 fbs |= AHCI_P_FBS_DEC; 1679 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1680 for (int i = 0; i < 1000; i++) { 1681 fbs = AHCI_READ(sc, 1682 AHCI_P_FBS(chp->ch_channel)); 1683 if ((fbs & AHCI_P_FBS_DEC) == 0) 1684 break; 1685 DELAY(1000); 1686 } 1687 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1688 /* follow non-device specific recovery */ 1689 drive = ATACH_NODRIVE; 1690 reset = true; 1691 } 1692 } else { 1693 /* not device specific, reset channel */ 1694 drive = ATACH_NODRIVE; 1695 reset = true; 1696 } 1697 } else 1698 drive = 0; 1699 1700 /* 1701 * If BSY or DRQ bits are set, must execute COMRESET to return 1702 * device to idle state. If drive is idle, it's enough to just 1703 * reset CMD.ST, it's not necessary to do software reset. 1704 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1705 * to unblock device processing if COMRESET was not done. 1706 */ 1707 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1708 ahci_reset_channel(chp, flags); 1709 goto out; 1710 } 1711 1712 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1713 ahci_channel_stop(sc, chp, flags); 1714 ahci_channel_start(sc, chp, flags, 1715 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1716 1717 ata_recovery_resume(chp, drive, tfd, flags); 1718 1719 out: 1720 /* Drive unblocked, back to normal operation */ 1721 return; 1722 } 1723 1724 static int 1725 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1726 size_t count, int op) 1727 { 1728 int error, seg; 1729 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1730 struct ahci_channel *achp = (struct ahci_channel *)chp; 1731 struct ahci_cmd_tbl *cmd_tbl; 1732 struct ahci_cmd_header *cmd_h; 1733 1734 cmd_h = &achp->ahcic_cmdh[slot]; 1735 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1736 1737 if (data == NULL) { 1738 cmd_h->cmdh_prdtl = 0; 1739 goto end; 1740 } 1741 1742 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1743 data, count, NULL, 1744 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1745 if (error) { 1746 printf("%s port %d: failed to load xfer: %d\n", 1747 AHCINAME(sc), chp->ch_channel, error); 1748 return error; 1749 } 1750 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1751 achp->ahcic_datad[slot]->dm_mapsize, 1752 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1753 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1754 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1755 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1756 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1757 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1758 } 1759 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1760 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1761 end: 1762 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1763 return 0; 1764 } 1765 1766 #if NATAPIBUS > 0 1767 static void 1768 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1769 { 1770 struct ata_channel *chp = ata_sc->sc_chan; 1771 struct atac_softc *atac = chp->ch_atac; 1772 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1773 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1774 /* 1775 * Fill in the scsipi_adapter. 1776 */ 1777 adapt->adapt_dev = atac->atac_dev; 1778 adapt->adapt_nchannels = atac->atac_nchannels; 1779 adapt->adapt_request = ahci_atapi_scsipi_request; 1780 adapt->adapt_minphys = ahci_atapi_minphys; 1781 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1782 1783 /* 1784 * Fill in the scsipi_channel. 1785 */ 1786 memset(chan, 0, sizeof(*chan)); 1787 chan->chan_adapter = adapt; 1788 chan->chan_bustype = &ahci_atapi_bustype; 1789 chan->chan_channel = chp->ch_channel; 1790 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1791 chan->chan_openings = 1; 1792 chan->chan_max_periph = 1; 1793 chan->chan_ntargets = 1; 1794 chan->chan_nluns = 1; 1795 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1796 atapiprint); 1797 } 1798 1799 static void 1800 ahci_atapi_minphys(struct buf *bp) 1801 { 1802 if (bp->b_bcount > MAXPHYS) 1803 bp->b_bcount = MAXPHYS; 1804 minphys(bp); 1805 } 1806 1807 /* 1808 * Kill off all pending xfers for a periph. 1809 * 1810 * Must be called at splbio(). 1811 */ 1812 static void 1813 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1814 { 1815 struct atac_softc *atac = 1816 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1817 struct ata_channel *chp = 1818 atac->atac_channels[periph->periph_channel->chan_channel]; 1819 1820 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1821 } 1822 1823 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1824 .c_start = ahci_atapi_start, 1825 .c_poll = ahci_atapi_poll, 1826 .c_abort = ahci_atapi_abort, 1827 .c_intr = ahci_atapi_complete, 1828 .c_kill_xfer = ahci_atapi_kill_xfer, 1829 }; 1830 1831 static void 1832 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1833 scsipi_adapter_req_t req, void *arg) 1834 { 1835 struct scsipi_adapter *adapt = chan->chan_adapter; 1836 struct scsipi_periph *periph; 1837 struct scsipi_xfer *sc_xfer; 1838 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1839 struct atac_softc *atac = &sc->sc_atac; 1840 struct ata_xfer *xfer; 1841 int channel = chan->chan_channel; 1842 int drive, s; 1843 1844 switch (req) { 1845 case ADAPTER_REQ_RUN_XFER: 1846 sc_xfer = arg; 1847 periph = sc_xfer->xs_periph; 1848 drive = periph->periph_target; 1849 if (!device_is_active(atac->atac_dev)) { 1850 sc_xfer->error = XS_DRIVER_STUFFUP; 1851 scsipi_done(sc_xfer); 1852 return; 1853 } 1854 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1855 if (xfer == NULL) { 1856 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1857 scsipi_done(sc_xfer); 1858 return; 1859 } 1860 1861 if (sc_xfer->xs_control & XS_CTL_POLL) 1862 xfer->c_flags |= C_POLL; 1863 xfer->c_drive = drive; 1864 xfer->c_flags |= C_ATAPI; 1865 xfer->c_databuf = sc_xfer->data; 1866 xfer->c_bcount = sc_xfer->datalen; 1867 xfer->ops = &ahci_atapi_xfer_ops; 1868 xfer->c_scsipi = sc_xfer; 1869 xfer->c_atapi.c_dscpoll = 0; 1870 s = splbio(); 1871 ata_exec_xfer(atac->atac_channels[channel], xfer); 1872 #ifdef DIAGNOSTIC 1873 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1874 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1875 panic("ahci_atapi_scsipi_request: polled command " 1876 "not done"); 1877 #endif 1878 splx(s); 1879 return; 1880 default: 1881 /* Not supported, nothing to do. */ 1882 ; 1883 } 1884 } 1885 1886 static int 1887 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1888 { 1889 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1890 struct ahci_channel *achp = (struct ahci_channel *)chp; 1891 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1892 struct ahci_cmd_tbl *cmd_tbl; 1893 struct ahci_cmd_header *cmd_h; 1894 1895 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1896 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1897 1898 ata_channel_lock_owned(chp); 1899 1900 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1901 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1902 cmd_tbl), DEBUG_XFERS); 1903 1904 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1905 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1906 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1907 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1908 1909 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1910 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1911 chp->ch_channel, cmd_h), DEBUG_XFERS); 1912 if (ahci_dma_setup(chp, xfer->c_slot, 1913 sc_xfer->datalen ? sc_xfer->data : NULL, 1914 sc_xfer->datalen, 1915 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1916 BUS_DMA_READ : BUS_DMA_WRITE)) { 1917 sc_xfer->error = XS_DRIVER_STUFFUP; 1918 return ATASTART_ABORT; 1919 } 1920 cmd_h->cmdh_flags = htole16( 1921 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1922 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1923 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1924 cmd_h->cmdh_prdbc = 0; 1925 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1927 1928 if (xfer->c_flags & C_POLL) { 1929 /* polled command, disable interrupts */ 1930 AHCI_WRITE(sc, AHCI_GHC, 1931 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1932 } 1933 /* start command */ 1934 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1935 1936 if ((xfer->c_flags & C_POLL) == 0) { 1937 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1938 ata_timeout, chp); 1939 return ATASTART_STARTED; 1940 } else 1941 return ATASTART_POLL; 1942 } 1943 1944 static void 1945 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1946 { 1947 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1948 struct ahci_channel *achp = (struct ahci_channel *)chp; 1949 1950 /* 1951 * Polled command. 1952 */ 1953 for (int i = 0; i < ATA_DELAY / 10; i++) { 1954 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1955 break; 1956 ahci_intr_port(achp); 1957 delay(10000); 1958 } 1959 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1960 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1961 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1962 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1963 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1964 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1965 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1966 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1967 DEBUG_XFERS); 1968 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1969 xfer->c_scsipi->error = XS_TIMEOUT; 1970 xfer->ops->c_intr(chp, xfer, 0); 1971 } 1972 /* reenable interrupts */ 1973 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1974 } 1975 1976 static void 1977 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1978 { 1979 ahci_atapi_complete(chp, xfer, 0); 1980 } 1981 1982 static int 1983 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1984 { 1985 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1986 struct ahci_channel *achp = (struct ahci_channel *)chp; 1987 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1988 1989 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1990 DEBUG_FUNCS); 1991 1992 if (ata_waitdrain_xfer_check(chp, xfer)) 1993 return 0; 1994 1995 if (xfer->c_flags & C_TIMEOU) { 1996 sc_xfer->error = XS_TIMEOUT; 1997 } 1998 1999 if (xfer->c_bcount > 0) { 2000 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2001 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2002 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2003 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2004 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2005 } 2006 2007 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2009 sc_xfer->resid = sc_xfer->datalen; 2010 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2011 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2012 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2013 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2014 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2015 sc_xfer->resid == sc_xfer->datalen)) { 2016 sc_xfer->error = XS_SHORTSENSE; 2017 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2018 if ((sc_xfer->xs_periph->periph_quirks & 2019 PQUIRK_NOSENSE) == 0) { 2020 /* ask scsipi to send a REQUEST_SENSE */ 2021 sc_xfer->error = XS_BUSY; 2022 sc_xfer->status = SCSI_CHECK; 2023 } 2024 } 2025 2026 ata_deactivate_xfer(chp, xfer); 2027 2028 ata_free_xfer(chp, xfer); 2029 scsipi_done(sc_xfer); 2030 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2031 atastart(chp); 2032 return 0; 2033 } 2034 2035 static void 2036 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2037 { 2038 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2039 bool deactivate = true; 2040 2041 /* remove this command from xfer queue */ 2042 switch (reason) { 2043 case KILL_GONE_INACTIVE: 2044 deactivate = false; 2045 /* FALLTHROUGH */ 2046 case KILL_GONE: 2047 sc_xfer->error = XS_DRIVER_STUFFUP; 2048 break; 2049 case KILL_RESET: 2050 sc_xfer->error = XS_RESET; 2051 break; 2052 case KILL_REQUEUE: 2053 sc_xfer->error = XS_REQUEUE; 2054 break; 2055 default: 2056 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2057 panic("ahci_ata_atapi_kill_xfer"); 2058 } 2059 2060 if (deactivate) 2061 ata_deactivate_xfer(chp, xfer); 2062 2063 ata_free_xfer(chp, xfer); 2064 scsipi_done(sc_xfer); 2065 } 2066 2067 static void 2068 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2069 { 2070 struct scsipi_channel *chan = sc->sc_channel; 2071 struct scsipi_periph *periph; 2072 struct ataparams ids; 2073 struct ataparams *id = &ids; 2074 struct ahci_softc *ahcic = 2075 device_private(chan->chan_adapter->adapt_dev); 2076 struct atac_softc *atac = &ahcic->sc_atac; 2077 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2078 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2079 struct scsipibus_attach_args sa; 2080 char serial_number[21], model[41], firmware_revision[9]; 2081 int s; 2082 2083 /* skip if already attached */ 2084 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2085 return; 2086 2087 /* if no ATAPI device detected at attach time, skip */ 2088 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2089 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2090 "not present\n", target), DEBUG_PROBE); 2091 return; 2092 } 2093 2094 /* Some ATAPI devices need a bit more time after software reset. */ 2095 delay(5000); 2096 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2097 #ifdef ATAPI_DEBUG_PROBE 2098 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2099 AHCINAME(ahcic), target, 2100 id->atap_config & ATAPI_CFG_CMD_MASK, 2101 id->atap_config & ATAPI_CFG_DRQ_MASK); 2102 #endif 2103 periph = scsipi_alloc_periph(M_NOWAIT); 2104 if (periph == NULL) { 2105 aprint_error_dev(sc->sc_dev, 2106 "unable to allocate periph for drive %d\n", 2107 target); 2108 return; 2109 } 2110 periph->periph_dev = NULL; 2111 periph->periph_channel = chan; 2112 periph->periph_switch = &atapi_probe_periphsw; 2113 periph->periph_target = target; 2114 periph->periph_lun = 0; 2115 periph->periph_quirks = PQUIRK_ONLYBIG; 2116 2117 #ifdef SCSIPI_DEBUG 2118 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2119 SCSIPI_DEBUG_TARGET == target) 2120 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2121 #endif 2122 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2123 if (id->atap_config & ATAPI_CFG_REMOV) 2124 periph->periph_flags |= PERIPH_REMOVABLE; 2125 if (periph->periph_type == T_SEQUENTIAL) { 2126 s = splbio(); 2127 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2128 splx(s); 2129 } 2130 2131 sa.sa_periph = periph; 2132 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2133 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2134 T_REMOV : T_FIXED; 2135 strnvisx(model, sizeof(model), id->atap_model, 40, 2136 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2137 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2138 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2139 strnvisx(firmware_revision, sizeof(firmware_revision), 2140 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2141 sa.sa_inqbuf.vendor = model; 2142 sa.sa_inqbuf.product = serial_number; 2143 sa.sa_inqbuf.revision = firmware_revision; 2144 2145 /* 2146 * Determine the operating mode capabilities of the device. 2147 */ 2148 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2149 periph->periph_cap |= PERIPH_CAP_CMD16; 2150 /* XXX This is gross. */ 2151 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2152 2153 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2154 2155 if (drvp->drv_softc) 2156 ata_probe_caps(drvp); 2157 else { 2158 s = splbio(); 2159 drvp->drive_type = ATA_DRIVET_NONE; 2160 splx(s); 2161 } 2162 } else { 2163 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2164 "failed for drive %s:%d:%d\n", 2165 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2166 s = splbio(); 2167 drvp->drive_type = ATA_DRIVET_NONE; 2168 splx(s); 2169 } 2170 } 2171 #endif /* NATAPIBUS */ 2172
Indexes created Fri Oct 17 00:09:41 GMT 2025