ahcisata_core.c revision 1.62
1 /* $NetBSD: ahcisata_core.c,v 1.62 2018/07/09 10:44:44 kamil Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.62 2018/07/09 10:44:44 kamil Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 struct ata_xfer *xfer); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 void ahci_channel_recover(struct ahci_softc *, struct ata_channel *, int); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending 125 }; 126 127 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 return 0; 170 } 171 172 static void 173 ahci_setup_ports(struct ahci_softc *sc) 174 { 175 int i, port; 176 177 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 178 if ((sc->sc_ahci_ports & (1U << i)) == 0) 179 continue; 180 if (port >= sc->sc_atac.atac_nchannels) { 181 aprint_error("%s: more ports than announced\n", 182 AHCINAME(sc)); 183 break; 184 } 185 ahci_setup_port(sc, i); 186 } 187 } 188 189 static void 190 ahci_reprobe_drives(struct ahci_softc *sc) 191 { 192 int i, port; 193 struct ahci_channel *achp; 194 struct ata_channel *chp; 195 196 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 197 if ((sc->sc_ahci_ports & (1U << i)) == 0) 198 continue; 199 if (port >= sc->sc_atac.atac_nchannels) { 200 aprint_error("%s: more ports than announced\n", 201 AHCINAME(sc)); 202 break; 203 } 204 achp = &sc->sc_channels[i]; 205 chp = &achp->ata_channel; 206 207 ahci_probe_drive(chp); 208 } 209 } 210 211 static void 212 ahci_setup_port(struct ahci_softc *sc, int i) 213 { 214 struct ahci_channel *achp; 215 216 achp = &sc->sc_channels[i]; 217 218 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 219 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 220 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 221 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 222 } 223 224 static void 225 ahci_enable_intrs(struct ahci_softc *sc) 226 { 227 228 /* clear interrupts */ 229 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 230 /* enable interrupts */ 231 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 232 } 233 234 void 235 ahci_attach(struct ahci_softc *sc) 236 { 237 uint32_t ahci_rev; 238 int i, j, port; 239 struct ahci_channel *achp; 240 struct ata_channel *chp; 241 int error; 242 int dmasize; 243 char buf[128]; 244 void *cmdhp; 245 void *cmdtblp; 246 247 if (sc->sc_save_init_data) { 248 ahci_enable(sc); 249 250 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 251 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 252 253 ahci_rev = AHCI_READ(sc, AHCI_VS); 254 if (AHCI_VS_MJR(ahci_rev) > 1 || 255 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 256 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 257 } else { 258 sc->sc_init_data.cap2 = 0; 259 } 260 if (sc->sc_init_data.ports == 0) { 261 sc->sc_init_data.ports = sc->sc_ahci_ports; 262 } 263 } 264 265 if (ahci_reset(sc) != 0) 266 return; 267 268 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 269 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 270 aprint_verbose_dev(sc->sc_atac.atac_dev, 271 "ignoring broken port multiplier support\n"); 272 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 273 } 274 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 275 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 276 ahci_rev = AHCI_READ(sc, AHCI_VS); 277 snprintb(buf, sizeof(buf), "\177\020" 278 /* "f\000\005NP\0" */ 279 "b\005SXS\0" 280 "b\006EMS\0" 281 "b\007CCCS\0" 282 /* "f\010\005NCS\0" */ 283 "b\015PSC\0" 284 "b\016SSC\0" 285 "b\017PMD\0" 286 "b\020FBSS\0" 287 "b\021SPM\0" 288 "b\022SAM\0" 289 "b\023SNZO\0" 290 "f\024\003ISS\0" 291 "=\001Gen1\0" 292 "=\002Gen2\0" 293 "=\003Gen3\0" 294 "b\030SCLO\0" 295 "b\031SAL\0" 296 "b\032SALP\0" 297 "b\033SSS\0" 298 "b\034SMPS\0" 299 "b\035SSNTF\0" 300 "b\036SNCQ\0" 301 "b\037S64A\0" 302 "\0", sc->sc_ahci_cap); 303 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 304 ", %d port%s, %d slot%s, CAP %s\n", 305 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 306 sc->sc_atac.atac_nchannels, 307 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 308 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 309 310 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 311 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 312 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 313 sc->sc_atac.atac_pio_cap = 4; 314 sc->sc_atac.atac_dma_cap = 2; 315 sc->sc_atac.atac_udma_cap = 6; 316 sc->sc_atac.atac_channels = sc->sc_chanarray; 317 sc->sc_atac.atac_probe = ahci_probe_drive; 318 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 319 sc->sc_atac.atac_set_modes = ahci_setup_channel; 320 #if NATAPIBUS > 0 321 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 322 #endif 323 324 dmasize = 325 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 326 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 327 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 328 if (error) { 329 aprint_error("%s: unable to allocate command header memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 return; 332 } 333 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 334 sc->sc_cmd_hdr_nseg, dmasize, 335 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 336 if (error) { 337 aprint_error("%s: unable to map command header memory" 338 ", error=%d\n", AHCINAME(sc), error); 339 return; 340 } 341 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 342 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 343 if (error) { 344 aprint_error("%s: unable to create command header map" 345 ", error=%d\n", AHCINAME(sc), error); 346 return; 347 } 348 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 349 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 350 if (error) { 351 aprint_error("%s: unable to load command header map" 352 ", error=%d\n", AHCINAME(sc), error); 353 return; 354 } 355 sc->sc_cmd_hdr = cmdhp; 356 357 ahci_enable_intrs(sc); 358 359 if (sc->sc_ahci_ports == 0) { 360 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 361 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 362 DEBUG_PROBE); 363 } 364 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 365 if ((sc->sc_ahci_ports & (1U << i)) == 0) 366 continue; 367 if (port >= sc->sc_atac.atac_nchannels) { 368 aprint_error("%s: more ports than announced\n", 369 AHCINAME(sc)); 370 break; 371 } 372 achp = &sc->sc_channels[i]; 373 chp = &achp->ata_channel; 374 sc->sc_chanarray[i] = chp; 375 chp->ch_channel = i; 376 chp->ch_atac = &sc->sc_atac; 377 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 378 if (chp->ch_queue == NULL) { 379 aprint_error("%s port %d: can't allocate memory for " 380 "command queue", AHCINAME(sc), i); 381 break; 382 } 383 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 384 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 385 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 386 BUS_DMA_NOWAIT); 387 if (error) { 388 aprint_error("%s: unable to allocate command table " 389 "memory, error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 393 achp->ahcic_cmd_tbl_nseg, dmasize, 394 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 395 if (error) { 396 aprint_error("%s: unable to map command table memory" 397 ", error=%d\n", AHCINAME(sc), error); 398 break; 399 } 400 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 401 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 402 if (error) { 403 aprint_error("%s: unable to create command table map" 404 ", error=%d\n", AHCINAME(sc), error); 405 break; 406 } 407 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 408 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 409 if (error) { 410 aprint_error("%s: unable to load command table map" 411 ", error=%d\n", AHCINAME(sc), error); 412 break; 413 } 414 achp->ahcic_cmdh = (struct ahci_cmd_header *) 415 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 416 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 417 AHCI_CMDH_SIZE * port; 418 achp->ahcic_rfis = (struct ahci_r_fis *) 419 ((char *)cmdhp + 420 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 421 AHCI_RFIS_SIZE * port); 422 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port; 425 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 426 "rfis %p (0x%" PRIx64 ")\n", i, 427 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 428 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 429 DEBUG_PROBE); 430 431 for (j = 0; j < sc->sc_ncmds; j++) { 432 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 433 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 434 achp->ahcic_bus_cmd_tbl[j] = 435 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 436 AHCI_CMDTBL_SIZE * j; 437 achp->ahcic_cmdh[j].cmdh_cmdtba = 438 htole64(achp->ahcic_bus_cmd_tbl[j]); 439 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 440 achp->ahcic_cmd_tbl[j], 441 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 442 /* The xfer DMA map */ 443 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 444 AHCI_NPRD, 0x400000 /* 4MB */, 0, 445 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 446 &achp->ahcic_datad[j]); 447 if (error) { 448 aprint_error("%s: couldn't alloc xfer DMA map, " 449 "error=%d\n", AHCINAME(sc), error); 450 goto end; 451 } 452 } 453 ahci_setup_port(sc, i); 454 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 455 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 456 aprint_error("%s: couldn't map channel %d " 457 "sata_status regs\n", AHCINAME(sc), i); 458 break; 459 } 460 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 461 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 462 aprint_error("%s: couldn't map channel %d " 463 "sata_control regs\n", AHCINAME(sc), i); 464 break; 465 } 466 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 467 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 468 aprint_error("%s: couldn't map channel %d " 469 "sata_error regs\n", AHCINAME(sc), i); 470 break; 471 } 472 ata_channel_attach(chp); 473 port++; 474 end: 475 continue; 476 } 477 } 478 479 int 480 ahci_detach(struct ahci_softc *sc, int flags) 481 { 482 struct atac_softc *atac; 483 struct ahci_channel *achp; 484 struct ata_channel *chp; 485 struct scsipi_adapter *adapt; 486 int i, j; 487 int error; 488 489 atac = &sc->sc_atac; 490 adapt = &atac->atac_atapi_adapter._generic; 491 492 for (i = 0; i < AHCI_MAX_PORTS; i++) { 493 achp = &sc->sc_channels[i]; 494 chp = &achp->ata_channel; 495 496 if ((sc->sc_ahci_ports & (1U << i)) == 0) 497 continue; 498 if (i >= sc->sc_atac.atac_nchannels) { 499 aprint_error("%s: more ports than announced\n", 500 AHCINAME(sc)); 501 break; 502 } 503 504 if (chp->atabus == NULL) 505 continue; 506 if ((error = config_detach(chp->atabus, flags)) != 0) 507 return error; 508 509 for (j = 0; j < sc->sc_ncmds; j++) 510 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 511 512 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 513 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 514 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 515 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 516 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 517 achp->ahcic_cmd_tbl_nseg); 518 519 chp->atabus = NULL; 520 521 ata_channel_detach(chp); 522 } 523 524 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 525 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 526 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 527 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 528 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 529 530 if (adapt->adapt_refcnt != 0) 531 return EBUSY; 532 533 return 0; 534 } 535 536 void 537 ahci_resume(struct ahci_softc *sc) 538 { 539 ahci_reset(sc); 540 ahci_setup_ports(sc); 541 ahci_reprobe_drives(sc); 542 ahci_enable_intrs(sc); 543 } 544 545 int 546 ahci_intr(void *v) 547 { 548 struct ahci_softc *sc = v; 549 uint32_t is; 550 int i, r = 0; 551 552 while ((is = AHCI_READ(sc, AHCI_IS))) { 553 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 554 DEBUG_INTR); 555 r = 1; 556 AHCI_WRITE(sc, AHCI_IS, is); 557 for (i = 0; i < AHCI_MAX_PORTS; i++) 558 if (is & (1U << i)) 559 ahci_intr_port(sc, &sc->sc_channels[i]); 560 } 561 return r; 562 } 563 564 static void 565 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 566 { 567 uint32_t is, tfd, sact; 568 struct ata_channel *chp = &achp->ata_channel; 569 struct ata_xfer *xfer; 570 int slot = -1; 571 bool recover = false; 572 573 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 574 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 575 576 AHCIDEBUG_PRINT(( 577 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 578 AHCINAME(sc), 579 chp->ch_channel, is, 580 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 581 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 582 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 583 DEBUG_INTR); 584 585 if ((chp->ch_flags & ATACH_NCQ) == 0) { 586 /* Non-NCQ operation */ 587 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 588 } else { 589 /* NCQ operation */ 590 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 591 } 592 593 /* Handle errors */ 594 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 595 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 596 /* Fatal errors */ 597 if (is & AHCI_P_IX_TFES) { 598 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 599 600 if ((chp->ch_flags & ATACH_NCQ) == 0) { 601 /* Slot valid only for Non-NCQ operation */ 602 slot = (AHCI_READ(sc, 603 AHCI_P_CMD(chp->ch_channel)) 604 & AHCI_P_CMD_CCS_MASK) 605 >> AHCI_P_CMD_CCS_SHIFT; 606 } 607 608 AHCIDEBUG_PRINT(( 609 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 610 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 611 DEBUG_INTR); 612 } else { 613 /* mark an error, and set BSY */ 614 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 615 WDCS_ERR | WDCS_BSY; 616 } 617 618 if (is & AHCI_P_IX_IFS) { 619 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 620 AHCINAME(sc), chp->ch_channel, 621 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 622 DEBUG_INTR); 623 } 624 625 if (!achp->ahcic_recovering) 626 recover = true; 627 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 628 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 629 630 /* D2H Register FIS or Set Device Bits */ 631 if ((tfd & WDCS_ERR) != 0) { 632 if (!achp->ahcic_recovering) 633 recover = true; 634 635 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 636 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 637 638 } 639 } else { 640 tfd = 0; 641 } 642 643 if (__predict_false(recover)) 644 ata_channel_freeze(chp); 645 646 if (slot >= 0) { 647 if ((achp->ahcic_cmds_active & __BIT(slot)) != 0 && 648 (sact & __BIT(slot)) == 0) { 649 xfer = ata_queue_hwslot_to_xfer(chp, slot); 650 xfer->c_intr(chp, xfer, tfd); 651 } 652 } else { 653 /* 654 * For NCQ, HBA halts processing when error is notified, 655 * and any further D2H FISes are ignored until the error 656 * condition is cleared. Hence if a command is inactive, 657 * it means it actually already finished successfully. 658 * Note: active slots can change as c_intr() callback 659 * can activate another command(s), so must only process 660 * commands active before we start processing. 661 */ 662 uint32_t aslots = achp->ahcic_cmds_active; 663 664 for (slot=0; slot < sc->sc_ncmds; slot++) { 665 if ((aslots & __BIT(slot)) != 0 && 666 (sact & __BIT(slot)) == 0) { 667 xfer = ata_queue_hwslot_to_xfer(chp, slot); 668 xfer->c_intr(chp, xfer, tfd); 669 } 670 } 671 } 672 673 if (__predict_false(recover)) { 674 ata_channel_thaw(chp); 675 ahci_channel_recover(sc, chp, tfd); 676 } 677 } 678 679 static void 680 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 681 { 682 struct ata_channel *chp = drvp->chnl_softc; 683 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 684 struct ata_xfer *xfer; 685 686 xfer = ata_get_xfer_ext(chp, C_RECOVERY, 0); 687 688 ata_channel_lock(chp); 689 690 AHCI_WRITE(sc, AHCI_GHC, 691 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 692 ahci_channel_stop(sc, chp, flags); 693 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp, xfer) != 0) 694 ata_reset_channel(chp, flags); 695 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 696 697 ata_channel_unlock(chp); 698 699 ata_free_xfer(chp, xfer); 700 701 return; 702 } 703 704 /* return error code from ata_bio */ 705 static int 706 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 707 { 708 struct ahci_channel *achp = (struct ahci_channel *)chp; 709 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 710 int i; 711 uint32_t is; 712 713 /* 714 * Base timeout is specified in ms. 715 * If we are allowed to sleep, wait a tick each round. 716 * Otherwise delay for 10ms on each round. 717 */ 718 if (flags & AT_WAIT) 719 timeout = MAX(1, mstohz(timeout)); 720 else 721 timeout = timeout / 10; 722 723 AHCI_CMDH_SYNC(sc, achp, slot, 724 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 725 /* start command */ 726 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 727 for (i = 0; i < timeout; i++) { 728 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 729 0) 730 return 0; 731 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 732 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 733 AHCI_P_IX_IFS | 734 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 735 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 736 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 737 /* 738 * we got the D2H FIS anyway, 739 * assume sig is valid. 740 * channel is restarted later 741 */ 742 return ERROR; 743 } 744 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 745 AHCINAME(sc), chp->ch_channel, is); 746 return ERR_DF; 747 } 748 ata_delay(chp, 10, "ahcifis", flags); 749 } 750 751 aprint_debug("%s channel %d: timeout sending FIS\n", 752 AHCINAME(sc), chp->ch_channel); 753 return TIMEOUT; 754 } 755 756 static int 757 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 758 uint32_t *sigp, struct ata_xfer *xfer) 759 { 760 struct ahci_channel *achp = (struct ahci_channel *)chp; 761 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 762 struct ahci_cmd_tbl *cmd_tbl; 763 struct ahci_cmd_header *cmd_h; 764 int i; 765 uint32_t sig; 766 767 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 768 ata_channel_lock_owned(chp); 769 770 again: 771 /* clear port interrupt register */ 772 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 773 /* clear SErrors and start operations */ 774 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 775 /* 776 * issue a command list override to clear BSY. 777 * This is needed if there's a PMP with no drive 778 * on port 0 779 */ 780 ahci_channel_start(sc, chp, flags, 1); 781 } else { 782 ahci_channel_start(sc, chp, flags, 0); 783 } 784 if (drive > 0) { 785 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 786 } 787 788 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 789 goto skip_reset; 790 791 /* polled command, assume interrupts are disabled */ 792 793 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 794 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 795 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 796 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 797 cmd_h->cmdh_prdbc = 0; 798 memset(cmd_tbl->cmdt_cfis, 0, 64); 799 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 800 cmd_tbl->cmdt_cfis[rhd_c] = drive; 801 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 802 switch(ahci_exec_fis(chp, 100, flags, xfer->c_slot)) { 803 case ERR_DF: 804 case TIMEOUT: 805 aprint_error("%s channel %d: setting WDCTL_RST failed " 806 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 807 if (sigp) 808 *sigp = 0xffffffff; 809 goto end; 810 default: 811 break; 812 } 813 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 814 (drive << AHCI_CMDH_F_PMP_SHIFT)); 815 cmd_h->cmdh_prdbc = 0; 816 memset(cmd_tbl->cmdt_cfis, 0, 64); 817 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 818 cmd_tbl->cmdt_cfis[rhd_c] = drive; 819 cmd_tbl->cmdt_cfis[rhd_control] = 0; 820 switch(ahci_exec_fis(chp, 310, flags, xfer->c_slot)) { 821 case ERR_DF: 822 case TIMEOUT: 823 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 824 drive == PMP_PORT_CTL) { 825 /* 826 * some controllers fails to reset when 827 * targeting a PMP but a single drive is attached. 828 * try again with port 0 829 */ 830 drive = 0; 831 ahci_channel_stop(sc, chp, flags); 832 goto again; 833 } 834 aprint_error("%s channel %d: clearing WDCTL_RST failed " 835 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 836 if (sigp) 837 *sigp = 0xffffffff; 838 goto end; 839 default: 840 break; 841 } 842 843 skip_reset: 844 /* 845 * wait 31s for BSY to clear 846 * This should not be needed, but some controllers clear the 847 * command slot before receiving the D2H FIS ... 848 */ 849 for (i = 0; i < AHCI_RST_WAIT; i++) { 850 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 851 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 852 break; 853 ata_delay(chp, 10, "ahcid2h", flags); 854 } 855 if (i == AHCI_RST_WAIT) { 856 aprint_error("%s: BSY never cleared, TD 0x%x\n", 857 AHCINAME(sc), sig); 858 if (sigp) 859 *sigp = 0xffffffff; 860 goto end; 861 } 862 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 863 DEBUG_PROBE); 864 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 865 if (sigp) 866 *sigp = sig; 867 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 868 AHCINAME(sc), chp->ch_channel, sig, 869 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 870 end: 871 ahci_channel_stop(sc, chp, flags); 872 ata_delay(chp, 500, "ahcirst", flags); 873 /* clear port interrupt register */ 874 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 875 ahci_channel_start(sc, chp, flags, 876 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 877 return 0; 878 } 879 880 static void 881 ahci_reset_channel(struct ata_channel *chp, int flags) 882 { 883 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 884 struct ahci_channel *achp = (struct ahci_channel *)chp; 885 int i, tfd; 886 887 ata_channel_lock(chp); 888 889 ahci_channel_stop(sc, chp, flags); 890 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 891 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 892 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 893 /* XXX and then ? */ 894 } 895 ata_kill_active(chp, KILL_RESET, flags); 896 ata_delay(chp, 500, "ahcirst", flags); 897 /* clear port interrupt register */ 898 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 899 /* clear SErrors and start operations */ 900 ahci_channel_start(sc, chp, flags, 901 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 902 /* wait 31s for BSY to clear */ 903 for (i = 0; i <AHCI_RST_WAIT; i++) { 904 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 905 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 906 break; 907 ata_delay(chp, 10, "ahcid2h", flags); 908 } 909 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 910 aprint_error("%s: BSY never cleared, TD 0x%x\n", 911 AHCINAME(sc), tfd); 912 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 913 DEBUG_PROBE); 914 /* clear port interrupt register */ 915 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 916 917 ata_channel_unlock(chp); 918 919 return; 920 } 921 922 static int 923 ahci_ata_addref(struct ata_drive_datas *drvp) 924 { 925 return 0; 926 } 927 928 static void 929 ahci_ata_delref(struct ata_drive_datas *drvp) 930 { 931 return; 932 } 933 934 static void 935 ahci_killpending(struct ata_drive_datas *drvp) 936 { 937 return; 938 } 939 940 static void 941 ahci_probe_drive(struct ata_channel *chp) 942 { 943 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 944 struct ahci_channel *achp = (struct ahci_channel *)chp; 945 uint32_t sig; 946 struct ata_xfer *xfer; 947 948 xfer = ata_get_xfer_ext(chp, 0, 0); 949 if (xfer == NULL) { 950 aprint_error_dev(sc->sc_atac.atac_dev, 951 "%s: failed to get xfer port %d\n", 952 __func__, chp->ch_channel); 953 return; 954 } 955 956 ata_channel_lock(chp); 957 958 /* bring interface up, accept FISs, power up and spin up device */ 959 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 960 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 961 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 962 /* reset the PHY and bring online */ 963 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 964 achp->ahcic_sstatus, AT_WAIT)) { 965 case SStatus_DET_DEV: 966 ata_delay(chp, 500, "ahcidv", AT_WAIT); 967 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 968 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig, 969 xfer); 970 } else { 971 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, xfer); 972 } 973 sata_interpret_sig(chp, 0, sig); 974 /* if we have a PMP attached, inform the controller */ 975 if (chp->ch_ndrives > PMP_PORT_CTL && 976 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 977 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 978 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 979 AHCI_P_CMD_PMA); 980 } 981 /* clear port interrupt register */ 982 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 983 984 /* and enable interrupts */ 985 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 986 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 987 AHCI_P_IX_IFS | 988 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 989 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 990 /* wait 500ms before actually starting operations */ 991 ata_delay(chp, 500, "ahciprb", AT_WAIT); 992 break; 993 994 default: 995 break; 996 } 997 ata_channel_unlock(chp); 998 } 999 1000 static void 1001 ahci_setup_channel(struct ata_channel *chp) 1002 { 1003 return; 1004 } 1005 1006 static int 1007 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1008 { 1009 struct ata_channel *chp = drvp->chnl_softc; 1010 struct ata_command *ata_c = &xfer->c_ata_c; 1011 int ret; 1012 int s; 1013 1014 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1015 chp->ch_channel, 1016 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1017 DEBUG_XFERS); 1018 if (ata_c->flags & AT_POLL) 1019 xfer->c_flags |= C_POLL; 1020 if (ata_c->flags & AT_WAIT) 1021 xfer->c_flags |= C_WAIT; 1022 xfer->c_drive = drvp->drive; 1023 xfer->c_databuf = ata_c->data; 1024 xfer->c_bcount = ata_c->bcount; 1025 xfer->c_start = ahci_cmd_start; 1026 xfer->c_poll = ahci_cmd_poll; 1027 xfer->c_abort = ahci_cmd_abort; 1028 xfer->c_intr = ahci_cmd_complete; 1029 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 1030 s = splbio(); 1031 ata_exec_xfer(chp, xfer); 1032 #ifdef DIAGNOSTIC 1033 if ((ata_c->flags & AT_POLL) != 0 && 1034 (ata_c->flags & AT_DONE) == 0) 1035 panic("ahci_exec_command: polled command not done"); 1036 #endif 1037 if (ata_c->flags & AT_DONE) { 1038 ret = ATACMD_COMPLETE; 1039 } else { 1040 if (ata_c->flags & AT_WAIT) { 1041 ata_channel_lock(chp); 1042 if ((ata_c->flags & AT_DONE) == 0) { 1043 ata_wait_xfer(chp, xfer); 1044 KASSERT((ata_c->flags & AT_DONE) != 0); 1045 } 1046 ata_channel_unlock(chp); 1047 ret = ATACMD_COMPLETE; 1048 } else { 1049 ret = ATACMD_QUEUED; 1050 } 1051 } 1052 splx(s); 1053 return ret; 1054 } 1055 1056 static int 1057 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1058 { 1059 struct ahci_softc *sc = AHCI_CH2SC(chp); 1060 struct ahci_channel *achp = (struct ahci_channel *)chp; 1061 struct ata_command *ata_c = &xfer->c_ata_c; 1062 int slot = xfer->c_slot; 1063 struct ahci_cmd_tbl *cmd_tbl; 1064 struct ahci_cmd_header *cmd_h; 1065 1066 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1067 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1068 ata_c->timeout, slot), 1069 DEBUG_XFERS); 1070 1071 ata_channel_lock_owned(chp); 1072 KASSERT((achp->ahcic_cmds_active & (1U << slot)) == 0); 1073 1074 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1075 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1076 cmd_tbl), DEBUG_XFERS); 1077 1078 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1079 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1080 1081 cmd_h = &achp->ahcic_cmdh[slot]; 1082 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1083 chp->ch_channel, cmd_h), DEBUG_XFERS); 1084 if (ahci_dma_setup(chp, slot, 1085 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1086 ata_c->data : NULL, 1087 ata_c->bcount, 1088 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1089 ata_c->flags |= AT_DF; 1090 return ATASTART_ABORT; 1091 } 1092 cmd_h->cmdh_flags = htole16( 1093 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1094 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1095 cmd_h->cmdh_prdbc = 0; 1096 AHCI_CMDH_SYNC(sc, achp, slot, 1097 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1098 1099 if (ata_c->flags & AT_POLL) { 1100 /* polled command, disable interrupts */ 1101 AHCI_WRITE(sc, AHCI_GHC, 1102 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1103 } 1104 /* start command */ 1105 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1106 /* and says we started this command */ 1107 achp->ahcic_cmds_active |= 1U << slot; 1108 1109 if ((ata_c->flags & AT_POLL) == 0) { 1110 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 1111 ata_timeout, xfer); 1112 return ATASTART_STARTED; 1113 } else 1114 return ATASTART_POLL; 1115 } 1116 1117 static void 1118 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1119 { 1120 struct ahci_softc *sc = AHCI_CH2SC(chp); 1121 struct ahci_channel *achp = (struct ahci_channel *)chp; 1122 1123 ata_channel_lock(chp); 1124 1125 /* 1126 * Polled command. 1127 */ 1128 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1129 if (xfer->c_ata_c.flags & AT_DONE) 1130 break; 1131 ata_channel_unlock(chp); 1132 ahci_intr_port(sc, achp); 1133 ata_channel_lock(chp); 1134 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1135 } 1136 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1137 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1138 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1139 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1140 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1141 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1142 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1143 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1144 DEBUG_XFERS); 1145 1146 ata_channel_unlock(chp); 1147 1148 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1149 xfer->c_ata_c.flags |= AT_TIMEOU; 1150 xfer->c_intr(chp, xfer, 0); 1151 } 1152 /* reenable interrupts */ 1153 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1154 } 1155 1156 static void 1157 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1158 { 1159 ahci_cmd_complete(chp, xfer, 0); 1160 } 1161 1162 static void 1163 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1164 { 1165 struct ahci_channel *achp = (struct ahci_channel *)chp; 1166 struct ata_command *ata_c = &xfer->c_ata_c; 1167 bool deactivate = true; 1168 1169 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1170 DEBUG_FUNCS); 1171 1172 switch (reason) { 1173 case KILL_GONE_INACTIVE: 1174 deactivate = false; 1175 /* FALLTHROUGH */ 1176 case KILL_GONE: 1177 ata_c->flags |= AT_GONE; 1178 break; 1179 case KILL_RESET: 1180 ata_c->flags |= AT_RESET; 1181 break; 1182 case KILL_REQUEUE: 1183 panic("%s: not supposed to be requeued\n", __func__); 1184 break; 1185 default: 1186 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1187 panic("ahci_cmd_kill_xfer"); 1188 } 1189 1190 if (deactivate) { 1191 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1192 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1193 ata_deactivate_xfer(chp, xfer); 1194 } 1195 1196 ahci_cmd_done_end(chp, xfer); 1197 } 1198 1199 static int 1200 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1201 { 1202 struct ata_command *ata_c = &xfer->c_ata_c; 1203 struct ahci_channel *achp = (struct ahci_channel *)chp; 1204 1205 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1206 chp->ch_channel, 1207 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1208 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1209 DEBUG_FUNCS); 1210 1211 if (ata_waitdrain_xfer_check(chp, xfer)) 1212 return 0; 1213 1214 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1215 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1216 ata_deactivate_xfer(chp, xfer); 1217 1218 if (xfer->c_flags & C_TIMEOU) { 1219 ata_c->flags |= AT_TIMEOU; 1220 } 1221 1222 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1223 ata_c->flags |= AT_TIMEOU; 1224 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1225 ata_c->r_error = AHCI_TFD_ERR(tfd); 1226 ata_c->flags |= AT_ERROR; 1227 } 1228 1229 if (ata_c->flags & AT_READREG) 1230 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1231 1232 ahci_cmd_done(chp, xfer); 1233 return 0; 1234 } 1235 1236 static void 1237 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1238 { 1239 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1240 struct ahci_channel *achp = (struct ahci_channel *)chp; 1241 struct ata_command *ata_c = &xfer->c_ata_c; 1242 uint16_t *idwordbuf; 1243 int flags = ata_c->flags; 1244 int i; 1245 1246 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n", 1247 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1248 1249 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1250 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1251 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1252 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1253 BUS_DMASYNC_POSTWRITE); 1254 bus_dmamap_unload(sc->sc_dmat, map); 1255 } 1256 1257 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1258 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1259 1260 /* ata(4) expects IDENTIFY data to be in host endianess */ 1261 if (ata_c->r_command == WDCC_IDENTIFY || 1262 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1263 idwordbuf = xfer->c_databuf; 1264 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1265 idwordbuf[i] = le16toh(idwordbuf[i]); 1266 } 1267 } 1268 1269 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1270 ata_c->flags |= AT_XFDONE; 1271 ahci_cmd_done_end(chp, xfer); 1272 if ((flags & (AT_TIMEOU|AT_ERROR)) == 0) 1273 atastart(chp); 1274 } 1275 1276 static void 1277 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1278 { 1279 struct ata_command *ata_c = &xfer->c_ata_c; 1280 1281 ata_channel_lock(chp); 1282 1283 ata_c->flags |= AT_DONE; 1284 1285 if (ata_c->flags & AT_WAIT) 1286 ata_wake_xfer(chp, xfer); 1287 1288 ata_channel_unlock(chp); 1289 return; 1290 } 1291 1292 static int 1293 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1294 { 1295 struct ata_channel *chp = drvp->chnl_softc; 1296 struct ata_bio *ata_bio = &xfer->c_bio; 1297 1298 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1299 chp->ch_channel, 1300 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1301 DEBUG_XFERS); 1302 if (ata_bio->flags & ATA_POLL) 1303 xfer->c_flags |= C_POLL; 1304 xfer->c_drive = drvp->drive; 1305 xfer->c_databuf = ata_bio->databuf; 1306 xfer->c_bcount = ata_bio->bcount; 1307 xfer->c_start = ahci_bio_start; 1308 xfer->c_poll = ahci_bio_poll; 1309 xfer->c_abort = ahci_bio_abort; 1310 xfer->c_intr = ahci_bio_complete; 1311 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1312 ata_exec_xfer(chp, xfer); 1313 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1314 } 1315 1316 static int 1317 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1318 { 1319 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1320 struct ahci_channel *achp = (struct ahci_channel *)chp; 1321 struct ata_bio *ata_bio = &xfer->c_bio; 1322 struct ahci_cmd_tbl *cmd_tbl; 1323 struct ahci_cmd_header *cmd_h; 1324 1325 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1326 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1327 1328 ata_channel_lock_owned(chp); 1329 1330 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1331 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1332 cmd_tbl), DEBUG_XFERS); 1333 1334 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1335 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1336 1337 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1338 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1339 chp->ch_channel, cmd_h), DEBUG_XFERS); 1340 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1341 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1342 ata_bio->error = ERR_DMA; 1343 ata_bio->r_error = 0; 1344 return ATASTART_ABORT; 1345 } 1346 cmd_h->cmdh_flags = htole16( 1347 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1348 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1349 cmd_h->cmdh_prdbc = 0; 1350 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1351 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1352 1353 if (xfer->c_flags & C_POLL) { 1354 /* polled command, disable interrupts */ 1355 AHCI_WRITE(sc, AHCI_GHC, 1356 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1357 } 1358 if (xfer->c_flags & C_NCQ) 1359 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1360 /* start command */ 1361 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1362 /* and says we started this command */ 1363 achp->ahcic_cmds_active |= 1U << xfer->c_slot; 1364 1365 if ((xfer->c_flags & C_POLL) == 0) { 1366 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1367 ata_timeout, xfer); 1368 return ATASTART_STARTED; 1369 } else 1370 return ATASTART_POLL; 1371 } 1372 1373 static void 1374 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1375 { 1376 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1377 struct ahci_channel *achp = (struct ahci_channel *)chp; 1378 1379 /* 1380 * Polled command. 1381 */ 1382 for (int i = 0; i < ATA_DELAY * 10; i++) { 1383 if (xfer->c_bio.flags & ATA_ITSDONE) 1384 break; 1385 ahci_intr_port(sc, achp); 1386 delay(100); 1387 } 1388 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1389 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1390 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1391 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1392 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1393 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1394 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1395 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1396 DEBUG_XFERS); 1397 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1398 xfer->c_bio.error = TIMEOUT; 1399 xfer->c_intr(chp, xfer, 0); 1400 } 1401 /* reenable interrupts */ 1402 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1403 } 1404 1405 static void 1406 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1407 { 1408 ahci_bio_complete(chp, xfer, 0); 1409 } 1410 1411 static void 1412 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1413 { 1414 int drive = xfer->c_drive; 1415 struct ata_bio *ata_bio = &xfer->c_bio; 1416 struct ahci_channel *achp = (struct ahci_channel *)chp; 1417 bool deactivate = true; 1418 1419 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1420 DEBUG_FUNCS); 1421 1422 ata_bio->flags |= ATA_ITSDONE; 1423 switch (reason) { 1424 case KILL_GONE_INACTIVE: 1425 deactivate = false; 1426 /* FALLTHROUGH */ 1427 case KILL_GONE: 1428 ata_bio->error = ERR_NODEV; 1429 break; 1430 case KILL_RESET: 1431 ata_bio->error = ERR_RESET; 1432 break; 1433 case KILL_REQUEUE: 1434 ata_bio->error = REQUEUE; 1435 break; 1436 default: 1437 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1438 panic("ahci_bio_kill_xfer"); 1439 } 1440 ata_bio->r_error = WDCE_ABRT; 1441 1442 if (deactivate) { 1443 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1444 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1445 ata_deactivate_xfer(chp, xfer); 1446 } 1447 1448 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1449 } 1450 1451 static int 1452 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1453 { 1454 struct ata_bio *ata_bio = &xfer->c_bio; 1455 int drive = xfer->c_drive; 1456 struct ahci_channel *achp = (struct ahci_channel *)chp; 1457 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1458 1459 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1460 DEBUG_FUNCS); 1461 1462 if (ata_waitdrain_xfer_check(chp, xfer)) 1463 return 0; 1464 1465 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1466 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1467 ata_deactivate_xfer(chp, xfer); 1468 1469 if (xfer->c_flags & C_TIMEOU) { 1470 ata_bio->error = TIMEOUT; 1471 } 1472 1473 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1474 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1475 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1476 BUS_DMASYNC_POSTWRITE); 1477 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1478 1479 ata_bio->flags |= ATA_ITSDONE; 1480 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1481 ata_bio->error = ERR_DF; 1482 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1483 ata_bio->error = ERROR; 1484 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1485 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1486 ata_bio->flags |= ATA_CORR; 1487 1488 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1489 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1490 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1491 ata_bio->bcount), DEBUG_XFERS); 1492 /* 1493 * If it was a write, complete data buffer may have been transfered 1494 * before error detection; in this case don't use cmdh_prdbc 1495 * as it won't reflect what was written to media. Assume nothing 1496 * was transfered and leave bcount as-is. 1497 * For queued commands, PRD Byte Count should not be used, and is 1498 * not required to be valid; in that case underflow is always illegal. 1499 */ 1500 if ((xfer->c_flags & C_NCQ) != 0) { 1501 if (ata_bio->error == NOERROR) 1502 ata_bio->bcount = 0; 1503 } else { 1504 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1505 ata_bio->bcount -= 1506 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1507 } 1508 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1509 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1510 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1511 atastart(chp); 1512 return 0; 1513 } 1514 1515 static void 1516 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1517 { 1518 int i; 1519 /* stop channel */ 1520 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1521 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1522 /* wait 1s for channel to stop */ 1523 for (i = 0; i <100; i++) { 1524 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1525 == 0) 1526 break; 1527 ata_delay(chp, 10, "ahcistop", flags); 1528 } 1529 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1530 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1531 /* XXX controller reset ? */ 1532 return; 1533 } 1534 1535 if (sc->sc_channel_stop) 1536 sc->sc_channel_stop(sc, chp); 1537 } 1538 1539 static void 1540 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1541 int flags, int clo) 1542 { 1543 int i; 1544 uint32_t p_cmd; 1545 /* clear error */ 1546 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1547 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1548 1549 if (clo) { 1550 /* issue command list override */ 1551 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1552 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1553 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1554 /* wait 1s for AHCI_CAP_CLO to clear */ 1555 for (i = 0; i <100; i++) { 1556 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1557 AHCI_P_CMD_CLO) == 0) 1558 break; 1559 ata_delay(chp, 10, "ahciclo", flags); 1560 } 1561 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1562 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1563 /* XXX controller reset ? */ 1564 return; 1565 } 1566 } 1567 1568 if (sc->sc_channel_start) 1569 sc->sc_channel_start(sc, chp); 1570 1571 /* and start controller */ 1572 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1573 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1574 if (chp->ch_ndrives > PMP_PORT_CTL && 1575 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1576 p_cmd |= AHCI_P_CMD_PMA; 1577 } 1578 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1579 } 1580 1581 static void 1582 ahci_hold(struct ahci_channel *achp) 1583 { 1584 achp->ahcic_cmds_hold |= achp->ahcic_cmds_active; 1585 achp->ahcic_cmds_active = 0; 1586 } 1587 1588 static void 1589 ahci_unhold(struct ahci_channel *achp) 1590 { 1591 achp->ahcic_cmds_active = achp->ahcic_cmds_hold; 1592 achp->ahcic_cmds_hold = 0; 1593 } 1594 1595 /* Recover channel after command failure */ 1596 void 1597 ahci_channel_recover(struct ahci_softc *sc, struct ata_channel *chp, int tfd) 1598 { 1599 struct ahci_channel *achp = (struct ahci_channel *)chp; 1600 struct ata_drive_datas *drvp; 1601 uint8_t slot, eslot, st, err; 1602 int drive = -1, error; 1603 struct ata_xfer *xfer; 1604 bool reset = false; 1605 1606 KASSERT(!achp->ahcic_recovering); 1607 1608 achp->ahcic_recovering = true; 1609 1610 /* 1611 * Read FBS to get the drive which caused the error, if PM is in use. 1612 * According to AHCI 1.3 spec, this register is available regardless 1613 * if FIS-based switching (FBSS) feature is supported, or disabled. 1614 * If FIS-based switching is not in use, it merely maintains single 1615 * pair of DRQ/BSY state, but it is enough since in that case we 1616 * never issue commands for more than one device at the time anyway. 1617 * XXX untested 1618 */ 1619 if (chp->ch_ndrives > PMP_PORT_CTL) { 1620 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1621 if (fbs & AHCI_P_FBS_SDE) { 1622 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1623 1624 /* 1625 * Tell HBA to reset PM port X (value in DWE) state, 1626 * and resume processing commands for other ports. 1627 */ 1628 fbs |= AHCI_P_FBS_DEC; 1629 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1630 for (int i = 0; i < 1000; i++) { 1631 fbs = AHCI_READ(sc, 1632 AHCI_P_FBS(chp->ch_channel)); 1633 if ((fbs & AHCI_P_FBS_DEC) == 0) 1634 break; 1635 DELAY(1000); 1636 } 1637 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1638 /* follow non-device specific recovery */ 1639 drive = -1; 1640 reset = true; 1641 } 1642 } else { 1643 /* not device specific, reset channel */ 1644 drive = -1; 1645 reset = true; 1646 } 1647 } else 1648 drive = 0; 1649 1650 drvp = &chp->ch_drive[drive]; 1651 1652 /* 1653 * If BSY or DRQ bits are set, must execute COMRESET to return 1654 * device to idle state. If drive is idle, it's enough to just 1655 * reset CMD.ST, it's not necessary to do software reset. 1656 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1657 * to unblock device processing if COMRESET was not done. 1658 */ 1659 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 1660 goto reset; 1661 1662 KASSERT(drive >= 0); 1663 ahci_channel_stop(sc, chp, AT_POLL); 1664 ahci_channel_start(sc, chp, AT_POLL, 1665 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1666 1667 ahci_hold(achp); 1668 1669 /* 1670 * When running NCQ commands, READ LOG EXT is necessary to clear the 1671 * error condition and unblock the device. 1672 */ 1673 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 1674 1675 ahci_unhold(achp); 1676 1677 switch (error) { 1678 case 0: 1679 /* Error out the particular NCQ xfer, then requeue the others */ 1680 if ((achp->ahcic_cmds_active & (1U << eslot)) != 0) { 1681 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 1682 xfer->c_flags |= C_RECOVERED; 1683 xfer->c_intr(chp, xfer, 1684 (err << AHCI_P_TFD_ERR_SHIFT) | st); 1685 } 1686 break; 1687 1688 case EOPNOTSUPP: 1689 /* 1690 * Non-NCQ command error, just find the slot and end with 1691 * the error. 1692 */ 1693 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1694 if ((achp->ahcic_cmds_active & (1U << slot)) != 0) { 1695 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1696 xfer->c_intr(chp, xfer, tfd); 1697 } 1698 } 1699 break; 1700 1701 case EAGAIN: 1702 /* 1703 * Failed to get resources to run the recovery command, must 1704 * reset the drive. This will also kill all still outstanding 1705 * transfers. 1706 */ 1707 reset: 1708 ahci_reset_channel(chp, AT_POLL); 1709 goto out; 1710 /* NOTREACHED */ 1711 1712 default: 1713 /* 1714 * The command to get the slot failed. Kill outstanding 1715 * commands for the same drive only. No need to reset 1716 * the drive, it's unblocked nevertheless. 1717 */ 1718 break; 1719 } 1720 1721 /* Requeue all unfinished commands for same drive as failed command */ 1722 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1723 if ((achp->ahcic_cmds_active & (1U << slot)) == 0) 1724 continue; 1725 1726 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1727 if (drive != xfer->c_drive) 1728 continue; 1729 1730 xfer->c_kill_xfer(chp, xfer, 1731 (error == 0) ? KILL_REQUEUE : KILL_RESET); 1732 } 1733 1734 out: 1735 /* Drive unblocked, back to normal operation */ 1736 achp->ahcic_recovering = false; 1737 atastart(chp); 1738 } 1739 1740 static int 1741 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1742 size_t count, int op) 1743 { 1744 int error, seg; 1745 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1746 struct ahci_channel *achp = (struct ahci_channel *)chp; 1747 struct ahci_cmd_tbl *cmd_tbl; 1748 struct ahci_cmd_header *cmd_h; 1749 1750 cmd_h = &achp->ahcic_cmdh[slot]; 1751 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1752 1753 if (data == NULL) { 1754 cmd_h->cmdh_prdtl = 0; 1755 goto end; 1756 } 1757 1758 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1759 data, count, NULL, 1760 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1761 if (error) { 1762 printf("%s port %d: failed to load xfer: %d\n", 1763 AHCINAME(sc), chp->ch_channel, error); 1764 return error; 1765 } 1766 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1767 achp->ahcic_datad[slot]->dm_mapsize, 1768 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1769 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1770 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1771 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1772 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1773 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1774 } 1775 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1776 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1777 end: 1778 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1779 return 0; 1780 } 1781 1782 #if NATAPIBUS > 0 1783 static void 1784 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1785 { 1786 struct ata_channel *chp = ata_sc->sc_chan; 1787 struct atac_softc *atac = chp->ch_atac; 1788 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1789 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1790 /* 1791 * Fill in the scsipi_adapter. 1792 */ 1793 adapt->adapt_dev = atac->atac_dev; 1794 adapt->adapt_nchannels = atac->atac_nchannels; 1795 adapt->adapt_request = ahci_atapi_scsipi_request; 1796 adapt->adapt_minphys = ahci_atapi_minphys; 1797 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1798 1799 /* 1800 * Fill in the scsipi_channel. 1801 */ 1802 memset(chan, 0, sizeof(*chan)); 1803 chan->chan_adapter = adapt; 1804 chan->chan_bustype = &ahci_atapi_bustype; 1805 chan->chan_channel = chp->ch_channel; 1806 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1807 chan->chan_openings = 1; 1808 chan->chan_max_periph = 1; 1809 chan->chan_ntargets = 1; 1810 chan->chan_nluns = 1; 1811 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1812 atapiprint); 1813 } 1814 1815 static void 1816 ahci_atapi_minphys(struct buf *bp) 1817 { 1818 if (bp->b_bcount > MAXPHYS) 1819 bp->b_bcount = MAXPHYS; 1820 minphys(bp); 1821 } 1822 1823 /* 1824 * Kill off all pending xfers for a periph. 1825 * 1826 * Must be called at splbio(). 1827 */ 1828 static void 1829 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1830 { 1831 struct atac_softc *atac = 1832 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1833 struct ata_channel *chp = 1834 atac->atac_channels[periph->periph_channel->chan_channel]; 1835 1836 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1837 } 1838 1839 static void 1840 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1841 scsipi_adapter_req_t req, void *arg) 1842 { 1843 struct scsipi_adapter *adapt = chan->chan_adapter; 1844 struct scsipi_periph *periph; 1845 struct scsipi_xfer *sc_xfer; 1846 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1847 struct atac_softc *atac = &sc->sc_atac; 1848 struct ata_xfer *xfer; 1849 int channel = chan->chan_channel; 1850 int drive, s; 1851 1852 switch (req) { 1853 case ADAPTER_REQ_RUN_XFER: 1854 sc_xfer = arg; 1855 periph = sc_xfer->xs_periph; 1856 drive = periph->periph_target; 1857 if (!device_is_active(atac->atac_dev)) { 1858 sc_xfer->error = XS_DRIVER_STUFFUP; 1859 scsipi_done(sc_xfer); 1860 return; 1861 } 1862 xfer = ata_get_xfer_ext(atac->atac_channels[channel], 0, 0); 1863 if (xfer == NULL) { 1864 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1865 scsipi_done(sc_xfer); 1866 return; 1867 } 1868 1869 if (sc_xfer->xs_control & XS_CTL_POLL) 1870 xfer->c_flags |= C_POLL; 1871 xfer->c_drive = drive; 1872 xfer->c_flags |= C_ATAPI; 1873 xfer->c_scsipi = sc_xfer; 1874 xfer->c_databuf = sc_xfer->data; 1875 xfer->c_bcount = sc_xfer->datalen; 1876 xfer->c_start = ahci_atapi_start; 1877 xfer->c_poll = ahci_atapi_poll; 1878 xfer->c_abort = ahci_atapi_abort; 1879 xfer->c_intr = ahci_atapi_complete; 1880 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1881 xfer->c_dscpoll = 0; 1882 s = splbio(); 1883 ata_exec_xfer(atac->atac_channels[channel], xfer); 1884 #ifdef DIAGNOSTIC 1885 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1886 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1887 panic("ahci_atapi_scsipi_request: polled command " 1888 "not done"); 1889 #endif 1890 splx(s); 1891 return; 1892 default: 1893 /* Not supported, nothing to do. */ 1894 ; 1895 } 1896 } 1897 1898 static int 1899 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1900 { 1901 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1902 struct ahci_channel *achp = (struct ahci_channel *)chp; 1903 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1904 struct ahci_cmd_tbl *cmd_tbl; 1905 struct ahci_cmd_header *cmd_h; 1906 1907 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1908 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1909 1910 ata_channel_lock_owned(chp); 1911 1912 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1913 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1914 cmd_tbl), DEBUG_XFERS); 1915 1916 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1917 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1918 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1919 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1920 1921 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1922 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1923 chp->ch_channel, cmd_h), DEBUG_XFERS); 1924 if (ahci_dma_setup(chp, xfer->c_slot, 1925 sc_xfer->datalen ? sc_xfer->data : NULL, 1926 sc_xfer->datalen, 1927 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1928 BUS_DMA_READ : BUS_DMA_WRITE)) { 1929 sc_xfer->error = XS_DRIVER_STUFFUP; 1930 return ATASTART_ABORT; 1931 } 1932 cmd_h->cmdh_flags = htole16( 1933 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1934 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1935 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1936 cmd_h->cmdh_prdbc = 0; 1937 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1938 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1939 1940 if (xfer->c_flags & C_POLL) { 1941 /* polled command, disable interrupts */ 1942 AHCI_WRITE(sc, AHCI_GHC, 1943 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1944 } 1945 /* start command */ 1946 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1947 /* and says we started this command */ 1948 achp->ahcic_cmds_active |= 1U << xfer->c_slot; 1949 1950 if ((xfer->c_flags & C_POLL) == 0) { 1951 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1952 ata_timeout, xfer); 1953 return ATASTART_STARTED; 1954 } else 1955 return ATASTART_POLL; 1956 } 1957 1958 static void 1959 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1960 { 1961 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1962 struct ahci_channel *achp = (struct ahci_channel *)chp; 1963 1964 /* 1965 * Polled command. 1966 */ 1967 for (int i = 0; i < ATA_DELAY / 10; i++) { 1968 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1969 break; 1970 ahci_intr_port(sc, achp); 1971 delay(10000); 1972 } 1973 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1974 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1975 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1976 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1977 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1978 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1979 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1980 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1981 DEBUG_XFERS); 1982 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1983 xfer->c_scsipi->error = XS_TIMEOUT; 1984 xfer->c_intr(chp, xfer, 0); 1985 } 1986 /* reenable interrupts */ 1987 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1988 } 1989 1990 static void 1991 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1992 { 1993 ahci_atapi_complete(chp, xfer, 0); 1994 } 1995 1996 static int 1997 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1998 { 1999 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2000 struct ahci_channel *achp = (struct ahci_channel *)chp; 2001 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 2002 2003 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 2004 DEBUG_FUNCS); 2005 2006 if (ata_waitdrain_xfer_check(chp, xfer)) 2007 return 0; 2008 2009 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 2010 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 2011 ata_deactivate_xfer(chp, xfer); 2012 2013 if (xfer->c_flags & C_TIMEOU) { 2014 sc_xfer->error = XS_TIMEOUT; 2015 } 2016 2017 if (xfer->c_bcount > 0) { 2018 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2019 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2020 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2021 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2022 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2023 } 2024 2025 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2026 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2027 sc_xfer->resid = sc_xfer->datalen; 2028 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2029 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2030 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2031 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2032 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2033 sc_xfer->resid == sc_xfer->datalen)) { 2034 sc_xfer->error = XS_SHORTSENSE; 2035 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2036 if ((sc_xfer->xs_periph->periph_quirks & 2037 PQUIRK_NOSENSE) == 0) { 2038 /* ask scsipi to send a REQUEST_SENSE */ 2039 sc_xfer->error = XS_BUSY; 2040 sc_xfer->status = SCSI_CHECK; 2041 } 2042 } 2043 ata_free_xfer(chp, xfer); 2044 scsipi_done(sc_xfer); 2045 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2046 atastart(chp); 2047 return 0; 2048 } 2049 2050 static void 2051 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2052 { 2053 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2054 struct ahci_channel *achp = (struct ahci_channel *)chp; 2055 bool deactivate = true; 2056 2057 /* remove this command from xfer queue */ 2058 switch (reason) { 2059 case KILL_GONE_INACTIVE: 2060 deactivate = false; 2061 /* FALLTHROUGH */ 2062 case KILL_GONE: 2063 sc_xfer->error = XS_DRIVER_STUFFUP; 2064 break; 2065 case KILL_RESET: 2066 sc_xfer->error = XS_RESET; 2067 break; 2068 case KILL_REQUEUE: 2069 sc_xfer->error = XS_REQUEUE; 2070 break; 2071 default: 2072 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2073 panic("ahci_ata_atapi_kill_xfer"); 2074 } 2075 2076 if (deactivate) { 2077 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 2078 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 2079 ata_deactivate_xfer(chp, xfer); 2080 } 2081 2082 ata_free_xfer(chp, xfer); 2083 scsipi_done(sc_xfer); 2084 } 2085 2086 static void 2087 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2088 { 2089 struct scsipi_channel *chan = sc->sc_channel; 2090 struct scsipi_periph *periph; 2091 struct ataparams ids; 2092 struct ataparams *id = &ids; 2093 struct ahci_softc *ahcic = 2094 device_private(chan->chan_adapter->adapt_dev); 2095 struct atac_softc *atac = &ahcic->sc_atac; 2096 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2097 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2098 struct scsipibus_attach_args sa; 2099 char serial_number[21], model[41], firmware_revision[9]; 2100 int s; 2101 2102 /* skip if already attached */ 2103 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2104 return; 2105 2106 /* if no ATAPI device detected at attach time, skip */ 2107 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2108 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2109 "not present\n", target), DEBUG_PROBE); 2110 return; 2111 } 2112 2113 /* Some ATAPI devices need a bit more time after software reset. */ 2114 delay(5000); 2115 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2116 #ifdef ATAPI_DEBUG_PROBE 2117 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2118 AHCINAME(ahcic), target, 2119 id->atap_config & ATAPI_CFG_CMD_MASK, 2120 id->atap_config & ATAPI_CFG_DRQ_MASK); 2121 #endif 2122 periph = scsipi_alloc_periph(M_NOWAIT); 2123 if (periph == NULL) { 2124 aprint_error_dev(sc->sc_dev, 2125 "unable to allocate periph for drive %d\n", 2126 target); 2127 return; 2128 } 2129 periph->periph_dev = NULL; 2130 periph->periph_channel = chan; 2131 periph->periph_switch = &atapi_probe_periphsw; 2132 periph->periph_target = target; 2133 periph->periph_lun = 0; 2134 periph->periph_quirks = PQUIRK_ONLYBIG; 2135 2136 #ifdef SCSIPI_DEBUG 2137 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2138 SCSIPI_DEBUG_TARGET == target) 2139 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2140 #endif 2141 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2142 if (id->atap_config & ATAPI_CFG_REMOV) 2143 periph->periph_flags |= PERIPH_REMOVABLE; 2144 if (periph->periph_type == T_SEQUENTIAL) { 2145 s = splbio(); 2146 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2147 splx(s); 2148 } 2149 2150 sa.sa_periph = periph; 2151 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2152 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2153 T_REMOV : T_FIXED; 2154 strnvisx(model, sizeof(model), id->atap_model, 40, 2155 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2156 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2157 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2158 strnvisx(firmware_revision, sizeof(firmware_revision), 2159 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2160 sa.sa_inqbuf.vendor = model; 2161 sa.sa_inqbuf.product = serial_number; 2162 sa.sa_inqbuf.revision = firmware_revision; 2163 2164 /* 2165 * Determine the operating mode capabilities of the device. 2166 */ 2167 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2168 periph->periph_cap |= PERIPH_CAP_CMD16; 2169 /* XXX This is gross. */ 2170 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2171 2172 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2173 2174 if (drvp->drv_softc) 2175 ata_probe_caps(drvp); 2176 else { 2177 s = splbio(); 2178 drvp->drive_type = ATA_DRIVET_NONE; 2179 splx(s); 2180 } 2181 } else { 2182 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2183 "failed for drive %s:%d:%d\n", 2184 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2185 s = splbio(); 2186 drvp->drive_type = ATA_DRIVET_NONE; 2187 splx(s); 2188 } 2189 } 2190 #endif /* NATAPIBUS */ 2191
Indexes created Wed Sep 24 05:09:52 GMT 2025