ahcisata_core.c revision 1.62.2.8
1 /* $NetBSD: ahcisata_core.c,v 1.62.2.8 2018/10/07 15:44:47 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.62.2.8 2018/10/07 15:44:47 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 void ahci_channel_recover(struct ahci_softc *, struct ata_channel *, int); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending 125 }; 126 127 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 return 0; 170 } 171 172 static void 173 ahci_setup_ports(struct ahci_softc *sc) 174 { 175 int i, port; 176 177 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 178 if ((sc->sc_ahci_ports & (1U << i)) == 0) 179 continue; 180 if (port >= sc->sc_atac.atac_nchannels) { 181 aprint_error("%s: more ports than announced\n", 182 AHCINAME(sc)); 183 break; 184 } 185 ahci_setup_port(sc, i); 186 } 187 } 188 189 static void 190 ahci_reprobe_drives(struct ahci_softc *sc) 191 { 192 int i, port; 193 struct ahci_channel *achp; 194 struct ata_channel *chp; 195 196 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 197 if ((sc->sc_ahci_ports & (1U << i)) == 0) 198 continue; 199 if (port >= sc->sc_atac.atac_nchannels) { 200 aprint_error("%s: more ports than announced\n", 201 AHCINAME(sc)); 202 break; 203 } 204 achp = &sc->sc_channels[i]; 205 chp = &achp->ata_channel; 206 207 ahci_probe_drive(chp); 208 } 209 } 210 211 static void 212 ahci_setup_port(struct ahci_softc *sc, int i) 213 { 214 struct ahci_channel *achp; 215 216 achp = &sc->sc_channels[i]; 217 218 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 219 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 220 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 221 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 222 } 223 224 static void 225 ahci_enable_intrs(struct ahci_softc *sc) 226 { 227 228 /* clear interrupts */ 229 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 230 /* enable interrupts */ 231 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 232 } 233 234 void 235 ahci_attach(struct ahci_softc *sc) 236 { 237 uint32_t ahci_rev; 238 int i, j, port; 239 struct ahci_channel *achp; 240 struct ata_channel *chp; 241 int error; 242 int dmasize; 243 char buf[128]; 244 void *cmdhp; 245 void *cmdtblp; 246 247 if (sc->sc_save_init_data) { 248 ahci_enable(sc); 249 250 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 251 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 252 253 ahci_rev = AHCI_READ(sc, AHCI_VS); 254 if (AHCI_VS_MJR(ahci_rev) > 1 || 255 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 256 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 257 } else { 258 sc->sc_init_data.cap2 = 0; 259 } 260 if (sc->sc_init_data.ports == 0) { 261 sc->sc_init_data.ports = sc->sc_ahci_ports; 262 } 263 } 264 265 if (ahci_reset(sc) != 0) 266 return; 267 268 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 269 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 270 aprint_verbose_dev(sc->sc_atac.atac_dev, 271 "ignoring broken port multiplier support\n"); 272 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 273 } 274 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 275 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 276 ahci_rev = AHCI_READ(sc, AHCI_VS); 277 snprintb(buf, sizeof(buf), "\177\020" 278 /* "f\000\005NP\0" */ 279 "b\005SXS\0" 280 "b\006EMS\0" 281 "b\007CCCS\0" 282 /* "f\010\005NCS\0" */ 283 "b\015PSC\0" 284 "b\016SSC\0" 285 "b\017PMD\0" 286 "b\020FBSS\0" 287 "b\021SPM\0" 288 "b\022SAM\0" 289 "b\023SNZO\0" 290 "f\024\003ISS\0" 291 "=\001Gen1\0" 292 "=\002Gen2\0" 293 "=\003Gen3\0" 294 "b\030SCLO\0" 295 "b\031SAL\0" 296 "b\032SALP\0" 297 "b\033SSS\0" 298 "b\034SMPS\0" 299 "b\035SSNTF\0" 300 "b\036SNCQ\0" 301 "b\037S64A\0" 302 "\0", sc->sc_ahci_cap); 303 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 304 ", %d port%s, %d slot%s, CAP %s\n", 305 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 306 sc->sc_atac.atac_nchannels, 307 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 308 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 309 310 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 311 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 312 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 313 sc->sc_atac.atac_pio_cap = 4; 314 sc->sc_atac.atac_dma_cap = 2; 315 sc->sc_atac.atac_udma_cap = 6; 316 sc->sc_atac.atac_channels = sc->sc_chanarray; 317 sc->sc_atac.atac_probe = ahci_probe_drive; 318 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 319 sc->sc_atac.atac_set_modes = ahci_setup_channel; 320 #if NATAPIBUS > 0 321 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 322 #endif 323 324 dmasize = 325 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 326 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 327 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 328 if (error) { 329 aprint_error("%s: unable to allocate command header memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 return; 332 } 333 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 334 sc->sc_cmd_hdr_nseg, dmasize, 335 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 336 if (error) { 337 aprint_error("%s: unable to map command header memory" 338 ", error=%d\n", AHCINAME(sc), error); 339 return; 340 } 341 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 342 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 343 if (error) { 344 aprint_error("%s: unable to create command header map" 345 ", error=%d\n", AHCINAME(sc), error); 346 return; 347 } 348 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 349 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 350 if (error) { 351 aprint_error("%s: unable to load command header map" 352 ", error=%d\n", AHCINAME(sc), error); 353 return; 354 } 355 sc->sc_cmd_hdr = cmdhp; 356 357 ahci_enable_intrs(sc); 358 359 if (sc->sc_ahci_ports == 0) { 360 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 361 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 362 DEBUG_PROBE); 363 } 364 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 365 if ((sc->sc_ahci_ports & (1U << i)) == 0) 366 continue; 367 if (port >= sc->sc_atac.atac_nchannels) { 368 aprint_error("%s: more ports than announced\n", 369 AHCINAME(sc)); 370 break; 371 } 372 achp = &sc->sc_channels[i]; 373 chp = &achp->ata_channel; 374 sc->sc_chanarray[i] = chp; 375 chp->ch_channel = i; 376 chp->ch_atac = &sc->sc_atac; 377 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 378 if (chp->ch_queue == NULL) { 379 aprint_error("%s port %d: can't allocate memory for " 380 "command queue", AHCINAME(sc), i); 381 break; 382 } 383 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 384 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 385 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 386 BUS_DMA_NOWAIT); 387 if (error) { 388 aprint_error("%s: unable to allocate command table " 389 "memory, error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 393 achp->ahcic_cmd_tbl_nseg, dmasize, 394 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 395 if (error) { 396 aprint_error("%s: unable to map command table memory" 397 ", error=%d\n", AHCINAME(sc), error); 398 break; 399 } 400 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 401 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 402 if (error) { 403 aprint_error("%s: unable to create command table map" 404 ", error=%d\n", AHCINAME(sc), error); 405 break; 406 } 407 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 408 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 409 if (error) { 410 aprint_error("%s: unable to load command table map" 411 ", error=%d\n", AHCINAME(sc), error); 412 break; 413 } 414 achp->ahcic_cmdh = (struct ahci_cmd_header *) 415 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 416 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 417 AHCI_CMDH_SIZE * port; 418 achp->ahcic_rfis = (struct ahci_r_fis *) 419 ((char *)cmdhp + 420 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 421 AHCI_RFIS_SIZE * port); 422 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port; 425 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 426 "rfis %p (0x%" PRIx64 ")\n", i, 427 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 428 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 429 DEBUG_PROBE); 430 431 for (j = 0; j < sc->sc_ncmds; j++) { 432 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 433 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 434 achp->ahcic_bus_cmd_tbl[j] = 435 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 436 AHCI_CMDTBL_SIZE * j; 437 achp->ahcic_cmdh[j].cmdh_cmdtba = 438 htole64(achp->ahcic_bus_cmd_tbl[j]); 439 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 440 achp->ahcic_cmd_tbl[j], 441 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 442 /* The xfer DMA map */ 443 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 444 AHCI_NPRD, 0x400000 /* 4MB */, 0, 445 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 446 &achp->ahcic_datad[j]); 447 if (error) { 448 aprint_error("%s: couldn't alloc xfer DMA map, " 449 "error=%d\n", AHCINAME(sc), error); 450 goto end; 451 } 452 } 453 ahci_setup_port(sc, i); 454 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 455 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 456 aprint_error("%s: couldn't map channel %d " 457 "sata_status regs\n", AHCINAME(sc), i); 458 break; 459 } 460 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 461 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 462 aprint_error("%s: couldn't map channel %d " 463 "sata_control regs\n", AHCINAME(sc), i); 464 break; 465 } 466 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 467 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 468 aprint_error("%s: couldn't map channel %d " 469 "sata_error regs\n", AHCINAME(sc), i); 470 break; 471 } 472 ata_channel_attach(chp); 473 port++; 474 end: 475 continue; 476 } 477 } 478 479 int 480 ahci_detach(struct ahci_softc *sc, int flags) 481 { 482 struct atac_softc *atac; 483 struct ahci_channel *achp; 484 struct ata_channel *chp; 485 struct scsipi_adapter *adapt; 486 int i, j; 487 int error; 488 489 atac = &sc->sc_atac; 490 adapt = &atac->atac_atapi_adapter._generic; 491 492 for (i = 0; i < AHCI_MAX_PORTS; i++) { 493 achp = &sc->sc_channels[i]; 494 chp = &achp->ata_channel; 495 496 if ((sc->sc_ahci_ports & (1U << i)) == 0) 497 continue; 498 if (i >= sc->sc_atac.atac_nchannels) { 499 aprint_error("%s: more ports than announced\n", 500 AHCINAME(sc)); 501 break; 502 } 503 504 if (chp->atabus == NULL) 505 continue; 506 if ((error = config_detach(chp->atabus, flags)) != 0) 507 return error; 508 509 for (j = 0; j < sc->sc_ncmds; j++) 510 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 511 512 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 513 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 514 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 515 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 516 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 517 achp->ahcic_cmd_tbl_nseg); 518 519 chp->atabus = NULL; 520 521 ata_channel_detach(chp); 522 } 523 524 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 525 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 526 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 527 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 528 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 529 530 if (adapt->adapt_refcnt != 0) 531 return EBUSY; 532 533 return 0; 534 } 535 536 void 537 ahci_resume(struct ahci_softc *sc) 538 { 539 ahci_reset(sc); 540 ahci_setup_ports(sc); 541 ahci_reprobe_drives(sc); 542 ahci_enable_intrs(sc); 543 } 544 545 int 546 ahci_intr(void *v) 547 { 548 struct ahci_softc *sc = v; 549 uint32_t is; 550 int i, r = 0; 551 552 while ((is = AHCI_READ(sc, AHCI_IS))) { 553 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 554 DEBUG_INTR); 555 r = 1; 556 AHCI_WRITE(sc, AHCI_IS, is); 557 for (i = 0; i < AHCI_MAX_PORTS; i++) 558 if (is & (1U << i)) 559 ahci_intr_port(sc, &sc->sc_channels[i]); 560 } 561 return r; 562 } 563 564 static void 565 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 566 { 567 uint32_t is, tfd, sact; 568 struct ata_channel *chp = &achp->ata_channel; 569 struct ata_xfer *xfer; 570 int slot = -1; 571 bool recover = false; 572 573 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 574 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 575 576 AHCIDEBUG_PRINT(( 577 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 578 AHCINAME(sc), 579 chp->ch_channel, is, 580 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 581 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 582 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 583 DEBUG_INTR); 584 585 if ((chp->ch_flags & ATACH_NCQ) == 0) { 586 /* Non-NCQ operation */ 587 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 588 } else { 589 /* NCQ operation */ 590 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 591 } 592 593 /* Handle errors */ 594 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 595 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 596 /* Fatal errors */ 597 if (is & AHCI_P_IX_TFES) { 598 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 599 600 if ((chp->ch_flags & ATACH_NCQ) == 0) { 601 /* Slot valid only for Non-NCQ operation */ 602 slot = (AHCI_READ(sc, 603 AHCI_P_CMD(chp->ch_channel)) 604 & AHCI_P_CMD_CCS_MASK) 605 >> AHCI_P_CMD_CCS_SHIFT; 606 } 607 608 AHCIDEBUG_PRINT(( 609 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 610 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 611 DEBUG_INTR); 612 } else { 613 /* mark an error, and set BSY */ 614 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 615 WDCS_ERR | WDCS_BSY; 616 } 617 618 if (is & AHCI_P_IX_IFS) { 619 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 620 AHCINAME(sc), chp->ch_channel, 621 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 622 DEBUG_INTR); 623 } 624 625 if (!achp->ahcic_recovering) 626 recover = true; 627 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 628 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 629 630 /* D2H Register FIS or Set Device Bits */ 631 if ((tfd & WDCS_ERR) != 0) { 632 if (!achp->ahcic_recovering) 633 recover = true; 634 635 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 636 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 637 638 } 639 } else { 640 tfd = 0; 641 } 642 643 if (__predict_false(recover)) 644 ata_channel_freeze(chp); 645 646 if (slot >= 0) { 647 if ((achp->ahcic_cmds_active & __BIT(slot)) != 0 && 648 (sact & __BIT(slot)) == 0) { 649 xfer = ata_queue_hwslot_to_xfer(chp, slot); 650 xfer->ops->c_intr(chp, xfer, tfd); 651 } 652 } else { 653 /* 654 * For NCQ, HBA halts processing when error is notified, 655 * and any further D2H FISes are ignored until the error 656 * condition is cleared. Hence if a command is inactive, 657 * it means it actually already finished successfully. 658 * Note: active slots can change as c_intr() callback 659 * can activate another command(s), so must only process 660 * commands active before we start processing. 661 */ 662 uint32_t aslots = achp->ahcic_cmds_active; 663 664 for (slot=0; slot < sc->sc_ncmds; slot++) { 665 if ((aslots & __BIT(slot)) != 0 && 666 (sact & __BIT(slot)) == 0) { 667 xfer = ata_queue_hwslot_to_xfer(chp, slot); 668 xfer->ops->c_intr(chp, xfer, tfd); 669 } 670 } 671 } 672 673 if (__predict_false(recover)) { 674 ata_channel_thaw(chp); 675 ahci_channel_recover(sc, chp, tfd); 676 } 677 } 678 679 static void 680 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 681 { 682 struct ata_channel *chp = drvp->chnl_softc; 683 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 684 uint8_t c_slot; 685 686 ata_channel_lock_owned(chp); 687 688 /* get a slot for running the command on */ 689 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 690 panic("%s: %s: failed to get xfer for reset, port %d\n", 691 device_xname(sc->sc_atac.atac_dev), 692 __func__, chp->ch_channel); 693 /* NOTREACHED */ 694 } 695 696 AHCI_WRITE(sc, AHCI_GHC, 697 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 698 ahci_channel_stop(sc, chp, flags); 699 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 700 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 701 702 ata_queue_free_slot(chp, c_slot); 703 } 704 705 /* return error code from ata_bio */ 706 static int 707 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 708 { 709 struct ahci_channel *achp = (struct ahci_channel *)chp; 710 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 711 int i; 712 uint32_t is; 713 714 /* 715 * Base timeout is specified in ms. 716 * If we are allowed to sleep, wait a tick each round. 717 * Otherwise delay for 10ms on each round. 718 */ 719 if (flags & AT_WAIT) 720 timeout = MAX(1, mstohz(timeout)); 721 else 722 timeout = timeout / 10; 723 724 AHCI_CMDH_SYNC(sc, achp, slot, 725 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 726 /* start command */ 727 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 728 for (i = 0; i < timeout; i++) { 729 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 730 0) 731 return 0; 732 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 733 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 734 AHCI_P_IX_IFS | 735 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 736 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 737 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 738 /* 739 * we got the D2H FIS anyway, 740 * assume sig is valid. 741 * channel is restarted later 742 */ 743 return ERROR; 744 } 745 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 746 AHCINAME(sc), chp->ch_channel, is); 747 return ERR_DF; 748 } 749 ata_delay(chp, 10, "ahcifis", flags); 750 } 751 752 aprint_debug("%s channel %d: timeout sending FIS\n", 753 AHCINAME(sc), chp->ch_channel); 754 return TIMEOUT; 755 } 756 757 static int 758 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 759 uint32_t *sigp, uint8_t c_slot) 760 { 761 struct ahci_channel *achp = (struct ahci_channel *)chp; 762 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 763 struct ahci_cmd_tbl *cmd_tbl; 764 struct ahci_cmd_header *cmd_h; 765 int i; 766 uint32_t sig; 767 768 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 769 ata_channel_lock_owned(chp); 770 771 again: 772 /* clear port interrupt register */ 773 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 774 /* clear SErrors and start operations */ 775 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 776 /* 777 * issue a command list override to clear BSY. 778 * This is needed if there's a PMP with no drive 779 * on port 0 780 */ 781 ahci_channel_start(sc, chp, flags, 1); 782 } else { 783 ahci_channel_start(sc, chp, flags, 0); 784 } 785 if (drive > 0) { 786 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 787 } 788 789 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 790 goto skip_reset; 791 792 /* polled command, assume interrupts are disabled */ 793 794 cmd_h = &achp->ahcic_cmdh[c_slot]; 795 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 796 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 797 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 798 cmd_h->cmdh_prdbc = 0; 799 memset(cmd_tbl->cmdt_cfis, 0, 64); 800 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 801 cmd_tbl->cmdt_cfis[rhd_c] = drive; 802 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 803 switch(ahci_exec_fis(chp, 100, flags, c_slot)) { 804 case ERR_DF: 805 case TIMEOUT: 806 aprint_error("%s channel %d: setting WDCTL_RST failed " 807 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 808 if (sigp) 809 *sigp = 0xffffffff; 810 goto end; 811 default: 812 break; 813 } 814 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 815 (drive << AHCI_CMDH_F_PMP_SHIFT)); 816 cmd_h->cmdh_prdbc = 0; 817 memset(cmd_tbl->cmdt_cfis, 0, 64); 818 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 819 cmd_tbl->cmdt_cfis[rhd_c] = drive; 820 cmd_tbl->cmdt_cfis[rhd_control] = 0; 821 switch(ahci_exec_fis(chp, 310, flags, c_slot)) { 822 case ERR_DF: 823 case TIMEOUT: 824 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 825 drive == PMP_PORT_CTL) { 826 /* 827 * some controllers fails to reset when 828 * targeting a PMP but a single drive is attached. 829 * try again with port 0 830 */ 831 drive = 0; 832 ahci_channel_stop(sc, chp, flags); 833 goto again; 834 } 835 aprint_error("%s channel %d: clearing WDCTL_RST failed " 836 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 837 if (sigp) 838 *sigp = 0xffffffff; 839 goto end; 840 default: 841 break; 842 } 843 844 skip_reset: 845 /* 846 * wait 31s for BSY to clear 847 * This should not be needed, but some controllers clear the 848 * command slot before receiving the D2H FIS ... 849 */ 850 for (i = 0; i < AHCI_RST_WAIT; i++) { 851 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 852 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 853 break; 854 ata_delay(chp, 10, "ahcid2h", flags); 855 } 856 if (i == AHCI_RST_WAIT) { 857 aprint_error("%s: BSY never cleared, TD 0x%x\n", 858 AHCINAME(sc), sig); 859 if (sigp) 860 *sigp = 0xffffffff; 861 goto end; 862 } 863 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 864 DEBUG_PROBE); 865 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 866 if (sigp) 867 *sigp = sig; 868 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 869 AHCINAME(sc), chp->ch_channel, sig, 870 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 871 end: 872 ahci_channel_stop(sc, chp, flags); 873 ata_delay(chp, 500, "ahcirst", flags); 874 /* clear port interrupt register */ 875 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 876 ahci_channel_start(sc, chp, flags, 877 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 878 return 0; 879 } 880 881 static void 882 ahci_reset_channel(struct ata_channel *chp, int flags) 883 { 884 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 885 struct ahci_channel *achp = (struct ahci_channel *)chp; 886 int i, tfd; 887 888 ata_channel_lock_owned(chp); 889 890 ahci_channel_stop(sc, chp, flags); 891 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 892 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 893 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 894 /* XXX and then ? */ 895 } 896 ata_kill_active(chp, KILL_RESET, flags); 897 ata_delay(chp, 500, "ahcirst", flags); 898 /* clear port interrupt register */ 899 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 900 /* clear SErrors and start operations */ 901 ahci_channel_start(sc, chp, flags, 902 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 903 /* wait 31s for BSY to clear */ 904 for (i = 0; i <AHCI_RST_WAIT; i++) { 905 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 906 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 907 break; 908 ata_delay(chp, 10, "ahcid2h", flags); 909 } 910 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 911 aprint_error("%s: BSY never cleared, TD 0x%x\n", 912 AHCINAME(sc), tfd); 913 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 914 DEBUG_PROBE); 915 /* clear port interrupt register */ 916 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 917 918 return; 919 } 920 921 static int 922 ahci_ata_addref(struct ata_drive_datas *drvp) 923 { 924 return 0; 925 } 926 927 static void 928 ahci_ata_delref(struct ata_drive_datas *drvp) 929 { 930 return; 931 } 932 933 static void 934 ahci_killpending(struct ata_drive_datas *drvp) 935 { 936 return; 937 } 938 939 static void 940 ahci_probe_drive(struct ata_channel *chp) 941 { 942 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 943 struct ahci_channel *achp = (struct ahci_channel *)chp; 944 uint32_t sig; 945 uint8_t c_slot; 946 947 ata_channel_lock(chp); 948 949 /* get a slot for running the command on */ 950 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 951 aprint_error_dev(sc->sc_atac.atac_dev, 952 "%s: failed to get xfer port %d\n", 953 __func__, chp->ch_channel); 954 ata_channel_unlock(chp); 955 return; 956 } 957 958 /* bring interface up, accept FISs, power up and spin up device */ 959 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 960 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 961 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 962 /* reset the PHY and bring online */ 963 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 964 achp->ahcic_sstatus, AT_WAIT)) { 965 case SStatus_DET_DEV: 966 ata_delay(chp, 500, "ahcidv", AT_WAIT); 967 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 968 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig, 969 c_slot); 970 } else { 971 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 972 } 973 sata_interpret_sig(chp, 0, sig); 974 /* if we have a PMP attached, inform the controller */ 975 if (chp->ch_ndrives > PMP_PORT_CTL && 976 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 977 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 978 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 979 AHCI_P_CMD_PMA); 980 } 981 /* clear port interrupt register */ 982 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 983 984 /* and enable interrupts */ 985 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 986 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 987 AHCI_P_IX_IFS | 988 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 989 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 990 /* wait 500ms before actually starting operations */ 991 ata_delay(chp, 500, "ahciprb", AT_WAIT); 992 break; 993 994 default: 995 break; 996 } 997 998 ata_queue_free_slot(chp, c_slot); 999 1000 ata_channel_unlock(chp); 1001 } 1002 1003 static void 1004 ahci_setup_channel(struct ata_channel *chp) 1005 { 1006 return; 1007 } 1008 1009 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1010 .c_start = ahci_cmd_start, 1011 .c_poll = ahci_cmd_poll, 1012 .c_abort = ahci_cmd_abort, 1013 .c_intr = ahci_cmd_complete, 1014 .c_kill_xfer = ahci_cmd_kill_xfer, 1015 }; 1016 1017 static int 1018 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1019 { 1020 struct ata_channel *chp = drvp->chnl_softc; 1021 struct ata_command *ata_c = &xfer->c_ata_c; 1022 int ret; 1023 int s; 1024 1025 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1026 chp->ch_channel, 1027 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1028 DEBUG_XFERS); 1029 if (ata_c->flags & AT_POLL) 1030 xfer->c_flags |= C_POLL; 1031 if (ata_c->flags & AT_WAIT) 1032 xfer->c_flags |= C_WAIT; 1033 xfer->c_drive = drvp->drive; 1034 xfer->c_databuf = ata_c->data; 1035 xfer->c_bcount = ata_c->bcount; 1036 xfer->ops = &ahci_cmd_xfer_ops; 1037 s = splbio(); 1038 ata_exec_xfer(chp, xfer); 1039 #ifdef DIAGNOSTIC 1040 if ((ata_c->flags & AT_POLL) != 0 && 1041 (ata_c->flags & AT_DONE) == 0) 1042 panic("ahci_exec_command: polled command not done"); 1043 #endif 1044 if (ata_c->flags & AT_DONE) { 1045 ret = ATACMD_COMPLETE; 1046 } else { 1047 if (ata_c->flags & AT_WAIT) { 1048 ata_wait_cmd(chp, xfer); 1049 ret = ATACMD_COMPLETE; 1050 } else { 1051 ret = ATACMD_QUEUED; 1052 } 1053 } 1054 splx(s); 1055 return ret; 1056 } 1057 1058 static int 1059 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1060 { 1061 struct ahci_softc *sc = AHCI_CH2SC(chp); 1062 struct ahci_channel *achp = (struct ahci_channel *)chp; 1063 struct ata_command *ata_c = &xfer->c_ata_c; 1064 int slot = xfer->c_slot; 1065 struct ahci_cmd_tbl *cmd_tbl; 1066 struct ahci_cmd_header *cmd_h; 1067 1068 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1069 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1070 ata_c->timeout, slot), 1071 DEBUG_XFERS); 1072 1073 ata_channel_lock_owned(chp); 1074 KASSERT((achp->ahcic_cmds_active & (1U << slot)) == 0); 1075 1076 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1077 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1078 cmd_tbl), DEBUG_XFERS); 1079 1080 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1081 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1082 1083 cmd_h = &achp->ahcic_cmdh[slot]; 1084 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1085 chp->ch_channel, cmd_h), DEBUG_XFERS); 1086 if (ahci_dma_setup(chp, slot, 1087 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1088 ata_c->data : NULL, 1089 ata_c->bcount, 1090 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1091 ata_c->flags |= AT_DF; 1092 return ATASTART_ABORT; 1093 } 1094 cmd_h->cmdh_flags = htole16( 1095 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1096 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1097 cmd_h->cmdh_prdbc = 0; 1098 AHCI_CMDH_SYNC(sc, achp, slot, 1099 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1100 1101 if (ata_c->flags & AT_POLL) { 1102 /* polled command, disable interrupts */ 1103 AHCI_WRITE(sc, AHCI_GHC, 1104 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1105 } 1106 /* start command */ 1107 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1108 /* and says we started this command */ 1109 achp->ahcic_cmds_active |= 1U << slot; 1110 1111 if ((ata_c->flags & AT_POLL) == 0) { 1112 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1113 ata_timeout, chp); 1114 return ATASTART_STARTED; 1115 } else 1116 return ATASTART_POLL; 1117 } 1118 1119 static void 1120 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1121 { 1122 struct ahci_softc *sc = AHCI_CH2SC(chp); 1123 struct ahci_channel *achp = (struct ahci_channel *)chp; 1124 1125 ata_channel_lock(chp); 1126 1127 /* 1128 * Polled command. 1129 */ 1130 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1131 if (xfer->c_ata_c.flags & AT_DONE) 1132 break; 1133 ata_channel_unlock(chp); 1134 ahci_intr_port(sc, achp); 1135 ata_channel_lock(chp); 1136 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1137 } 1138 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1139 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1140 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1141 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1142 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1143 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1144 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1145 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1146 DEBUG_XFERS); 1147 1148 ata_channel_unlock(chp); 1149 1150 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1151 xfer->c_ata_c.flags |= AT_TIMEOU; 1152 xfer->ops->c_intr(chp, xfer, 0); 1153 } 1154 /* reenable interrupts */ 1155 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1156 } 1157 1158 static void 1159 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1160 { 1161 ahci_cmd_complete(chp, xfer, 0); 1162 } 1163 1164 static void 1165 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1166 { 1167 struct ahci_channel *achp = (struct ahci_channel *)chp; 1168 struct ata_command *ata_c = &xfer->c_ata_c; 1169 bool deactivate = true; 1170 1171 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1172 DEBUG_FUNCS); 1173 1174 switch (reason) { 1175 case KILL_GONE_INACTIVE: 1176 deactivate = false; 1177 /* FALLTHROUGH */ 1178 case KILL_GONE: 1179 ata_c->flags |= AT_GONE; 1180 break; 1181 case KILL_RESET: 1182 ata_c->flags |= AT_RESET; 1183 break; 1184 case KILL_REQUEUE: 1185 panic("%s: not supposed to be requeued\n", __func__); 1186 break; 1187 default: 1188 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1189 panic("ahci_cmd_kill_xfer"); 1190 } 1191 1192 ahci_cmd_done_end(chp, xfer); 1193 1194 if (deactivate) { 1195 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1196 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1197 ata_deactivate_xfer(chp, xfer); 1198 } 1199 } 1200 1201 static int 1202 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1203 { 1204 struct ata_command *ata_c = &xfer->c_ata_c; 1205 struct ahci_channel *achp = (struct ahci_channel *)chp; 1206 1207 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1208 chp->ch_channel, 1209 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1210 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1211 DEBUG_FUNCS); 1212 1213 if (ata_waitdrain_xfer_check(chp, xfer)) 1214 return 0; 1215 1216 if (xfer->c_flags & C_TIMEOU) { 1217 ata_c->flags |= AT_TIMEOU; 1218 } 1219 1220 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1221 ata_c->flags |= AT_TIMEOU; 1222 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1223 ata_c->r_error = AHCI_TFD_ERR(tfd); 1224 ata_c->flags |= AT_ERROR; 1225 } 1226 1227 if (ata_c->flags & AT_READREG) 1228 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1229 1230 ahci_cmd_done(chp, xfer); 1231 1232 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1233 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1234 ata_deactivate_xfer(chp, xfer); 1235 1236 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1237 atastart(chp); 1238 1239 return 0; 1240 } 1241 1242 static void 1243 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1244 { 1245 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1246 struct ahci_channel *achp = (struct ahci_channel *)chp; 1247 struct ata_command *ata_c = &xfer->c_ata_c; 1248 uint16_t *idwordbuf; 1249 int i; 1250 1251 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n", 1252 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1253 1254 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1255 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1256 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1257 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1258 BUS_DMASYNC_POSTWRITE); 1259 bus_dmamap_unload(sc->sc_dmat, map); 1260 } 1261 1262 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1263 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1264 1265 /* ata(4) expects IDENTIFY data to be in host endianess */ 1266 if (ata_c->r_command == WDCC_IDENTIFY || 1267 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1268 idwordbuf = xfer->c_databuf; 1269 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1270 idwordbuf[i] = le16toh(idwordbuf[i]); 1271 } 1272 } 1273 1274 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1275 ata_c->flags |= AT_XFDONE; 1276 1277 ahci_cmd_done_end(chp, xfer); 1278 } 1279 1280 static void 1281 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1282 { 1283 struct ata_command *ata_c = &xfer->c_ata_c; 1284 1285 ata_c->flags |= AT_DONE; 1286 } 1287 1288 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1289 .c_start = ahci_bio_start, 1290 .c_poll = ahci_bio_poll, 1291 .c_abort = ahci_bio_abort, 1292 .c_intr = ahci_bio_complete, 1293 .c_kill_xfer = ahci_bio_kill_xfer, 1294 }; 1295 1296 static int 1297 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1298 { 1299 struct ata_channel *chp = drvp->chnl_softc; 1300 struct ata_bio *ata_bio = &xfer->c_bio; 1301 1302 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1303 chp->ch_channel, 1304 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1305 DEBUG_XFERS); 1306 if (ata_bio->flags & ATA_POLL) 1307 xfer->c_flags |= C_POLL; 1308 xfer->c_drive = drvp->drive; 1309 xfer->c_databuf = ata_bio->databuf; 1310 xfer->c_bcount = ata_bio->bcount; 1311 xfer->ops = &ahci_bio_xfer_ops; 1312 ata_exec_xfer(chp, xfer); 1313 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1314 } 1315 1316 static int 1317 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1318 { 1319 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1320 struct ahci_channel *achp = (struct ahci_channel *)chp; 1321 struct ata_bio *ata_bio = &xfer->c_bio; 1322 struct ahci_cmd_tbl *cmd_tbl; 1323 struct ahci_cmd_header *cmd_h; 1324 1325 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1326 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1327 1328 ata_channel_lock_owned(chp); 1329 1330 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1331 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1332 cmd_tbl), DEBUG_XFERS); 1333 1334 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1335 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1336 1337 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1338 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1339 chp->ch_channel, cmd_h), DEBUG_XFERS); 1340 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1341 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1342 ata_bio->error = ERR_DMA; 1343 ata_bio->r_error = 0; 1344 return ATASTART_ABORT; 1345 } 1346 cmd_h->cmdh_flags = htole16( 1347 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1348 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1349 cmd_h->cmdh_prdbc = 0; 1350 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1351 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1352 1353 if (xfer->c_flags & C_POLL) { 1354 /* polled command, disable interrupts */ 1355 AHCI_WRITE(sc, AHCI_GHC, 1356 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1357 } 1358 if (xfer->c_flags & C_NCQ) 1359 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1360 /* start command */ 1361 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1362 /* and says we started this command */ 1363 achp->ahcic_cmds_active |= 1U << xfer->c_slot; 1364 1365 if ((xfer->c_flags & C_POLL) == 0) { 1366 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1367 ata_timeout, chp); 1368 return ATASTART_STARTED; 1369 } else 1370 return ATASTART_POLL; 1371 } 1372 1373 static void 1374 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1375 { 1376 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1377 struct ahci_channel *achp = (struct ahci_channel *)chp; 1378 1379 /* 1380 * Polled command. 1381 */ 1382 for (int i = 0; i < ATA_DELAY * 10; i++) { 1383 if (xfer->c_bio.flags & ATA_ITSDONE) 1384 break; 1385 ahci_intr_port(sc, achp); 1386 delay(100); 1387 } 1388 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1389 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1390 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1391 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1392 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1393 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1394 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1395 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1396 DEBUG_XFERS); 1397 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1398 xfer->c_bio.error = TIMEOUT; 1399 xfer->ops->c_intr(chp, xfer, 0); 1400 } 1401 /* reenable interrupts */ 1402 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1403 } 1404 1405 static void 1406 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1407 { 1408 ahci_bio_complete(chp, xfer, 0); 1409 } 1410 1411 static void 1412 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1413 { 1414 int drive = xfer->c_drive; 1415 struct ata_bio *ata_bio = &xfer->c_bio; 1416 struct ahci_channel *achp = (struct ahci_channel *)chp; 1417 bool deactivate = true; 1418 1419 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1420 DEBUG_FUNCS); 1421 1422 ata_bio->flags |= ATA_ITSDONE; 1423 switch (reason) { 1424 case KILL_GONE_INACTIVE: 1425 deactivate = false; 1426 /* FALLTHROUGH */ 1427 case KILL_GONE: 1428 ata_bio->error = ERR_NODEV; 1429 break; 1430 case KILL_RESET: 1431 ata_bio->error = ERR_RESET; 1432 break; 1433 case KILL_REQUEUE: 1434 ata_bio->error = REQUEUE; 1435 break; 1436 default: 1437 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1438 panic("ahci_bio_kill_xfer"); 1439 } 1440 ata_bio->r_error = WDCE_ABRT; 1441 1442 if (deactivate) { 1443 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1444 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1445 ata_deactivate_xfer(chp, xfer); 1446 } 1447 1448 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1449 } 1450 1451 static int 1452 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1453 { 1454 struct ata_bio *ata_bio = &xfer->c_bio; 1455 int drive = xfer->c_drive; 1456 struct ahci_channel *achp = (struct ahci_channel *)chp; 1457 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1458 1459 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1460 DEBUG_FUNCS); 1461 1462 if (ata_waitdrain_xfer_check(chp, xfer)) 1463 return 0; 1464 1465 if (xfer->c_flags & C_TIMEOU) { 1466 ata_bio->error = TIMEOUT; 1467 } 1468 1469 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1470 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1471 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1472 BUS_DMASYNC_POSTWRITE); 1473 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1474 1475 ata_bio->flags |= ATA_ITSDONE; 1476 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1477 ata_bio->error = ERR_DF; 1478 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1479 ata_bio->error = ERROR; 1480 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1481 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1482 ata_bio->flags |= ATA_CORR; 1483 1484 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1485 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1486 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1487 ata_bio->bcount), DEBUG_XFERS); 1488 /* 1489 * If it was a write, complete data buffer may have been transfered 1490 * before error detection; in this case don't use cmdh_prdbc 1491 * as it won't reflect what was written to media. Assume nothing 1492 * was transfered and leave bcount as-is. 1493 * For queued commands, PRD Byte Count should not be used, and is 1494 * not required to be valid; in that case underflow is always illegal. 1495 */ 1496 if ((xfer->c_flags & C_NCQ) != 0) { 1497 if (ata_bio->error == NOERROR) 1498 ata_bio->bcount = 0; 1499 } else { 1500 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1501 ata_bio->bcount -= 1502 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1503 } 1504 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1505 1506 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1507 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1508 ata_deactivate_xfer(chp, xfer); 1509 1510 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1511 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1512 atastart(chp); 1513 return 0; 1514 } 1515 1516 static void 1517 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1518 { 1519 int i; 1520 /* stop channel */ 1521 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1522 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1523 /* wait 1s for channel to stop */ 1524 for (i = 0; i <100; i++) { 1525 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1526 == 0) 1527 break; 1528 ata_delay(chp, 10, "ahcistop", flags); 1529 } 1530 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1531 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1532 /* XXX controller reset ? */ 1533 return; 1534 } 1535 1536 if (sc->sc_channel_stop) 1537 sc->sc_channel_stop(sc, chp); 1538 } 1539 1540 static void 1541 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1542 int flags, int clo) 1543 { 1544 int i; 1545 uint32_t p_cmd; 1546 /* clear error */ 1547 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1548 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1549 1550 if (clo) { 1551 /* issue command list override */ 1552 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1553 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1554 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1555 /* wait 1s for AHCI_CAP_CLO to clear */ 1556 for (i = 0; i <100; i++) { 1557 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1558 AHCI_P_CMD_CLO) == 0) 1559 break; 1560 ata_delay(chp, 10, "ahciclo", flags); 1561 } 1562 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1563 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1564 /* XXX controller reset ? */ 1565 return; 1566 } 1567 } 1568 1569 if (sc->sc_channel_start) 1570 sc->sc_channel_start(sc, chp); 1571 1572 /* and start controller */ 1573 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1574 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1575 if (chp->ch_ndrives > PMP_PORT_CTL && 1576 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1577 p_cmd |= AHCI_P_CMD_PMA; 1578 } 1579 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1580 } 1581 1582 static void 1583 ahci_hold(struct ahci_channel *achp) 1584 { 1585 achp->ahcic_cmds_hold |= achp->ahcic_cmds_active; 1586 achp->ahcic_cmds_active = 0; 1587 } 1588 1589 static void 1590 ahci_unhold(struct ahci_channel *achp) 1591 { 1592 achp->ahcic_cmds_active = achp->ahcic_cmds_hold; 1593 achp->ahcic_cmds_hold = 0; 1594 } 1595 1596 /* Recover channel after command failure */ 1597 void 1598 ahci_channel_recover(struct ahci_softc *sc, struct ata_channel *chp, int tfd) 1599 { 1600 struct ahci_channel *achp = (struct ahci_channel *)chp; 1601 struct ata_drive_datas *drvp; 1602 uint8_t slot, eslot, st, err; 1603 int drive = -1, error; 1604 struct ata_xfer *xfer; 1605 bool reset = false; 1606 1607 KASSERT(!achp->ahcic_recovering); 1608 1609 achp->ahcic_recovering = true; 1610 1611 /* 1612 * Read FBS to get the drive which caused the error, if PM is in use. 1613 * According to AHCI 1.3 spec, this register is available regardless 1614 * if FIS-based switching (FBSS) feature is supported, or disabled. 1615 * If FIS-based switching is not in use, it merely maintains single 1616 * pair of DRQ/BSY state, but it is enough since in that case we 1617 * never issue commands for more than one device at the time anyway. 1618 * XXX untested 1619 */ 1620 if (chp->ch_ndrives > PMP_PORT_CTL) { 1621 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1622 if (fbs & AHCI_P_FBS_SDE) { 1623 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1624 1625 /* 1626 * Tell HBA to reset PM port X (value in DWE) state, 1627 * and resume processing commands for other ports. 1628 */ 1629 fbs |= AHCI_P_FBS_DEC; 1630 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1631 for (int i = 0; i < 1000; i++) { 1632 fbs = AHCI_READ(sc, 1633 AHCI_P_FBS(chp->ch_channel)); 1634 if ((fbs & AHCI_P_FBS_DEC) == 0) 1635 break; 1636 DELAY(1000); 1637 } 1638 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1639 /* follow non-device specific recovery */ 1640 drive = -1; 1641 reset = true; 1642 } 1643 } else { 1644 /* not device specific, reset channel */ 1645 drive = -1; 1646 reset = true; 1647 } 1648 } else 1649 drive = 0; 1650 1651 drvp = &chp->ch_drive[drive]; 1652 1653 /* 1654 * If BSY or DRQ bits are set, must execute COMRESET to return 1655 * device to idle state. If drive is idle, it's enough to just 1656 * reset CMD.ST, it's not necessary to do software reset. 1657 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1658 * to unblock device processing if COMRESET was not done. 1659 */ 1660 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 1661 goto reset; 1662 1663 KASSERT(drive >= 0); 1664 ahci_channel_stop(sc, chp, AT_POLL); 1665 ahci_channel_start(sc, chp, AT_POLL, 1666 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1667 1668 ahci_hold(achp); 1669 1670 /* 1671 * When running NCQ commands, READ LOG EXT is necessary to clear the 1672 * error condition and unblock the device. 1673 */ 1674 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 1675 1676 ahci_unhold(achp); 1677 1678 switch (error) { 1679 case 0: 1680 /* Error out the particular NCQ xfer, then requeue the others */ 1681 if ((achp->ahcic_cmds_active & (1U << eslot)) != 0) { 1682 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 1683 xfer->c_flags |= C_RECOVERED; 1684 xfer->ops->c_intr(chp, xfer, 1685 (err << AHCI_P_TFD_ERR_SHIFT) | st); 1686 } 1687 break; 1688 1689 case EOPNOTSUPP: 1690 /* 1691 * Non-NCQ command error, just find the slot and end with 1692 * the error. 1693 */ 1694 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1695 if ((achp->ahcic_cmds_active & (1U << slot)) != 0) { 1696 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1697 xfer->ops->c_intr(chp, xfer, tfd); 1698 } 1699 } 1700 break; 1701 1702 case EAGAIN: 1703 /* 1704 * Failed to get resources to run the recovery command, must 1705 * reset the drive. This will also kill all still outstanding 1706 * transfers. 1707 */ 1708 reset: 1709 ata_channel_lock(chp); 1710 ahci_reset_channel(chp, AT_POLL); 1711 ata_channel_unlock(chp); 1712 goto out; 1713 /* NOTREACHED */ 1714 1715 default: 1716 /* 1717 * The command to get the slot failed. Kill outstanding 1718 * commands for the same drive only. No need to reset 1719 * the drive, it's unblocked nevertheless. 1720 */ 1721 break; 1722 } 1723 1724 /* Requeue all unfinished commands for same drive as failed command */ 1725 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1726 if ((achp->ahcic_cmds_active & (1U << slot)) == 0) 1727 continue; 1728 1729 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1730 if (drive != xfer->c_drive) 1731 continue; 1732 1733 xfer->ops->c_kill_xfer(chp, xfer, 1734 (error == 0) ? KILL_REQUEUE : KILL_RESET); 1735 } 1736 1737 out: 1738 /* Drive unblocked, back to normal operation */ 1739 achp->ahcic_recovering = false; 1740 atastart(chp); 1741 } 1742 1743 static int 1744 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1745 size_t count, int op) 1746 { 1747 int error, seg; 1748 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1749 struct ahci_channel *achp = (struct ahci_channel *)chp; 1750 struct ahci_cmd_tbl *cmd_tbl; 1751 struct ahci_cmd_header *cmd_h; 1752 1753 cmd_h = &achp->ahcic_cmdh[slot]; 1754 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1755 1756 if (data == NULL) { 1757 cmd_h->cmdh_prdtl = 0; 1758 goto end; 1759 } 1760 1761 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1762 data, count, NULL, 1763 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1764 if (error) { 1765 printf("%s port %d: failed to load xfer: %d\n", 1766 AHCINAME(sc), chp->ch_channel, error); 1767 return error; 1768 } 1769 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1770 achp->ahcic_datad[slot]->dm_mapsize, 1771 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1772 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1773 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1774 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1775 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1776 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1777 } 1778 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1779 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1780 end: 1781 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1782 return 0; 1783 } 1784 1785 #if NATAPIBUS > 0 1786 static void 1787 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1788 { 1789 struct ata_channel *chp = ata_sc->sc_chan; 1790 struct atac_softc *atac = chp->ch_atac; 1791 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1792 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1793 /* 1794 * Fill in the scsipi_adapter. 1795 */ 1796 adapt->adapt_dev = atac->atac_dev; 1797 adapt->adapt_nchannels = atac->atac_nchannels; 1798 adapt->adapt_request = ahci_atapi_scsipi_request; 1799 adapt->adapt_minphys = ahci_atapi_minphys; 1800 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1801 1802 /* 1803 * Fill in the scsipi_channel. 1804 */ 1805 memset(chan, 0, sizeof(*chan)); 1806 chan->chan_adapter = adapt; 1807 chan->chan_bustype = &ahci_atapi_bustype; 1808 chan->chan_channel = chp->ch_channel; 1809 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1810 chan->chan_openings = 1; 1811 chan->chan_max_periph = 1; 1812 chan->chan_ntargets = 1; 1813 chan->chan_nluns = 1; 1814 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1815 atapiprint); 1816 } 1817 1818 static void 1819 ahci_atapi_minphys(struct buf *bp) 1820 { 1821 if (bp->b_bcount > MAXPHYS) 1822 bp->b_bcount = MAXPHYS; 1823 minphys(bp); 1824 } 1825 1826 /* 1827 * Kill off all pending xfers for a periph. 1828 * 1829 * Must be called at splbio(). 1830 */ 1831 static void 1832 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1833 { 1834 struct atac_softc *atac = 1835 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1836 struct ata_channel *chp = 1837 atac->atac_channels[periph->periph_channel->chan_channel]; 1838 1839 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1840 } 1841 1842 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1843 .c_start = ahci_atapi_start, 1844 .c_poll = ahci_atapi_poll, 1845 .c_abort = ahci_atapi_abort, 1846 .c_intr = ahci_atapi_complete, 1847 .c_kill_xfer = ahci_atapi_kill_xfer, 1848 }; 1849 1850 static void 1851 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1852 scsipi_adapter_req_t req, void *arg) 1853 { 1854 struct scsipi_adapter *adapt = chan->chan_adapter; 1855 struct scsipi_periph *periph; 1856 struct scsipi_xfer *sc_xfer; 1857 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1858 struct atac_softc *atac = &sc->sc_atac; 1859 struct ata_xfer *xfer; 1860 int channel = chan->chan_channel; 1861 int drive, s; 1862 1863 switch (req) { 1864 case ADAPTER_REQ_RUN_XFER: 1865 sc_xfer = arg; 1866 periph = sc_xfer->xs_periph; 1867 drive = periph->periph_target; 1868 if (!device_is_active(atac->atac_dev)) { 1869 sc_xfer->error = XS_DRIVER_STUFFUP; 1870 scsipi_done(sc_xfer); 1871 return; 1872 } 1873 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1874 if (xfer == NULL) { 1875 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1876 scsipi_done(sc_xfer); 1877 return; 1878 } 1879 1880 if (sc_xfer->xs_control & XS_CTL_POLL) 1881 xfer->c_flags |= C_POLL; 1882 xfer->c_drive = drive; 1883 xfer->c_flags |= C_ATAPI; 1884 xfer->c_databuf = sc_xfer->data; 1885 xfer->c_bcount = sc_xfer->datalen; 1886 xfer->ops = &ahci_atapi_xfer_ops; 1887 xfer->c_scsipi = sc_xfer; 1888 xfer->c_atapi.c_dscpoll = 0; 1889 s = splbio(); 1890 ata_exec_xfer(atac->atac_channels[channel], xfer); 1891 #ifdef DIAGNOSTIC 1892 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1893 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1894 panic("ahci_atapi_scsipi_request: polled command " 1895 "not done"); 1896 #endif 1897 splx(s); 1898 return; 1899 default: 1900 /* Not supported, nothing to do. */ 1901 ; 1902 } 1903 } 1904 1905 static int 1906 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1907 { 1908 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1909 struct ahci_channel *achp = (struct ahci_channel *)chp; 1910 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1911 struct ahci_cmd_tbl *cmd_tbl; 1912 struct ahci_cmd_header *cmd_h; 1913 1914 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1915 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1916 1917 ata_channel_lock_owned(chp); 1918 1919 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1920 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1921 cmd_tbl), DEBUG_XFERS); 1922 1923 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1924 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1925 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1926 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1927 1928 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1929 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1930 chp->ch_channel, cmd_h), DEBUG_XFERS); 1931 if (ahci_dma_setup(chp, xfer->c_slot, 1932 sc_xfer->datalen ? sc_xfer->data : NULL, 1933 sc_xfer->datalen, 1934 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1935 BUS_DMA_READ : BUS_DMA_WRITE)) { 1936 sc_xfer->error = XS_DRIVER_STUFFUP; 1937 return ATASTART_ABORT; 1938 } 1939 cmd_h->cmdh_flags = htole16( 1940 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1941 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1942 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1943 cmd_h->cmdh_prdbc = 0; 1944 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1946 1947 if (xfer->c_flags & C_POLL) { 1948 /* polled command, disable interrupts */ 1949 AHCI_WRITE(sc, AHCI_GHC, 1950 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1951 } 1952 /* start command */ 1953 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1954 /* and says we started this command */ 1955 achp->ahcic_cmds_active |= 1U << xfer->c_slot; 1956 1957 if ((xfer->c_flags & C_POLL) == 0) { 1958 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1959 ata_timeout, chp); 1960 return ATASTART_STARTED; 1961 } else 1962 return ATASTART_POLL; 1963 } 1964 1965 static void 1966 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1967 { 1968 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1969 struct ahci_channel *achp = (struct ahci_channel *)chp; 1970 1971 /* 1972 * Polled command. 1973 */ 1974 for (int i = 0; i < ATA_DELAY / 10; i++) { 1975 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1976 break; 1977 ahci_intr_port(sc, achp); 1978 delay(10000); 1979 } 1980 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1981 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1982 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1983 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1984 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1985 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1986 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1987 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1988 DEBUG_XFERS); 1989 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1990 xfer->c_scsipi->error = XS_TIMEOUT; 1991 xfer->ops->c_intr(chp, xfer, 0); 1992 } 1993 /* reenable interrupts */ 1994 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1995 } 1996 1997 static void 1998 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1999 { 2000 ahci_atapi_complete(chp, xfer, 0); 2001 } 2002 2003 static int 2004 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 2005 { 2006 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2007 struct ahci_channel *achp = (struct ahci_channel *)chp; 2008 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 2009 2010 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 2011 DEBUG_FUNCS); 2012 2013 if (ata_waitdrain_xfer_check(chp, xfer)) 2014 return 0; 2015 2016 if (xfer->c_flags & C_TIMEOU) { 2017 sc_xfer->error = XS_TIMEOUT; 2018 } 2019 2020 if (xfer->c_bcount > 0) { 2021 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2022 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2023 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2024 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2025 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2026 } 2027 2028 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2029 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2030 sc_xfer->resid = sc_xfer->datalen; 2031 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2032 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2033 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2034 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2035 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2036 sc_xfer->resid == sc_xfer->datalen)) { 2037 sc_xfer->error = XS_SHORTSENSE; 2038 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2039 if ((sc_xfer->xs_periph->periph_quirks & 2040 PQUIRK_NOSENSE) == 0) { 2041 /* ask scsipi to send a REQUEST_SENSE */ 2042 sc_xfer->error = XS_BUSY; 2043 sc_xfer->status = SCSI_CHECK; 2044 } 2045 } 2046 2047 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 2048 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 2049 ata_deactivate_xfer(chp, xfer); 2050 2051 ata_free_xfer(chp, xfer); 2052 scsipi_done(sc_xfer); 2053 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2054 atastart(chp); 2055 return 0; 2056 } 2057 2058 static void 2059 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2060 { 2061 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2062 struct ahci_channel *achp = (struct ahci_channel *)chp; 2063 bool deactivate = true; 2064 2065 /* remove this command from xfer queue */ 2066 switch (reason) { 2067 case KILL_GONE_INACTIVE: 2068 deactivate = false; 2069 /* FALLTHROUGH */ 2070 case KILL_GONE: 2071 sc_xfer->error = XS_DRIVER_STUFFUP; 2072 break; 2073 case KILL_RESET: 2074 sc_xfer->error = XS_RESET; 2075 break; 2076 case KILL_REQUEUE: 2077 sc_xfer->error = XS_REQUEUE; 2078 break; 2079 default: 2080 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2081 panic("ahci_ata_atapi_kill_xfer"); 2082 } 2083 2084 if (deactivate) { 2085 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 2086 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 2087 ata_deactivate_xfer(chp, xfer); 2088 } 2089 2090 ata_free_xfer(chp, xfer); 2091 scsipi_done(sc_xfer); 2092 } 2093 2094 static void 2095 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2096 { 2097 struct scsipi_channel *chan = sc->sc_channel; 2098 struct scsipi_periph *periph; 2099 struct ataparams ids; 2100 struct ataparams *id = &ids; 2101 struct ahci_softc *ahcic = 2102 device_private(chan->chan_adapter->adapt_dev); 2103 struct atac_softc *atac = &ahcic->sc_atac; 2104 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2105 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2106 struct scsipibus_attach_args sa; 2107 char serial_number[21], model[41], firmware_revision[9]; 2108 int s; 2109 2110 /* skip if already attached */ 2111 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2112 return; 2113 2114 /* if no ATAPI device detected at attach time, skip */ 2115 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2116 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2117 "not present\n", target), DEBUG_PROBE); 2118 return; 2119 } 2120 2121 /* Some ATAPI devices need a bit more time after software reset. */ 2122 delay(5000); 2123 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2124 #ifdef ATAPI_DEBUG_PROBE 2125 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2126 AHCINAME(ahcic), target, 2127 id->atap_config & ATAPI_CFG_CMD_MASK, 2128 id->atap_config & ATAPI_CFG_DRQ_MASK); 2129 #endif 2130 periph = scsipi_alloc_periph(M_NOWAIT); 2131 if (periph == NULL) { 2132 aprint_error_dev(sc->sc_dev, 2133 "unable to allocate periph for drive %d\n", 2134 target); 2135 return; 2136 } 2137 periph->periph_dev = NULL; 2138 periph->periph_channel = chan; 2139 periph->periph_switch = &atapi_probe_periphsw; 2140 periph->periph_target = target; 2141 periph->periph_lun = 0; 2142 periph->periph_quirks = PQUIRK_ONLYBIG; 2143 2144 #ifdef SCSIPI_DEBUG 2145 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2146 SCSIPI_DEBUG_TARGET == target) 2147 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2148 #endif 2149 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2150 if (id->atap_config & ATAPI_CFG_REMOV) 2151 periph->periph_flags |= PERIPH_REMOVABLE; 2152 if (periph->periph_type == T_SEQUENTIAL) { 2153 s = splbio(); 2154 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2155 splx(s); 2156 } 2157 2158 sa.sa_periph = periph; 2159 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2160 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2161 T_REMOV : T_FIXED; 2162 strnvisx(model, sizeof(model), id->atap_model, 40, 2163 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2164 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2165 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2166 strnvisx(firmware_revision, sizeof(firmware_revision), 2167 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2168 sa.sa_inqbuf.vendor = model; 2169 sa.sa_inqbuf.product = serial_number; 2170 sa.sa_inqbuf.revision = firmware_revision; 2171 2172 /* 2173 * Determine the operating mode capabilities of the device. 2174 */ 2175 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2176 periph->periph_cap |= PERIPH_CAP_CMD16; 2177 /* XXX This is gross. */ 2178 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2179 2180 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2181 2182 if (drvp->drv_softc) 2183 ata_probe_caps(drvp); 2184 else { 2185 s = splbio(); 2186 drvp->drive_type = ATA_DRIVET_NONE; 2187 splx(s); 2188 } 2189 } else { 2190 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2191 "failed for drive %s:%d:%d\n", 2192 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2193 s = splbio(); 2194 drvp->drive_type = ATA_DRIVET_NONE; 2195 splx(s); 2196 } 2197 } 2198 #endif /* NATAPIBUS */ 2199
Indexes created Fri Oct 17 00:09:41 GMT 2025