ahcisata_core.c revision 1.62.2.9
1 /* $NetBSD: ahcisata_core.c,v 1.62.2.9 2018/10/11 20:57:51 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.62.2.9 2018/10/11 20:57:51 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 void ahci_channel_recover(struct ahci_softc *, struct ata_channel *, int); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending 125 }; 126 127 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 return 0; 170 } 171 172 static void 173 ahci_setup_ports(struct ahci_softc *sc) 174 { 175 int i, port; 176 177 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 178 if ((sc->sc_ahci_ports & (1U << i)) == 0) 179 continue; 180 if (port >= sc->sc_atac.atac_nchannels) { 181 aprint_error("%s: more ports than announced\n", 182 AHCINAME(sc)); 183 break; 184 } 185 ahci_setup_port(sc, i); 186 } 187 } 188 189 static void 190 ahci_reprobe_drives(struct ahci_softc *sc) 191 { 192 int i, port; 193 struct ahci_channel *achp; 194 struct ata_channel *chp; 195 196 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 197 if ((sc->sc_ahci_ports & (1U << i)) == 0) 198 continue; 199 if (port >= sc->sc_atac.atac_nchannels) { 200 aprint_error("%s: more ports than announced\n", 201 AHCINAME(sc)); 202 break; 203 } 204 achp = &sc->sc_channels[i]; 205 chp = &achp->ata_channel; 206 207 ahci_probe_drive(chp); 208 } 209 } 210 211 static void 212 ahci_setup_port(struct ahci_softc *sc, int i) 213 { 214 struct ahci_channel *achp; 215 216 achp = &sc->sc_channels[i]; 217 218 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 219 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 220 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 221 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 222 } 223 224 static void 225 ahci_enable_intrs(struct ahci_softc *sc) 226 { 227 228 /* clear interrupts */ 229 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 230 /* enable interrupts */ 231 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 232 } 233 234 void 235 ahci_attach(struct ahci_softc *sc) 236 { 237 uint32_t ahci_rev; 238 int i, j, port; 239 struct ahci_channel *achp; 240 struct ata_channel *chp; 241 int error; 242 int dmasize; 243 char buf[128]; 244 void *cmdhp; 245 void *cmdtblp; 246 247 if (sc->sc_save_init_data) { 248 ahci_enable(sc); 249 250 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 251 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 252 253 ahci_rev = AHCI_READ(sc, AHCI_VS); 254 if (AHCI_VS_MJR(ahci_rev) > 1 || 255 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 256 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 257 } else { 258 sc->sc_init_data.cap2 = 0; 259 } 260 if (sc->sc_init_data.ports == 0) { 261 sc->sc_init_data.ports = sc->sc_ahci_ports; 262 } 263 } 264 265 if (ahci_reset(sc) != 0) 266 return; 267 268 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 269 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 270 aprint_verbose_dev(sc->sc_atac.atac_dev, 271 "ignoring broken port multiplier support\n"); 272 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 273 } 274 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 275 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 276 ahci_rev = AHCI_READ(sc, AHCI_VS); 277 snprintb(buf, sizeof(buf), "\177\020" 278 /* "f\000\005NP\0" */ 279 "b\005SXS\0" 280 "b\006EMS\0" 281 "b\007CCCS\0" 282 /* "f\010\005NCS\0" */ 283 "b\015PSC\0" 284 "b\016SSC\0" 285 "b\017PMD\0" 286 "b\020FBSS\0" 287 "b\021SPM\0" 288 "b\022SAM\0" 289 "b\023SNZO\0" 290 "f\024\003ISS\0" 291 "=\001Gen1\0" 292 "=\002Gen2\0" 293 "=\003Gen3\0" 294 "b\030SCLO\0" 295 "b\031SAL\0" 296 "b\032SALP\0" 297 "b\033SSS\0" 298 "b\034SMPS\0" 299 "b\035SSNTF\0" 300 "b\036SNCQ\0" 301 "b\037S64A\0" 302 "\0", sc->sc_ahci_cap); 303 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 304 ", %d port%s, %d slot%s, CAP %s\n", 305 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 306 sc->sc_atac.atac_nchannels, 307 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 308 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 309 310 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 311 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 312 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 313 sc->sc_atac.atac_pio_cap = 4; 314 sc->sc_atac.atac_dma_cap = 2; 315 sc->sc_atac.atac_udma_cap = 6; 316 sc->sc_atac.atac_channels = sc->sc_chanarray; 317 sc->sc_atac.atac_probe = ahci_probe_drive; 318 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 319 sc->sc_atac.atac_set_modes = ahci_setup_channel; 320 #if NATAPIBUS > 0 321 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 322 #endif 323 324 dmasize = 325 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 326 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 327 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 328 if (error) { 329 aprint_error("%s: unable to allocate command header memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 return; 332 } 333 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 334 sc->sc_cmd_hdr_nseg, dmasize, 335 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 336 if (error) { 337 aprint_error("%s: unable to map command header memory" 338 ", error=%d\n", AHCINAME(sc), error); 339 return; 340 } 341 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 342 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 343 if (error) { 344 aprint_error("%s: unable to create command header map" 345 ", error=%d\n", AHCINAME(sc), error); 346 return; 347 } 348 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 349 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 350 if (error) { 351 aprint_error("%s: unable to load command header map" 352 ", error=%d\n", AHCINAME(sc), error); 353 return; 354 } 355 sc->sc_cmd_hdr = cmdhp; 356 357 ahci_enable_intrs(sc); 358 359 if (sc->sc_ahci_ports == 0) { 360 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 361 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 362 DEBUG_PROBE); 363 } 364 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 365 if ((sc->sc_ahci_ports & (1U << i)) == 0) 366 continue; 367 if (port >= sc->sc_atac.atac_nchannels) { 368 aprint_error("%s: more ports than announced\n", 369 AHCINAME(sc)); 370 break; 371 } 372 achp = &sc->sc_channels[i]; 373 chp = &achp->ata_channel; 374 sc->sc_chanarray[i] = chp; 375 chp->ch_channel = i; 376 chp->ch_atac = &sc->sc_atac; 377 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 378 if (chp->ch_queue == NULL) { 379 aprint_error("%s port %d: can't allocate memory for " 380 "command queue", AHCINAME(sc), i); 381 break; 382 } 383 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 384 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 385 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 386 BUS_DMA_NOWAIT); 387 if (error) { 388 aprint_error("%s: unable to allocate command table " 389 "memory, error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 393 achp->ahcic_cmd_tbl_nseg, dmasize, 394 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 395 if (error) { 396 aprint_error("%s: unable to map command table memory" 397 ", error=%d\n", AHCINAME(sc), error); 398 break; 399 } 400 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 401 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 402 if (error) { 403 aprint_error("%s: unable to create command table map" 404 ", error=%d\n", AHCINAME(sc), error); 405 break; 406 } 407 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 408 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 409 if (error) { 410 aprint_error("%s: unable to load command table map" 411 ", error=%d\n", AHCINAME(sc), error); 412 break; 413 } 414 achp->ahcic_cmdh = (struct ahci_cmd_header *) 415 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 416 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 417 AHCI_CMDH_SIZE * port; 418 achp->ahcic_rfis = (struct ahci_r_fis *) 419 ((char *)cmdhp + 420 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 421 AHCI_RFIS_SIZE * port); 422 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port; 425 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 426 "rfis %p (0x%" PRIx64 ")\n", i, 427 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 428 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 429 DEBUG_PROBE); 430 431 for (j = 0; j < sc->sc_ncmds; j++) { 432 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 433 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 434 achp->ahcic_bus_cmd_tbl[j] = 435 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 436 AHCI_CMDTBL_SIZE * j; 437 achp->ahcic_cmdh[j].cmdh_cmdtba = 438 htole64(achp->ahcic_bus_cmd_tbl[j]); 439 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 440 achp->ahcic_cmd_tbl[j], 441 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 442 /* The xfer DMA map */ 443 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 444 AHCI_NPRD, 0x400000 /* 4MB */, 0, 445 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 446 &achp->ahcic_datad[j]); 447 if (error) { 448 aprint_error("%s: couldn't alloc xfer DMA map, " 449 "error=%d\n", AHCINAME(sc), error); 450 goto end; 451 } 452 } 453 ahci_setup_port(sc, i); 454 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 455 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 456 aprint_error("%s: couldn't map channel %d " 457 "sata_status regs\n", AHCINAME(sc), i); 458 break; 459 } 460 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 461 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 462 aprint_error("%s: couldn't map channel %d " 463 "sata_control regs\n", AHCINAME(sc), i); 464 break; 465 } 466 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 467 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 468 aprint_error("%s: couldn't map channel %d " 469 "sata_error regs\n", AHCINAME(sc), i); 470 break; 471 } 472 ata_channel_attach(chp); 473 port++; 474 end: 475 continue; 476 } 477 } 478 479 int 480 ahci_detach(struct ahci_softc *sc, int flags) 481 { 482 struct atac_softc *atac; 483 struct ahci_channel *achp; 484 struct ata_channel *chp; 485 struct scsipi_adapter *adapt; 486 int i, j; 487 int error; 488 489 atac = &sc->sc_atac; 490 adapt = &atac->atac_atapi_adapter._generic; 491 492 for (i = 0; i < AHCI_MAX_PORTS; i++) { 493 achp = &sc->sc_channels[i]; 494 chp = &achp->ata_channel; 495 496 if ((sc->sc_ahci_ports & (1U << i)) == 0) 497 continue; 498 if (i >= sc->sc_atac.atac_nchannels) { 499 aprint_error("%s: more ports than announced\n", 500 AHCINAME(sc)); 501 break; 502 } 503 504 if (chp->atabus == NULL) 505 continue; 506 if ((error = config_detach(chp->atabus, flags)) != 0) 507 return error; 508 509 for (j = 0; j < sc->sc_ncmds; j++) 510 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 511 512 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 513 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 514 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 515 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 516 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 517 achp->ahcic_cmd_tbl_nseg); 518 519 chp->atabus = NULL; 520 521 ata_channel_detach(chp); 522 } 523 524 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 525 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 526 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 527 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 528 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 529 530 if (adapt->adapt_refcnt != 0) 531 return EBUSY; 532 533 return 0; 534 } 535 536 void 537 ahci_resume(struct ahci_softc *sc) 538 { 539 ahci_reset(sc); 540 ahci_setup_ports(sc); 541 ahci_reprobe_drives(sc); 542 ahci_enable_intrs(sc); 543 } 544 545 int 546 ahci_intr(void *v) 547 { 548 struct ahci_softc *sc = v; 549 uint32_t is; 550 int i, r = 0; 551 552 while ((is = AHCI_READ(sc, AHCI_IS))) { 553 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 554 DEBUG_INTR); 555 r = 1; 556 AHCI_WRITE(sc, AHCI_IS, is); 557 for (i = 0; i < AHCI_MAX_PORTS; i++) 558 if (is & (1U << i)) 559 ahci_intr_port(sc, &sc->sc_channels[i]); 560 } 561 return r; 562 } 563 564 static void 565 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 566 { 567 uint32_t is, tfd, sact; 568 struct ata_channel *chp = &achp->ata_channel; 569 struct ata_xfer *xfer; 570 int slot = -1; 571 bool recover = false; 572 uint32_t aslots; 573 574 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 575 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 576 577 AHCIDEBUG_PRINT(( 578 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 579 AHCINAME(sc), 580 chp->ch_channel, is, 581 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 582 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 583 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 584 DEBUG_INTR); 585 586 if ((chp->ch_flags & ATACH_NCQ) == 0) { 587 /* Non-NCQ operation */ 588 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 589 } else { 590 /* NCQ operation */ 591 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 592 } 593 594 /* Handle errors */ 595 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 596 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 597 /* Fatal errors */ 598 if (is & AHCI_P_IX_TFES) { 599 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 600 601 if ((chp->ch_flags & ATACH_NCQ) == 0) { 602 /* Slot valid only for Non-NCQ operation */ 603 slot = (AHCI_READ(sc, 604 AHCI_P_CMD(chp->ch_channel)) 605 & AHCI_P_CMD_CCS_MASK) 606 >> AHCI_P_CMD_CCS_SHIFT; 607 } 608 609 AHCIDEBUG_PRINT(( 610 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 611 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 612 DEBUG_INTR); 613 } else { 614 /* mark an error, and set BSY */ 615 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 616 WDCS_ERR | WDCS_BSY; 617 } 618 619 if (is & AHCI_P_IX_IFS) { 620 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 621 AHCINAME(sc), chp->ch_channel, 622 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 623 DEBUG_INTR); 624 } 625 626 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 627 recover = true; 628 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 629 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 630 631 /* D2H Register FIS or Set Device Bits */ 632 if ((tfd & WDCS_ERR) != 0) { 633 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 634 recover = true; 635 636 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 637 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 638 639 } 640 } else { 641 tfd = 0; 642 } 643 644 if (__predict_false(recover)) 645 ata_channel_freeze(chp); 646 647 aslots = ata_queue_active(chp); 648 649 if (slot >= 0) { 650 if ((aslots & __BIT(slot)) != 0 && 651 (sact & __BIT(slot)) == 0) { 652 xfer = ata_queue_hwslot_to_xfer(chp, slot); 653 xfer->ops->c_intr(chp, xfer, tfd); 654 } 655 } else { 656 /* 657 * For NCQ, HBA halts processing when error is notified, 658 * and any further D2H FISes are ignored until the error 659 * condition is cleared. Hence if a command is inactive, 660 * it means it actually already finished successfully. 661 * Note: active slots can change as c_intr() callback 662 * can activate another command(s), so must only process 663 * commands active before we start processing. 664 */ 665 666 for (slot=0; slot < sc->sc_ncmds; slot++) { 667 if ((aslots & __BIT(slot)) != 0 && 668 (sact & __BIT(slot)) == 0) { 669 xfer = ata_queue_hwslot_to_xfer(chp, slot); 670 xfer->ops->c_intr(chp, xfer, tfd); 671 } 672 } 673 } 674 675 if (__predict_false(recover)) { 676 ata_channel_thaw(chp); 677 ahci_channel_recover(sc, chp, tfd); 678 } 679 } 680 681 static void 682 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 683 { 684 struct ata_channel *chp = drvp->chnl_softc; 685 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 686 uint8_t c_slot; 687 688 ata_channel_lock_owned(chp); 689 690 /* get a slot for running the command on */ 691 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 692 panic("%s: %s: failed to get xfer for reset, port %d\n", 693 device_xname(sc->sc_atac.atac_dev), 694 __func__, chp->ch_channel); 695 /* NOTREACHED */ 696 } 697 698 AHCI_WRITE(sc, AHCI_GHC, 699 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 700 ahci_channel_stop(sc, chp, flags); 701 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 702 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 703 704 ata_queue_free_slot(chp, c_slot); 705 } 706 707 /* return error code from ata_bio */ 708 static int 709 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 710 { 711 struct ahci_channel *achp = (struct ahci_channel *)chp; 712 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 713 int i; 714 uint32_t is; 715 716 /* 717 * Base timeout is specified in ms. 718 * If we are allowed to sleep, wait a tick each round. 719 * Otherwise delay for 10ms on each round. 720 */ 721 if (flags & AT_WAIT) 722 timeout = MAX(1, mstohz(timeout)); 723 else 724 timeout = timeout / 10; 725 726 AHCI_CMDH_SYNC(sc, achp, slot, 727 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 728 /* start command */ 729 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 730 for (i = 0; i < timeout; i++) { 731 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 732 0) 733 return 0; 734 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 735 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 736 AHCI_P_IX_IFS | 737 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 738 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 739 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 740 /* 741 * we got the D2H FIS anyway, 742 * assume sig is valid. 743 * channel is restarted later 744 */ 745 return ERROR; 746 } 747 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 748 AHCINAME(sc), chp->ch_channel, is); 749 return ERR_DF; 750 } 751 ata_delay(chp, 10, "ahcifis", flags); 752 } 753 754 aprint_debug("%s channel %d: timeout sending FIS\n", 755 AHCINAME(sc), chp->ch_channel); 756 return TIMEOUT; 757 } 758 759 static int 760 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 761 uint32_t *sigp, uint8_t c_slot) 762 { 763 struct ahci_channel *achp = (struct ahci_channel *)chp; 764 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 765 struct ahci_cmd_tbl *cmd_tbl; 766 struct ahci_cmd_header *cmd_h; 767 int i; 768 uint32_t sig; 769 770 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 771 ata_channel_lock_owned(chp); 772 773 again: 774 /* clear port interrupt register */ 775 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 776 /* clear SErrors and start operations */ 777 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 778 /* 779 * issue a command list override to clear BSY. 780 * This is needed if there's a PMP with no drive 781 * on port 0 782 */ 783 ahci_channel_start(sc, chp, flags, 1); 784 } else { 785 ahci_channel_start(sc, chp, flags, 0); 786 } 787 if (drive > 0) { 788 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 789 } 790 791 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 792 goto skip_reset; 793 794 /* polled command, assume interrupts are disabled */ 795 796 cmd_h = &achp->ahcic_cmdh[c_slot]; 797 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 798 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 799 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 800 cmd_h->cmdh_prdbc = 0; 801 memset(cmd_tbl->cmdt_cfis, 0, 64); 802 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 803 cmd_tbl->cmdt_cfis[rhd_c] = drive; 804 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 805 switch(ahci_exec_fis(chp, 100, flags, c_slot)) { 806 case ERR_DF: 807 case TIMEOUT: 808 aprint_error("%s channel %d: setting WDCTL_RST failed " 809 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 810 if (sigp) 811 *sigp = 0xffffffff; 812 goto end; 813 default: 814 break; 815 } 816 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 817 (drive << AHCI_CMDH_F_PMP_SHIFT)); 818 cmd_h->cmdh_prdbc = 0; 819 memset(cmd_tbl->cmdt_cfis, 0, 64); 820 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 821 cmd_tbl->cmdt_cfis[rhd_c] = drive; 822 cmd_tbl->cmdt_cfis[rhd_control] = 0; 823 switch(ahci_exec_fis(chp, 310, flags, c_slot)) { 824 case ERR_DF: 825 case TIMEOUT: 826 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 827 drive == PMP_PORT_CTL) { 828 /* 829 * some controllers fails to reset when 830 * targeting a PMP but a single drive is attached. 831 * try again with port 0 832 */ 833 drive = 0; 834 ahci_channel_stop(sc, chp, flags); 835 goto again; 836 } 837 aprint_error("%s channel %d: clearing WDCTL_RST failed " 838 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 839 if (sigp) 840 *sigp = 0xffffffff; 841 goto end; 842 default: 843 break; 844 } 845 846 skip_reset: 847 /* 848 * wait 31s for BSY to clear 849 * This should not be needed, but some controllers clear the 850 * command slot before receiving the D2H FIS ... 851 */ 852 for (i = 0; i < AHCI_RST_WAIT; i++) { 853 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 854 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 855 break; 856 ata_delay(chp, 10, "ahcid2h", flags); 857 } 858 if (i == AHCI_RST_WAIT) { 859 aprint_error("%s: BSY never cleared, TD 0x%x\n", 860 AHCINAME(sc), sig); 861 if (sigp) 862 *sigp = 0xffffffff; 863 goto end; 864 } 865 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 866 DEBUG_PROBE); 867 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 868 if (sigp) 869 *sigp = sig; 870 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 871 AHCINAME(sc), chp->ch_channel, sig, 872 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 873 end: 874 ahci_channel_stop(sc, chp, flags); 875 ata_delay(chp, 500, "ahcirst", flags); 876 /* clear port interrupt register */ 877 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 878 ahci_channel_start(sc, chp, flags, 879 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 880 return 0; 881 } 882 883 static void 884 ahci_reset_channel(struct ata_channel *chp, int flags) 885 { 886 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 887 struct ahci_channel *achp = (struct ahci_channel *)chp; 888 int i, tfd; 889 890 ata_channel_lock_owned(chp); 891 892 ahci_channel_stop(sc, chp, flags); 893 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 894 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 895 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 896 /* XXX and then ? */ 897 } 898 ata_kill_active(chp, KILL_RESET, flags); 899 ata_delay(chp, 500, "ahcirst", flags); 900 /* clear port interrupt register */ 901 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 902 /* clear SErrors and start operations */ 903 ahci_channel_start(sc, chp, flags, 904 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 905 /* wait 31s for BSY to clear */ 906 for (i = 0; i <AHCI_RST_WAIT; i++) { 907 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 908 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 909 break; 910 ata_delay(chp, 10, "ahcid2h", flags); 911 } 912 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 913 aprint_error("%s: BSY never cleared, TD 0x%x\n", 914 AHCINAME(sc), tfd); 915 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 916 DEBUG_PROBE); 917 /* clear port interrupt register */ 918 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 919 920 return; 921 } 922 923 static int 924 ahci_ata_addref(struct ata_drive_datas *drvp) 925 { 926 return 0; 927 } 928 929 static void 930 ahci_ata_delref(struct ata_drive_datas *drvp) 931 { 932 return; 933 } 934 935 static void 936 ahci_killpending(struct ata_drive_datas *drvp) 937 { 938 return; 939 } 940 941 static void 942 ahci_probe_drive(struct ata_channel *chp) 943 { 944 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 945 struct ahci_channel *achp = (struct ahci_channel *)chp; 946 uint32_t sig; 947 uint8_t c_slot; 948 949 ata_channel_lock(chp); 950 951 /* get a slot for running the command on */ 952 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 953 aprint_error_dev(sc->sc_atac.atac_dev, 954 "%s: failed to get xfer port %d\n", 955 __func__, chp->ch_channel); 956 ata_channel_unlock(chp); 957 return; 958 } 959 960 /* bring interface up, accept FISs, power up and spin up device */ 961 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 962 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 963 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 964 /* reset the PHY and bring online */ 965 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 966 achp->ahcic_sstatus, AT_WAIT)) { 967 case SStatus_DET_DEV: 968 ata_delay(chp, 500, "ahcidv", AT_WAIT); 969 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 970 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig, 971 c_slot); 972 } else { 973 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 974 } 975 sata_interpret_sig(chp, 0, sig); 976 /* if we have a PMP attached, inform the controller */ 977 if (chp->ch_ndrives > PMP_PORT_CTL && 978 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 979 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 980 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 981 AHCI_P_CMD_PMA); 982 } 983 /* clear port interrupt register */ 984 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 985 986 /* and enable interrupts */ 987 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 988 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 989 AHCI_P_IX_IFS | 990 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 991 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 992 /* wait 500ms before actually starting operations */ 993 ata_delay(chp, 500, "ahciprb", AT_WAIT); 994 break; 995 996 default: 997 break; 998 } 999 1000 ata_queue_free_slot(chp, c_slot); 1001 1002 ata_channel_unlock(chp); 1003 } 1004 1005 static void 1006 ahci_setup_channel(struct ata_channel *chp) 1007 { 1008 return; 1009 } 1010 1011 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1012 .c_start = ahci_cmd_start, 1013 .c_poll = ahci_cmd_poll, 1014 .c_abort = ahci_cmd_abort, 1015 .c_intr = ahci_cmd_complete, 1016 .c_kill_xfer = ahci_cmd_kill_xfer, 1017 }; 1018 1019 static int 1020 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1021 { 1022 struct ata_channel *chp = drvp->chnl_softc; 1023 struct ata_command *ata_c = &xfer->c_ata_c; 1024 int ret; 1025 int s; 1026 1027 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1028 chp->ch_channel, 1029 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1030 DEBUG_XFERS); 1031 if (ata_c->flags & AT_POLL) 1032 xfer->c_flags |= C_POLL; 1033 if (ata_c->flags & AT_WAIT) 1034 xfer->c_flags |= C_WAIT; 1035 xfer->c_drive = drvp->drive; 1036 xfer->c_databuf = ata_c->data; 1037 xfer->c_bcount = ata_c->bcount; 1038 xfer->ops = &ahci_cmd_xfer_ops; 1039 s = splbio(); 1040 ata_exec_xfer(chp, xfer); 1041 #ifdef DIAGNOSTIC 1042 if ((ata_c->flags & AT_POLL) != 0 && 1043 (ata_c->flags & AT_DONE) == 0) 1044 panic("ahci_exec_command: polled command not done"); 1045 #endif 1046 if (ata_c->flags & AT_DONE) { 1047 ret = ATACMD_COMPLETE; 1048 } else { 1049 if (ata_c->flags & AT_WAIT) { 1050 ata_wait_cmd(chp, xfer); 1051 ret = ATACMD_COMPLETE; 1052 } else { 1053 ret = ATACMD_QUEUED; 1054 } 1055 } 1056 splx(s); 1057 return ret; 1058 } 1059 1060 static int 1061 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1062 { 1063 struct ahci_softc *sc = AHCI_CH2SC(chp); 1064 struct ahci_channel *achp = (struct ahci_channel *)chp; 1065 struct ata_command *ata_c = &xfer->c_ata_c; 1066 int slot = xfer->c_slot; 1067 struct ahci_cmd_tbl *cmd_tbl; 1068 struct ahci_cmd_header *cmd_h; 1069 1070 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1071 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1072 ata_c->timeout, slot), 1073 DEBUG_XFERS); 1074 1075 ata_channel_lock_owned(chp); 1076 1077 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1078 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1079 cmd_tbl), DEBUG_XFERS); 1080 1081 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1082 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1083 1084 cmd_h = &achp->ahcic_cmdh[slot]; 1085 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1086 chp->ch_channel, cmd_h), DEBUG_XFERS); 1087 if (ahci_dma_setup(chp, slot, 1088 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1089 ata_c->data : NULL, 1090 ata_c->bcount, 1091 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1092 ata_c->flags |= AT_DF; 1093 return ATASTART_ABORT; 1094 } 1095 cmd_h->cmdh_flags = htole16( 1096 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1097 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1098 cmd_h->cmdh_prdbc = 0; 1099 AHCI_CMDH_SYNC(sc, achp, slot, 1100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1101 1102 if (ata_c->flags & AT_POLL) { 1103 /* polled command, disable interrupts */ 1104 AHCI_WRITE(sc, AHCI_GHC, 1105 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1106 } 1107 /* start command */ 1108 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1109 1110 if ((ata_c->flags & AT_POLL) == 0) { 1111 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1112 ata_timeout, chp); 1113 return ATASTART_STARTED; 1114 } else 1115 return ATASTART_POLL; 1116 } 1117 1118 static void 1119 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1120 { 1121 struct ahci_softc *sc = AHCI_CH2SC(chp); 1122 struct ahci_channel *achp = (struct ahci_channel *)chp; 1123 1124 ata_channel_lock(chp); 1125 1126 /* 1127 * Polled command. 1128 */ 1129 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1130 if (xfer->c_ata_c.flags & AT_DONE) 1131 break; 1132 ata_channel_unlock(chp); 1133 ahci_intr_port(sc, achp); 1134 ata_channel_lock(chp); 1135 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1136 } 1137 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1138 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1139 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1140 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1141 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1142 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1143 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1144 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1145 DEBUG_XFERS); 1146 1147 ata_channel_unlock(chp); 1148 1149 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1150 xfer->c_ata_c.flags |= AT_TIMEOU; 1151 xfer->ops->c_intr(chp, xfer, 0); 1152 } 1153 /* reenable interrupts */ 1154 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1155 } 1156 1157 static void 1158 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1159 { 1160 ahci_cmd_complete(chp, xfer, 0); 1161 } 1162 1163 static void 1164 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1165 { 1166 struct ata_command *ata_c = &xfer->c_ata_c; 1167 bool deactivate = true; 1168 1169 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1170 DEBUG_FUNCS); 1171 1172 switch (reason) { 1173 case KILL_GONE_INACTIVE: 1174 deactivate = false; 1175 /* FALLTHROUGH */ 1176 case KILL_GONE: 1177 ata_c->flags |= AT_GONE; 1178 break; 1179 case KILL_RESET: 1180 ata_c->flags |= AT_RESET; 1181 break; 1182 case KILL_REQUEUE: 1183 panic("%s: not supposed to be requeued\n", __func__); 1184 break; 1185 default: 1186 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1187 panic("ahci_cmd_kill_xfer"); 1188 } 1189 1190 ahci_cmd_done_end(chp, xfer); 1191 1192 if (deactivate) 1193 ata_deactivate_xfer(chp, xfer); 1194 } 1195 1196 static int 1197 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1198 { 1199 struct ata_command *ata_c = &xfer->c_ata_c; 1200 struct ahci_channel *achp = (struct ahci_channel *)chp; 1201 1202 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1203 chp->ch_channel, 1204 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1205 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1206 DEBUG_FUNCS); 1207 1208 if (ata_waitdrain_xfer_check(chp, xfer)) 1209 return 0; 1210 1211 if (xfer->c_flags & C_TIMEOU) { 1212 ata_c->flags |= AT_TIMEOU; 1213 } 1214 1215 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1216 ata_c->flags |= AT_TIMEOU; 1217 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1218 ata_c->r_error = AHCI_TFD_ERR(tfd); 1219 ata_c->flags |= AT_ERROR; 1220 } 1221 1222 if (ata_c->flags & AT_READREG) 1223 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1224 1225 ahci_cmd_done(chp, xfer); 1226 1227 ata_deactivate_xfer(chp, xfer); 1228 1229 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1230 atastart(chp); 1231 1232 return 0; 1233 } 1234 1235 static void 1236 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1237 { 1238 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1239 struct ahci_channel *achp = (struct ahci_channel *)chp; 1240 struct ata_command *ata_c = &xfer->c_ata_c; 1241 uint16_t *idwordbuf; 1242 int i; 1243 1244 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n", 1245 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1246 1247 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1248 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1249 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1250 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1251 BUS_DMASYNC_POSTWRITE); 1252 bus_dmamap_unload(sc->sc_dmat, map); 1253 } 1254 1255 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1256 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1257 1258 /* ata(4) expects IDENTIFY data to be in host endianess */ 1259 if (ata_c->r_command == WDCC_IDENTIFY || 1260 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1261 idwordbuf = xfer->c_databuf; 1262 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1263 idwordbuf[i] = le16toh(idwordbuf[i]); 1264 } 1265 } 1266 1267 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1268 ata_c->flags |= AT_XFDONE; 1269 1270 ahci_cmd_done_end(chp, xfer); 1271 } 1272 1273 static void 1274 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1275 { 1276 struct ata_command *ata_c = &xfer->c_ata_c; 1277 1278 ata_c->flags |= AT_DONE; 1279 } 1280 1281 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1282 .c_start = ahci_bio_start, 1283 .c_poll = ahci_bio_poll, 1284 .c_abort = ahci_bio_abort, 1285 .c_intr = ahci_bio_complete, 1286 .c_kill_xfer = ahci_bio_kill_xfer, 1287 }; 1288 1289 static int 1290 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1291 { 1292 struct ata_channel *chp = drvp->chnl_softc; 1293 struct ata_bio *ata_bio = &xfer->c_bio; 1294 1295 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1296 chp->ch_channel, 1297 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1298 DEBUG_XFERS); 1299 if (ata_bio->flags & ATA_POLL) 1300 xfer->c_flags |= C_POLL; 1301 xfer->c_drive = drvp->drive; 1302 xfer->c_databuf = ata_bio->databuf; 1303 xfer->c_bcount = ata_bio->bcount; 1304 xfer->ops = &ahci_bio_xfer_ops; 1305 ata_exec_xfer(chp, xfer); 1306 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1307 } 1308 1309 static int 1310 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1311 { 1312 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1313 struct ahci_channel *achp = (struct ahci_channel *)chp; 1314 struct ata_bio *ata_bio = &xfer->c_bio; 1315 struct ahci_cmd_tbl *cmd_tbl; 1316 struct ahci_cmd_header *cmd_h; 1317 1318 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1319 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1320 1321 ata_channel_lock_owned(chp); 1322 1323 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1324 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1325 cmd_tbl), DEBUG_XFERS); 1326 1327 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1328 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1329 1330 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1331 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1332 chp->ch_channel, cmd_h), DEBUG_XFERS); 1333 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1334 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1335 ata_bio->error = ERR_DMA; 1336 ata_bio->r_error = 0; 1337 return ATASTART_ABORT; 1338 } 1339 cmd_h->cmdh_flags = htole16( 1340 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1341 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1342 cmd_h->cmdh_prdbc = 0; 1343 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1344 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1345 1346 if (xfer->c_flags & C_POLL) { 1347 /* polled command, disable interrupts */ 1348 AHCI_WRITE(sc, AHCI_GHC, 1349 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1350 } 1351 if (xfer->c_flags & C_NCQ) 1352 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1353 /* start command */ 1354 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1355 1356 if ((xfer->c_flags & C_POLL) == 0) { 1357 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1358 ata_timeout, chp); 1359 return ATASTART_STARTED; 1360 } else 1361 return ATASTART_POLL; 1362 } 1363 1364 static void 1365 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1366 { 1367 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1368 struct ahci_channel *achp = (struct ahci_channel *)chp; 1369 1370 /* 1371 * Polled command. 1372 */ 1373 for (int i = 0; i < ATA_DELAY * 10; i++) { 1374 if (xfer->c_bio.flags & ATA_ITSDONE) 1375 break; 1376 ahci_intr_port(sc, achp); 1377 delay(100); 1378 } 1379 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1380 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1381 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1382 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1383 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1384 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1385 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1386 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1387 DEBUG_XFERS); 1388 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1389 xfer->c_bio.error = TIMEOUT; 1390 xfer->ops->c_intr(chp, xfer, 0); 1391 } 1392 /* reenable interrupts */ 1393 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1394 } 1395 1396 static void 1397 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1398 { 1399 ahci_bio_complete(chp, xfer, 0); 1400 } 1401 1402 static void 1403 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1404 { 1405 int drive = xfer->c_drive; 1406 struct ata_bio *ata_bio = &xfer->c_bio; 1407 bool deactivate = true; 1408 1409 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1410 DEBUG_FUNCS); 1411 1412 ata_bio->flags |= ATA_ITSDONE; 1413 switch (reason) { 1414 case KILL_GONE_INACTIVE: 1415 deactivate = false; 1416 /* FALLTHROUGH */ 1417 case KILL_GONE: 1418 ata_bio->error = ERR_NODEV; 1419 break; 1420 case KILL_RESET: 1421 ata_bio->error = ERR_RESET; 1422 break; 1423 case KILL_REQUEUE: 1424 ata_bio->error = REQUEUE; 1425 break; 1426 default: 1427 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1428 panic("ahci_bio_kill_xfer"); 1429 } 1430 ata_bio->r_error = WDCE_ABRT; 1431 1432 if (deactivate) 1433 ata_deactivate_xfer(chp, xfer); 1434 1435 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1436 } 1437 1438 static int 1439 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1440 { 1441 struct ata_bio *ata_bio = &xfer->c_bio; 1442 int drive = xfer->c_drive; 1443 struct ahci_channel *achp = (struct ahci_channel *)chp; 1444 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1445 1446 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1447 DEBUG_FUNCS); 1448 1449 if (ata_waitdrain_xfer_check(chp, xfer)) 1450 return 0; 1451 1452 if (xfer->c_flags & C_TIMEOU) { 1453 ata_bio->error = TIMEOUT; 1454 } 1455 1456 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1457 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1458 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1459 BUS_DMASYNC_POSTWRITE); 1460 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1461 1462 ata_bio->flags |= ATA_ITSDONE; 1463 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1464 ata_bio->error = ERR_DF; 1465 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1466 ata_bio->error = ERROR; 1467 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1468 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1469 ata_bio->flags |= ATA_CORR; 1470 1471 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1472 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1473 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1474 ata_bio->bcount), DEBUG_XFERS); 1475 /* 1476 * If it was a write, complete data buffer may have been transfered 1477 * before error detection; in this case don't use cmdh_prdbc 1478 * as it won't reflect what was written to media. Assume nothing 1479 * was transfered and leave bcount as-is. 1480 * For queued commands, PRD Byte Count should not be used, and is 1481 * not required to be valid; in that case underflow is always illegal. 1482 */ 1483 if ((xfer->c_flags & C_NCQ) != 0) { 1484 if (ata_bio->error == NOERROR) 1485 ata_bio->bcount = 0; 1486 } else { 1487 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1488 ata_bio->bcount -= 1489 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1490 } 1491 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1492 1493 ata_deactivate_xfer(chp, xfer); 1494 1495 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1496 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1497 atastart(chp); 1498 return 0; 1499 } 1500 1501 static void 1502 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1503 { 1504 int i; 1505 /* stop channel */ 1506 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1507 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1508 /* wait 1s for channel to stop */ 1509 for (i = 0; i <100; i++) { 1510 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1511 == 0) 1512 break; 1513 ata_delay(chp, 10, "ahcistop", flags); 1514 } 1515 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1516 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1517 /* XXX controller reset ? */ 1518 return; 1519 } 1520 1521 if (sc->sc_channel_stop) 1522 sc->sc_channel_stop(sc, chp); 1523 } 1524 1525 static void 1526 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1527 int flags, int clo) 1528 { 1529 int i; 1530 uint32_t p_cmd; 1531 /* clear error */ 1532 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1533 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1534 1535 if (clo) { 1536 /* issue command list override */ 1537 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1538 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1539 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1540 /* wait 1s for AHCI_CAP_CLO to clear */ 1541 for (i = 0; i <100; i++) { 1542 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1543 AHCI_P_CMD_CLO) == 0) 1544 break; 1545 ata_delay(chp, 10, "ahciclo", flags); 1546 } 1547 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1548 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1549 /* XXX controller reset ? */ 1550 return; 1551 } 1552 } 1553 1554 if (sc->sc_channel_start) 1555 sc->sc_channel_start(sc, chp); 1556 1557 /* and start controller */ 1558 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1559 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1560 if (chp->ch_ndrives > PMP_PORT_CTL && 1561 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1562 p_cmd |= AHCI_P_CMD_PMA; 1563 } 1564 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1565 } 1566 1567 /* Recover channel after command failure */ 1568 void 1569 ahci_channel_recover(struct ahci_softc *sc, struct ata_channel *chp, int tfd) 1570 { 1571 int drive = ATACH_NODRIVE; 1572 bool reset = false; 1573 1574 ata_channel_lock(chp); 1575 KASSERT(!ISSET(chp->ch_flags, ATACH_RECOVERING)); 1576 SET(chp->ch_flags, ATACH_RECOVERING); 1577 ata_channel_unlock(chp); 1578 1579 /* 1580 * Read FBS to get the drive which caused the error, if PM is in use. 1581 * According to AHCI 1.3 spec, this register is available regardless 1582 * if FIS-based switching (FBSS) feature is supported, or disabled. 1583 * If FIS-based switching is not in use, it merely maintains single 1584 * pair of DRQ/BSY state, but it is enough since in that case we 1585 * never issue commands for more than one device at the time anyway. 1586 * XXX untested 1587 */ 1588 if (chp->ch_ndrives > PMP_PORT_CTL) { 1589 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1590 if (fbs & AHCI_P_FBS_SDE) { 1591 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1592 1593 /* 1594 * Tell HBA to reset PM port X (value in DWE) state, 1595 * and resume processing commands for other ports. 1596 */ 1597 fbs |= AHCI_P_FBS_DEC; 1598 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1599 for (int i = 0; i < 1000; i++) { 1600 fbs = AHCI_READ(sc, 1601 AHCI_P_FBS(chp->ch_channel)); 1602 if ((fbs & AHCI_P_FBS_DEC) == 0) 1603 break; 1604 DELAY(1000); 1605 } 1606 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1607 /* follow non-device specific recovery */ 1608 drive = ATACH_NODRIVE; 1609 reset = true; 1610 } 1611 } else { 1612 /* not device specific, reset channel */ 1613 drive = ATACH_NODRIVE; 1614 reset = true; 1615 } 1616 } else 1617 drive = 0; 1618 1619 /* 1620 * If BSY or DRQ bits are set, must execute COMRESET to return 1621 * device to idle state. If drive is idle, it's enough to just 1622 * reset CMD.ST, it's not necessary to do software reset. 1623 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1624 * to unblock device processing if COMRESET was not done. 1625 */ 1626 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1627 ata_channel_lock(chp); 1628 ahci_reset_channel(chp, AT_POLL); 1629 ata_channel_unlock(chp); 1630 goto out; 1631 } 1632 1633 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1634 ahci_channel_stop(sc, chp, AT_POLL); 1635 ahci_channel_start(sc, chp, AT_POLL, 1636 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1637 1638 ata_recovery_resume(chp, drive, tfd, AT_POLL); 1639 1640 out: 1641 /* Drive unblocked, back to normal operation */ 1642 ata_channel_lock(chp); 1643 CLR(chp->ch_flags, ATACH_RECOVERING); 1644 ata_channel_unlock(chp); 1645 1646 atastart(chp); 1647 } 1648 1649 static int 1650 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1651 size_t count, int op) 1652 { 1653 int error, seg; 1654 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1655 struct ahci_channel *achp = (struct ahci_channel *)chp; 1656 struct ahci_cmd_tbl *cmd_tbl; 1657 struct ahci_cmd_header *cmd_h; 1658 1659 cmd_h = &achp->ahcic_cmdh[slot]; 1660 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1661 1662 if (data == NULL) { 1663 cmd_h->cmdh_prdtl = 0; 1664 goto end; 1665 } 1666 1667 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1668 data, count, NULL, 1669 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1670 if (error) { 1671 printf("%s port %d: failed to load xfer: %d\n", 1672 AHCINAME(sc), chp->ch_channel, error); 1673 return error; 1674 } 1675 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1676 achp->ahcic_datad[slot]->dm_mapsize, 1677 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1678 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1679 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1680 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1681 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1682 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1683 } 1684 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1685 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1686 end: 1687 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1688 return 0; 1689 } 1690 1691 #if NATAPIBUS > 0 1692 static void 1693 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1694 { 1695 struct ata_channel *chp = ata_sc->sc_chan; 1696 struct atac_softc *atac = chp->ch_atac; 1697 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1698 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1699 /* 1700 * Fill in the scsipi_adapter. 1701 */ 1702 adapt->adapt_dev = atac->atac_dev; 1703 adapt->adapt_nchannels = atac->atac_nchannels; 1704 adapt->adapt_request = ahci_atapi_scsipi_request; 1705 adapt->adapt_minphys = ahci_atapi_minphys; 1706 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1707 1708 /* 1709 * Fill in the scsipi_channel. 1710 */ 1711 memset(chan, 0, sizeof(*chan)); 1712 chan->chan_adapter = adapt; 1713 chan->chan_bustype = &ahci_atapi_bustype; 1714 chan->chan_channel = chp->ch_channel; 1715 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1716 chan->chan_openings = 1; 1717 chan->chan_max_periph = 1; 1718 chan->chan_ntargets = 1; 1719 chan->chan_nluns = 1; 1720 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1721 atapiprint); 1722 } 1723 1724 static void 1725 ahci_atapi_minphys(struct buf *bp) 1726 { 1727 if (bp->b_bcount > MAXPHYS) 1728 bp->b_bcount = MAXPHYS; 1729 minphys(bp); 1730 } 1731 1732 /* 1733 * Kill off all pending xfers for a periph. 1734 * 1735 * Must be called at splbio(). 1736 */ 1737 static void 1738 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1739 { 1740 struct atac_softc *atac = 1741 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1742 struct ata_channel *chp = 1743 atac->atac_channels[periph->periph_channel->chan_channel]; 1744 1745 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1746 } 1747 1748 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1749 .c_start = ahci_atapi_start, 1750 .c_poll = ahci_atapi_poll, 1751 .c_abort = ahci_atapi_abort, 1752 .c_intr = ahci_atapi_complete, 1753 .c_kill_xfer = ahci_atapi_kill_xfer, 1754 }; 1755 1756 static void 1757 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1758 scsipi_adapter_req_t req, void *arg) 1759 { 1760 struct scsipi_adapter *adapt = chan->chan_adapter; 1761 struct scsipi_periph *periph; 1762 struct scsipi_xfer *sc_xfer; 1763 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1764 struct atac_softc *atac = &sc->sc_atac; 1765 struct ata_xfer *xfer; 1766 int channel = chan->chan_channel; 1767 int drive, s; 1768 1769 switch (req) { 1770 case ADAPTER_REQ_RUN_XFER: 1771 sc_xfer = arg; 1772 periph = sc_xfer->xs_periph; 1773 drive = periph->periph_target; 1774 if (!device_is_active(atac->atac_dev)) { 1775 sc_xfer->error = XS_DRIVER_STUFFUP; 1776 scsipi_done(sc_xfer); 1777 return; 1778 } 1779 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1780 if (xfer == NULL) { 1781 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1782 scsipi_done(sc_xfer); 1783 return; 1784 } 1785 1786 if (sc_xfer->xs_control & XS_CTL_POLL) 1787 xfer->c_flags |= C_POLL; 1788 xfer->c_drive = drive; 1789 xfer->c_flags |= C_ATAPI; 1790 xfer->c_databuf = sc_xfer->data; 1791 xfer->c_bcount = sc_xfer->datalen; 1792 xfer->ops = &ahci_atapi_xfer_ops; 1793 xfer->c_scsipi = sc_xfer; 1794 xfer->c_atapi.c_dscpoll = 0; 1795 s = splbio(); 1796 ata_exec_xfer(atac->atac_channels[channel], xfer); 1797 #ifdef DIAGNOSTIC 1798 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1799 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1800 panic("ahci_atapi_scsipi_request: polled command " 1801 "not done"); 1802 #endif 1803 splx(s); 1804 return; 1805 default: 1806 /* Not supported, nothing to do. */ 1807 ; 1808 } 1809 } 1810 1811 static int 1812 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1813 { 1814 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1815 struct ahci_channel *achp = (struct ahci_channel *)chp; 1816 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1817 struct ahci_cmd_tbl *cmd_tbl; 1818 struct ahci_cmd_header *cmd_h; 1819 1820 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1821 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1822 1823 ata_channel_lock_owned(chp); 1824 1825 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1826 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1827 cmd_tbl), DEBUG_XFERS); 1828 1829 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1830 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1831 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1832 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1833 1834 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1835 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1836 chp->ch_channel, cmd_h), DEBUG_XFERS); 1837 if (ahci_dma_setup(chp, xfer->c_slot, 1838 sc_xfer->datalen ? sc_xfer->data : NULL, 1839 sc_xfer->datalen, 1840 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1841 BUS_DMA_READ : BUS_DMA_WRITE)) { 1842 sc_xfer->error = XS_DRIVER_STUFFUP; 1843 return ATASTART_ABORT; 1844 } 1845 cmd_h->cmdh_flags = htole16( 1846 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1847 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1848 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1849 cmd_h->cmdh_prdbc = 0; 1850 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1851 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1852 1853 if (xfer->c_flags & C_POLL) { 1854 /* polled command, disable interrupts */ 1855 AHCI_WRITE(sc, AHCI_GHC, 1856 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1857 } 1858 /* start command */ 1859 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1860 1861 if ((xfer->c_flags & C_POLL) == 0) { 1862 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1863 ata_timeout, chp); 1864 return ATASTART_STARTED; 1865 } else 1866 return ATASTART_POLL; 1867 } 1868 1869 static void 1870 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1871 { 1872 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1873 struct ahci_channel *achp = (struct ahci_channel *)chp; 1874 1875 /* 1876 * Polled command. 1877 */ 1878 for (int i = 0; i < ATA_DELAY / 10; i++) { 1879 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1880 break; 1881 ahci_intr_port(sc, achp); 1882 delay(10000); 1883 } 1884 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1885 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1886 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1887 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1888 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1889 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1890 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1891 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1892 DEBUG_XFERS); 1893 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1894 xfer->c_scsipi->error = XS_TIMEOUT; 1895 xfer->ops->c_intr(chp, xfer, 0); 1896 } 1897 /* reenable interrupts */ 1898 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1899 } 1900 1901 static void 1902 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1903 { 1904 ahci_atapi_complete(chp, xfer, 0); 1905 } 1906 1907 static int 1908 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1909 { 1910 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1911 struct ahci_channel *achp = (struct ahci_channel *)chp; 1912 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1913 1914 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1915 DEBUG_FUNCS); 1916 1917 if (ata_waitdrain_xfer_check(chp, xfer)) 1918 return 0; 1919 1920 if (xfer->c_flags & C_TIMEOU) { 1921 sc_xfer->error = XS_TIMEOUT; 1922 } 1923 1924 if (xfer->c_bcount > 0) { 1925 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1926 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1927 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1928 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1929 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1930 } 1931 1932 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1934 sc_xfer->resid = sc_xfer->datalen; 1935 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1936 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1937 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1938 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1939 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1940 sc_xfer->resid == sc_xfer->datalen)) { 1941 sc_xfer->error = XS_SHORTSENSE; 1942 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 1943 if ((sc_xfer->xs_periph->periph_quirks & 1944 PQUIRK_NOSENSE) == 0) { 1945 /* ask scsipi to send a REQUEST_SENSE */ 1946 sc_xfer->error = XS_BUSY; 1947 sc_xfer->status = SCSI_CHECK; 1948 } 1949 } 1950 1951 ata_deactivate_xfer(chp, xfer); 1952 1953 ata_free_xfer(chp, xfer); 1954 scsipi_done(sc_xfer); 1955 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1956 atastart(chp); 1957 return 0; 1958 } 1959 1960 static void 1961 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1962 { 1963 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1964 bool deactivate = true; 1965 1966 /* remove this command from xfer queue */ 1967 switch (reason) { 1968 case KILL_GONE_INACTIVE: 1969 deactivate = false; 1970 /* FALLTHROUGH */ 1971 case KILL_GONE: 1972 sc_xfer->error = XS_DRIVER_STUFFUP; 1973 break; 1974 case KILL_RESET: 1975 sc_xfer->error = XS_RESET; 1976 break; 1977 case KILL_REQUEUE: 1978 sc_xfer->error = XS_REQUEUE; 1979 break; 1980 default: 1981 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1982 panic("ahci_ata_atapi_kill_xfer"); 1983 } 1984 1985 if (deactivate) 1986 ata_deactivate_xfer(chp, xfer); 1987 1988 ata_free_xfer(chp, xfer); 1989 scsipi_done(sc_xfer); 1990 } 1991 1992 static void 1993 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1994 { 1995 struct scsipi_channel *chan = sc->sc_channel; 1996 struct scsipi_periph *periph; 1997 struct ataparams ids; 1998 struct ataparams *id = &ids; 1999 struct ahci_softc *ahcic = 2000 device_private(chan->chan_adapter->adapt_dev); 2001 struct atac_softc *atac = &ahcic->sc_atac; 2002 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2003 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2004 struct scsipibus_attach_args sa; 2005 char serial_number[21], model[41], firmware_revision[9]; 2006 int s; 2007 2008 /* skip if already attached */ 2009 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2010 return; 2011 2012 /* if no ATAPI device detected at attach time, skip */ 2013 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2014 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2015 "not present\n", target), DEBUG_PROBE); 2016 return; 2017 } 2018 2019 /* Some ATAPI devices need a bit more time after software reset. */ 2020 delay(5000); 2021 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2022 #ifdef ATAPI_DEBUG_PROBE 2023 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2024 AHCINAME(ahcic), target, 2025 id->atap_config & ATAPI_CFG_CMD_MASK, 2026 id->atap_config & ATAPI_CFG_DRQ_MASK); 2027 #endif 2028 periph = scsipi_alloc_periph(M_NOWAIT); 2029 if (periph == NULL) { 2030 aprint_error_dev(sc->sc_dev, 2031 "unable to allocate periph for drive %d\n", 2032 target); 2033 return; 2034 } 2035 periph->periph_dev = NULL; 2036 periph->periph_channel = chan; 2037 periph->periph_switch = &atapi_probe_periphsw; 2038 periph->periph_target = target; 2039 periph->periph_lun = 0; 2040 periph->periph_quirks = PQUIRK_ONLYBIG; 2041 2042 #ifdef SCSIPI_DEBUG 2043 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2044 SCSIPI_DEBUG_TARGET == target) 2045 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2046 #endif 2047 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2048 if (id->atap_config & ATAPI_CFG_REMOV) 2049 periph->periph_flags |= PERIPH_REMOVABLE; 2050 if (periph->periph_type == T_SEQUENTIAL) { 2051 s = splbio(); 2052 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2053 splx(s); 2054 } 2055 2056 sa.sa_periph = periph; 2057 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2058 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2059 T_REMOV : T_FIXED; 2060 strnvisx(model, sizeof(model), id->atap_model, 40, 2061 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2062 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2063 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2064 strnvisx(firmware_revision, sizeof(firmware_revision), 2065 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2066 sa.sa_inqbuf.vendor = model; 2067 sa.sa_inqbuf.product = serial_number; 2068 sa.sa_inqbuf.revision = firmware_revision; 2069 2070 /* 2071 * Determine the operating mode capabilities of the device. 2072 */ 2073 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2074 periph->periph_cap |= PERIPH_CAP_CMD16; 2075 /* XXX This is gross. */ 2076 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2077 2078 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2079 2080 if (drvp->drv_softc) 2081 ata_probe_caps(drvp); 2082 else { 2083 s = splbio(); 2084 drvp->drive_type = ATA_DRIVET_NONE; 2085 splx(s); 2086 } 2087 } else { 2088 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2089 "failed for drive %s:%d:%d\n", 2090 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2091 s = splbio(); 2092 drvp->drive_type = ATA_DRIVET_NONE; 2093 splx(s); 2094 } 2095 } 2096 #endif /* NATAPIBUS */ 2097
Indexes created Fri Oct 17 00:09:41 GMT 2025