ahcisata_core.c revision 1.63
1 /* $NetBSD: ahcisata_core.c,v 1.63 2018/09/18 21:28:22 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.63 2018/09/18 21:28:22 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 struct ata_xfer *xfer); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 void ahci_channel_recover(struct ahci_softc *, struct ata_channel *, int); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending 125 }; 126 127 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 return 0; 170 } 171 172 static void 173 ahci_setup_ports(struct ahci_softc *sc) 174 { 175 int i, port; 176 177 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 178 if ((sc->sc_ahci_ports & (1U << i)) == 0) 179 continue; 180 if (port >= sc->sc_atac.atac_nchannels) { 181 aprint_error("%s: more ports than announced\n", 182 AHCINAME(sc)); 183 break; 184 } 185 ahci_setup_port(sc, i); 186 } 187 } 188 189 static void 190 ahci_reprobe_drives(struct ahci_softc *sc) 191 { 192 int i, port; 193 struct ahci_channel *achp; 194 struct ata_channel *chp; 195 196 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 197 if ((sc->sc_ahci_ports & (1U << i)) == 0) 198 continue; 199 if (port >= sc->sc_atac.atac_nchannels) { 200 aprint_error("%s: more ports than announced\n", 201 AHCINAME(sc)); 202 break; 203 } 204 achp = &sc->sc_channels[i]; 205 chp = &achp->ata_channel; 206 207 ahci_probe_drive(chp); 208 } 209 } 210 211 static void 212 ahci_setup_port(struct ahci_softc *sc, int i) 213 { 214 struct ahci_channel *achp; 215 216 achp = &sc->sc_channels[i]; 217 218 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 219 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 220 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 221 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 222 } 223 224 static void 225 ahci_enable_intrs(struct ahci_softc *sc) 226 { 227 228 /* clear interrupts */ 229 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 230 /* enable interrupts */ 231 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 232 } 233 234 void 235 ahci_attach(struct ahci_softc *sc) 236 { 237 uint32_t ahci_rev; 238 int i, j, port; 239 struct ahci_channel *achp; 240 struct ata_channel *chp; 241 int error; 242 int dmasize; 243 char buf[128]; 244 void *cmdhp; 245 void *cmdtblp; 246 247 if (sc->sc_save_init_data) { 248 ahci_enable(sc); 249 250 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 251 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 252 253 ahci_rev = AHCI_READ(sc, AHCI_VS); 254 if (AHCI_VS_MJR(ahci_rev) > 1 || 255 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 256 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 257 } else { 258 sc->sc_init_data.cap2 = 0; 259 } 260 if (sc->sc_init_data.ports == 0) { 261 sc->sc_init_data.ports = sc->sc_ahci_ports; 262 } 263 } 264 265 if (ahci_reset(sc) != 0) 266 return; 267 268 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 269 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 270 aprint_verbose_dev(sc->sc_atac.atac_dev, 271 "ignoring broken port multiplier support\n"); 272 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 273 } 274 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 275 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 276 ahci_rev = AHCI_READ(sc, AHCI_VS); 277 snprintb(buf, sizeof(buf), "\177\020" 278 /* "f\000\005NP\0" */ 279 "b\005SXS\0" 280 "b\006EMS\0" 281 "b\007CCCS\0" 282 /* "f\010\005NCS\0" */ 283 "b\015PSC\0" 284 "b\016SSC\0" 285 "b\017PMD\0" 286 "b\020FBSS\0" 287 "b\021SPM\0" 288 "b\022SAM\0" 289 "b\023SNZO\0" 290 "f\024\003ISS\0" 291 "=\001Gen1\0" 292 "=\002Gen2\0" 293 "=\003Gen3\0" 294 "b\030SCLO\0" 295 "b\031SAL\0" 296 "b\032SALP\0" 297 "b\033SSS\0" 298 "b\034SMPS\0" 299 "b\035SSNTF\0" 300 "b\036SNCQ\0" 301 "b\037S64A\0" 302 "\0", sc->sc_ahci_cap); 303 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 304 ", %d port%s, %d slot%s, CAP %s\n", 305 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 306 sc->sc_atac.atac_nchannels, 307 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 308 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 309 310 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 311 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 312 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 313 sc->sc_atac.atac_pio_cap = 4; 314 sc->sc_atac.atac_dma_cap = 2; 315 sc->sc_atac.atac_udma_cap = 6; 316 sc->sc_atac.atac_channels = sc->sc_chanarray; 317 sc->sc_atac.atac_probe = ahci_probe_drive; 318 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 319 sc->sc_atac.atac_set_modes = ahci_setup_channel; 320 #if NATAPIBUS > 0 321 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 322 #endif 323 324 dmasize = 325 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 326 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 327 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 328 if (error) { 329 aprint_error("%s: unable to allocate command header memory" 330 ", error=%d\n", AHCINAME(sc), error); 331 return; 332 } 333 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 334 sc->sc_cmd_hdr_nseg, dmasize, 335 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 336 if (error) { 337 aprint_error("%s: unable to map command header memory" 338 ", error=%d\n", AHCINAME(sc), error); 339 return; 340 } 341 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 342 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 343 if (error) { 344 aprint_error("%s: unable to create command header map" 345 ", error=%d\n", AHCINAME(sc), error); 346 return; 347 } 348 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 349 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 350 if (error) { 351 aprint_error("%s: unable to load command header map" 352 ", error=%d\n", AHCINAME(sc), error); 353 return; 354 } 355 sc->sc_cmd_hdr = cmdhp; 356 357 ahci_enable_intrs(sc); 358 359 if (sc->sc_ahci_ports == 0) { 360 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 361 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 362 DEBUG_PROBE); 363 } 364 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 365 if ((sc->sc_ahci_ports & (1U << i)) == 0) 366 continue; 367 if (port >= sc->sc_atac.atac_nchannels) { 368 aprint_error("%s: more ports than announced\n", 369 AHCINAME(sc)); 370 break; 371 } 372 achp = &sc->sc_channels[i]; 373 chp = &achp->ata_channel; 374 sc->sc_chanarray[i] = chp; 375 chp->ch_channel = i; 376 chp->ch_atac = &sc->sc_atac; 377 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 378 if (chp->ch_queue == NULL) { 379 aprint_error("%s port %d: can't allocate memory for " 380 "command queue", AHCINAME(sc), i); 381 break; 382 } 383 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 384 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 385 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 386 BUS_DMA_NOWAIT); 387 if (error) { 388 aprint_error("%s: unable to allocate command table " 389 "memory, error=%d\n", AHCINAME(sc), error); 390 break; 391 } 392 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 393 achp->ahcic_cmd_tbl_nseg, dmasize, 394 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 395 if (error) { 396 aprint_error("%s: unable to map command table memory" 397 ", error=%d\n", AHCINAME(sc), error); 398 break; 399 } 400 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 401 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 402 if (error) { 403 aprint_error("%s: unable to create command table map" 404 ", error=%d\n", AHCINAME(sc), error); 405 break; 406 } 407 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 408 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 409 if (error) { 410 aprint_error("%s: unable to load command table map" 411 ", error=%d\n", AHCINAME(sc), error); 412 break; 413 } 414 achp->ahcic_cmdh = (struct ahci_cmd_header *) 415 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 416 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 417 AHCI_CMDH_SIZE * port; 418 achp->ahcic_rfis = (struct ahci_r_fis *) 419 ((char *)cmdhp + 420 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 421 AHCI_RFIS_SIZE * port); 422 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port; 425 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 426 "rfis %p (0x%" PRIx64 ")\n", i, 427 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 428 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 429 DEBUG_PROBE); 430 431 for (j = 0; j < sc->sc_ncmds; j++) { 432 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 433 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 434 achp->ahcic_bus_cmd_tbl[j] = 435 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 436 AHCI_CMDTBL_SIZE * j; 437 achp->ahcic_cmdh[j].cmdh_cmdtba = 438 htole64(achp->ahcic_bus_cmd_tbl[j]); 439 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 440 achp->ahcic_cmd_tbl[j], 441 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 442 /* The xfer DMA map */ 443 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 444 AHCI_NPRD, 0x400000 /* 4MB */, 0, 445 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 446 &achp->ahcic_datad[j]); 447 if (error) { 448 aprint_error("%s: couldn't alloc xfer DMA map, " 449 "error=%d\n", AHCINAME(sc), error); 450 goto end; 451 } 452 } 453 ahci_setup_port(sc, i); 454 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 455 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 456 aprint_error("%s: couldn't map channel %d " 457 "sata_status regs\n", AHCINAME(sc), i); 458 break; 459 } 460 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 461 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 462 aprint_error("%s: couldn't map channel %d " 463 "sata_control regs\n", AHCINAME(sc), i); 464 break; 465 } 466 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 467 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 468 aprint_error("%s: couldn't map channel %d " 469 "sata_error regs\n", AHCINAME(sc), i); 470 break; 471 } 472 ata_channel_attach(chp); 473 port++; 474 end: 475 continue; 476 } 477 } 478 479 int 480 ahci_detach(struct ahci_softc *sc, int flags) 481 { 482 struct atac_softc *atac; 483 struct ahci_channel *achp; 484 struct ata_channel *chp; 485 struct scsipi_adapter *adapt; 486 int i, j; 487 int error; 488 489 atac = &sc->sc_atac; 490 adapt = &atac->atac_atapi_adapter._generic; 491 492 for (i = 0; i < AHCI_MAX_PORTS; i++) { 493 achp = &sc->sc_channels[i]; 494 chp = &achp->ata_channel; 495 496 if ((sc->sc_ahci_ports & (1U << i)) == 0) 497 continue; 498 if (i >= sc->sc_atac.atac_nchannels) { 499 aprint_error("%s: more ports than announced\n", 500 AHCINAME(sc)); 501 break; 502 } 503 504 if (chp->atabus == NULL) 505 continue; 506 if ((error = config_detach(chp->atabus, flags)) != 0) 507 return error; 508 509 for (j = 0; j < sc->sc_ncmds; j++) 510 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 511 512 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 513 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 514 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 515 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 516 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 517 achp->ahcic_cmd_tbl_nseg); 518 519 chp->atabus = NULL; 520 521 ata_channel_detach(chp); 522 } 523 524 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 525 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 526 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 527 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 528 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 529 530 if (adapt->adapt_refcnt != 0) 531 return EBUSY; 532 533 return 0; 534 } 535 536 void 537 ahci_resume(struct ahci_softc *sc) 538 { 539 ahci_reset(sc); 540 ahci_setup_ports(sc); 541 ahci_reprobe_drives(sc); 542 ahci_enable_intrs(sc); 543 } 544 545 int 546 ahci_intr(void *v) 547 { 548 struct ahci_softc *sc = v; 549 uint32_t is; 550 int i, r = 0; 551 552 while ((is = AHCI_READ(sc, AHCI_IS))) { 553 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 554 DEBUG_INTR); 555 r = 1; 556 AHCI_WRITE(sc, AHCI_IS, is); 557 for (i = 0; i < AHCI_MAX_PORTS; i++) 558 if (is & (1U << i)) 559 ahci_intr_port(sc, &sc->sc_channels[i]); 560 } 561 return r; 562 } 563 564 static void 565 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 566 { 567 uint32_t is, tfd, sact; 568 struct ata_channel *chp = &achp->ata_channel; 569 struct ata_xfer *xfer; 570 int slot = -1; 571 bool recover = false; 572 573 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 574 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 575 576 AHCIDEBUG_PRINT(( 577 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 578 AHCINAME(sc), 579 chp->ch_channel, is, 580 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 581 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 582 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 583 DEBUG_INTR); 584 585 if ((chp->ch_flags & ATACH_NCQ) == 0) { 586 /* Non-NCQ operation */ 587 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 588 } else { 589 /* NCQ operation */ 590 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 591 } 592 593 /* Handle errors */ 594 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 595 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 596 /* Fatal errors */ 597 if (is & AHCI_P_IX_TFES) { 598 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 599 600 if ((chp->ch_flags & ATACH_NCQ) == 0) { 601 /* Slot valid only for Non-NCQ operation */ 602 slot = (AHCI_READ(sc, 603 AHCI_P_CMD(chp->ch_channel)) 604 & AHCI_P_CMD_CCS_MASK) 605 >> AHCI_P_CMD_CCS_SHIFT; 606 } 607 608 AHCIDEBUG_PRINT(( 609 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 610 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 611 DEBUG_INTR); 612 } else { 613 /* mark an error, and set BSY */ 614 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 615 WDCS_ERR | WDCS_BSY; 616 } 617 618 if (is & AHCI_P_IX_IFS) { 619 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 620 AHCINAME(sc), chp->ch_channel, 621 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 622 DEBUG_INTR); 623 } 624 625 if (!achp->ahcic_recovering) 626 recover = true; 627 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 628 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 629 630 /* D2H Register FIS or Set Device Bits */ 631 if ((tfd & WDCS_ERR) != 0) { 632 if (!achp->ahcic_recovering) 633 recover = true; 634 635 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 636 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 637 638 } 639 } else { 640 tfd = 0; 641 } 642 643 if (__predict_false(recover)) 644 ata_channel_freeze(chp); 645 646 if (slot >= 0) { 647 if ((achp->ahcic_cmds_active & __BIT(slot)) != 0 && 648 (sact & __BIT(slot)) == 0) { 649 xfer = ata_queue_hwslot_to_xfer(chp, slot); 650 xfer->c_intr(chp, xfer, tfd); 651 } 652 } else { 653 /* 654 * For NCQ, HBA halts processing when error is notified, 655 * and any further D2H FISes are ignored until the error 656 * condition is cleared. Hence if a command is inactive, 657 * it means it actually already finished successfully. 658 * Note: active slots can change as c_intr() callback 659 * can activate another command(s), so must only process 660 * commands active before we start processing. 661 */ 662 uint32_t aslots = achp->ahcic_cmds_active; 663 664 for (slot=0; slot < sc->sc_ncmds; slot++) { 665 if ((aslots & __BIT(slot)) != 0 && 666 (sact & __BIT(slot)) == 0) { 667 xfer = ata_queue_hwslot_to_xfer(chp, slot); 668 xfer->c_intr(chp, xfer, tfd); 669 } 670 } 671 } 672 673 if (__predict_false(recover)) { 674 ata_channel_thaw(chp); 675 ahci_channel_recover(sc, chp, tfd); 676 } 677 } 678 679 static void 680 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 681 { 682 struct ata_channel *chp = drvp->chnl_softc; 683 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 684 struct ata_xfer *xfer; 685 686 xfer = ata_get_xfer_ext(chp, C_RECOVERY, 0); 687 688 ata_channel_lock(chp); 689 690 AHCI_WRITE(sc, AHCI_GHC, 691 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 692 ahci_channel_stop(sc, chp, flags); 693 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp, xfer) != 0) 694 ata_reset_channel(chp, flags); 695 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 696 697 ata_channel_unlock(chp); 698 699 ata_free_xfer(chp, xfer); 700 701 return; 702 } 703 704 /* return error code from ata_bio */ 705 static int 706 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 707 { 708 struct ahci_channel *achp = (struct ahci_channel *)chp; 709 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 710 int i; 711 uint32_t is; 712 713 /* 714 * Base timeout is specified in ms. 715 * If we are allowed to sleep, wait a tick each round. 716 * Otherwise delay for 10ms on each round. 717 */ 718 if (flags & AT_WAIT) 719 timeout = MAX(1, mstohz(timeout)); 720 else 721 timeout = timeout / 10; 722 723 AHCI_CMDH_SYNC(sc, achp, slot, 724 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 725 /* start command */ 726 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 727 for (i = 0; i < timeout; i++) { 728 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 729 0) 730 return 0; 731 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 732 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 733 AHCI_P_IX_IFS | 734 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 735 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 736 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 737 /* 738 * we got the D2H FIS anyway, 739 * assume sig is valid. 740 * channel is restarted later 741 */ 742 return ERROR; 743 } 744 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 745 AHCINAME(sc), chp->ch_channel, is); 746 return ERR_DF; 747 } 748 ata_delay(chp, 10, "ahcifis", flags); 749 } 750 751 aprint_debug("%s channel %d: timeout sending FIS\n", 752 AHCINAME(sc), chp->ch_channel); 753 return TIMEOUT; 754 } 755 756 static int 757 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 758 uint32_t *sigp, struct ata_xfer *xfer) 759 { 760 struct ahci_channel *achp = (struct ahci_channel *)chp; 761 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 762 struct ahci_cmd_tbl *cmd_tbl; 763 struct ahci_cmd_header *cmd_h; 764 int i; 765 uint32_t sig; 766 767 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 768 ata_channel_lock_owned(chp); 769 770 again: 771 /* clear port interrupt register */ 772 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 773 /* clear SErrors and start operations */ 774 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 775 /* 776 * issue a command list override to clear BSY. 777 * This is needed if there's a PMP with no drive 778 * on port 0 779 */ 780 ahci_channel_start(sc, chp, flags, 1); 781 } else { 782 ahci_channel_start(sc, chp, flags, 0); 783 } 784 if (drive > 0) { 785 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 786 } 787 788 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 789 goto skip_reset; 790 791 /* polled command, assume interrupts are disabled */ 792 793 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 794 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 795 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 796 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 797 cmd_h->cmdh_prdbc = 0; 798 memset(cmd_tbl->cmdt_cfis, 0, 64); 799 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 800 cmd_tbl->cmdt_cfis[rhd_c] = drive; 801 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 802 switch(ahci_exec_fis(chp, 100, flags, xfer->c_slot)) { 803 case ERR_DF: 804 case TIMEOUT: 805 aprint_error("%s channel %d: setting WDCTL_RST failed " 806 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 807 if (sigp) 808 *sigp = 0xffffffff; 809 goto end; 810 default: 811 break; 812 } 813 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 814 (drive << AHCI_CMDH_F_PMP_SHIFT)); 815 cmd_h->cmdh_prdbc = 0; 816 memset(cmd_tbl->cmdt_cfis, 0, 64); 817 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 818 cmd_tbl->cmdt_cfis[rhd_c] = drive; 819 cmd_tbl->cmdt_cfis[rhd_control] = 0; 820 switch(ahci_exec_fis(chp, 310, flags, xfer->c_slot)) { 821 case ERR_DF: 822 case TIMEOUT: 823 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 824 drive == PMP_PORT_CTL) { 825 /* 826 * some controllers fails to reset when 827 * targeting a PMP but a single drive is attached. 828 * try again with port 0 829 */ 830 drive = 0; 831 ahci_channel_stop(sc, chp, flags); 832 goto again; 833 } 834 aprint_error("%s channel %d: clearing WDCTL_RST failed " 835 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 836 if (sigp) 837 *sigp = 0xffffffff; 838 goto end; 839 default: 840 break; 841 } 842 843 skip_reset: 844 /* 845 * wait 31s for BSY to clear 846 * This should not be needed, but some controllers clear the 847 * command slot before receiving the D2H FIS ... 848 */ 849 for (i = 0; i < AHCI_RST_WAIT; i++) { 850 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 851 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 852 break; 853 ata_delay(chp, 10, "ahcid2h", flags); 854 } 855 if (i == AHCI_RST_WAIT) { 856 aprint_error("%s: BSY never cleared, TD 0x%x\n", 857 AHCINAME(sc), sig); 858 if (sigp) 859 *sigp = 0xffffffff; 860 goto end; 861 } 862 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 863 DEBUG_PROBE); 864 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 865 if (sigp) 866 *sigp = sig; 867 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 868 AHCINAME(sc), chp->ch_channel, sig, 869 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 870 end: 871 ahci_channel_stop(sc, chp, flags); 872 ata_delay(chp, 500, "ahcirst", flags); 873 /* clear port interrupt register */ 874 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 875 ahci_channel_start(sc, chp, flags, 876 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 877 return 0; 878 } 879 880 static void 881 ahci_reset_channel(struct ata_channel *chp, int flags) 882 { 883 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 884 struct ahci_channel *achp = (struct ahci_channel *)chp; 885 int i, tfd; 886 887 ata_channel_lock(chp); 888 889 ahci_channel_stop(sc, chp, flags); 890 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 891 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 892 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 893 /* XXX and then ? */ 894 } 895 ata_kill_active(chp, KILL_RESET, flags); 896 ata_delay(chp, 500, "ahcirst", flags); 897 /* clear port interrupt register */ 898 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 899 /* clear SErrors and start operations */ 900 ahci_channel_start(sc, chp, flags, 901 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 902 /* wait 31s for BSY to clear */ 903 for (i = 0; i <AHCI_RST_WAIT; i++) { 904 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 905 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 906 break; 907 ata_delay(chp, 10, "ahcid2h", flags); 908 } 909 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 910 aprint_error("%s: BSY never cleared, TD 0x%x\n", 911 AHCINAME(sc), tfd); 912 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 913 DEBUG_PROBE); 914 /* clear port interrupt register */ 915 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 916 917 ata_channel_unlock(chp); 918 919 return; 920 } 921 922 static int 923 ahci_ata_addref(struct ata_drive_datas *drvp) 924 { 925 return 0; 926 } 927 928 static void 929 ahci_ata_delref(struct ata_drive_datas *drvp) 930 { 931 return; 932 } 933 934 static void 935 ahci_killpending(struct ata_drive_datas *drvp) 936 { 937 return; 938 } 939 940 static void 941 ahci_probe_drive(struct ata_channel *chp) 942 { 943 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 944 struct ahci_channel *achp = (struct ahci_channel *)chp; 945 uint32_t sig; 946 struct ata_xfer *xfer; 947 948 xfer = ata_get_xfer_ext(chp, 0, 0); 949 if (xfer == NULL) { 950 aprint_error_dev(sc->sc_atac.atac_dev, 951 "%s: failed to get xfer port %d\n", 952 __func__, chp->ch_channel); 953 return; 954 } 955 956 ata_channel_lock(chp); 957 958 /* bring interface up, accept FISs, power up and spin up device */ 959 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 960 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 961 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 962 /* reset the PHY and bring online */ 963 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 964 achp->ahcic_sstatus, AT_WAIT)) { 965 case SStatus_DET_DEV: 966 ata_delay(chp, 500, "ahcidv", AT_WAIT); 967 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 968 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig, 969 xfer); 970 } else { 971 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, xfer); 972 } 973 sata_interpret_sig(chp, 0, sig); 974 /* if we have a PMP attached, inform the controller */ 975 if (chp->ch_ndrives > PMP_PORT_CTL && 976 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 977 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 978 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 979 AHCI_P_CMD_PMA); 980 } 981 /* clear port interrupt register */ 982 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 983 984 /* and enable interrupts */ 985 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 986 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 987 AHCI_P_IX_IFS | 988 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 989 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 990 /* wait 500ms before actually starting operations */ 991 ata_delay(chp, 500, "ahciprb", AT_WAIT); 992 break; 993 994 default: 995 break; 996 } 997 ata_channel_unlock(chp); 998 999 ata_free_xfer(chp, xfer); 1000 } 1001 1002 static void 1003 ahci_setup_channel(struct ata_channel *chp) 1004 { 1005 return; 1006 } 1007 1008 static int 1009 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1010 { 1011 struct ata_channel *chp = drvp->chnl_softc; 1012 struct ata_command *ata_c = &xfer->c_ata_c; 1013 int ret; 1014 int s; 1015 1016 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1017 chp->ch_channel, 1018 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1019 DEBUG_XFERS); 1020 if (ata_c->flags & AT_POLL) 1021 xfer->c_flags |= C_POLL; 1022 if (ata_c->flags & AT_WAIT) 1023 xfer->c_flags |= C_WAIT; 1024 xfer->c_drive = drvp->drive; 1025 xfer->c_databuf = ata_c->data; 1026 xfer->c_bcount = ata_c->bcount; 1027 xfer->c_start = ahci_cmd_start; 1028 xfer->c_poll = ahci_cmd_poll; 1029 xfer->c_abort = ahci_cmd_abort; 1030 xfer->c_intr = ahci_cmd_complete; 1031 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 1032 s = splbio(); 1033 ata_exec_xfer(chp, xfer); 1034 #ifdef DIAGNOSTIC 1035 if ((ata_c->flags & AT_POLL) != 0 && 1036 (ata_c->flags & AT_DONE) == 0) 1037 panic("ahci_exec_command: polled command not done"); 1038 #endif 1039 if (ata_c->flags & AT_DONE) { 1040 ret = ATACMD_COMPLETE; 1041 } else { 1042 if (ata_c->flags & AT_WAIT) { 1043 ata_channel_lock(chp); 1044 if ((ata_c->flags & AT_DONE) == 0) { 1045 ata_wait_xfer(chp, xfer); 1046 KASSERT((ata_c->flags & AT_DONE) != 0); 1047 } 1048 ata_channel_unlock(chp); 1049 ret = ATACMD_COMPLETE; 1050 } else { 1051 ret = ATACMD_QUEUED; 1052 } 1053 } 1054 splx(s); 1055 return ret; 1056 } 1057 1058 static int 1059 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1060 { 1061 struct ahci_softc *sc = AHCI_CH2SC(chp); 1062 struct ahci_channel *achp = (struct ahci_channel *)chp; 1063 struct ata_command *ata_c = &xfer->c_ata_c; 1064 int slot = xfer->c_slot; 1065 struct ahci_cmd_tbl *cmd_tbl; 1066 struct ahci_cmd_header *cmd_h; 1067 1068 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1069 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1070 ata_c->timeout, slot), 1071 DEBUG_XFERS); 1072 1073 ata_channel_lock_owned(chp); 1074 KASSERT((achp->ahcic_cmds_active & (1U << slot)) == 0); 1075 1076 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1077 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1078 cmd_tbl), DEBUG_XFERS); 1079 1080 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1081 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1082 1083 cmd_h = &achp->ahcic_cmdh[slot]; 1084 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1085 chp->ch_channel, cmd_h), DEBUG_XFERS); 1086 if (ahci_dma_setup(chp, slot, 1087 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1088 ata_c->data : NULL, 1089 ata_c->bcount, 1090 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1091 ata_c->flags |= AT_DF; 1092 return ATASTART_ABORT; 1093 } 1094 cmd_h->cmdh_flags = htole16( 1095 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1096 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1097 cmd_h->cmdh_prdbc = 0; 1098 AHCI_CMDH_SYNC(sc, achp, slot, 1099 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1100 1101 if (ata_c->flags & AT_POLL) { 1102 /* polled command, disable interrupts */ 1103 AHCI_WRITE(sc, AHCI_GHC, 1104 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1105 } 1106 /* start command */ 1107 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1108 /* and says we started this command */ 1109 achp->ahcic_cmds_active |= 1U << slot; 1110 1111 if ((ata_c->flags & AT_POLL) == 0) { 1112 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 1113 ata_timeout, xfer); 1114 return ATASTART_STARTED; 1115 } else 1116 return ATASTART_POLL; 1117 } 1118 1119 static void 1120 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1121 { 1122 struct ahci_softc *sc = AHCI_CH2SC(chp); 1123 struct ahci_channel *achp = (struct ahci_channel *)chp; 1124 1125 ata_channel_lock(chp); 1126 1127 /* 1128 * Polled command. 1129 */ 1130 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1131 if (xfer->c_ata_c.flags & AT_DONE) 1132 break; 1133 ata_channel_unlock(chp); 1134 ahci_intr_port(sc, achp); 1135 ata_channel_lock(chp); 1136 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1137 } 1138 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1139 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1140 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1141 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1142 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1143 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1144 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1145 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1146 DEBUG_XFERS); 1147 1148 ata_channel_unlock(chp); 1149 1150 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1151 xfer->c_ata_c.flags |= AT_TIMEOU; 1152 xfer->c_intr(chp, xfer, 0); 1153 } 1154 /* reenable interrupts */ 1155 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1156 } 1157 1158 static void 1159 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1160 { 1161 ahci_cmd_complete(chp, xfer, 0); 1162 } 1163 1164 static void 1165 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1166 { 1167 struct ahci_channel *achp = (struct ahci_channel *)chp; 1168 struct ata_command *ata_c = &xfer->c_ata_c; 1169 bool deactivate = true; 1170 1171 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1172 DEBUG_FUNCS); 1173 1174 switch (reason) { 1175 case KILL_GONE_INACTIVE: 1176 deactivate = false; 1177 /* FALLTHROUGH */ 1178 case KILL_GONE: 1179 ata_c->flags |= AT_GONE; 1180 break; 1181 case KILL_RESET: 1182 ata_c->flags |= AT_RESET; 1183 break; 1184 case KILL_REQUEUE: 1185 panic("%s: not supposed to be requeued\n", __func__); 1186 break; 1187 default: 1188 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1189 panic("ahci_cmd_kill_xfer"); 1190 } 1191 1192 if (deactivate) { 1193 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1194 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1195 ata_deactivate_xfer(chp, xfer); 1196 } 1197 1198 ahci_cmd_done_end(chp, xfer); 1199 } 1200 1201 static int 1202 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1203 { 1204 struct ata_command *ata_c = &xfer->c_ata_c; 1205 struct ahci_channel *achp = (struct ahci_channel *)chp; 1206 1207 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1208 chp->ch_channel, 1209 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1210 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1211 DEBUG_FUNCS); 1212 1213 if (ata_waitdrain_xfer_check(chp, xfer)) 1214 return 0; 1215 1216 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1217 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1218 ata_deactivate_xfer(chp, xfer); 1219 1220 if (xfer->c_flags & C_TIMEOU) { 1221 ata_c->flags |= AT_TIMEOU; 1222 } 1223 1224 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1225 ata_c->flags |= AT_TIMEOU; 1226 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1227 ata_c->r_error = AHCI_TFD_ERR(tfd); 1228 ata_c->flags |= AT_ERROR; 1229 } 1230 1231 if (ata_c->flags & AT_READREG) 1232 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1233 1234 ahci_cmd_done(chp, xfer); 1235 return 0; 1236 } 1237 1238 static void 1239 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1240 { 1241 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1242 struct ahci_channel *achp = (struct ahci_channel *)chp; 1243 struct ata_command *ata_c = &xfer->c_ata_c; 1244 uint16_t *idwordbuf; 1245 int flags = ata_c->flags; 1246 int i; 1247 1248 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n", 1249 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1250 1251 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1252 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1253 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1254 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1255 BUS_DMASYNC_POSTWRITE); 1256 bus_dmamap_unload(sc->sc_dmat, map); 1257 } 1258 1259 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1260 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1261 1262 /* ata(4) expects IDENTIFY data to be in host endianess */ 1263 if (ata_c->r_command == WDCC_IDENTIFY || 1264 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1265 idwordbuf = xfer->c_databuf; 1266 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1267 idwordbuf[i] = le16toh(idwordbuf[i]); 1268 } 1269 } 1270 1271 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1272 ata_c->flags |= AT_XFDONE; 1273 ahci_cmd_done_end(chp, xfer); 1274 if ((flags & (AT_TIMEOU|AT_ERROR)) == 0) 1275 atastart(chp); 1276 } 1277 1278 static void 1279 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1280 { 1281 struct ata_command *ata_c = &xfer->c_ata_c; 1282 1283 ata_channel_lock(chp); 1284 1285 ata_c->flags |= AT_DONE; 1286 1287 if (ata_c->flags & AT_WAIT) 1288 ata_wake_xfer(chp, xfer); 1289 1290 ata_channel_unlock(chp); 1291 return; 1292 } 1293 1294 static int 1295 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1296 { 1297 struct ata_channel *chp = drvp->chnl_softc; 1298 struct ata_bio *ata_bio = &xfer->c_bio; 1299 1300 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1301 chp->ch_channel, 1302 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1303 DEBUG_XFERS); 1304 if (ata_bio->flags & ATA_POLL) 1305 xfer->c_flags |= C_POLL; 1306 xfer->c_drive = drvp->drive; 1307 xfer->c_databuf = ata_bio->databuf; 1308 xfer->c_bcount = ata_bio->bcount; 1309 xfer->c_start = ahci_bio_start; 1310 xfer->c_poll = ahci_bio_poll; 1311 xfer->c_abort = ahci_bio_abort; 1312 xfer->c_intr = ahci_bio_complete; 1313 xfer->c_kill_xfer = ahci_bio_kill_xfer; 1314 ata_exec_xfer(chp, xfer); 1315 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1316 } 1317 1318 static int 1319 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1320 { 1321 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1322 struct ahci_channel *achp = (struct ahci_channel *)chp; 1323 struct ata_bio *ata_bio = &xfer->c_bio; 1324 struct ahci_cmd_tbl *cmd_tbl; 1325 struct ahci_cmd_header *cmd_h; 1326 1327 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1328 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1329 1330 ata_channel_lock_owned(chp); 1331 1332 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1333 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1334 cmd_tbl), DEBUG_XFERS); 1335 1336 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1337 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1338 1339 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1340 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1341 chp->ch_channel, cmd_h), DEBUG_XFERS); 1342 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1343 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1344 ata_bio->error = ERR_DMA; 1345 ata_bio->r_error = 0; 1346 return ATASTART_ABORT; 1347 } 1348 cmd_h->cmdh_flags = htole16( 1349 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1350 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1351 cmd_h->cmdh_prdbc = 0; 1352 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1353 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1354 1355 if (xfer->c_flags & C_POLL) { 1356 /* polled command, disable interrupts */ 1357 AHCI_WRITE(sc, AHCI_GHC, 1358 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1359 } 1360 if (xfer->c_flags & C_NCQ) 1361 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1362 /* start command */ 1363 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1364 /* and says we started this command */ 1365 achp->ahcic_cmds_active |= 1U << xfer->c_slot; 1366 1367 if ((xfer->c_flags & C_POLL) == 0) { 1368 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1369 ata_timeout, xfer); 1370 return ATASTART_STARTED; 1371 } else 1372 return ATASTART_POLL; 1373 } 1374 1375 static void 1376 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1377 { 1378 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1379 struct ahci_channel *achp = (struct ahci_channel *)chp; 1380 1381 /* 1382 * Polled command. 1383 */ 1384 for (int i = 0; i < ATA_DELAY * 10; i++) { 1385 if (xfer->c_bio.flags & ATA_ITSDONE) 1386 break; 1387 ahci_intr_port(sc, achp); 1388 delay(100); 1389 } 1390 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1391 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1392 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1393 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1394 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1395 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1396 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1397 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1398 DEBUG_XFERS); 1399 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1400 xfer->c_bio.error = TIMEOUT; 1401 xfer->c_intr(chp, xfer, 0); 1402 } 1403 /* reenable interrupts */ 1404 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1405 } 1406 1407 static void 1408 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1409 { 1410 ahci_bio_complete(chp, xfer, 0); 1411 } 1412 1413 static void 1414 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1415 { 1416 int drive = xfer->c_drive; 1417 struct ata_bio *ata_bio = &xfer->c_bio; 1418 struct ahci_channel *achp = (struct ahci_channel *)chp; 1419 bool deactivate = true; 1420 1421 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1422 DEBUG_FUNCS); 1423 1424 ata_bio->flags |= ATA_ITSDONE; 1425 switch (reason) { 1426 case KILL_GONE_INACTIVE: 1427 deactivate = false; 1428 /* FALLTHROUGH */ 1429 case KILL_GONE: 1430 ata_bio->error = ERR_NODEV; 1431 break; 1432 case KILL_RESET: 1433 ata_bio->error = ERR_RESET; 1434 break; 1435 case KILL_REQUEUE: 1436 ata_bio->error = REQUEUE; 1437 break; 1438 default: 1439 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1440 panic("ahci_bio_kill_xfer"); 1441 } 1442 ata_bio->r_error = WDCE_ABRT; 1443 1444 if (deactivate) { 1445 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1446 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1447 ata_deactivate_xfer(chp, xfer); 1448 } 1449 1450 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1451 } 1452 1453 static int 1454 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1455 { 1456 struct ata_bio *ata_bio = &xfer->c_bio; 1457 int drive = xfer->c_drive; 1458 struct ahci_channel *achp = (struct ahci_channel *)chp; 1459 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1460 1461 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1462 DEBUG_FUNCS); 1463 1464 if (ata_waitdrain_xfer_check(chp, xfer)) 1465 return 0; 1466 1467 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 1468 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 1469 ata_deactivate_xfer(chp, xfer); 1470 1471 if (xfer->c_flags & C_TIMEOU) { 1472 ata_bio->error = TIMEOUT; 1473 } 1474 1475 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1476 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1477 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1478 BUS_DMASYNC_POSTWRITE); 1479 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1480 1481 ata_bio->flags |= ATA_ITSDONE; 1482 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1483 ata_bio->error = ERR_DF; 1484 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1485 ata_bio->error = ERROR; 1486 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1487 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1488 ata_bio->flags |= ATA_CORR; 1489 1490 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1491 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1492 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1493 ata_bio->bcount), DEBUG_XFERS); 1494 /* 1495 * If it was a write, complete data buffer may have been transfered 1496 * before error detection; in this case don't use cmdh_prdbc 1497 * as it won't reflect what was written to media. Assume nothing 1498 * was transfered and leave bcount as-is. 1499 * For queued commands, PRD Byte Count should not be used, and is 1500 * not required to be valid; in that case underflow is always illegal. 1501 */ 1502 if ((xfer->c_flags & C_NCQ) != 0) { 1503 if (ata_bio->error == NOERROR) 1504 ata_bio->bcount = 0; 1505 } else { 1506 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1507 ata_bio->bcount -= 1508 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1509 } 1510 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1511 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1512 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1513 atastart(chp); 1514 return 0; 1515 } 1516 1517 static void 1518 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1519 { 1520 int i; 1521 /* stop channel */ 1522 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1523 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1524 /* wait 1s for channel to stop */ 1525 for (i = 0; i <100; i++) { 1526 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1527 == 0) 1528 break; 1529 ata_delay(chp, 10, "ahcistop", flags); 1530 } 1531 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1532 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1533 /* XXX controller reset ? */ 1534 return; 1535 } 1536 1537 if (sc->sc_channel_stop) 1538 sc->sc_channel_stop(sc, chp); 1539 } 1540 1541 static void 1542 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1543 int flags, int clo) 1544 { 1545 int i; 1546 uint32_t p_cmd; 1547 /* clear error */ 1548 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1549 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1550 1551 if (clo) { 1552 /* issue command list override */ 1553 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1554 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1555 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1556 /* wait 1s for AHCI_CAP_CLO to clear */ 1557 for (i = 0; i <100; i++) { 1558 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1559 AHCI_P_CMD_CLO) == 0) 1560 break; 1561 ata_delay(chp, 10, "ahciclo", flags); 1562 } 1563 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1564 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1565 /* XXX controller reset ? */ 1566 return; 1567 } 1568 } 1569 1570 if (sc->sc_channel_start) 1571 sc->sc_channel_start(sc, chp); 1572 1573 /* and start controller */ 1574 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1575 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1576 if (chp->ch_ndrives > PMP_PORT_CTL && 1577 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1578 p_cmd |= AHCI_P_CMD_PMA; 1579 } 1580 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1581 } 1582 1583 static void 1584 ahci_hold(struct ahci_channel *achp) 1585 { 1586 achp->ahcic_cmds_hold |= achp->ahcic_cmds_active; 1587 achp->ahcic_cmds_active = 0; 1588 } 1589 1590 static void 1591 ahci_unhold(struct ahci_channel *achp) 1592 { 1593 achp->ahcic_cmds_active = achp->ahcic_cmds_hold; 1594 achp->ahcic_cmds_hold = 0; 1595 } 1596 1597 /* Recover channel after command failure */ 1598 void 1599 ahci_channel_recover(struct ahci_softc *sc, struct ata_channel *chp, int tfd) 1600 { 1601 struct ahci_channel *achp = (struct ahci_channel *)chp; 1602 struct ata_drive_datas *drvp; 1603 uint8_t slot, eslot, st, err; 1604 int drive = -1, error; 1605 struct ata_xfer *xfer; 1606 bool reset = false; 1607 1608 KASSERT(!achp->ahcic_recovering); 1609 1610 achp->ahcic_recovering = true; 1611 1612 /* 1613 * Read FBS to get the drive which caused the error, if PM is in use. 1614 * According to AHCI 1.3 spec, this register is available regardless 1615 * if FIS-based switching (FBSS) feature is supported, or disabled. 1616 * If FIS-based switching is not in use, it merely maintains single 1617 * pair of DRQ/BSY state, but it is enough since in that case we 1618 * never issue commands for more than one device at the time anyway. 1619 * XXX untested 1620 */ 1621 if (chp->ch_ndrives > PMP_PORT_CTL) { 1622 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1623 if (fbs & AHCI_P_FBS_SDE) { 1624 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1625 1626 /* 1627 * Tell HBA to reset PM port X (value in DWE) state, 1628 * and resume processing commands for other ports. 1629 */ 1630 fbs |= AHCI_P_FBS_DEC; 1631 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1632 for (int i = 0; i < 1000; i++) { 1633 fbs = AHCI_READ(sc, 1634 AHCI_P_FBS(chp->ch_channel)); 1635 if ((fbs & AHCI_P_FBS_DEC) == 0) 1636 break; 1637 DELAY(1000); 1638 } 1639 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1640 /* follow non-device specific recovery */ 1641 drive = -1; 1642 reset = true; 1643 } 1644 } else { 1645 /* not device specific, reset channel */ 1646 drive = -1; 1647 reset = true; 1648 } 1649 } else 1650 drive = 0; 1651 1652 drvp = &chp->ch_drive[drive]; 1653 1654 /* 1655 * If BSY or DRQ bits are set, must execute COMRESET to return 1656 * device to idle state. If drive is idle, it's enough to just 1657 * reset CMD.ST, it's not necessary to do software reset. 1658 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1659 * to unblock device processing if COMRESET was not done. 1660 */ 1661 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 1662 goto reset; 1663 1664 KASSERT(drive >= 0); 1665 ahci_channel_stop(sc, chp, AT_POLL); 1666 ahci_channel_start(sc, chp, AT_POLL, 1667 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1668 1669 ahci_hold(achp); 1670 1671 /* 1672 * When running NCQ commands, READ LOG EXT is necessary to clear the 1673 * error condition and unblock the device. 1674 */ 1675 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 1676 1677 ahci_unhold(achp); 1678 1679 switch (error) { 1680 case 0: 1681 /* Error out the particular NCQ xfer, then requeue the others */ 1682 if ((achp->ahcic_cmds_active & (1U << eslot)) != 0) { 1683 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 1684 xfer->c_flags |= C_RECOVERED; 1685 xfer->c_intr(chp, xfer, 1686 (err << AHCI_P_TFD_ERR_SHIFT) | st); 1687 } 1688 break; 1689 1690 case EOPNOTSUPP: 1691 /* 1692 * Non-NCQ command error, just find the slot and end with 1693 * the error. 1694 */ 1695 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1696 if ((achp->ahcic_cmds_active & (1U << slot)) != 0) { 1697 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1698 xfer->c_intr(chp, xfer, tfd); 1699 } 1700 } 1701 break; 1702 1703 case EAGAIN: 1704 /* 1705 * Failed to get resources to run the recovery command, must 1706 * reset the drive. This will also kill all still outstanding 1707 * transfers. 1708 */ 1709 reset: 1710 ahci_reset_channel(chp, AT_POLL); 1711 goto out; 1712 /* NOTREACHED */ 1713 1714 default: 1715 /* 1716 * The command to get the slot failed. Kill outstanding 1717 * commands for the same drive only. No need to reset 1718 * the drive, it's unblocked nevertheless. 1719 */ 1720 break; 1721 } 1722 1723 /* Requeue all unfinished commands for same drive as failed command */ 1724 for (slot = 0; slot < sc->sc_ncmds; slot++) { 1725 if ((achp->ahcic_cmds_active & (1U << slot)) == 0) 1726 continue; 1727 1728 xfer = ata_queue_hwslot_to_xfer(chp, slot); 1729 if (drive != xfer->c_drive) 1730 continue; 1731 1732 xfer->c_kill_xfer(chp, xfer, 1733 (error == 0) ? KILL_REQUEUE : KILL_RESET); 1734 } 1735 1736 out: 1737 /* Drive unblocked, back to normal operation */ 1738 achp->ahcic_recovering = false; 1739 atastart(chp); 1740 } 1741 1742 static int 1743 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1744 size_t count, int op) 1745 { 1746 int error, seg; 1747 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1748 struct ahci_channel *achp = (struct ahci_channel *)chp; 1749 struct ahci_cmd_tbl *cmd_tbl; 1750 struct ahci_cmd_header *cmd_h; 1751 1752 cmd_h = &achp->ahcic_cmdh[slot]; 1753 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1754 1755 if (data == NULL) { 1756 cmd_h->cmdh_prdtl = 0; 1757 goto end; 1758 } 1759 1760 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1761 data, count, NULL, 1762 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1763 if (error) { 1764 printf("%s port %d: failed to load xfer: %d\n", 1765 AHCINAME(sc), chp->ch_channel, error); 1766 return error; 1767 } 1768 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1769 achp->ahcic_datad[slot]->dm_mapsize, 1770 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1771 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1772 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1773 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1774 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1775 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1776 } 1777 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1778 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1779 end: 1780 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1781 return 0; 1782 } 1783 1784 #if NATAPIBUS > 0 1785 static void 1786 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1787 { 1788 struct ata_channel *chp = ata_sc->sc_chan; 1789 struct atac_softc *atac = chp->ch_atac; 1790 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1791 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1792 /* 1793 * Fill in the scsipi_adapter. 1794 */ 1795 adapt->adapt_dev = atac->atac_dev; 1796 adapt->adapt_nchannels = atac->atac_nchannels; 1797 adapt->adapt_request = ahci_atapi_scsipi_request; 1798 adapt->adapt_minphys = ahci_atapi_minphys; 1799 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1800 1801 /* 1802 * Fill in the scsipi_channel. 1803 */ 1804 memset(chan, 0, sizeof(*chan)); 1805 chan->chan_adapter = adapt; 1806 chan->chan_bustype = &ahci_atapi_bustype; 1807 chan->chan_channel = chp->ch_channel; 1808 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1809 chan->chan_openings = 1; 1810 chan->chan_max_periph = 1; 1811 chan->chan_ntargets = 1; 1812 chan->chan_nluns = 1; 1813 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1814 atapiprint); 1815 } 1816 1817 static void 1818 ahci_atapi_minphys(struct buf *bp) 1819 { 1820 if (bp->b_bcount > MAXPHYS) 1821 bp->b_bcount = MAXPHYS; 1822 minphys(bp); 1823 } 1824 1825 /* 1826 * Kill off all pending xfers for a periph. 1827 * 1828 * Must be called at splbio(). 1829 */ 1830 static void 1831 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1832 { 1833 struct atac_softc *atac = 1834 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1835 struct ata_channel *chp = 1836 atac->atac_channels[periph->periph_channel->chan_channel]; 1837 1838 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1839 } 1840 1841 static void 1842 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1843 scsipi_adapter_req_t req, void *arg) 1844 { 1845 struct scsipi_adapter *adapt = chan->chan_adapter; 1846 struct scsipi_periph *periph; 1847 struct scsipi_xfer *sc_xfer; 1848 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1849 struct atac_softc *atac = &sc->sc_atac; 1850 struct ata_xfer *xfer; 1851 int channel = chan->chan_channel; 1852 int drive, s; 1853 1854 switch (req) { 1855 case ADAPTER_REQ_RUN_XFER: 1856 sc_xfer = arg; 1857 periph = sc_xfer->xs_periph; 1858 drive = periph->periph_target; 1859 if (!device_is_active(atac->atac_dev)) { 1860 sc_xfer->error = XS_DRIVER_STUFFUP; 1861 scsipi_done(sc_xfer); 1862 return; 1863 } 1864 xfer = ata_get_xfer_ext(atac->atac_channels[channel], 0, 0); 1865 if (xfer == NULL) { 1866 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1867 scsipi_done(sc_xfer); 1868 return; 1869 } 1870 1871 if (sc_xfer->xs_control & XS_CTL_POLL) 1872 xfer->c_flags |= C_POLL; 1873 xfer->c_drive = drive; 1874 xfer->c_flags |= C_ATAPI; 1875 xfer->c_scsipi = sc_xfer; 1876 xfer->c_databuf = sc_xfer->data; 1877 xfer->c_bcount = sc_xfer->datalen; 1878 xfer->c_start = ahci_atapi_start; 1879 xfer->c_poll = ahci_atapi_poll; 1880 xfer->c_abort = ahci_atapi_abort; 1881 xfer->c_intr = ahci_atapi_complete; 1882 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1883 xfer->c_dscpoll = 0; 1884 s = splbio(); 1885 ata_exec_xfer(atac->atac_channels[channel], xfer); 1886 #ifdef DIAGNOSTIC 1887 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1888 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1889 panic("ahci_atapi_scsipi_request: polled command " 1890 "not done"); 1891 #endif 1892 splx(s); 1893 return; 1894 default: 1895 /* Not supported, nothing to do. */ 1896 ; 1897 } 1898 } 1899 1900 static int 1901 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1902 { 1903 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1904 struct ahci_channel *achp = (struct ahci_channel *)chp; 1905 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1906 struct ahci_cmd_tbl *cmd_tbl; 1907 struct ahci_cmd_header *cmd_h; 1908 1909 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1910 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1911 1912 ata_channel_lock_owned(chp); 1913 1914 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1915 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1916 cmd_tbl), DEBUG_XFERS); 1917 1918 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1919 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1920 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1921 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1922 1923 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1924 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1925 chp->ch_channel, cmd_h), DEBUG_XFERS); 1926 if (ahci_dma_setup(chp, xfer->c_slot, 1927 sc_xfer->datalen ? sc_xfer->data : NULL, 1928 sc_xfer->datalen, 1929 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1930 BUS_DMA_READ : BUS_DMA_WRITE)) { 1931 sc_xfer->error = XS_DRIVER_STUFFUP; 1932 return ATASTART_ABORT; 1933 } 1934 cmd_h->cmdh_flags = htole16( 1935 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1936 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1937 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1938 cmd_h->cmdh_prdbc = 0; 1939 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1941 1942 if (xfer->c_flags & C_POLL) { 1943 /* polled command, disable interrupts */ 1944 AHCI_WRITE(sc, AHCI_GHC, 1945 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1946 } 1947 /* start command */ 1948 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1949 /* and says we started this command */ 1950 achp->ahcic_cmds_active |= 1U << xfer->c_slot; 1951 1952 if ((xfer->c_flags & C_POLL) == 0) { 1953 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1954 ata_timeout, xfer); 1955 return ATASTART_STARTED; 1956 } else 1957 return ATASTART_POLL; 1958 } 1959 1960 static void 1961 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1962 { 1963 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1964 struct ahci_channel *achp = (struct ahci_channel *)chp; 1965 1966 /* 1967 * Polled command. 1968 */ 1969 for (int i = 0; i < ATA_DELAY / 10; i++) { 1970 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1971 break; 1972 ahci_intr_port(sc, achp); 1973 delay(10000); 1974 } 1975 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1976 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1977 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1978 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1979 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1980 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1981 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1982 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1983 DEBUG_XFERS); 1984 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1985 xfer->c_scsipi->error = XS_TIMEOUT; 1986 xfer->c_intr(chp, xfer, 0); 1987 } 1988 /* reenable interrupts */ 1989 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1990 } 1991 1992 static void 1993 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1994 { 1995 ahci_atapi_complete(chp, xfer, 0); 1996 } 1997 1998 static int 1999 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 2000 { 2001 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2002 struct ahci_channel *achp = (struct ahci_channel *)chp; 2003 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 2004 2005 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 2006 DEBUG_FUNCS); 2007 2008 if (ata_waitdrain_xfer_check(chp, xfer)) 2009 return 0; 2010 2011 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 2012 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 2013 ata_deactivate_xfer(chp, xfer); 2014 2015 if (xfer->c_flags & C_TIMEOU) { 2016 sc_xfer->error = XS_TIMEOUT; 2017 } 2018 2019 if (xfer->c_bcount > 0) { 2020 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2021 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2022 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2023 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2024 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2025 } 2026 2027 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2028 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2029 sc_xfer->resid = sc_xfer->datalen; 2030 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2031 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2032 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2033 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2034 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2035 sc_xfer->resid == sc_xfer->datalen)) { 2036 sc_xfer->error = XS_SHORTSENSE; 2037 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2038 if ((sc_xfer->xs_periph->periph_quirks & 2039 PQUIRK_NOSENSE) == 0) { 2040 /* ask scsipi to send a REQUEST_SENSE */ 2041 sc_xfer->error = XS_BUSY; 2042 sc_xfer->status = SCSI_CHECK; 2043 } 2044 } 2045 ata_free_xfer(chp, xfer); 2046 scsipi_done(sc_xfer); 2047 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2048 atastart(chp); 2049 return 0; 2050 } 2051 2052 static void 2053 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2054 { 2055 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2056 struct ahci_channel *achp = (struct ahci_channel *)chp; 2057 bool deactivate = true; 2058 2059 /* remove this command from xfer queue */ 2060 switch (reason) { 2061 case KILL_GONE_INACTIVE: 2062 deactivate = false; 2063 /* FALLTHROUGH */ 2064 case KILL_GONE: 2065 sc_xfer->error = XS_DRIVER_STUFFUP; 2066 break; 2067 case KILL_RESET: 2068 sc_xfer->error = XS_RESET; 2069 break; 2070 case KILL_REQUEUE: 2071 sc_xfer->error = XS_REQUEUE; 2072 break; 2073 default: 2074 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2075 panic("ahci_ata_atapi_kill_xfer"); 2076 } 2077 2078 if (deactivate) { 2079 KASSERT((achp->ahcic_cmds_active & (1U << xfer->c_slot)) != 0); 2080 achp->ahcic_cmds_active &= ~(1U << xfer->c_slot); 2081 ata_deactivate_xfer(chp, xfer); 2082 } 2083 2084 ata_free_xfer(chp, xfer); 2085 scsipi_done(sc_xfer); 2086 } 2087 2088 static void 2089 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2090 { 2091 struct scsipi_channel *chan = sc->sc_channel; 2092 struct scsipi_periph *periph; 2093 struct ataparams ids; 2094 struct ataparams *id = &ids; 2095 struct ahci_softc *ahcic = 2096 device_private(chan->chan_adapter->adapt_dev); 2097 struct atac_softc *atac = &ahcic->sc_atac; 2098 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2099 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2100 struct scsipibus_attach_args sa; 2101 char serial_number[21], model[41], firmware_revision[9]; 2102 int s; 2103 2104 /* skip if already attached */ 2105 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2106 return; 2107 2108 /* if no ATAPI device detected at attach time, skip */ 2109 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2110 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2111 "not present\n", target), DEBUG_PROBE); 2112 return; 2113 } 2114 2115 /* Some ATAPI devices need a bit more time after software reset. */ 2116 delay(5000); 2117 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2118 #ifdef ATAPI_DEBUG_PROBE 2119 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2120 AHCINAME(ahcic), target, 2121 id->atap_config & ATAPI_CFG_CMD_MASK, 2122 id->atap_config & ATAPI_CFG_DRQ_MASK); 2123 #endif 2124 periph = scsipi_alloc_periph(M_NOWAIT); 2125 if (periph == NULL) { 2126 aprint_error_dev(sc->sc_dev, 2127 "unable to allocate periph for drive %d\n", 2128 target); 2129 return; 2130 } 2131 periph->periph_dev = NULL; 2132 periph->periph_channel = chan; 2133 periph->periph_switch = &atapi_probe_periphsw; 2134 periph->periph_target = target; 2135 periph->periph_lun = 0; 2136 periph->periph_quirks = PQUIRK_ONLYBIG; 2137 2138 #ifdef SCSIPI_DEBUG 2139 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2140 SCSIPI_DEBUG_TARGET == target) 2141 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2142 #endif 2143 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2144 if (id->atap_config & ATAPI_CFG_REMOV) 2145 periph->periph_flags |= PERIPH_REMOVABLE; 2146 if (periph->periph_type == T_SEQUENTIAL) { 2147 s = splbio(); 2148 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2149 splx(s); 2150 } 2151 2152 sa.sa_periph = periph; 2153 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2154 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2155 T_REMOV : T_FIXED; 2156 strnvisx(model, sizeof(model), id->atap_model, 40, 2157 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2158 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2159 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2160 strnvisx(firmware_revision, sizeof(firmware_revision), 2161 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2162 sa.sa_inqbuf.vendor = model; 2163 sa.sa_inqbuf.product = serial_number; 2164 sa.sa_inqbuf.revision = firmware_revision; 2165 2166 /* 2167 * Determine the operating mode capabilities of the device. 2168 */ 2169 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2170 periph->periph_cap |= PERIPH_CAP_CMD16; 2171 /* XXX This is gross. */ 2172 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2173 2174 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2175 2176 if (drvp->drv_softc) 2177 ata_probe_caps(drvp); 2178 else { 2179 s = splbio(); 2180 drvp->drive_type = ATA_DRIVET_NONE; 2181 splx(s); 2182 } 2183 } else { 2184 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2185 "failed for drive %s:%d:%d\n", 2186 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2187 s = splbio(); 2188 drvp->drive_type = ATA_DRIVET_NONE; 2189 splx(s); 2190 } 2191 } 2192 #endif /* NATAPIBUS */ 2193
Indexes created Fri Oct 17 00:09:41 GMT 2025