ahcisata_core.c revision 1.64
1 /* $NetBSD: ahcisata_core.c,v 1.64 2018/10/22 20:13:47 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.64 2018/10/22 20:13:47 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 129 static void ahci_setup_port(struct ahci_softc *sc, int i); 130 131 static void 132 ahci_enable(struct ahci_softc *sc) 133 { 134 uint32_t ghc; 135 136 ghc = AHCI_READ(sc, AHCI_GHC); 137 if (!(ghc & AHCI_GHC_AE)) { 138 ghc |= AHCI_GHC_AE; 139 AHCI_WRITE(sc, AHCI_GHC, ghc); 140 } 141 } 142 143 static int 144 ahci_reset(struct ahci_softc *sc) 145 { 146 int i; 147 148 /* reset controller */ 149 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 150 /* wait up to 1s for reset to complete */ 151 for (i = 0; i < 1000; i++) { 152 delay(1000); 153 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 154 break; 155 } 156 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 157 aprint_error("%s: reset failed\n", AHCINAME(sc)); 158 return -1; 159 } 160 /* enable ahci mode */ 161 ahci_enable(sc); 162 163 if (sc->sc_save_init_data) { 164 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 165 if (sc->sc_init_data.cap2) 166 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 167 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 168 } 169 170 return 0; 171 } 172 173 static void 174 ahci_setup_ports(struct ahci_softc *sc) 175 { 176 int i, port; 177 178 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 179 if ((sc->sc_ahci_ports & (1U << i)) == 0) 180 continue; 181 if (port >= sc->sc_atac.atac_nchannels) { 182 aprint_error("%s: more ports than announced\n", 183 AHCINAME(sc)); 184 break; 185 } 186 ahci_setup_port(sc, i); 187 } 188 } 189 190 static void 191 ahci_reprobe_drives(struct ahci_softc *sc) 192 { 193 int i, port; 194 struct ahci_channel *achp; 195 struct ata_channel *chp; 196 197 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 198 if ((sc->sc_ahci_ports & (1U << i)) == 0) 199 continue; 200 if (port >= sc->sc_atac.atac_nchannels) { 201 aprint_error("%s: more ports than announced\n", 202 AHCINAME(sc)); 203 break; 204 } 205 achp = &sc->sc_channels[i]; 206 chp = &achp->ata_channel; 207 208 ahci_probe_drive(chp); 209 } 210 } 211 212 static void 213 ahci_setup_port(struct ahci_softc *sc, int i) 214 { 215 struct ahci_channel *achp; 216 217 achp = &sc->sc_channels[i]; 218 219 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 220 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 221 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 222 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 223 } 224 225 static void 226 ahci_enable_intrs(struct ahci_softc *sc) 227 { 228 229 /* clear interrupts */ 230 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 231 /* enable interrupts */ 232 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 233 } 234 235 void 236 ahci_attach(struct ahci_softc *sc) 237 { 238 uint32_t ahci_rev; 239 int i, j, port; 240 struct ahci_channel *achp; 241 struct ata_channel *chp; 242 int error; 243 int dmasize; 244 char buf[128]; 245 void *cmdhp; 246 void *cmdtblp; 247 248 if (sc->sc_save_init_data) { 249 ahci_enable(sc); 250 251 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 252 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 253 254 ahci_rev = AHCI_READ(sc, AHCI_VS); 255 if (AHCI_VS_MJR(ahci_rev) > 1 || 256 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 257 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 258 } else { 259 sc->sc_init_data.cap2 = 0; 260 } 261 if (sc->sc_init_data.ports == 0) { 262 sc->sc_init_data.ports = sc->sc_ahci_ports; 263 } 264 } 265 266 if (ahci_reset(sc) != 0) 267 return; 268 269 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 270 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 271 aprint_verbose_dev(sc->sc_atac.atac_dev, 272 "ignoring broken port multiplier support\n"); 273 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 274 } 275 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 276 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 277 ahci_rev = AHCI_READ(sc, AHCI_VS); 278 snprintb(buf, sizeof(buf), "\177\020" 279 /* "f\000\005NP\0" */ 280 "b\005SXS\0" 281 "b\006EMS\0" 282 "b\007CCCS\0" 283 /* "f\010\005NCS\0" */ 284 "b\015PSC\0" 285 "b\016SSC\0" 286 "b\017PMD\0" 287 "b\020FBSS\0" 288 "b\021SPM\0" 289 "b\022SAM\0" 290 "b\023SNZO\0" 291 "f\024\003ISS\0" 292 "=\001Gen1\0" 293 "=\002Gen2\0" 294 "=\003Gen3\0" 295 "b\030SCLO\0" 296 "b\031SAL\0" 297 "b\032SALP\0" 298 "b\033SSS\0" 299 "b\034SMPS\0" 300 "b\035SSNTF\0" 301 "b\036SNCQ\0" 302 "b\037S64A\0" 303 "\0", sc->sc_ahci_cap); 304 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 305 ", %d port%s, %d slot%s, CAP %s\n", 306 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 307 sc->sc_atac.atac_nchannels, 308 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 309 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 310 311 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 312 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 313 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 314 sc->sc_atac.atac_pio_cap = 4; 315 sc->sc_atac.atac_dma_cap = 2; 316 sc->sc_atac.atac_udma_cap = 6; 317 sc->sc_atac.atac_channels = sc->sc_chanarray; 318 sc->sc_atac.atac_probe = ahci_probe_drive; 319 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 320 sc->sc_atac.atac_set_modes = ahci_setup_channel; 321 #if NATAPIBUS > 0 322 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 323 #endif 324 325 dmasize = 326 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 327 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 328 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 329 if (error) { 330 aprint_error("%s: unable to allocate command header memory" 331 ", error=%d\n", AHCINAME(sc), error); 332 return; 333 } 334 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 335 sc->sc_cmd_hdr_nseg, dmasize, 336 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 337 if (error) { 338 aprint_error("%s: unable to map command header memory" 339 ", error=%d\n", AHCINAME(sc), error); 340 return; 341 } 342 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 343 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 344 if (error) { 345 aprint_error("%s: unable to create command header map" 346 ", error=%d\n", AHCINAME(sc), error); 347 return; 348 } 349 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 350 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 351 if (error) { 352 aprint_error("%s: unable to load command header map" 353 ", error=%d\n", AHCINAME(sc), error); 354 return; 355 } 356 sc->sc_cmd_hdr = cmdhp; 357 358 ahci_enable_intrs(sc); 359 360 if (sc->sc_ahci_ports == 0) { 361 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 362 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 363 DEBUG_PROBE); 364 } 365 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 366 if ((sc->sc_ahci_ports & (1U << i)) == 0) 367 continue; 368 if (port >= sc->sc_atac.atac_nchannels) { 369 aprint_error("%s: more ports than announced\n", 370 AHCINAME(sc)); 371 break; 372 } 373 achp = &sc->sc_channels[i]; 374 chp = &achp->ata_channel; 375 sc->sc_chanarray[i] = chp; 376 chp->ch_channel = i; 377 chp->ch_atac = &sc->sc_atac; 378 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 379 if (chp->ch_queue == NULL) { 380 aprint_error("%s port %d: can't allocate memory for " 381 "command queue", AHCINAME(sc), i); 382 break; 383 } 384 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 385 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 386 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 387 BUS_DMA_NOWAIT); 388 if (error) { 389 aprint_error("%s: unable to allocate command table " 390 "memory, error=%d\n", AHCINAME(sc), error); 391 break; 392 } 393 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 394 achp->ahcic_cmd_tbl_nseg, dmasize, 395 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 396 if (error) { 397 aprint_error("%s: unable to map command table memory" 398 ", error=%d\n", AHCINAME(sc), error); 399 break; 400 } 401 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 402 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 403 if (error) { 404 aprint_error("%s: unable to create command table map" 405 ", error=%d\n", AHCINAME(sc), error); 406 break; 407 } 408 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 409 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 410 if (error) { 411 aprint_error("%s: unable to load command table map" 412 ", error=%d\n", AHCINAME(sc), error); 413 break; 414 } 415 achp->ahcic_cmdh = (struct ahci_cmd_header *) 416 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 417 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 418 AHCI_CMDH_SIZE * port; 419 achp->ahcic_rfis = (struct ahci_r_fis *) 420 ((char *)cmdhp + 421 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 422 AHCI_RFIS_SIZE * port); 423 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 424 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 425 AHCI_RFIS_SIZE * port; 426 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 427 "rfis %p (0x%" PRIx64 ")\n", i, 428 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 429 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 430 DEBUG_PROBE); 431 432 for (j = 0; j < sc->sc_ncmds; j++) { 433 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 434 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 435 achp->ahcic_bus_cmd_tbl[j] = 436 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 437 AHCI_CMDTBL_SIZE * j; 438 achp->ahcic_cmdh[j].cmdh_cmdtba = 439 htole64(achp->ahcic_bus_cmd_tbl[j]); 440 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 441 achp->ahcic_cmd_tbl[j], 442 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 443 /* The xfer DMA map */ 444 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 445 AHCI_NPRD, 0x400000 /* 4MB */, 0, 446 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 447 &achp->ahcic_datad[j]); 448 if (error) { 449 aprint_error("%s: couldn't alloc xfer DMA map, " 450 "error=%d\n", AHCINAME(sc), error); 451 goto end; 452 } 453 } 454 ahci_setup_port(sc, i); 455 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 456 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 457 aprint_error("%s: couldn't map channel %d " 458 "sata_status regs\n", AHCINAME(sc), i); 459 break; 460 } 461 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 462 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 463 aprint_error("%s: couldn't map channel %d " 464 "sata_control regs\n", AHCINAME(sc), i); 465 break; 466 } 467 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 468 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 469 aprint_error("%s: couldn't map channel %d " 470 "sata_error regs\n", AHCINAME(sc), i); 471 break; 472 } 473 ata_channel_attach(chp); 474 port++; 475 end: 476 continue; 477 } 478 } 479 480 int 481 ahci_detach(struct ahci_softc *sc, int flags) 482 { 483 struct atac_softc *atac; 484 struct ahci_channel *achp; 485 struct ata_channel *chp; 486 struct scsipi_adapter *adapt; 487 int i, j; 488 int error; 489 490 atac = &sc->sc_atac; 491 adapt = &atac->atac_atapi_adapter._generic; 492 493 for (i = 0; i < AHCI_MAX_PORTS; i++) { 494 achp = &sc->sc_channels[i]; 495 chp = &achp->ata_channel; 496 497 if ((sc->sc_ahci_ports & (1U << i)) == 0) 498 continue; 499 if (i >= sc->sc_atac.atac_nchannels) { 500 aprint_error("%s: more ports than announced\n", 501 AHCINAME(sc)); 502 break; 503 } 504 505 if (chp->atabus == NULL) 506 continue; 507 if ((error = config_detach(chp->atabus, flags)) != 0) 508 return error; 509 510 for (j = 0; j < sc->sc_ncmds; j++) 511 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 512 513 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 514 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 515 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 516 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 517 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 518 achp->ahcic_cmd_tbl_nseg); 519 520 chp->atabus = NULL; 521 522 ata_channel_detach(chp); 523 } 524 525 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 526 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 527 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 528 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 529 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 530 531 if (adapt->adapt_refcnt != 0) 532 return EBUSY; 533 534 return 0; 535 } 536 537 void 538 ahci_resume(struct ahci_softc *sc) 539 { 540 ahci_reset(sc); 541 ahci_setup_ports(sc); 542 ahci_reprobe_drives(sc); 543 ahci_enable_intrs(sc); 544 } 545 546 int 547 ahci_intr(void *v) 548 { 549 struct ahci_softc *sc = v; 550 uint32_t is; 551 int i, r = 0; 552 553 while ((is = AHCI_READ(sc, AHCI_IS))) { 554 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 555 DEBUG_INTR); 556 r = 1; 557 AHCI_WRITE(sc, AHCI_IS, is); 558 for (i = 0; i < AHCI_MAX_PORTS; i++) 559 if (is & (1U << i)) 560 ahci_intr_port(sc, &sc->sc_channels[i]); 561 } 562 return r; 563 } 564 565 static void 566 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 567 { 568 uint32_t is, tfd, sact; 569 struct ata_channel *chp = &achp->ata_channel; 570 struct ata_xfer *xfer; 571 int slot = -1; 572 bool recover = false; 573 uint32_t aslots; 574 575 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 576 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 577 578 AHCIDEBUG_PRINT(( 579 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 580 AHCINAME(sc), 581 chp->ch_channel, is, 582 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 583 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 584 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 585 DEBUG_INTR); 586 587 if ((chp->ch_flags & ATACH_NCQ) == 0) { 588 /* Non-NCQ operation */ 589 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 590 } else { 591 /* NCQ operation */ 592 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 593 } 594 595 /* Handle errors */ 596 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 597 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 598 /* Fatal errors */ 599 if (is & AHCI_P_IX_TFES) { 600 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 601 602 if ((chp->ch_flags & ATACH_NCQ) == 0) { 603 /* Slot valid only for Non-NCQ operation */ 604 slot = (AHCI_READ(sc, 605 AHCI_P_CMD(chp->ch_channel)) 606 & AHCI_P_CMD_CCS_MASK) 607 >> AHCI_P_CMD_CCS_SHIFT; 608 } 609 610 AHCIDEBUG_PRINT(( 611 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 612 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 613 DEBUG_INTR); 614 } else { 615 /* mark an error, and set BSY */ 616 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 617 WDCS_ERR | WDCS_BSY; 618 } 619 620 if (is & AHCI_P_IX_IFS) { 621 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 622 AHCINAME(sc), chp->ch_channel, 623 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 624 DEBUG_INTR); 625 } 626 627 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 628 recover = true; 629 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 630 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 631 632 /* D2H Register FIS or Set Device Bits */ 633 if ((tfd & WDCS_ERR) != 0) { 634 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 635 recover = true; 636 637 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 638 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 639 640 } 641 } else { 642 tfd = 0; 643 } 644 645 if (__predict_false(recover)) 646 ata_channel_freeze(chp); 647 648 aslots = ata_queue_active(chp); 649 650 if (slot >= 0) { 651 if ((aslots & __BIT(slot)) != 0 && 652 (sact & __BIT(slot)) == 0) { 653 xfer = ata_queue_hwslot_to_xfer(chp, slot); 654 xfer->ops->c_intr(chp, xfer, tfd); 655 } 656 } else { 657 /* 658 * For NCQ, HBA halts processing when error is notified, 659 * and any further D2H FISes are ignored until the error 660 * condition is cleared. Hence if a command is inactive, 661 * it means it actually already finished successfully. 662 * Note: active slots can change as c_intr() callback 663 * can activate another command(s), so must only process 664 * commands active before we start processing. 665 */ 666 667 for (slot=0; slot < sc->sc_ncmds; slot++) { 668 if ((aslots & __BIT(slot)) != 0 && 669 (sact & __BIT(slot)) == 0) { 670 xfer = ata_queue_hwslot_to_xfer(chp, slot); 671 xfer->ops->c_intr(chp, xfer, tfd); 672 } 673 } 674 } 675 676 if (__predict_false(recover)) { 677 ata_channel_lock(chp); 678 ata_channel_thaw_locked(chp); 679 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 680 ata_channel_unlock(chp); 681 } 682 } 683 684 static void 685 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 686 { 687 struct ata_channel *chp = drvp->chnl_softc; 688 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 689 uint8_t c_slot; 690 691 ata_channel_lock_owned(chp); 692 693 /* get a slot for running the command on */ 694 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 695 panic("%s: %s: failed to get xfer for reset, port %d\n", 696 device_xname(sc->sc_atac.atac_dev), 697 __func__, chp->ch_channel); 698 /* NOTREACHED */ 699 } 700 701 AHCI_WRITE(sc, AHCI_GHC, 702 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 703 ahci_channel_stop(sc, chp, flags); 704 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 705 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 706 707 ata_queue_free_slot(chp, c_slot); 708 } 709 710 /* return error code from ata_bio */ 711 static int 712 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 713 { 714 struct ahci_channel *achp = (struct ahci_channel *)chp; 715 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 716 int i; 717 uint32_t is; 718 719 /* 720 * Base timeout is specified in ms. 721 * If we are allowed to sleep, wait a tick each round. 722 * Otherwise delay for 10ms on each round. 723 */ 724 if (flags & AT_WAIT) 725 timeout = MAX(1, mstohz(timeout)); 726 else 727 timeout = timeout / 10; 728 729 AHCI_CMDH_SYNC(sc, achp, slot, 730 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 731 /* start command */ 732 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 733 for (i = 0; i < timeout; i++) { 734 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 735 0) 736 return 0; 737 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 738 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 739 AHCI_P_IX_IFS | 740 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 741 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 742 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 743 /* 744 * we got the D2H FIS anyway, 745 * assume sig is valid. 746 * channel is restarted later 747 */ 748 return ERROR; 749 } 750 aprint_debug("%s channel %d: error 0x%x sending FIS\n", 751 AHCINAME(sc), chp->ch_channel, is); 752 return ERR_DF; 753 } 754 ata_delay(chp, 10, "ahcifis", flags); 755 } 756 757 aprint_debug("%s channel %d: timeout sending FIS\n", 758 AHCINAME(sc), chp->ch_channel); 759 return TIMEOUT; 760 } 761 762 static int 763 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 764 uint32_t *sigp, uint8_t c_slot) 765 { 766 struct ahci_channel *achp = (struct ahci_channel *)chp; 767 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 768 struct ahci_cmd_tbl *cmd_tbl; 769 struct ahci_cmd_header *cmd_h; 770 int i; 771 uint32_t sig; 772 773 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 774 ata_channel_lock_owned(chp); 775 776 again: 777 /* clear port interrupt register */ 778 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 779 /* clear SErrors and start operations */ 780 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 781 /* 782 * issue a command list override to clear BSY. 783 * This is needed if there's a PMP with no drive 784 * on port 0 785 */ 786 ahci_channel_start(sc, chp, flags, 1); 787 } else { 788 ahci_channel_start(sc, chp, flags, 0); 789 } 790 if (drive > 0) { 791 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 792 } 793 794 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 795 goto skip_reset; 796 797 /* polled command, assume interrupts are disabled */ 798 799 cmd_h = &achp->ahcic_cmdh[c_slot]; 800 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 801 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 802 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 803 cmd_h->cmdh_prdbc = 0; 804 memset(cmd_tbl->cmdt_cfis, 0, 64); 805 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 806 cmd_tbl->cmdt_cfis[rhd_c] = drive; 807 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 808 switch(ahci_exec_fis(chp, 100, flags, c_slot)) { 809 case ERR_DF: 810 case TIMEOUT: 811 aprint_error("%s channel %d: setting WDCTL_RST failed " 812 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 813 if (sigp) 814 *sigp = 0xffffffff; 815 goto end; 816 default: 817 break; 818 } 819 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 820 (drive << AHCI_CMDH_F_PMP_SHIFT)); 821 cmd_h->cmdh_prdbc = 0; 822 memset(cmd_tbl->cmdt_cfis, 0, 64); 823 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 824 cmd_tbl->cmdt_cfis[rhd_c] = drive; 825 cmd_tbl->cmdt_cfis[rhd_control] = 0; 826 switch(ahci_exec_fis(chp, 310, flags, c_slot)) { 827 case ERR_DF: 828 case TIMEOUT: 829 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 && 830 drive == PMP_PORT_CTL) { 831 /* 832 * some controllers fails to reset when 833 * targeting a PMP but a single drive is attached. 834 * try again with port 0 835 */ 836 drive = 0; 837 ahci_channel_stop(sc, chp, flags); 838 goto again; 839 } 840 aprint_error("%s channel %d: clearing WDCTL_RST failed " 841 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 842 if (sigp) 843 *sigp = 0xffffffff; 844 goto end; 845 default: 846 break; 847 } 848 849 skip_reset: 850 /* 851 * wait 31s for BSY to clear 852 * This should not be needed, but some controllers clear the 853 * command slot before receiving the D2H FIS ... 854 */ 855 for (i = 0; i < AHCI_RST_WAIT; i++) { 856 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 857 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 858 break; 859 ata_delay(chp, 10, "ahcid2h", flags); 860 } 861 if (i == AHCI_RST_WAIT) { 862 aprint_error("%s: BSY never cleared, TD 0x%x\n", 863 AHCINAME(sc), sig); 864 if (sigp) 865 *sigp = 0xffffffff; 866 goto end; 867 } 868 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 869 DEBUG_PROBE); 870 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 871 if (sigp) 872 *sigp = sig; 873 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 874 AHCINAME(sc), chp->ch_channel, sig, 875 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 876 end: 877 ahci_channel_stop(sc, chp, flags); 878 ata_delay(chp, 500, "ahcirst", flags); 879 /* clear port interrupt register */ 880 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 881 ahci_channel_start(sc, chp, flags, 882 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 883 return 0; 884 } 885 886 static void 887 ahci_reset_channel(struct ata_channel *chp, int flags) 888 { 889 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 890 struct ahci_channel *achp = (struct ahci_channel *)chp; 891 int i, tfd; 892 893 ata_channel_lock_owned(chp); 894 895 ahci_channel_stop(sc, chp, flags); 896 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 897 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 898 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 899 /* XXX and then ? */ 900 } 901 ata_kill_active(chp, KILL_RESET, flags); 902 ata_delay(chp, 500, "ahcirst", flags); 903 /* clear port interrupt register */ 904 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 905 /* clear SErrors and start operations */ 906 ahci_channel_start(sc, chp, flags, 907 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 908 /* wait 31s for BSY to clear */ 909 for (i = 0; i <AHCI_RST_WAIT; i++) { 910 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 911 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 912 break; 913 ata_delay(chp, 10, "ahcid2h", flags); 914 } 915 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 916 aprint_error("%s: BSY never cleared, TD 0x%x\n", 917 AHCINAME(sc), tfd); 918 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 919 DEBUG_PROBE); 920 /* clear port interrupt register */ 921 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 922 923 return; 924 } 925 926 static int 927 ahci_ata_addref(struct ata_drive_datas *drvp) 928 { 929 return 0; 930 } 931 932 static void 933 ahci_ata_delref(struct ata_drive_datas *drvp) 934 { 935 return; 936 } 937 938 static void 939 ahci_killpending(struct ata_drive_datas *drvp) 940 { 941 return; 942 } 943 944 static void 945 ahci_probe_drive(struct ata_channel *chp) 946 { 947 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 948 struct ahci_channel *achp = (struct ahci_channel *)chp; 949 uint32_t sig; 950 uint8_t c_slot; 951 952 ata_channel_lock(chp); 953 954 /* get a slot for running the command on */ 955 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 956 aprint_error_dev(sc->sc_atac.atac_dev, 957 "%s: failed to get xfer port %d\n", 958 __func__, chp->ch_channel); 959 ata_channel_unlock(chp); 960 return; 961 } 962 963 /* bring interface up, accept FISs, power up and spin up device */ 964 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 965 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 966 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 967 /* reset the PHY and bring online */ 968 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 969 achp->ahcic_sstatus, AT_WAIT)) { 970 case SStatus_DET_DEV: 971 ata_delay(chp, 500, "ahcidv", AT_WAIT); 972 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 973 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig, 974 c_slot); 975 } else { 976 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 977 } 978 sata_interpret_sig(chp, 0, sig); 979 /* if we have a PMP attached, inform the controller */ 980 if (chp->ch_ndrives > PMP_PORT_CTL && 981 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 982 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 983 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 984 AHCI_P_CMD_PMA); 985 } 986 /* clear port interrupt register */ 987 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 988 989 /* and enable interrupts */ 990 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 991 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 992 AHCI_P_IX_IFS | 993 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 994 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 995 /* wait 500ms before actually starting operations */ 996 ata_delay(chp, 500, "ahciprb", AT_WAIT); 997 break; 998 999 default: 1000 break; 1001 } 1002 1003 ata_queue_free_slot(chp, c_slot); 1004 1005 ata_channel_unlock(chp); 1006 } 1007 1008 static void 1009 ahci_setup_channel(struct ata_channel *chp) 1010 { 1011 return; 1012 } 1013 1014 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1015 .c_start = ahci_cmd_start, 1016 .c_poll = ahci_cmd_poll, 1017 .c_abort = ahci_cmd_abort, 1018 .c_intr = ahci_cmd_complete, 1019 .c_kill_xfer = ahci_cmd_kill_xfer, 1020 }; 1021 1022 static int 1023 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1024 { 1025 struct ata_channel *chp = drvp->chnl_softc; 1026 struct ata_command *ata_c = &xfer->c_ata_c; 1027 int ret; 1028 int s; 1029 1030 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1031 chp->ch_channel, 1032 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1033 DEBUG_XFERS); 1034 if (ata_c->flags & AT_POLL) 1035 xfer->c_flags |= C_POLL; 1036 if (ata_c->flags & AT_WAIT) 1037 xfer->c_flags |= C_WAIT; 1038 xfer->c_drive = drvp->drive; 1039 xfer->c_databuf = ata_c->data; 1040 xfer->c_bcount = ata_c->bcount; 1041 xfer->ops = &ahci_cmd_xfer_ops; 1042 s = splbio(); 1043 ata_exec_xfer(chp, xfer); 1044 #ifdef DIAGNOSTIC 1045 if ((ata_c->flags & AT_POLL) != 0 && 1046 (ata_c->flags & AT_DONE) == 0) 1047 panic("ahci_exec_command: polled command not done"); 1048 #endif 1049 if (ata_c->flags & AT_DONE) { 1050 ret = ATACMD_COMPLETE; 1051 } else { 1052 if (ata_c->flags & AT_WAIT) { 1053 ata_wait_cmd(chp, xfer); 1054 ret = ATACMD_COMPLETE; 1055 } else { 1056 ret = ATACMD_QUEUED; 1057 } 1058 } 1059 splx(s); 1060 return ret; 1061 } 1062 1063 static int 1064 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1065 { 1066 struct ahci_softc *sc = AHCI_CH2SC(chp); 1067 struct ahci_channel *achp = (struct ahci_channel *)chp; 1068 struct ata_command *ata_c = &xfer->c_ata_c; 1069 int slot = xfer->c_slot; 1070 struct ahci_cmd_tbl *cmd_tbl; 1071 struct ahci_cmd_header *cmd_h; 1072 1073 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1074 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1075 ata_c->timeout, slot), 1076 DEBUG_XFERS); 1077 1078 ata_channel_lock_owned(chp); 1079 1080 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1081 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1082 cmd_tbl), DEBUG_XFERS); 1083 1084 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1085 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1086 1087 cmd_h = &achp->ahcic_cmdh[slot]; 1088 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1089 chp->ch_channel, cmd_h), DEBUG_XFERS); 1090 if (ahci_dma_setup(chp, slot, 1091 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1092 ata_c->data : NULL, 1093 ata_c->bcount, 1094 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1095 ata_c->flags |= AT_DF; 1096 return ATASTART_ABORT; 1097 } 1098 cmd_h->cmdh_flags = htole16( 1099 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1100 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1101 cmd_h->cmdh_prdbc = 0; 1102 AHCI_CMDH_SYNC(sc, achp, slot, 1103 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1104 1105 if (ata_c->flags & AT_POLL) { 1106 /* polled command, disable interrupts */ 1107 AHCI_WRITE(sc, AHCI_GHC, 1108 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1109 } 1110 /* start command */ 1111 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1112 1113 if ((ata_c->flags & AT_POLL) == 0) { 1114 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1115 ata_timeout, chp); 1116 return ATASTART_STARTED; 1117 } else 1118 return ATASTART_POLL; 1119 } 1120 1121 static void 1122 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1123 { 1124 struct ahci_softc *sc = AHCI_CH2SC(chp); 1125 struct ahci_channel *achp = (struct ahci_channel *)chp; 1126 1127 ata_channel_lock(chp); 1128 1129 /* 1130 * Polled command. 1131 */ 1132 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1133 if (xfer->c_ata_c.flags & AT_DONE) 1134 break; 1135 ata_channel_unlock(chp); 1136 ahci_intr_port(sc, achp); 1137 ata_channel_lock(chp); 1138 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1139 } 1140 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1141 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1142 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1143 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1144 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1145 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1146 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1147 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1148 DEBUG_XFERS); 1149 1150 ata_channel_unlock(chp); 1151 1152 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1153 xfer->c_ata_c.flags |= AT_TIMEOU; 1154 xfer->ops->c_intr(chp, xfer, 0); 1155 } 1156 /* reenable interrupts */ 1157 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1158 } 1159 1160 static void 1161 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1162 { 1163 ahci_cmd_complete(chp, xfer, 0); 1164 } 1165 1166 static void 1167 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1168 { 1169 struct ata_command *ata_c = &xfer->c_ata_c; 1170 bool deactivate = true; 1171 1172 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 1173 DEBUG_FUNCS); 1174 1175 switch (reason) { 1176 case KILL_GONE_INACTIVE: 1177 deactivate = false; 1178 /* FALLTHROUGH */ 1179 case KILL_GONE: 1180 ata_c->flags |= AT_GONE; 1181 break; 1182 case KILL_RESET: 1183 ata_c->flags |= AT_RESET; 1184 break; 1185 case KILL_REQUEUE: 1186 panic("%s: not supposed to be requeued\n", __func__); 1187 break; 1188 default: 1189 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1190 panic("ahci_cmd_kill_xfer"); 1191 } 1192 1193 ahci_cmd_done_end(chp, xfer); 1194 1195 if (deactivate) 1196 ata_deactivate_xfer(chp, xfer); 1197 } 1198 1199 static int 1200 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1201 { 1202 struct ata_command *ata_c = &xfer->c_ata_c; 1203 struct ahci_channel *achp = (struct ahci_channel *)chp; 1204 1205 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 1206 chp->ch_channel, 1207 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1208 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1209 DEBUG_FUNCS); 1210 1211 if (ata_waitdrain_xfer_check(chp, xfer)) 1212 return 0; 1213 1214 if (xfer->c_flags & C_TIMEOU) { 1215 ata_c->flags |= AT_TIMEOU; 1216 } 1217 1218 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1219 ata_c->flags |= AT_TIMEOU; 1220 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1221 ata_c->r_error = AHCI_TFD_ERR(tfd); 1222 ata_c->flags |= AT_ERROR; 1223 } 1224 1225 if (ata_c->flags & AT_READREG) 1226 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1227 1228 ahci_cmd_done(chp, xfer); 1229 1230 ata_deactivate_xfer(chp, xfer); 1231 1232 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1233 atastart(chp); 1234 1235 return 0; 1236 } 1237 1238 static void 1239 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1240 { 1241 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1242 struct ahci_channel *achp = (struct ahci_channel *)chp; 1243 struct ata_command *ata_c = &xfer->c_ata_c; 1244 uint16_t *idwordbuf; 1245 int i; 1246 1247 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d flags %#x/%#x\n", 1248 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1249 1250 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1251 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1252 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1253 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1254 BUS_DMASYNC_POSTWRITE); 1255 bus_dmamap_unload(sc->sc_dmat, map); 1256 } 1257 1258 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1259 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1260 1261 /* ata(4) expects IDENTIFY data to be in host endianess */ 1262 if (ata_c->r_command == WDCC_IDENTIFY || 1263 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1264 idwordbuf = xfer->c_databuf; 1265 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1266 idwordbuf[i] = le16toh(idwordbuf[i]); 1267 } 1268 } 1269 1270 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1271 ata_c->flags |= AT_XFDONE; 1272 1273 ahci_cmd_done_end(chp, xfer); 1274 } 1275 1276 static void 1277 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1278 { 1279 struct ata_command *ata_c = &xfer->c_ata_c; 1280 1281 ata_c->flags |= AT_DONE; 1282 } 1283 1284 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1285 .c_start = ahci_bio_start, 1286 .c_poll = ahci_bio_poll, 1287 .c_abort = ahci_bio_abort, 1288 .c_intr = ahci_bio_complete, 1289 .c_kill_xfer = ahci_bio_kill_xfer, 1290 }; 1291 1292 static int 1293 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1294 { 1295 struct ata_channel *chp = drvp->chnl_softc; 1296 struct ata_bio *ata_bio = &xfer->c_bio; 1297 1298 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1299 chp->ch_channel, 1300 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1301 DEBUG_XFERS); 1302 if (ata_bio->flags & ATA_POLL) 1303 xfer->c_flags |= C_POLL; 1304 xfer->c_drive = drvp->drive; 1305 xfer->c_databuf = ata_bio->databuf; 1306 xfer->c_bcount = ata_bio->bcount; 1307 xfer->ops = &ahci_bio_xfer_ops; 1308 ata_exec_xfer(chp, xfer); 1309 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1310 } 1311 1312 static int 1313 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1314 { 1315 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1316 struct ahci_channel *achp = (struct ahci_channel *)chp; 1317 struct ata_bio *ata_bio = &xfer->c_bio; 1318 struct ahci_cmd_tbl *cmd_tbl; 1319 struct ahci_cmd_header *cmd_h; 1320 1321 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1322 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1323 1324 ata_channel_lock_owned(chp); 1325 1326 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1327 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1328 cmd_tbl), DEBUG_XFERS); 1329 1330 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1331 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1332 1333 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1334 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1335 chp->ch_channel, cmd_h), DEBUG_XFERS); 1336 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1337 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1338 ata_bio->error = ERR_DMA; 1339 ata_bio->r_error = 0; 1340 return ATASTART_ABORT; 1341 } 1342 cmd_h->cmdh_flags = htole16( 1343 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1344 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1345 cmd_h->cmdh_prdbc = 0; 1346 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1347 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1348 1349 if (xfer->c_flags & C_POLL) { 1350 /* polled command, disable interrupts */ 1351 AHCI_WRITE(sc, AHCI_GHC, 1352 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1353 } 1354 if (xfer->c_flags & C_NCQ) 1355 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1356 /* start command */ 1357 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1358 1359 if ((xfer->c_flags & C_POLL) == 0) { 1360 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1361 ata_timeout, chp); 1362 return ATASTART_STARTED; 1363 } else 1364 return ATASTART_POLL; 1365 } 1366 1367 static void 1368 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1369 { 1370 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1371 struct ahci_channel *achp = (struct ahci_channel *)chp; 1372 1373 /* 1374 * Polled command. 1375 */ 1376 for (int i = 0; i < ATA_DELAY * 10; i++) { 1377 if (xfer->c_bio.flags & ATA_ITSDONE) 1378 break; 1379 ahci_intr_port(sc, achp); 1380 delay(100); 1381 } 1382 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1383 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1384 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1385 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1386 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1387 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1388 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1389 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1390 DEBUG_XFERS); 1391 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1392 xfer->c_bio.error = TIMEOUT; 1393 xfer->ops->c_intr(chp, xfer, 0); 1394 } 1395 /* reenable interrupts */ 1396 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1397 } 1398 1399 static void 1400 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1401 { 1402 ahci_bio_complete(chp, xfer, 0); 1403 } 1404 1405 static void 1406 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1407 { 1408 int drive = xfer->c_drive; 1409 struct ata_bio *ata_bio = &xfer->c_bio; 1410 bool deactivate = true; 1411 1412 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1413 DEBUG_FUNCS); 1414 1415 ata_bio->flags |= ATA_ITSDONE; 1416 switch (reason) { 1417 case KILL_GONE_INACTIVE: 1418 deactivate = false; 1419 /* FALLTHROUGH */ 1420 case KILL_GONE: 1421 ata_bio->error = ERR_NODEV; 1422 break; 1423 case KILL_RESET: 1424 ata_bio->error = ERR_RESET; 1425 break; 1426 case KILL_REQUEUE: 1427 ata_bio->error = REQUEUE; 1428 break; 1429 default: 1430 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1431 panic("ahci_bio_kill_xfer"); 1432 } 1433 ata_bio->r_error = WDCE_ABRT; 1434 1435 if (deactivate) 1436 ata_deactivate_xfer(chp, xfer); 1437 1438 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1439 } 1440 1441 static int 1442 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1443 { 1444 struct ata_bio *ata_bio = &xfer->c_bio; 1445 int drive = xfer->c_drive; 1446 struct ahci_channel *achp = (struct ahci_channel *)chp; 1447 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1448 1449 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1450 DEBUG_FUNCS); 1451 1452 if (ata_waitdrain_xfer_check(chp, xfer)) 1453 return 0; 1454 1455 if (xfer->c_flags & C_TIMEOU) { 1456 ata_bio->error = TIMEOUT; 1457 } 1458 1459 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1460 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1461 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1462 BUS_DMASYNC_POSTWRITE); 1463 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1464 1465 ata_bio->flags |= ATA_ITSDONE; 1466 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1467 ata_bio->error = ERR_DF; 1468 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1469 ata_bio->error = ERROR; 1470 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1471 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1472 ata_bio->flags |= ATA_CORR; 1473 1474 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1475 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1476 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1477 ata_bio->bcount), DEBUG_XFERS); 1478 /* 1479 * If it was a write, complete data buffer may have been transfered 1480 * before error detection; in this case don't use cmdh_prdbc 1481 * as it won't reflect what was written to media. Assume nothing 1482 * was transfered and leave bcount as-is. 1483 * For queued commands, PRD Byte Count should not be used, and is 1484 * not required to be valid; in that case underflow is always illegal. 1485 */ 1486 if ((xfer->c_flags & C_NCQ) != 0) { 1487 if (ata_bio->error == NOERROR) 1488 ata_bio->bcount = 0; 1489 } else { 1490 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1491 ata_bio->bcount -= 1492 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1493 } 1494 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1495 1496 ata_deactivate_xfer(chp, xfer); 1497 1498 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1499 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1500 atastart(chp); 1501 return 0; 1502 } 1503 1504 static void 1505 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1506 { 1507 int i; 1508 /* stop channel */ 1509 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1510 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1511 /* wait 1s for channel to stop */ 1512 for (i = 0; i <100; i++) { 1513 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1514 == 0) 1515 break; 1516 ata_delay(chp, 10, "ahcistop", flags); 1517 } 1518 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1519 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1520 /* XXX controller reset ? */ 1521 return; 1522 } 1523 1524 if (sc->sc_channel_stop) 1525 sc->sc_channel_stop(sc, chp); 1526 } 1527 1528 static void 1529 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1530 int flags, int clo) 1531 { 1532 int i; 1533 uint32_t p_cmd; 1534 /* clear error */ 1535 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1536 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1537 1538 if (clo) { 1539 /* issue command list override */ 1540 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1541 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1542 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1543 /* wait 1s for AHCI_CAP_CLO to clear */ 1544 for (i = 0; i <100; i++) { 1545 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1546 AHCI_P_CMD_CLO) == 0) 1547 break; 1548 ata_delay(chp, 10, "ahciclo", flags); 1549 } 1550 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1551 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1552 /* XXX controller reset ? */ 1553 return; 1554 } 1555 } 1556 1557 if (sc->sc_channel_start) 1558 sc->sc_channel_start(sc, chp); 1559 1560 /* and start controller */ 1561 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1562 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1563 if (chp->ch_ndrives > PMP_PORT_CTL && 1564 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1565 p_cmd |= AHCI_P_CMD_PMA; 1566 } 1567 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1568 } 1569 1570 /* Recover channel after command failure */ 1571 static void 1572 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1573 { 1574 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1575 int drive = ATACH_NODRIVE; 1576 bool reset = false; 1577 1578 ata_channel_lock_owned(chp); 1579 1580 /* 1581 * Read FBS to get the drive which caused the error, if PM is in use. 1582 * According to AHCI 1.3 spec, this register is available regardless 1583 * if FIS-based switching (FBSS) feature is supported, or disabled. 1584 * If FIS-based switching is not in use, it merely maintains single 1585 * pair of DRQ/BSY state, but it is enough since in that case we 1586 * never issue commands for more than one device at the time anyway. 1587 * XXX untested 1588 */ 1589 if (chp->ch_ndrives > PMP_PORT_CTL) { 1590 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1591 if (fbs & AHCI_P_FBS_SDE) { 1592 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1593 1594 /* 1595 * Tell HBA to reset PM port X (value in DWE) state, 1596 * and resume processing commands for other ports. 1597 */ 1598 fbs |= AHCI_P_FBS_DEC; 1599 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1600 for (int i = 0; i < 1000; i++) { 1601 fbs = AHCI_READ(sc, 1602 AHCI_P_FBS(chp->ch_channel)); 1603 if ((fbs & AHCI_P_FBS_DEC) == 0) 1604 break; 1605 DELAY(1000); 1606 } 1607 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1608 /* follow non-device specific recovery */ 1609 drive = ATACH_NODRIVE; 1610 reset = true; 1611 } 1612 } else { 1613 /* not device specific, reset channel */ 1614 drive = ATACH_NODRIVE; 1615 reset = true; 1616 } 1617 } else 1618 drive = 0; 1619 1620 /* 1621 * If BSY or DRQ bits are set, must execute COMRESET to return 1622 * device to idle state. If drive is idle, it's enough to just 1623 * reset CMD.ST, it's not necessary to do software reset. 1624 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1625 * to unblock device processing if COMRESET was not done. 1626 */ 1627 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1628 ahci_reset_channel(chp, flags); 1629 goto out; 1630 } 1631 1632 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1633 ahci_channel_stop(sc, chp, flags); 1634 ahci_channel_start(sc, chp, flags, 1635 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1636 1637 ata_recovery_resume(chp, drive, tfd, flags); 1638 1639 out: 1640 /* Drive unblocked, back to normal operation */ 1641 return; 1642 } 1643 1644 static int 1645 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1646 size_t count, int op) 1647 { 1648 int error, seg; 1649 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1650 struct ahci_channel *achp = (struct ahci_channel *)chp; 1651 struct ahci_cmd_tbl *cmd_tbl; 1652 struct ahci_cmd_header *cmd_h; 1653 1654 cmd_h = &achp->ahcic_cmdh[slot]; 1655 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1656 1657 if (data == NULL) { 1658 cmd_h->cmdh_prdtl = 0; 1659 goto end; 1660 } 1661 1662 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1663 data, count, NULL, 1664 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1665 if (error) { 1666 printf("%s port %d: failed to load xfer: %d\n", 1667 AHCINAME(sc), chp->ch_channel, error); 1668 return error; 1669 } 1670 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1671 achp->ahcic_datad[slot]->dm_mapsize, 1672 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1673 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1674 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1675 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1676 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1677 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1678 } 1679 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1680 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1681 end: 1682 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1683 return 0; 1684 } 1685 1686 #if NATAPIBUS > 0 1687 static void 1688 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1689 { 1690 struct ata_channel *chp = ata_sc->sc_chan; 1691 struct atac_softc *atac = chp->ch_atac; 1692 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1693 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1694 /* 1695 * Fill in the scsipi_adapter. 1696 */ 1697 adapt->adapt_dev = atac->atac_dev; 1698 adapt->adapt_nchannels = atac->atac_nchannels; 1699 adapt->adapt_request = ahci_atapi_scsipi_request; 1700 adapt->adapt_minphys = ahci_atapi_minphys; 1701 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1702 1703 /* 1704 * Fill in the scsipi_channel. 1705 */ 1706 memset(chan, 0, sizeof(*chan)); 1707 chan->chan_adapter = adapt; 1708 chan->chan_bustype = &ahci_atapi_bustype; 1709 chan->chan_channel = chp->ch_channel; 1710 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1711 chan->chan_openings = 1; 1712 chan->chan_max_periph = 1; 1713 chan->chan_ntargets = 1; 1714 chan->chan_nluns = 1; 1715 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1716 atapiprint); 1717 } 1718 1719 static void 1720 ahci_atapi_minphys(struct buf *bp) 1721 { 1722 if (bp->b_bcount > MAXPHYS) 1723 bp->b_bcount = MAXPHYS; 1724 minphys(bp); 1725 } 1726 1727 /* 1728 * Kill off all pending xfers for a periph. 1729 * 1730 * Must be called at splbio(). 1731 */ 1732 static void 1733 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1734 { 1735 struct atac_softc *atac = 1736 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1737 struct ata_channel *chp = 1738 atac->atac_channels[periph->periph_channel->chan_channel]; 1739 1740 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1741 } 1742 1743 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1744 .c_start = ahci_atapi_start, 1745 .c_poll = ahci_atapi_poll, 1746 .c_abort = ahci_atapi_abort, 1747 .c_intr = ahci_atapi_complete, 1748 .c_kill_xfer = ahci_atapi_kill_xfer, 1749 }; 1750 1751 static void 1752 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1753 scsipi_adapter_req_t req, void *arg) 1754 { 1755 struct scsipi_adapter *adapt = chan->chan_adapter; 1756 struct scsipi_periph *periph; 1757 struct scsipi_xfer *sc_xfer; 1758 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1759 struct atac_softc *atac = &sc->sc_atac; 1760 struct ata_xfer *xfer; 1761 int channel = chan->chan_channel; 1762 int drive, s; 1763 1764 switch (req) { 1765 case ADAPTER_REQ_RUN_XFER: 1766 sc_xfer = arg; 1767 periph = sc_xfer->xs_periph; 1768 drive = periph->periph_target; 1769 if (!device_is_active(atac->atac_dev)) { 1770 sc_xfer->error = XS_DRIVER_STUFFUP; 1771 scsipi_done(sc_xfer); 1772 return; 1773 } 1774 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1775 if (xfer == NULL) { 1776 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1777 scsipi_done(sc_xfer); 1778 return; 1779 } 1780 1781 if (sc_xfer->xs_control & XS_CTL_POLL) 1782 xfer->c_flags |= C_POLL; 1783 xfer->c_drive = drive; 1784 xfer->c_flags |= C_ATAPI; 1785 xfer->c_databuf = sc_xfer->data; 1786 xfer->c_bcount = sc_xfer->datalen; 1787 xfer->ops = &ahci_atapi_xfer_ops; 1788 xfer->c_scsipi = sc_xfer; 1789 xfer->c_atapi.c_dscpoll = 0; 1790 s = splbio(); 1791 ata_exec_xfer(atac->atac_channels[channel], xfer); 1792 #ifdef DIAGNOSTIC 1793 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1794 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1795 panic("ahci_atapi_scsipi_request: polled command " 1796 "not done"); 1797 #endif 1798 splx(s); 1799 return; 1800 default: 1801 /* Not supported, nothing to do. */ 1802 ; 1803 } 1804 } 1805 1806 static int 1807 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1808 { 1809 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1810 struct ahci_channel *achp = (struct ahci_channel *)chp; 1811 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1812 struct ahci_cmd_tbl *cmd_tbl; 1813 struct ahci_cmd_header *cmd_h; 1814 1815 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1816 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1817 1818 ata_channel_lock_owned(chp); 1819 1820 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1821 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1822 cmd_tbl), DEBUG_XFERS); 1823 1824 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1825 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1826 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1827 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1828 1829 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1830 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1831 chp->ch_channel, cmd_h), DEBUG_XFERS); 1832 if (ahci_dma_setup(chp, xfer->c_slot, 1833 sc_xfer->datalen ? sc_xfer->data : NULL, 1834 sc_xfer->datalen, 1835 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1836 BUS_DMA_READ : BUS_DMA_WRITE)) { 1837 sc_xfer->error = XS_DRIVER_STUFFUP; 1838 return ATASTART_ABORT; 1839 } 1840 cmd_h->cmdh_flags = htole16( 1841 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1842 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1843 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1844 cmd_h->cmdh_prdbc = 0; 1845 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1847 1848 if (xfer->c_flags & C_POLL) { 1849 /* polled command, disable interrupts */ 1850 AHCI_WRITE(sc, AHCI_GHC, 1851 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1852 } 1853 /* start command */ 1854 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1855 1856 if ((xfer->c_flags & C_POLL) == 0) { 1857 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1858 ata_timeout, chp); 1859 return ATASTART_STARTED; 1860 } else 1861 return ATASTART_POLL; 1862 } 1863 1864 static void 1865 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1866 { 1867 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1868 struct ahci_channel *achp = (struct ahci_channel *)chp; 1869 1870 /* 1871 * Polled command. 1872 */ 1873 for (int i = 0; i < ATA_DELAY / 10; i++) { 1874 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1875 break; 1876 ahci_intr_port(sc, achp); 1877 delay(10000); 1878 } 1879 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1880 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1881 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1882 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1883 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1884 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1885 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1886 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1887 DEBUG_XFERS); 1888 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1889 xfer->c_scsipi->error = XS_TIMEOUT; 1890 xfer->ops->c_intr(chp, xfer, 0); 1891 } 1892 /* reenable interrupts */ 1893 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1894 } 1895 1896 static void 1897 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1898 { 1899 ahci_atapi_complete(chp, xfer, 0); 1900 } 1901 1902 static int 1903 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1904 { 1905 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1906 struct ahci_channel *achp = (struct ahci_channel *)chp; 1907 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1908 1909 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1910 DEBUG_FUNCS); 1911 1912 if (ata_waitdrain_xfer_check(chp, xfer)) 1913 return 0; 1914 1915 if (xfer->c_flags & C_TIMEOU) { 1916 sc_xfer->error = XS_TIMEOUT; 1917 } 1918 1919 if (xfer->c_bcount > 0) { 1920 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1921 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1922 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1923 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1924 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1925 } 1926 1927 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1928 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1929 sc_xfer->resid = sc_xfer->datalen; 1930 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1931 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1932 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1933 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1934 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1935 sc_xfer->resid == sc_xfer->datalen)) { 1936 sc_xfer->error = XS_SHORTSENSE; 1937 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 1938 if ((sc_xfer->xs_periph->periph_quirks & 1939 PQUIRK_NOSENSE) == 0) { 1940 /* ask scsipi to send a REQUEST_SENSE */ 1941 sc_xfer->error = XS_BUSY; 1942 sc_xfer->status = SCSI_CHECK; 1943 } 1944 } 1945 1946 ata_deactivate_xfer(chp, xfer); 1947 1948 ata_free_xfer(chp, xfer); 1949 scsipi_done(sc_xfer); 1950 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1951 atastart(chp); 1952 return 0; 1953 } 1954 1955 static void 1956 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1957 { 1958 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1959 bool deactivate = true; 1960 1961 /* remove this command from xfer queue */ 1962 switch (reason) { 1963 case KILL_GONE_INACTIVE: 1964 deactivate = false; 1965 /* FALLTHROUGH */ 1966 case KILL_GONE: 1967 sc_xfer->error = XS_DRIVER_STUFFUP; 1968 break; 1969 case KILL_RESET: 1970 sc_xfer->error = XS_RESET; 1971 break; 1972 case KILL_REQUEUE: 1973 sc_xfer->error = XS_REQUEUE; 1974 break; 1975 default: 1976 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1977 panic("ahci_ata_atapi_kill_xfer"); 1978 } 1979 1980 if (deactivate) 1981 ata_deactivate_xfer(chp, xfer); 1982 1983 ata_free_xfer(chp, xfer); 1984 scsipi_done(sc_xfer); 1985 } 1986 1987 static void 1988 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1989 { 1990 struct scsipi_channel *chan = sc->sc_channel; 1991 struct scsipi_periph *periph; 1992 struct ataparams ids; 1993 struct ataparams *id = &ids; 1994 struct ahci_softc *ahcic = 1995 device_private(chan->chan_adapter->adapt_dev); 1996 struct atac_softc *atac = &ahcic->sc_atac; 1997 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1998 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1999 struct scsipibus_attach_args sa; 2000 char serial_number[21], model[41], firmware_revision[9]; 2001 int s; 2002 2003 /* skip if already attached */ 2004 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2005 return; 2006 2007 /* if no ATAPI device detected at attach time, skip */ 2008 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2009 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2010 "not present\n", target), DEBUG_PROBE); 2011 return; 2012 } 2013 2014 /* Some ATAPI devices need a bit more time after software reset. */ 2015 delay(5000); 2016 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2017 #ifdef ATAPI_DEBUG_PROBE 2018 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2019 AHCINAME(ahcic), target, 2020 id->atap_config & ATAPI_CFG_CMD_MASK, 2021 id->atap_config & ATAPI_CFG_DRQ_MASK); 2022 #endif 2023 periph = scsipi_alloc_periph(M_NOWAIT); 2024 if (periph == NULL) { 2025 aprint_error_dev(sc->sc_dev, 2026 "unable to allocate periph for drive %d\n", 2027 target); 2028 return; 2029 } 2030 periph->periph_dev = NULL; 2031 periph->periph_channel = chan; 2032 periph->periph_switch = &atapi_probe_periphsw; 2033 periph->periph_target = target; 2034 periph->periph_lun = 0; 2035 periph->periph_quirks = PQUIRK_ONLYBIG; 2036 2037 #ifdef SCSIPI_DEBUG 2038 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2039 SCSIPI_DEBUG_TARGET == target) 2040 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2041 #endif 2042 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2043 if (id->atap_config & ATAPI_CFG_REMOV) 2044 periph->periph_flags |= PERIPH_REMOVABLE; 2045 if (periph->periph_type == T_SEQUENTIAL) { 2046 s = splbio(); 2047 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2048 splx(s); 2049 } 2050 2051 sa.sa_periph = periph; 2052 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2053 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2054 T_REMOV : T_FIXED; 2055 strnvisx(model, sizeof(model), id->atap_model, 40, 2056 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2057 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2058 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2059 strnvisx(firmware_revision, sizeof(firmware_revision), 2060 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2061 sa.sa_inqbuf.vendor = model; 2062 sa.sa_inqbuf.product = serial_number; 2063 sa.sa_inqbuf.revision = firmware_revision; 2064 2065 /* 2066 * Determine the operating mode capabilities of the device. 2067 */ 2068 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2069 periph->periph_cap |= PERIPH_CAP_CMD16; 2070 /* XXX This is gross. */ 2071 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2072 2073 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2074 2075 if (drvp->drv_softc) 2076 ata_probe_caps(drvp); 2077 else { 2078 s = splbio(); 2079 drvp->drive_type = ATA_DRIVET_NONE; 2080 splx(s); 2081 } 2082 } else { 2083 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2084 "failed for drive %s:%d:%d\n", 2085 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2086 s = splbio(); 2087 drvp->drive_type = ATA_DRIVET_NONE; 2088 splx(s); 2089 } 2090 } 2091 #endif /* NATAPIBUS */ 2092
Indexes created Wed Sep 24 05:09:52 GMT 2025