ahcisata_core.c revision 1.68
1 /* $NetBSD: ahcisata_core.c,v 1.68 2018/11/19 21:52:24 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.68 2018/11/19 21:52:24 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 129 static void ahci_setup_port(struct ahci_softc *sc, int i); 130 131 static void 132 ahci_enable(struct ahci_softc *sc) 133 { 134 uint32_t ghc; 135 136 ghc = AHCI_READ(sc, AHCI_GHC); 137 if (!(ghc & AHCI_GHC_AE)) { 138 ghc |= AHCI_GHC_AE; 139 AHCI_WRITE(sc, AHCI_GHC, ghc); 140 } 141 } 142 143 static int 144 ahci_reset(struct ahci_softc *sc) 145 { 146 int i; 147 148 /* reset controller */ 149 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 150 /* wait up to 1s for reset to complete */ 151 for (i = 0; i < 1000; i++) { 152 delay(1000); 153 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 154 break; 155 } 156 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 157 aprint_error("%s: reset failed\n", AHCINAME(sc)); 158 return -1; 159 } 160 /* enable ahci mode */ 161 ahci_enable(sc); 162 163 if (sc->sc_save_init_data) { 164 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 165 if (sc->sc_init_data.cap2) 166 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 167 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 168 } 169 170 return 0; 171 } 172 173 static void 174 ahci_setup_ports(struct ahci_softc *sc) 175 { 176 int i, port; 177 178 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 179 if ((sc->sc_ahci_ports & (1U << i)) == 0) 180 continue; 181 if (port >= sc->sc_atac.atac_nchannels) { 182 aprint_error("%s: more ports than announced\n", 183 AHCINAME(sc)); 184 break; 185 } 186 ahci_setup_port(sc, i); 187 port++; 188 } 189 } 190 191 static void 192 ahci_reprobe_drives(struct ahci_softc *sc) 193 { 194 int i, port; 195 struct ahci_channel *achp; 196 struct ata_channel *chp; 197 198 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 199 if ((sc->sc_ahci_ports & (1U << i)) == 0) 200 continue; 201 if (port >= sc->sc_atac.atac_nchannels) { 202 aprint_error("%s: more ports than announced\n", 203 AHCINAME(sc)); 204 break; 205 } 206 achp = &sc->sc_channels[i]; 207 chp = &achp->ata_channel; 208 209 ahci_probe_drive(chp); 210 port++; 211 } 212 } 213 214 static void 215 ahci_setup_port(struct ahci_softc *sc, int i) 216 { 217 struct ahci_channel *achp; 218 219 achp = &sc->sc_channels[i]; 220 221 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 222 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 223 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 224 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 225 } 226 227 static void 228 ahci_enable_intrs(struct ahci_softc *sc) 229 { 230 231 /* clear interrupts */ 232 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 233 /* enable interrupts */ 234 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 235 } 236 237 void 238 ahci_attach(struct ahci_softc *sc) 239 { 240 uint32_t ahci_rev; 241 int i, j, port; 242 struct ahci_channel *achp; 243 struct ata_channel *chp; 244 int error; 245 int dmasize; 246 char buf[128]; 247 void *cmdhp; 248 void *cmdtblp; 249 250 if (sc->sc_save_init_data) { 251 ahci_enable(sc); 252 253 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 254 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 255 256 ahci_rev = AHCI_READ(sc, AHCI_VS); 257 if (AHCI_VS_MJR(ahci_rev) > 1 || 258 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 259 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 260 } else { 261 sc->sc_init_data.cap2 = 0; 262 } 263 if (sc->sc_init_data.ports == 0) { 264 sc->sc_init_data.ports = sc->sc_ahci_ports; 265 } 266 } 267 268 if (ahci_reset(sc) != 0) 269 return; 270 271 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 272 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 273 aprint_verbose_dev(sc->sc_atac.atac_dev, 274 "ignoring broken port multiplier support\n"); 275 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 276 } 277 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 278 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 279 ahci_rev = AHCI_READ(sc, AHCI_VS); 280 snprintb(buf, sizeof(buf), "\177\020" 281 /* "f\000\005NP\0" */ 282 "b\005SXS\0" 283 "b\006EMS\0" 284 "b\007CCCS\0" 285 /* "f\010\005NCS\0" */ 286 "b\015PSC\0" 287 "b\016SSC\0" 288 "b\017PMD\0" 289 "b\020FBSS\0" 290 "b\021SPM\0" 291 "b\022SAM\0" 292 "b\023SNZO\0" 293 "f\024\003ISS\0" 294 "=\001Gen1\0" 295 "=\002Gen2\0" 296 "=\003Gen3\0" 297 "b\030SCLO\0" 298 "b\031SAL\0" 299 "b\032SALP\0" 300 "b\033SSS\0" 301 "b\034SMPS\0" 302 "b\035SSNTF\0" 303 "b\036SNCQ\0" 304 "b\037S64A\0" 305 "\0", sc->sc_ahci_cap); 306 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 307 ", %d port%s, %d slot%s, CAP %s\n", 308 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 309 sc->sc_atac.atac_nchannels, 310 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 311 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 312 313 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 314 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 315 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 316 sc->sc_atac.atac_pio_cap = 4; 317 sc->sc_atac.atac_dma_cap = 2; 318 sc->sc_atac.atac_udma_cap = 6; 319 sc->sc_atac.atac_channels = sc->sc_chanarray; 320 sc->sc_atac.atac_probe = ahci_probe_drive; 321 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 322 sc->sc_atac.atac_set_modes = ahci_setup_channel; 323 #if NATAPIBUS > 0 324 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 325 #endif 326 327 dmasize = 328 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 329 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 330 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 331 if (error) { 332 aprint_error("%s: unable to allocate command header memory" 333 ", error=%d\n", AHCINAME(sc), error); 334 return; 335 } 336 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 337 sc->sc_cmd_hdr_nseg, dmasize, 338 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 339 if (error) { 340 aprint_error("%s: unable to map command header memory" 341 ", error=%d\n", AHCINAME(sc), error); 342 return; 343 } 344 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 345 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 346 if (error) { 347 aprint_error("%s: unable to create command header map" 348 ", error=%d\n", AHCINAME(sc), error); 349 return; 350 } 351 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 352 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 353 if (error) { 354 aprint_error("%s: unable to load command header map" 355 ", error=%d\n", AHCINAME(sc), error); 356 return; 357 } 358 sc->sc_cmd_hdr = cmdhp; 359 360 ahci_enable_intrs(sc); 361 362 if (sc->sc_ahci_ports == 0) { 363 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 364 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 365 DEBUG_PROBE); 366 } 367 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 368 if ((sc->sc_ahci_ports & (1U << i)) == 0) 369 continue; 370 if (port >= sc->sc_atac.atac_nchannels) { 371 aprint_error("%s: more ports than announced\n", 372 AHCINAME(sc)); 373 break; 374 } 375 achp = &sc->sc_channels[i]; 376 chp = &achp->ata_channel; 377 sc->sc_chanarray[i] = chp; 378 chp->ch_channel = i; 379 chp->ch_atac = &sc->sc_atac; 380 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 381 if (chp->ch_queue == NULL) { 382 aprint_error("%s port %d: can't allocate memory for " 383 "command queue", AHCINAME(sc), i); 384 break; 385 } 386 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 387 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 388 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 389 BUS_DMA_NOWAIT); 390 if (error) { 391 aprint_error("%s: unable to allocate command table " 392 "memory, error=%d\n", AHCINAME(sc), error); 393 break; 394 } 395 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 396 achp->ahcic_cmd_tbl_nseg, dmasize, 397 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 398 if (error) { 399 aprint_error("%s: unable to map command table memory" 400 ", error=%d\n", AHCINAME(sc), error); 401 break; 402 } 403 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 404 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 405 if (error) { 406 aprint_error("%s: unable to create command table map" 407 ", error=%d\n", AHCINAME(sc), error); 408 break; 409 } 410 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 411 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 412 if (error) { 413 aprint_error("%s: unable to load command table map" 414 ", error=%d\n", AHCINAME(sc), error); 415 break; 416 } 417 achp->ahcic_cmdh = (struct ahci_cmd_header *) 418 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 419 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 420 AHCI_CMDH_SIZE * port; 421 achp->ahcic_rfis = (struct ahci_r_fis *) 422 ((char *)cmdhp + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port); 425 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 426 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 427 AHCI_RFIS_SIZE * port; 428 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 429 "rfis %p (0x%" PRIx64 ")\n", i, 430 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 431 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 432 DEBUG_PROBE); 433 434 for (j = 0; j < sc->sc_ncmds; j++) { 435 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 436 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 437 achp->ahcic_bus_cmd_tbl[j] = 438 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 439 AHCI_CMDTBL_SIZE * j; 440 achp->ahcic_cmdh[j].cmdh_cmdtba = 441 htole64(achp->ahcic_bus_cmd_tbl[j]); 442 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 443 achp->ahcic_cmd_tbl[j], 444 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 445 /* The xfer DMA map */ 446 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 447 AHCI_NPRD, 0x400000 /* 4MB */, 0, 448 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 449 &achp->ahcic_datad[j]); 450 if (error) { 451 aprint_error("%s: couldn't alloc xfer DMA map, " 452 "error=%d\n", AHCINAME(sc), error); 453 goto end; 454 } 455 } 456 ahci_setup_port(sc, i); 457 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 458 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 459 aprint_error("%s: couldn't map port %d " 460 "sata_status regs\n", AHCINAME(sc), i); 461 break; 462 } 463 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 464 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 465 aprint_error("%s: couldn't map port %d " 466 "sata_control regs\n", AHCINAME(sc), i); 467 break; 468 } 469 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 470 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 471 aprint_error("%s: couldn't map port %d " 472 "sata_error regs\n", AHCINAME(sc), i); 473 break; 474 } 475 ata_channel_attach(chp); 476 port++; 477 end: 478 continue; 479 } 480 } 481 482 void 483 ahci_childdetached(struct ahci_softc *sc, device_t child) 484 { 485 struct ahci_channel *achp; 486 struct ata_channel *chp; 487 488 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 489 achp = &sc->sc_channels[i]; 490 chp = &achp->ata_channel; 491 492 if ((sc->sc_ahci_ports & (1U << i)) == 0) 493 continue; 494 495 if (child == chp->atabus) 496 chp->atabus = NULL; 497 } 498 } 499 500 int 501 ahci_detach(struct ahci_softc *sc, int flags) 502 { 503 struct atac_softc *atac; 504 struct ahci_channel *achp; 505 struct ata_channel *chp; 506 struct scsipi_adapter *adapt; 507 int i, j, port; 508 int error; 509 510 atac = &sc->sc_atac; 511 adapt = &atac->atac_atapi_adapter._generic; 512 513 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 514 achp = &sc->sc_channels[i]; 515 chp = &achp->ata_channel; 516 517 if ((sc->sc_ahci_ports & (1U << i)) == 0) 518 continue; 519 if (port >= sc->sc_atac.atac_nchannels) { 520 aprint_error("%s: more ports than announced\n", 521 AHCINAME(sc)); 522 break; 523 } 524 525 if (chp->atabus != NULL) { 526 if ((error = config_detach(chp->atabus, flags)) != 0) 527 return error; 528 529 KASSERT(chp->atabus == NULL); 530 } 531 532 if (chp->ch_flags & ATACH_DETACHED) 533 continue; 534 535 for (j = 0; j < sc->sc_ncmds; j++) 536 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 537 538 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 539 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 540 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 541 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 542 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 543 achp->ahcic_cmd_tbl_nseg); 544 545 ata_channel_detach(chp); 546 port++; 547 } 548 549 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 550 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 551 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 552 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 553 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 554 555 if (adapt->adapt_refcnt != 0) 556 return EBUSY; 557 558 return 0; 559 } 560 561 void 562 ahci_resume(struct ahci_softc *sc) 563 { 564 ahci_reset(sc); 565 ahci_setup_ports(sc); 566 ahci_reprobe_drives(sc); 567 ahci_enable_intrs(sc); 568 } 569 570 int 571 ahci_intr(void *v) 572 { 573 struct ahci_softc *sc = v; 574 uint32_t is; 575 int i, r = 0; 576 577 while ((is = AHCI_READ(sc, AHCI_IS))) { 578 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 579 DEBUG_INTR); 580 r = 1; 581 AHCI_WRITE(sc, AHCI_IS, is); 582 for (i = 0; i < AHCI_MAX_PORTS; i++) 583 if (is & (1U << i)) 584 ahci_intr_port(sc, &sc->sc_channels[i]); 585 } 586 return r; 587 } 588 589 static void 590 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 591 { 592 uint32_t is, tfd, sact; 593 struct ata_channel *chp = &achp->ata_channel; 594 struct ata_xfer *xfer; 595 int slot = -1; 596 bool recover = false; 597 uint32_t aslots; 598 599 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 600 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 601 602 AHCIDEBUG_PRINT(( 603 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 604 AHCINAME(sc), 605 chp->ch_channel, is, 606 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 607 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 608 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 609 DEBUG_INTR); 610 611 if ((chp->ch_flags & ATACH_NCQ) == 0) { 612 /* Non-NCQ operation */ 613 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 614 } else { 615 /* NCQ operation */ 616 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 617 } 618 619 /* Handle errors */ 620 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 621 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 622 /* Fatal errors */ 623 if (is & AHCI_P_IX_TFES) { 624 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 625 626 if ((chp->ch_flags & ATACH_NCQ) == 0) { 627 /* Slot valid only for Non-NCQ operation */ 628 slot = (AHCI_READ(sc, 629 AHCI_P_CMD(chp->ch_channel)) 630 & AHCI_P_CMD_CCS_MASK) 631 >> AHCI_P_CMD_CCS_SHIFT; 632 } 633 634 AHCIDEBUG_PRINT(( 635 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 636 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 637 DEBUG_INTR); 638 } else { 639 /* mark an error, and set BSY */ 640 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 641 WDCS_ERR | WDCS_BSY; 642 } 643 644 if (is & AHCI_P_IX_IFS) { 645 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 646 AHCINAME(sc), chp->ch_channel, 647 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 648 DEBUG_INTR); 649 } 650 651 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 652 recover = true; 653 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 654 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 655 656 /* D2H Register FIS or Set Device Bits */ 657 if ((tfd & WDCS_ERR) != 0) { 658 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 659 recover = true; 660 661 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 662 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 663 664 } 665 } else { 666 tfd = 0; 667 } 668 669 if (__predict_false(recover)) 670 ata_channel_freeze(chp); 671 672 aslots = ata_queue_active(chp); 673 674 if (slot >= 0) { 675 if ((aslots & __BIT(slot)) != 0 && 676 (sact & __BIT(slot)) == 0) { 677 xfer = ata_queue_hwslot_to_xfer(chp, slot); 678 xfer->ops->c_intr(chp, xfer, tfd); 679 } 680 } else { 681 /* 682 * For NCQ, HBA halts processing when error is notified, 683 * and any further D2H FISes are ignored until the error 684 * condition is cleared. Hence if a command is inactive, 685 * it means it actually already finished successfully. 686 * Note: active slots can change as c_intr() callback 687 * can activate another command(s), so must only process 688 * commands active before we start processing. 689 */ 690 691 for (slot=0; slot < sc->sc_ncmds; slot++) { 692 if ((aslots & __BIT(slot)) != 0 && 693 (sact & __BIT(slot)) == 0) { 694 xfer = ata_queue_hwslot_to_xfer(chp, slot); 695 xfer->ops->c_intr(chp, xfer, tfd); 696 } 697 } 698 } 699 700 if (__predict_false(recover)) { 701 ata_channel_lock(chp); 702 ata_channel_thaw_locked(chp); 703 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 704 ata_channel_unlock(chp); 705 } 706 } 707 708 static void 709 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 710 { 711 struct ata_channel *chp = drvp->chnl_softc; 712 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 713 uint8_t c_slot; 714 715 ata_channel_lock_owned(chp); 716 717 /* get a slot for running the command on */ 718 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 719 panic("%s: %s: failed to get xfer for reset, port %d\n", 720 device_xname(sc->sc_atac.atac_dev), 721 __func__, chp->ch_channel); 722 /* NOTREACHED */ 723 } 724 725 AHCI_WRITE(sc, AHCI_GHC, 726 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 727 ahci_channel_stop(sc, chp, flags); 728 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 729 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 730 731 ata_queue_free_slot(chp, c_slot); 732 } 733 734 /* return error code from ata_bio */ 735 static int 736 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 737 { 738 struct ahci_channel *achp = (struct ahci_channel *)chp; 739 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 740 int i; 741 uint32_t is; 742 743 /* 744 * Base timeout is specified in ms. 745 * If we are allowed to sleep, wait a tick each round. 746 * Otherwise delay for 10ms on each round. 747 */ 748 if (flags & AT_WAIT) 749 timeout = MAX(1, mstohz(timeout)); 750 else 751 timeout = timeout / 10; 752 753 AHCI_CMDH_SYNC(sc, achp, slot, 754 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 755 /* start command */ 756 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 757 for (i = 0; i < timeout; i++) { 758 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 759 0) 760 return 0; 761 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 762 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 763 AHCI_P_IX_IFS | 764 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 765 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 766 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 767 /* 768 * we got the D2H FIS anyway, 769 * assume sig is valid. 770 * channel is restarted later 771 */ 772 return ERROR; 773 } 774 aprint_debug("%s port %d: error 0x%x sending FIS\n", 775 AHCINAME(sc), chp->ch_channel, is); 776 return ERR_DF; 777 } 778 ata_delay(chp, 10, "ahcifis", flags); 779 } 780 781 aprint_debug("%s port %d: timeout sending FIS\n", 782 AHCINAME(sc), chp->ch_channel); 783 return TIMEOUT; 784 } 785 786 static int 787 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 788 uint32_t *sigp, uint8_t c_slot) 789 { 790 struct ahci_channel *achp = (struct ahci_channel *)chp; 791 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 792 struct ahci_cmd_tbl *cmd_tbl; 793 struct ahci_cmd_header *cmd_h; 794 int i, error = 0; 795 uint32_t sig; 796 797 ata_channel_lock_owned(chp); 798 799 /* clear port interrupt register */ 800 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 801 /* clear SErrors and start operations */ 802 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 803 /* 804 * issue a command list override to clear BSY. 805 * This is needed if there's a PMP with no drive 806 * on port 0 807 */ 808 ahci_channel_start(sc, chp, flags, 1); 809 } else { 810 /* Can't handle command still running without CLO */ 811 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 812 813 ahci_channel_start(sc, chp, flags, 0); 814 } 815 if (drive > 0) { 816 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 817 } 818 819 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 820 goto skip_reset; 821 822 /* polled command, assume interrupts are disabled */ 823 824 cmd_h = &achp->ahcic_cmdh[c_slot]; 825 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 826 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 827 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 828 cmd_h->cmdh_prdbc = 0; 829 memset(cmd_tbl->cmdt_cfis, 0, 64); 830 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 831 cmd_tbl->cmdt_cfis[rhd_c] = drive; 832 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST; 833 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 834 case ERR_DF: 835 case TIMEOUT: 836 aprint_error("%s port %d: setting WDCTL_RST failed " 837 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 838 error = EBUSY; 839 goto end; 840 default: 841 break; 842 } 843 844 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 845 (drive << AHCI_CMDH_F_PMP_SHIFT)); 846 cmd_h->cmdh_prdbc = 0; 847 memset(cmd_tbl->cmdt_cfis, 0, 64); 848 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 849 cmd_tbl->cmdt_cfis[rhd_c] = drive; 850 cmd_tbl->cmdt_cfis[rhd_control] = 0; 851 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 852 case ERR_DF: 853 case TIMEOUT: 854 aprint_error("%s port %d: clearing WDCTL_RST failed " 855 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 856 error = EBUSY; 857 goto end; 858 default: 859 break; 860 } 861 862 skip_reset: 863 /* 864 * wait 31s for BSY to clear 865 * This should not be needed, but some controllers clear the 866 * command slot before receiving the D2H FIS ... 867 */ 868 for (i = 0; i < AHCI_RST_WAIT; i++) { 869 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 870 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 871 break; 872 ata_delay(chp, 10, "ahcid2h", flags); 873 } 874 if (i == AHCI_RST_WAIT) { 875 aprint_error("%s: BSY never cleared, TD 0x%x\n", 876 AHCINAME(sc), sig); 877 goto end; 878 } 879 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 880 DEBUG_PROBE); 881 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 882 if (sigp) 883 *sigp = sig; 884 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 885 AHCINAME(sc), chp->ch_channel, sig, 886 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 887 end: 888 ahci_channel_stop(sc, chp, flags); 889 ata_delay(chp, 500, "ahcirst", flags); 890 /* clear port interrupt register */ 891 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 892 ahci_channel_start(sc, chp, flags, 893 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 894 return error; 895 } 896 897 static void 898 ahci_reset_channel(struct ata_channel *chp, int flags) 899 { 900 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 901 struct ahci_channel *achp = (struct ahci_channel *)chp; 902 int i, tfd; 903 904 ata_channel_lock_owned(chp); 905 906 ahci_channel_stop(sc, chp, flags); 907 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 908 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 909 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 910 /* XXX and then ? */ 911 } 912 ata_kill_active(chp, KILL_RESET, flags); 913 ata_delay(chp, 500, "ahcirst", flags); 914 /* clear port interrupt register */ 915 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 916 /* clear SErrors and start operations */ 917 ahci_channel_start(sc, chp, flags, 918 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 919 /* wait 31s for BSY to clear */ 920 for (i = 0; i < AHCI_RST_WAIT; i++) { 921 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 922 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 923 break; 924 ata_delay(chp, 10, "ahcid2h", flags); 925 } 926 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 927 aprint_error("%s: BSY never cleared, TD 0x%x\n", 928 AHCINAME(sc), tfd); 929 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 930 DEBUG_PROBE); 931 /* clear port interrupt register */ 932 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 933 934 return; 935 } 936 937 static int 938 ahci_ata_addref(struct ata_drive_datas *drvp) 939 { 940 return 0; 941 } 942 943 static void 944 ahci_ata_delref(struct ata_drive_datas *drvp) 945 { 946 return; 947 } 948 949 static void 950 ahci_killpending(struct ata_drive_datas *drvp) 951 { 952 return; 953 } 954 955 static void 956 ahci_probe_drive(struct ata_channel *chp) 957 { 958 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 959 struct ahci_channel *achp = (struct ahci_channel *)chp; 960 uint32_t sig; 961 uint8_t c_slot; 962 int error; 963 964 ata_channel_lock(chp); 965 966 /* get a slot for running the command on */ 967 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 968 aprint_error_dev(sc->sc_atac.atac_dev, 969 "%s: failed to get xfer port %d\n", 970 __func__, chp->ch_channel); 971 ata_channel_unlock(chp); 972 return; 973 } 974 975 /* bring interface up, accept FISs, power up and spin up device */ 976 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 977 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 978 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 979 /* reset the PHY and bring online */ 980 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 981 achp->ahcic_sstatus, AT_WAIT)) { 982 case SStatus_DET_DEV: 983 ata_delay(chp, 500, "ahcidv", AT_WAIT); 984 985 /* Initial value, used in case the soft reset fails */ 986 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 987 988 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 989 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 990 &sig, c_slot); 991 992 /* If probe for PMP failed, just fallback to drive 0 */ 993 if (error) { 994 aprint_error("%s port %d: drive %d reset " 995 "failing, disabling PMP\n", 996 AHCINAME(sc), chp->ch_channel, 997 PMP_PORT_CTL); 998 999 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1000 ahci_reset_channel(chp, AT_WAIT); 1001 } 1002 } else { 1003 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1004 } 1005 sata_interpret_sig(chp, 0, sig); 1006 /* if we have a PMP attached, inform the controller */ 1007 if (chp->ch_ndrives > PMP_PORT_CTL && 1008 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1009 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1010 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1011 AHCI_P_CMD_PMA); 1012 } 1013 /* clear port interrupt register */ 1014 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1015 1016 /* and enable interrupts */ 1017 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1018 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1019 AHCI_P_IX_IFS | 1020 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1021 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1022 /* wait 500ms before actually starting operations */ 1023 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1024 break; 1025 1026 default: 1027 break; 1028 } 1029 1030 ata_queue_free_slot(chp, c_slot); 1031 1032 ata_channel_unlock(chp); 1033 } 1034 1035 static void 1036 ahci_setup_channel(struct ata_channel *chp) 1037 { 1038 return; 1039 } 1040 1041 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1042 .c_start = ahci_cmd_start, 1043 .c_poll = ahci_cmd_poll, 1044 .c_abort = ahci_cmd_abort, 1045 .c_intr = ahci_cmd_complete, 1046 .c_kill_xfer = ahci_cmd_kill_xfer, 1047 }; 1048 1049 static int 1050 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1051 { 1052 struct ata_channel *chp = drvp->chnl_softc; 1053 struct ata_command *ata_c = &xfer->c_ata_c; 1054 int ret; 1055 int s; 1056 1057 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1058 chp->ch_channel, 1059 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1060 DEBUG_XFERS); 1061 if (ata_c->flags & AT_POLL) 1062 xfer->c_flags |= C_POLL; 1063 if (ata_c->flags & AT_WAIT) 1064 xfer->c_flags |= C_WAIT; 1065 xfer->c_drive = drvp->drive; 1066 xfer->c_databuf = ata_c->data; 1067 xfer->c_bcount = ata_c->bcount; 1068 xfer->ops = &ahci_cmd_xfer_ops; 1069 s = splbio(); 1070 ata_exec_xfer(chp, xfer); 1071 #ifdef DIAGNOSTIC 1072 if ((ata_c->flags & AT_POLL) != 0 && 1073 (ata_c->flags & AT_DONE) == 0) 1074 panic("ahci_exec_command: polled command not done"); 1075 #endif 1076 if (ata_c->flags & AT_DONE) { 1077 ret = ATACMD_COMPLETE; 1078 } else { 1079 if (ata_c->flags & AT_WAIT) { 1080 ata_wait_cmd(chp, xfer); 1081 ret = ATACMD_COMPLETE; 1082 } else { 1083 ret = ATACMD_QUEUED; 1084 } 1085 } 1086 splx(s); 1087 return ret; 1088 } 1089 1090 static int 1091 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1092 { 1093 struct ahci_softc *sc = AHCI_CH2SC(chp); 1094 struct ahci_channel *achp = (struct ahci_channel *)chp; 1095 struct ata_command *ata_c = &xfer->c_ata_c; 1096 int slot = xfer->c_slot; 1097 struct ahci_cmd_tbl *cmd_tbl; 1098 struct ahci_cmd_header *cmd_h; 1099 1100 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1101 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1102 ata_c->timeout, slot), 1103 DEBUG_XFERS); 1104 1105 ata_channel_lock_owned(chp); 1106 1107 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1108 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1109 cmd_tbl), DEBUG_XFERS); 1110 1111 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1112 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1113 1114 cmd_h = &achp->ahcic_cmdh[slot]; 1115 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1116 chp->ch_channel, cmd_h), DEBUG_XFERS); 1117 if (ahci_dma_setup(chp, slot, 1118 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1119 ata_c->data : NULL, 1120 ata_c->bcount, 1121 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1122 ata_c->flags |= AT_DF; 1123 return ATASTART_ABORT; 1124 } 1125 cmd_h->cmdh_flags = htole16( 1126 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1127 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1128 cmd_h->cmdh_prdbc = 0; 1129 AHCI_CMDH_SYNC(sc, achp, slot, 1130 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1131 1132 if (ata_c->flags & AT_POLL) { 1133 /* polled command, disable interrupts */ 1134 AHCI_WRITE(sc, AHCI_GHC, 1135 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1136 } 1137 /* start command */ 1138 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1139 1140 if ((ata_c->flags & AT_POLL) == 0) { 1141 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1142 ata_timeout, chp); 1143 return ATASTART_STARTED; 1144 } else 1145 return ATASTART_POLL; 1146 } 1147 1148 static void 1149 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1150 { 1151 struct ahci_softc *sc = AHCI_CH2SC(chp); 1152 struct ahci_channel *achp = (struct ahci_channel *)chp; 1153 1154 ata_channel_lock(chp); 1155 1156 /* 1157 * Polled command. 1158 */ 1159 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1160 if (xfer->c_ata_c.flags & AT_DONE) 1161 break; 1162 ata_channel_unlock(chp); 1163 ahci_intr_port(sc, achp); 1164 ata_channel_lock(chp); 1165 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1166 } 1167 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1168 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1169 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1170 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1171 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1172 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1173 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1174 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1175 DEBUG_XFERS); 1176 1177 ata_channel_unlock(chp); 1178 1179 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1180 xfer->c_ata_c.flags |= AT_TIMEOU; 1181 xfer->ops->c_intr(chp, xfer, 0); 1182 } 1183 /* reenable interrupts */ 1184 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1185 } 1186 1187 static void 1188 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1189 { 1190 ahci_cmd_complete(chp, xfer, 0); 1191 } 1192 1193 static void 1194 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1195 { 1196 struct ata_command *ata_c = &xfer->c_ata_c; 1197 bool deactivate = true; 1198 1199 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1200 DEBUG_FUNCS); 1201 1202 switch (reason) { 1203 case KILL_GONE_INACTIVE: 1204 deactivate = false; 1205 /* FALLTHROUGH */ 1206 case KILL_GONE: 1207 ata_c->flags |= AT_GONE; 1208 break; 1209 case KILL_RESET: 1210 ata_c->flags |= AT_RESET; 1211 break; 1212 case KILL_REQUEUE: 1213 panic("%s: not supposed to be requeued\n", __func__); 1214 break; 1215 default: 1216 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1217 panic("ahci_cmd_kill_xfer"); 1218 } 1219 1220 ahci_cmd_done_end(chp, xfer); 1221 1222 if (deactivate) 1223 ata_deactivate_xfer(chp, xfer); 1224 } 1225 1226 static int 1227 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1228 { 1229 struct ata_command *ata_c = &xfer->c_ata_c; 1230 struct ahci_channel *achp = (struct ahci_channel *)chp; 1231 1232 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1233 chp->ch_channel, 1234 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1235 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1236 DEBUG_FUNCS); 1237 1238 if (ata_waitdrain_xfer_check(chp, xfer)) 1239 return 0; 1240 1241 if (xfer->c_flags & C_TIMEOU) { 1242 ata_c->flags |= AT_TIMEOU; 1243 } 1244 1245 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1246 ata_c->flags |= AT_TIMEOU; 1247 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1248 ata_c->r_error = AHCI_TFD_ERR(tfd); 1249 ata_c->flags |= AT_ERROR; 1250 } 1251 1252 if (ata_c->flags & AT_READREG) 1253 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1254 1255 ahci_cmd_done(chp, xfer); 1256 1257 ata_deactivate_xfer(chp, xfer); 1258 1259 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1260 atastart(chp); 1261 1262 return 0; 1263 } 1264 1265 static void 1266 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1267 { 1268 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1269 struct ahci_channel *achp = (struct ahci_channel *)chp; 1270 struct ata_command *ata_c = &xfer->c_ata_c; 1271 uint16_t *idwordbuf; 1272 int i; 1273 1274 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1275 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1276 1277 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1278 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1279 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1280 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1281 BUS_DMASYNC_POSTWRITE); 1282 bus_dmamap_unload(sc->sc_dmat, map); 1283 } 1284 1285 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1286 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1287 1288 /* ata(4) expects IDENTIFY data to be in host endianess */ 1289 if (ata_c->r_command == WDCC_IDENTIFY || 1290 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1291 idwordbuf = xfer->c_databuf; 1292 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1293 idwordbuf[i] = le16toh(idwordbuf[i]); 1294 } 1295 } 1296 1297 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1298 ata_c->flags |= AT_XFDONE; 1299 1300 ahci_cmd_done_end(chp, xfer); 1301 } 1302 1303 static void 1304 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1305 { 1306 struct ata_command *ata_c = &xfer->c_ata_c; 1307 1308 ata_c->flags |= AT_DONE; 1309 } 1310 1311 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1312 .c_start = ahci_bio_start, 1313 .c_poll = ahci_bio_poll, 1314 .c_abort = ahci_bio_abort, 1315 .c_intr = ahci_bio_complete, 1316 .c_kill_xfer = ahci_bio_kill_xfer, 1317 }; 1318 1319 static int 1320 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1321 { 1322 struct ata_channel *chp = drvp->chnl_softc; 1323 struct ata_bio *ata_bio = &xfer->c_bio; 1324 1325 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1326 chp->ch_channel, 1327 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1328 DEBUG_XFERS); 1329 if (ata_bio->flags & ATA_POLL) 1330 xfer->c_flags |= C_POLL; 1331 xfer->c_drive = drvp->drive; 1332 xfer->c_databuf = ata_bio->databuf; 1333 xfer->c_bcount = ata_bio->bcount; 1334 xfer->ops = &ahci_bio_xfer_ops; 1335 ata_exec_xfer(chp, xfer); 1336 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1337 } 1338 1339 static int 1340 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1341 { 1342 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1343 struct ahci_channel *achp = (struct ahci_channel *)chp; 1344 struct ata_bio *ata_bio = &xfer->c_bio; 1345 struct ahci_cmd_tbl *cmd_tbl; 1346 struct ahci_cmd_header *cmd_h; 1347 1348 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1349 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1350 1351 ata_channel_lock_owned(chp); 1352 1353 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1354 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1355 cmd_tbl), DEBUG_XFERS); 1356 1357 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1358 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1359 1360 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1361 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1362 chp->ch_channel, cmd_h), DEBUG_XFERS); 1363 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1364 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1365 ata_bio->error = ERR_DMA; 1366 ata_bio->r_error = 0; 1367 return ATASTART_ABORT; 1368 } 1369 cmd_h->cmdh_flags = htole16( 1370 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1371 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1372 cmd_h->cmdh_prdbc = 0; 1373 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1375 1376 if (xfer->c_flags & C_POLL) { 1377 /* polled command, disable interrupts */ 1378 AHCI_WRITE(sc, AHCI_GHC, 1379 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1380 } 1381 if (xfer->c_flags & C_NCQ) 1382 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1383 /* start command */ 1384 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1385 1386 if ((xfer->c_flags & C_POLL) == 0) { 1387 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1388 ata_timeout, chp); 1389 return ATASTART_STARTED; 1390 } else 1391 return ATASTART_POLL; 1392 } 1393 1394 static void 1395 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1396 { 1397 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1398 struct ahci_channel *achp = (struct ahci_channel *)chp; 1399 1400 /* 1401 * Polled command. 1402 */ 1403 for (int i = 0; i < ATA_DELAY * 10; i++) { 1404 if (xfer->c_bio.flags & ATA_ITSDONE) 1405 break; 1406 ahci_intr_port(sc, achp); 1407 delay(100); 1408 } 1409 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1410 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1411 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1412 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1413 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1414 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1415 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1416 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1417 DEBUG_XFERS); 1418 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1419 xfer->c_bio.error = TIMEOUT; 1420 xfer->ops->c_intr(chp, xfer, 0); 1421 } 1422 /* reenable interrupts */ 1423 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1424 } 1425 1426 static void 1427 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1428 { 1429 ahci_bio_complete(chp, xfer, 0); 1430 } 1431 1432 static void 1433 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1434 { 1435 int drive = xfer->c_drive; 1436 struct ata_bio *ata_bio = &xfer->c_bio; 1437 bool deactivate = true; 1438 1439 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1440 DEBUG_FUNCS); 1441 1442 ata_bio->flags |= ATA_ITSDONE; 1443 switch (reason) { 1444 case KILL_GONE_INACTIVE: 1445 deactivate = false; 1446 /* FALLTHROUGH */ 1447 case KILL_GONE: 1448 ata_bio->error = ERR_NODEV; 1449 break; 1450 case KILL_RESET: 1451 ata_bio->error = ERR_RESET; 1452 break; 1453 case KILL_REQUEUE: 1454 ata_bio->error = REQUEUE; 1455 break; 1456 default: 1457 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1458 panic("ahci_bio_kill_xfer"); 1459 } 1460 ata_bio->r_error = WDCE_ABRT; 1461 1462 if (deactivate) 1463 ata_deactivate_xfer(chp, xfer); 1464 1465 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1466 } 1467 1468 static int 1469 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1470 { 1471 struct ata_bio *ata_bio = &xfer->c_bio; 1472 int drive = xfer->c_drive; 1473 struct ahci_channel *achp = (struct ahci_channel *)chp; 1474 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1475 1476 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1477 DEBUG_FUNCS); 1478 1479 if (ata_waitdrain_xfer_check(chp, xfer)) 1480 return 0; 1481 1482 if (xfer->c_flags & C_TIMEOU) { 1483 ata_bio->error = TIMEOUT; 1484 } 1485 1486 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1487 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1488 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1489 BUS_DMASYNC_POSTWRITE); 1490 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1491 1492 ata_bio->flags |= ATA_ITSDONE; 1493 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1494 ata_bio->error = ERR_DF; 1495 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1496 ata_bio->error = ERROR; 1497 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1498 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1499 ata_bio->flags |= ATA_CORR; 1500 1501 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1502 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1503 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1504 ata_bio->bcount), DEBUG_XFERS); 1505 /* 1506 * If it was a write, complete data buffer may have been transfered 1507 * before error detection; in this case don't use cmdh_prdbc 1508 * as it won't reflect what was written to media. Assume nothing 1509 * was transfered and leave bcount as-is. 1510 * For queued commands, PRD Byte Count should not be used, and is 1511 * not required to be valid; in that case underflow is always illegal. 1512 */ 1513 if ((xfer->c_flags & C_NCQ) != 0) { 1514 if (ata_bio->error == NOERROR) 1515 ata_bio->bcount = 0; 1516 } else { 1517 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1518 ata_bio->bcount -= 1519 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1520 } 1521 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1522 1523 ata_deactivate_xfer(chp, xfer); 1524 1525 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1526 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1527 atastart(chp); 1528 return 0; 1529 } 1530 1531 static void 1532 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1533 { 1534 int i; 1535 /* stop channel */ 1536 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1537 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1538 /* wait 1s for channel to stop */ 1539 for (i = 0; i <100; i++) { 1540 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1541 == 0) 1542 break; 1543 ata_delay(chp, 10, "ahcistop", flags); 1544 } 1545 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1546 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1547 /* XXX controller reset ? */ 1548 return; 1549 } 1550 1551 if (sc->sc_channel_stop) 1552 sc->sc_channel_stop(sc, chp); 1553 } 1554 1555 static void 1556 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1557 int flags, int clo) 1558 { 1559 int i; 1560 uint32_t p_cmd; 1561 /* clear error */ 1562 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1563 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1564 1565 if (clo) { 1566 /* issue command list override */ 1567 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1568 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1569 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1570 /* wait 1s for AHCI_CAP_CLO to clear */ 1571 for (i = 0; i <100; i++) { 1572 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1573 AHCI_P_CMD_CLO) == 0) 1574 break; 1575 ata_delay(chp, 10, "ahciclo", flags); 1576 } 1577 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1578 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1579 /* XXX controller reset ? */ 1580 return; 1581 } 1582 } 1583 1584 if (sc->sc_channel_start) 1585 sc->sc_channel_start(sc, chp); 1586 1587 /* and start controller */ 1588 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1589 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1590 if (chp->ch_ndrives > PMP_PORT_CTL && 1591 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1592 p_cmd |= AHCI_P_CMD_PMA; 1593 } 1594 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1595 } 1596 1597 /* Recover channel after command failure */ 1598 static void 1599 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1600 { 1601 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1602 int drive = ATACH_NODRIVE; 1603 bool reset = false; 1604 1605 ata_channel_lock_owned(chp); 1606 1607 /* 1608 * Read FBS to get the drive which caused the error, if PM is in use. 1609 * According to AHCI 1.3 spec, this register is available regardless 1610 * if FIS-based switching (FBSS) feature is supported, or disabled. 1611 * If FIS-based switching is not in use, it merely maintains single 1612 * pair of DRQ/BSY state, but it is enough since in that case we 1613 * never issue commands for more than one device at the time anyway. 1614 * XXX untested 1615 */ 1616 if (chp->ch_ndrives > PMP_PORT_CTL) { 1617 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1618 if (fbs & AHCI_P_FBS_SDE) { 1619 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1620 1621 /* 1622 * Tell HBA to reset PM port X (value in DWE) state, 1623 * and resume processing commands for other ports. 1624 */ 1625 fbs |= AHCI_P_FBS_DEC; 1626 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1627 for (int i = 0; i < 1000; i++) { 1628 fbs = AHCI_READ(sc, 1629 AHCI_P_FBS(chp->ch_channel)); 1630 if ((fbs & AHCI_P_FBS_DEC) == 0) 1631 break; 1632 DELAY(1000); 1633 } 1634 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1635 /* follow non-device specific recovery */ 1636 drive = ATACH_NODRIVE; 1637 reset = true; 1638 } 1639 } else { 1640 /* not device specific, reset channel */ 1641 drive = ATACH_NODRIVE; 1642 reset = true; 1643 } 1644 } else 1645 drive = 0; 1646 1647 /* 1648 * If BSY or DRQ bits are set, must execute COMRESET to return 1649 * device to idle state. If drive is idle, it's enough to just 1650 * reset CMD.ST, it's not necessary to do software reset. 1651 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1652 * to unblock device processing if COMRESET was not done. 1653 */ 1654 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1655 ahci_reset_channel(chp, flags); 1656 goto out; 1657 } 1658 1659 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1660 ahci_channel_stop(sc, chp, flags); 1661 ahci_channel_start(sc, chp, flags, 1662 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1663 1664 ata_recovery_resume(chp, drive, tfd, flags); 1665 1666 out: 1667 /* Drive unblocked, back to normal operation */ 1668 return; 1669 } 1670 1671 static int 1672 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1673 size_t count, int op) 1674 { 1675 int error, seg; 1676 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1677 struct ahci_channel *achp = (struct ahci_channel *)chp; 1678 struct ahci_cmd_tbl *cmd_tbl; 1679 struct ahci_cmd_header *cmd_h; 1680 1681 cmd_h = &achp->ahcic_cmdh[slot]; 1682 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1683 1684 if (data == NULL) { 1685 cmd_h->cmdh_prdtl = 0; 1686 goto end; 1687 } 1688 1689 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1690 data, count, NULL, 1691 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1692 if (error) { 1693 printf("%s port %d: failed to load xfer: %d\n", 1694 AHCINAME(sc), chp->ch_channel, error); 1695 return error; 1696 } 1697 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1698 achp->ahcic_datad[slot]->dm_mapsize, 1699 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1700 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1701 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1702 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1703 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1704 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1705 } 1706 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1707 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1708 end: 1709 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1710 return 0; 1711 } 1712 1713 #if NATAPIBUS > 0 1714 static void 1715 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1716 { 1717 struct ata_channel *chp = ata_sc->sc_chan; 1718 struct atac_softc *atac = chp->ch_atac; 1719 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1720 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1721 /* 1722 * Fill in the scsipi_adapter. 1723 */ 1724 adapt->adapt_dev = atac->atac_dev; 1725 adapt->adapt_nchannels = atac->atac_nchannels; 1726 adapt->adapt_request = ahci_atapi_scsipi_request; 1727 adapt->adapt_minphys = ahci_atapi_minphys; 1728 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1729 1730 /* 1731 * Fill in the scsipi_channel. 1732 */ 1733 memset(chan, 0, sizeof(*chan)); 1734 chan->chan_adapter = adapt; 1735 chan->chan_bustype = &ahci_atapi_bustype; 1736 chan->chan_channel = chp->ch_channel; 1737 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1738 chan->chan_openings = 1; 1739 chan->chan_max_periph = 1; 1740 chan->chan_ntargets = 1; 1741 chan->chan_nluns = 1; 1742 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1743 atapiprint); 1744 } 1745 1746 static void 1747 ahci_atapi_minphys(struct buf *bp) 1748 { 1749 if (bp->b_bcount > MAXPHYS) 1750 bp->b_bcount = MAXPHYS; 1751 minphys(bp); 1752 } 1753 1754 /* 1755 * Kill off all pending xfers for a periph. 1756 * 1757 * Must be called at splbio(). 1758 */ 1759 static void 1760 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1761 { 1762 struct atac_softc *atac = 1763 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1764 struct ata_channel *chp = 1765 atac->atac_channels[periph->periph_channel->chan_channel]; 1766 1767 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1768 } 1769 1770 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1771 .c_start = ahci_atapi_start, 1772 .c_poll = ahci_atapi_poll, 1773 .c_abort = ahci_atapi_abort, 1774 .c_intr = ahci_atapi_complete, 1775 .c_kill_xfer = ahci_atapi_kill_xfer, 1776 }; 1777 1778 static void 1779 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1780 scsipi_adapter_req_t req, void *arg) 1781 { 1782 struct scsipi_adapter *adapt = chan->chan_adapter; 1783 struct scsipi_periph *periph; 1784 struct scsipi_xfer *sc_xfer; 1785 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1786 struct atac_softc *atac = &sc->sc_atac; 1787 struct ata_xfer *xfer; 1788 int channel = chan->chan_channel; 1789 int drive, s; 1790 1791 switch (req) { 1792 case ADAPTER_REQ_RUN_XFER: 1793 sc_xfer = arg; 1794 periph = sc_xfer->xs_periph; 1795 drive = periph->periph_target; 1796 if (!device_is_active(atac->atac_dev)) { 1797 sc_xfer->error = XS_DRIVER_STUFFUP; 1798 scsipi_done(sc_xfer); 1799 return; 1800 } 1801 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1802 if (xfer == NULL) { 1803 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1804 scsipi_done(sc_xfer); 1805 return; 1806 } 1807 1808 if (sc_xfer->xs_control & XS_CTL_POLL) 1809 xfer->c_flags |= C_POLL; 1810 xfer->c_drive = drive; 1811 xfer->c_flags |= C_ATAPI; 1812 xfer->c_databuf = sc_xfer->data; 1813 xfer->c_bcount = sc_xfer->datalen; 1814 xfer->ops = &ahci_atapi_xfer_ops; 1815 xfer->c_scsipi = sc_xfer; 1816 xfer->c_atapi.c_dscpoll = 0; 1817 s = splbio(); 1818 ata_exec_xfer(atac->atac_channels[channel], xfer); 1819 #ifdef DIAGNOSTIC 1820 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1821 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1822 panic("ahci_atapi_scsipi_request: polled command " 1823 "not done"); 1824 #endif 1825 splx(s); 1826 return; 1827 default: 1828 /* Not supported, nothing to do. */ 1829 ; 1830 } 1831 } 1832 1833 static int 1834 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1835 { 1836 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1837 struct ahci_channel *achp = (struct ahci_channel *)chp; 1838 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1839 struct ahci_cmd_tbl *cmd_tbl; 1840 struct ahci_cmd_header *cmd_h; 1841 1842 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1843 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1844 1845 ata_channel_lock_owned(chp); 1846 1847 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1848 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1849 cmd_tbl), DEBUG_XFERS); 1850 1851 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1852 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1853 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1854 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1855 1856 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1857 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1858 chp->ch_channel, cmd_h), DEBUG_XFERS); 1859 if (ahci_dma_setup(chp, xfer->c_slot, 1860 sc_xfer->datalen ? sc_xfer->data : NULL, 1861 sc_xfer->datalen, 1862 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1863 BUS_DMA_READ : BUS_DMA_WRITE)) { 1864 sc_xfer->error = XS_DRIVER_STUFFUP; 1865 return ATASTART_ABORT; 1866 } 1867 cmd_h->cmdh_flags = htole16( 1868 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1869 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1870 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1871 cmd_h->cmdh_prdbc = 0; 1872 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1873 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1874 1875 if (xfer->c_flags & C_POLL) { 1876 /* polled command, disable interrupts */ 1877 AHCI_WRITE(sc, AHCI_GHC, 1878 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1879 } 1880 /* start command */ 1881 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1882 1883 if ((xfer->c_flags & C_POLL) == 0) { 1884 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1885 ata_timeout, chp); 1886 return ATASTART_STARTED; 1887 } else 1888 return ATASTART_POLL; 1889 } 1890 1891 static void 1892 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1893 { 1894 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1895 struct ahci_channel *achp = (struct ahci_channel *)chp; 1896 1897 /* 1898 * Polled command. 1899 */ 1900 for (int i = 0; i < ATA_DELAY / 10; i++) { 1901 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1902 break; 1903 ahci_intr_port(sc, achp); 1904 delay(10000); 1905 } 1906 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1907 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1908 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1909 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1910 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1911 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1912 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1913 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1914 DEBUG_XFERS); 1915 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1916 xfer->c_scsipi->error = XS_TIMEOUT; 1917 xfer->ops->c_intr(chp, xfer, 0); 1918 } 1919 /* reenable interrupts */ 1920 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1921 } 1922 1923 static void 1924 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1925 { 1926 ahci_atapi_complete(chp, xfer, 0); 1927 } 1928 1929 static int 1930 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1931 { 1932 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1933 struct ahci_channel *achp = (struct ahci_channel *)chp; 1934 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1935 1936 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1937 DEBUG_FUNCS); 1938 1939 if (ata_waitdrain_xfer_check(chp, xfer)) 1940 return 0; 1941 1942 if (xfer->c_flags & C_TIMEOU) { 1943 sc_xfer->error = XS_TIMEOUT; 1944 } 1945 1946 if (xfer->c_bcount > 0) { 1947 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1948 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1949 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1950 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1951 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1952 } 1953 1954 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1955 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1956 sc_xfer->resid = sc_xfer->datalen; 1957 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1958 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1959 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1960 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1961 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1962 sc_xfer->resid == sc_xfer->datalen)) { 1963 sc_xfer->error = XS_SHORTSENSE; 1964 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 1965 if ((sc_xfer->xs_periph->periph_quirks & 1966 PQUIRK_NOSENSE) == 0) { 1967 /* ask scsipi to send a REQUEST_SENSE */ 1968 sc_xfer->error = XS_BUSY; 1969 sc_xfer->status = SCSI_CHECK; 1970 } 1971 } 1972 1973 ata_deactivate_xfer(chp, xfer); 1974 1975 ata_free_xfer(chp, xfer); 1976 scsipi_done(sc_xfer); 1977 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1978 atastart(chp); 1979 return 0; 1980 } 1981 1982 static void 1983 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1984 { 1985 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1986 bool deactivate = true; 1987 1988 /* remove this command from xfer queue */ 1989 switch (reason) { 1990 case KILL_GONE_INACTIVE: 1991 deactivate = false; 1992 /* FALLTHROUGH */ 1993 case KILL_GONE: 1994 sc_xfer->error = XS_DRIVER_STUFFUP; 1995 break; 1996 case KILL_RESET: 1997 sc_xfer->error = XS_RESET; 1998 break; 1999 case KILL_REQUEUE: 2000 sc_xfer->error = XS_REQUEUE; 2001 break; 2002 default: 2003 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2004 panic("ahci_ata_atapi_kill_xfer"); 2005 } 2006 2007 if (deactivate) 2008 ata_deactivate_xfer(chp, xfer); 2009 2010 ata_free_xfer(chp, xfer); 2011 scsipi_done(sc_xfer); 2012 } 2013 2014 static void 2015 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2016 { 2017 struct scsipi_channel *chan = sc->sc_channel; 2018 struct scsipi_periph *periph; 2019 struct ataparams ids; 2020 struct ataparams *id = &ids; 2021 struct ahci_softc *ahcic = 2022 device_private(chan->chan_adapter->adapt_dev); 2023 struct atac_softc *atac = &ahcic->sc_atac; 2024 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2025 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2026 struct scsipibus_attach_args sa; 2027 char serial_number[21], model[41], firmware_revision[9]; 2028 int s; 2029 2030 /* skip if already attached */ 2031 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2032 return; 2033 2034 /* if no ATAPI device detected at attach time, skip */ 2035 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2036 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2037 "not present\n", target), DEBUG_PROBE); 2038 return; 2039 } 2040 2041 /* Some ATAPI devices need a bit more time after software reset. */ 2042 delay(5000); 2043 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2044 #ifdef ATAPI_DEBUG_PROBE 2045 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2046 AHCINAME(ahcic), target, 2047 id->atap_config & ATAPI_CFG_CMD_MASK, 2048 id->atap_config & ATAPI_CFG_DRQ_MASK); 2049 #endif 2050 periph = scsipi_alloc_periph(M_NOWAIT); 2051 if (periph == NULL) { 2052 aprint_error_dev(sc->sc_dev, 2053 "unable to allocate periph for drive %d\n", 2054 target); 2055 return; 2056 } 2057 periph->periph_dev = NULL; 2058 periph->periph_channel = chan; 2059 periph->periph_switch = &atapi_probe_periphsw; 2060 periph->periph_target = target; 2061 periph->periph_lun = 0; 2062 periph->periph_quirks = PQUIRK_ONLYBIG; 2063 2064 #ifdef SCSIPI_DEBUG 2065 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2066 SCSIPI_DEBUG_TARGET == target) 2067 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2068 #endif 2069 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2070 if (id->atap_config & ATAPI_CFG_REMOV) 2071 periph->periph_flags |= PERIPH_REMOVABLE; 2072 if (periph->periph_type == T_SEQUENTIAL) { 2073 s = splbio(); 2074 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2075 splx(s); 2076 } 2077 2078 sa.sa_periph = periph; 2079 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2080 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2081 T_REMOV : T_FIXED; 2082 strnvisx(model, sizeof(model), id->atap_model, 40, 2083 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2084 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2085 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2086 strnvisx(firmware_revision, sizeof(firmware_revision), 2087 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2088 sa.sa_inqbuf.vendor = model; 2089 sa.sa_inqbuf.product = serial_number; 2090 sa.sa_inqbuf.revision = firmware_revision; 2091 2092 /* 2093 * Determine the operating mode capabilities of the device. 2094 */ 2095 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2096 periph->periph_cap |= PERIPH_CAP_CMD16; 2097 /* XXX This is gross. */ 2098 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2099 2100 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2101 2102 if (drvp->drv_softc) 2103 ata_probe_caps(drvp); 2104 else { 2105 s = splbio(); 2106 drvp->drive_type = ATA_DRIVET_NONE; 2107 splx(s); 2108 } 2109 } else { 2110 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2111 "failed for drive %s:%d:%d\n", 2112 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2113 s = splbio(); 2114 drvp->drive_type = ATA_DRIVET_NONE; 2115 splx(s); 2116 } 2117 } 2118 #endif /* NATAPIBUS */ 2119
Indexes created Thu Sep 25 16:09:42 GMT 2025