ahcisata_core.c revision 1.7
1 /* $NetBSD: ahcisata_core.c,v 1.7 2007/11/12 20:10:32 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.7 2007/11/12 20:10:32 joerg Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/ic/wdcreg.h> 47 #include <dev/ata/atareg.h> 48 #include <dev/ata/satavar.h> 49 #include <dev/ata/satareg.h> 50 #include <dev/ic/ahcisatavar.h> 51 52 #ifdef AHCI_DEBUG 53 int ahcidebug_mask = 0x0; 54 #endif 55 56 void ahci_probe_drive(struct ata_channel *); 57 void ahci_setup_channel(struct ata_channel *); 58 59 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 60 void ahci_reset_drive(struct ata_drive_datas *, int); 61 void ahci_reset_channel(struct ata_channel *, int); 62 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 63 int ahci_ata_addref(struct ata_drive_datas *); 64 void ahci_ata_delref(struct ata_drive_datas *); 65 void ahci_killpending(struct ata_drive_datas *); 66 67 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 68 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 69 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 70 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 71 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 72 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 73 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 75 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 76 void ahci_timeout(void *); 77 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 78 79 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 80 81 const struct ata_bustype ahci_ata_bustype = { 82 SCSIPI_BUSTYPE_ATA, 83 ahci_ata_bio, 84 ahci_reset_drive, 85 ahci_reset_channel, 86 ahci_exec_command, 87 ata_get_params, 88 ahci_ata_addref, 89 ahci_ata_delref, 90 ahci_killpending 91 }; 92 93 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 94 95 static void ahci_setup_port(struct ahci_softc *sc, int i); 96 97 int 98 ahci_reset(struct ahci_softc *sc) 99 { 100 int i; 101 102 /* reset controller */ 103 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 104 /* wait up to 1s for reset to complete */ 105 for (i = 0; i < 1000; i++) { 106 delay(1000); 107 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 108 break; 109 } 110 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 111 aprint_error("%s: reset failed\n", AHCINAME(sc)); 112 return -1; 113 } 114 /* enable ahci mode */ 115 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 116 return 0; 117 } 118 119 void 120 ahci_setup_ports(struct ahci_softc *sc) 121 { 122 u_int32_t ahci_ports; 123 int i, port; 124 125 ahci_ports = AHCI_READ(sc, AHCI_PI); 126 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 127 if ((ahci_ports & (1 << i)) == 0) 128 continue; 129 if (port >= sc->sc_atac.atac_nchannels) { 130 aprint_error("%s: more ports than announced\n", 131 AHCINAME(sc)); 132 break; 133 } 134 ahci_setup_port(sc, i); 135 } 136 } 137 138 void 139 ahci_reprobe_drives(struct ahci_softc *sc) 140 { 141 u_int32_t ahci_ports; 142 int i, port; 143 struct ahci_channel *achp; 144 struct ata_channel *chp; 145 146 ahci_ports = AHCI_READ(sc, AHCI_PI); 147 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 148 if ((ahci_ports & (1 << i)) == 0) 149 continue; 150 if (port >= sc->sc_atac.atac_nchannels) { 151 aprint_error("%s: more ports than announced\n", 152 AHCINAME(sc)); 153 break; 154 } 155 achp = &sc->sc_channels[i]; 156 chp = &achp->ata_channel; 157 158 ahci_probe_drive(chp); 159 } 160 } 161 162 static void 163 ahci_setup_port(struct ahci_softc *sc, int i) 164 { 165 struct ahci_channel *achp; 166 167 achp = &sc->sc_channels[i]; 168 169 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 170 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 171 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 172 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 173 } 174 175 void 176 ahci_enable_intrs(struct ahci_softc *sc) 177 { 178 179 /* clear interrupts */ 180 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 181 /* enable interrupts */ 182 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 183 } 184 185 void 186 ahci_attach(struct ahci_softc *sc) 187 { 188 u_int32_t ahci_cap, ahci_rev, ahci_ports; 189 int i, j, port; 190 struct ahci_channel *achp; 191 struct ata_channel *chp; 192 int error; 193 bus_dma_segment_t seg; 194 int rseg; 195 int dmasize; 196 void *cmdhp; 197 void *cmdtblp; 198 199 if (ahci_reset(sc) != 0) 200 return; 201 202 ahci_cap = AHCI_READ(sc, AHCI_CAP); 203 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 204 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 205 ahci_rev = AHCI_READ(sc, AHCI_VS); 206 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 207 switch(ahci_rev) { 208 case AHCI_VS_10: 209 aprint_normal("1.0"); 210 break; 211 case AHCI_VS_11: 212 aprint_normal("1.1"); 213 break; 214 default: 215 aprint_normal("0x%x", ahci_rev); 216 break; 217 } 218 219 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 220 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 221 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 222 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 223 sc->sc_atac.atac_pio_cap = 4; 224 sc->sc_atac.atac_dma_cap = 2; 225 sc->sc_atac.atac_udma_cap = 6; 226 sc->sc_atac.atac_channels = sc->sc_chanarray; 227 sc->sc_atac.atac_atapibus_attach = NULL; /* XXX */ 228 sc->sc_atac.atac_probe = ahci_probe_drive; 229 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 230 sc->sc_atac.atac_set_modes = ahci_setup_channel; 231 232 dmasize = 233 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 234 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 235 &seg, 1, &rseg, BUS_DMA_NOWAIT); 236 if (error) { 237 aprint_error("%s: unable to allocate command header memory" 238 ", error=%d\n", AHCINAME(sc), error); 239 return; 240 } 241 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 242 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 243 if (error) { 244 aprint_error("%s: unable to map command header memory" 245 ", error=%d\n", AHCINAME(sc), error); 246 return; 247 } 248 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 249 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 250 if (error) { 251 aprint_error("%s: unable to create command header map" 252 ", error=%d\n", AHCINAME(sc), error); 253 return; 254 } 255 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 256 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 257 if (error) { 258 aprint_error("%s: unable to load command header map" 259 ", error=%d\n", AHCINAME(sc), error); 260 return; 261 } 262 sc->sc_cmd_hdr = cmdhp; 263 264 ahci_enable_intrs(sc); 265 266 ahci_ports = AHCI_READ(sc, AHCI_PI); 267 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 268 if ((ahci_ports & (1 << i)) == 0) 269 continue; 270 if (port >= sc->sc_atac.atac_nchannels) { 271 aprint_error("%s: more ports than announced\n", 272 AHCINAME(sc)); 273 break; 274 } 275 achp = &sc->sc_channels[i]; 276 chp = (struct ata_channel *)achp; 277 sc->sc_chanarray[i] = chp; 278 chp->ch_channel = i; 279 chp->ch_atac = &sc->sc_atac; 280 chp->ch_queue = malloc(sizeof(struct ata_queue), 281 M_DEVBUF, M_NOWAIT); 282 if (chp->ch_queue == NULL) { 283 aprint_error("%s port %d: can't allocate memory for " 284 "command queue", AHCINAME(sc), i); 285 break; 286 } 287 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 288 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 289 &seg, 1, &rseg, BUS_DMA_NOWAIT); 290 if (error) { 291 aprint_error("%s: unable to allocate command table " 292 "memory, error=%d\n", AHCINAME(sc), error); 293 break; 294 } 295 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 296 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 297 if (error) { 298 aprint_error("%s: unable to map command table memory" 299 ", error=%d\n", AHCINAME(sc), error); 300 break; 301 } 302 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 303 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 304 if (error) { 305 aprint_error("%s: unable to create command table map" 306 ", error=%d\n", AHCINAME(sc), error); 307 break; 308 } 309 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 310 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 311 if (error) { 312 aprint_error("%s: unable to load command table map" 313 ", error=%d\n", AHCINAME(sc), error); 314 break; 315 } 316 achp->ahcic_cmdh = (struct ahci_cmd_header *) 317 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 318 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 319 AHCI_CMDH_SIZE * port; 320 achp->ahcic_rfis = (struct ahci_r_fis *) 321 ((char *)cmdhp + 322 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 323 AHCI_RFIS_SIZE * port); 324 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 325 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 326 AHCI_RFIS_SIZE * port; 327 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 328 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 329 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 330 DEBUG_PROBE); 331 332 for (j = 0; j < sc->sc_ncmds; j++) { 333 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 334 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 335 achp->ahcic_bus_cmd_tbl[j] = 336 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 337 AHCI_CMDTBL_SIZE * j; 338 achp->ahcic_cmdh[j].cmdh_cmdtba = 339 htole32(achp->ahcic_bus_cmd_tbl[j]); 340 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 341 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 342 achp->ahcic_cmd_tbl[j], 343 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 344 /* The xfer DMA map */ 345 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 346 AHCI_NPRD, 0x400000 /* 4MB */, 0, 347 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 348 &achp->ahcic_datad[j]); 349 if (error) { 350 aprint_error("%s: couldn't alloc xfer DMA map, " 351 "error=%d\n", AHCINAME(sc), error); 352 goto end; 353 } 354 } 355 ahci_setup_port(sc, i); 356 chp->ch_ndrive = 1; 357 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 358 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 359 aprint_error("%s: couldn't map channel %d " 360 "sata_status regs\n", AHCINAME(sc), i); 361 break; 362 } 363 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 364 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 365 aprint_error("%s: couldn't map channel %d " 366 "sata_control regs\n", AHCINAME(sc), i); 367 break; 368 } 369 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 370 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 371 aprint_error("%s: couldn't map channel %d " 372 "sata_error regs\n", AHCINAME(sc), i); 373 break; 374 } 375 ata_channel_attach(chp); 376 port++; 377 end: 378 continue; 379 } 380 } 381 382 int 383 ahci_intr(void *v) 384 { 385 struct ahci_softc *sc = v; 386 u_int32_t is; 387 int i, r = 0; 388 389 while ((is = AHCI_READ(sc, AHCI_IS))) { 390 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 391 DEBUG_INTR); 392 r = 1; 393 AHCI_WRITE(sc, AHCI_IS, is); 394 for (i = 0; i < AHCI_MAX_PORTS; i++) 395 if (is & (1 << i)) 396 ahci_intr_port(sc, &sc->sc_channels[i]); 397 } 398 return r; 399 } 400 401 void 402 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 403 { 404 u_int32_t is, tfd; 405 struct ata_channel *chp = &achp->ata_channel; 406 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 407 int slot; 408 409 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 410 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 411 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 412 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 413 DEBUG_INTR); 414 415 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 416 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 417 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 418 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 419 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 420 return; 421 /* stop channel */ 422 ahci_channel_stop(sc, chp, 0); 423 if (slot != 0) { 424 printf("ahci_intr_port: slot %d\n", slot); 425 panic("ahci_intr_port"); 426 } 427 if (is & AHCI_P_IX_TFES) { 428 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 429 chp->ch_error = 430 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 431 chp->ch_status = (tfd & 0xff); 432 } else { 433 /* emulate a CRC error */ 434 chp->ch_error = WDCE_CRC; 435 chp->ch_status = WDCS_ERR; 436 } 437 xfer->c_intr(chp, xfer, is); 438 /* if channel has not been restarted, do it now */ 439 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 440 == 0) 441 ahci_channel_start(sc, chp); 442 } else { 443 slot = 0; /* XXX */ 444 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 445 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 446 chp->ch_channel, is, achp->ahcic_cmds_active, 447 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 448 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 449 return; 450 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 451 == 0) { 452 xfer->c_intr(chp, xfer, 0); 453 } 454 } 455 } 456 457 void 458 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 459 { 460 struct ata_channel *chp = drvp->chnl_softc; 461 ata_reset_channel(chp, flags); 462 return; 463 } 464 465 void 466 ahci_reset_channel(struct ata_channel *chp, int flags) 467 { 468 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 469 struct ahci_channel *achp = (struct ahci_channel *)chp; 470 471 ahci_channel_stop(sc, chp, flags); 472 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 473 achp->ahcic_sstatus) != SStatus_DET_DEV) { 474 printf("%s: port reset failed\n", AHCINAME(sc)); 475 /* XXX and then ? */ 476 } 477 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 478 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 479 if (chp->ch_queue->active_xfer) { 480 chp->ch_queue->active_xfer->c_kill_xfer(chp, 481 chp->ch_queue->active_xfer, KILL_RESET); 482 } 483 ahci_channel_start(sc, chp); 484 return; 485 } 486 487 int 488 ahci_ata_addref(struct ata_drive_datas *drvp) 489 { 490 return 0; 491 } 492 493 void 494 ahci_ata_delref(struct ata_drive_datas *drvp) 495 { 496 return; 497 } 498 499 void 500 ahci_killpending(struct ata_drive_datas *drvp) 501 { 502 return; 503 } 504 505 void 506 ahci_probe_drive(struct ata_channel *chp) 507 { 508 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 509 struct ahci_channel *achp = (struct ahci_channel *)chp; 510 int i, s; 511 u_int32_t sig; 512 513 /* XXX This should be done by other code. */ 514 for (i = 0; i < chp->ch_ndrive; i++) { 515 chp->ch_drive[i].chnl_softc = chp; 516 chp->ch_drive[i].drive = i; 517 } 518 519 /* bring interface up, power up and spin up device */ 520 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 521 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 522 /* reset the PHY and bring online */ 523 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 524 achp->ahcic_sstatus)) { 525 case SStatus_DET_DEV: 526 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 527 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 528 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 529 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 530 AHCINAME(sc), chp->ch_channel, sig, 531 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 532 /* 533 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 534 * cases we get wrong values here, so ignore it. 535 */ 536 s = splbio(); 537 if ((sig & 0xffff0000) == 0xeb140000) { 538 aprint_error("%s port %d: ATAPI device ignored\n", 539 AHCINAME(sc), chp->ch_channel); 540 chp->ch_drive[0].drive_flags |= 0 /* DRIVE_ATAPI XXX */; 541 } else 542 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 543 splx(s); 544 /* enable interrupts */ 545 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 546 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 547 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 548 AHCI_P_IX_DHRS); 549 /* and start operations */ 550 ahci_channel_start(sc, chp); 551 break; 552 553 default: 554 break; 555 } 556 } 557 558 void 559 ahci_setup_channel(struct ata_channel *chp) 560 { 561 return; 562 } 563 564 int 565 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 566 { 567 struct ata_channel *chp = drvp->chnl_softc; 568 struct ata_xfer *xfer; 569 int ret; 570 int s; 571 572 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 573 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 574 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 575 DEBUG_XFERS); 576 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 577 ATAXF_NOSLEEP); 578 if (xfer == NULL) { 579 return ATACMD_TRY_AGAIN; 580 } 581 if (ata_c->flags & AT_POLL) 582 xfer->c_flags |= C_POLL; 583 if (ata_c->flags & AT_WAIT) 584 xfer->c_flags |= C_WAIT; 585 xfer->c_drive = drvp->drive; 586 xfer->c_databuf = ata_c->data; 587 xfer->c_bcount = ata_c->bcount; 588 xfer->c_cmd = ata_c; 589 xfer->c_start = ahci_cmd_start; 590 xfer->c_intr = ahci_cmd_complete; 591 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 592 s = splbio(); 593 ata_exec_xfer(chp, xfer); 594 #ifdef DIAGNOSTIC 595 if ((ata_c->flags & AT_POLL) != 0 && 596 (ata_c->flags & AT_DONE) == 0) 597 panic("ahci_exec_command: polled command not done"); 598 #endif 599 if (ata_c->flags & AT_DONE) { 600 ret = ATACMD_COMPLETE; 601 } else { 602 if (ata_c->flags & AT_WAIT) { 603 while ((ata_c->flags & AT_DONE) == 0) { 604 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 605 } 606 ret = ATACMD_COMPLETE; 607 } else { 608 ret = ATACMD_QUEUED; 609 } 610 } 611 splx(s); 612 return ret; 613 } 614 615 void 616 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 617 { 618 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 619 struct ahci_channel *achp = (struct ahci_channel *)chp; 620 struct ata_command *ata_c = xfer->c_cmd; 621 int slot = 0 /* XXX slot */; 622 struct ahci_cmd_tbl *cmd_tbl; 623 struct ahci_cmd_header *cmd_h; 624 u_int8_t *fis; 625 int i; 626 int channel = chp->ch_channel; 627 628 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 629 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 630 631 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 632 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 633 cmd_tbl), DEBUG_XFERS); 634 fis = cmd_tbl->cmdt_cfis; 635 636 fis[0] = 0x27; /* host to device */ 637 fis[1] = 0x80; /* command FIS */ 638 fis[2] = ata_c->r_command; 639 fis[3] = ata_c->r_features; 640 fis[4] = ata_c->r_sector; 641 fis[5] = ata_c->r_cyl & 0xff; 642 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 643 fis[7] = ata_c->r_head & 0x0f; 644 fis[8] = 0; 645 fis[9] = 0; 646 fis[10] = 0; 647 fis[11] = 0; 648 fis[12] = ata_c->r_count; 649 fis[13] = 0; 650 fis[14] = 0; 651 fis[15] = WDCTL_4BIT; 652 fis[16] = 0; 653 fis[17] = 0; 654 fis[18] = 0; 655 fis[19] = 0; 656 657 cmd_h = &achp->ahcic_cmdh[slot]; 658 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 659 chp->ch_channel, cmd_h), DEBUG_XFERS); 660 if (ahci_dma_setup(chp, slot, 661 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 662 ata_c->bcount, 663 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 664 ata_c->flags |= AT_DF; 665 ahci_cmd_complete(chp, xfer, slot); 666 return; 667 } 668 cmd_h->cmdh_flags = htole16( 669 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 670 20 /* fis lenght */ / 4); 671 cmd_h->cmdh_prdbc = 0; 672 AHCI_CMDH_SYNC(sc, achp, slot, 673 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 674 675 if (ata_c->flags & AT_POLL) { 676 /* polled command, disable interrupts */ 677 AHCI_WRITE(sc, AHCI_GHC, 678 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 679 } 680 chp->ch_flags |= ATACH_IRQ_WAIT; 681 chp->ch_status = 0; 682 /* start command */ 683 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 684 /* and says we started this command */ 685 achp->ahcic_cmds_active |= 1 << slot; 686 687 if ((ata_c->flags & AT_POLL) == 0) { 688 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 689 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 690 ahci_timeout, chp); 691 return; 692 } 693 /* 694 * Polled command. 695 */ 696 for (i = 0; i < ata_c->timeout / 10; i++) { 697 if (ata_c->flags & AT_DONE) 698 break; 699 ahci_intr_port(sc, achp); 700 if (ata_c->flags & AT_WAIT) 701 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 702 else 703 delay(10000); 704 } 705 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 706 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 707 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 708 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 709 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 710 DEBUG_XFERS); 711 if ((ata_c->flags & AT_DONE) == 0) { 712 ata_c->flags |= AT_TIMEOU; 713 ahci_cmd_complete(chp, xfer, slot); 714 } 715 /* reenable interrupts */ 716 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 717 } 718 719 void 720 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 721 { 722 struct ata_command *ata_c = xfer->c_cmd; 723 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 724 DEBUG_FUNCS); 725 726 switch (reason) { 727 case KILL_GONE: 728 ata_c->flags |= AT_GONE; 729 break; 730 case KILL_RESET: 731 ata_c->flags |= AT_RESET; 732 break; 733 default: 734 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 735 panic("ahci_cmd_kill_xfer"); 736 } 737 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 738 } 739 740 int 741 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 742 { 743 int slot = 0; /* XXX slot */ 744 struct ata_command *ata_c = xfer->c_cmd; 745 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 746 747 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 748 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 749 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 750 DEBUG_FUNCS); 751 chp->ch_flags &= ~ATACH_IRQ_WAIT; 752 if (xfer->c_flags & C_TIMEOU) { 753 ata_c->flags |= AT_TIMEOU; 754 } else 755 callout_stop(&chp->ch_callout); 756 757 chp->ch_queue->active_xfer = NULL; 758 759 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 760 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 761 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 762 wakeup(&chp->ch_queue->active_xfer); 763 return 0; 764 } 765 if (is) { 766 ata_c->r_head = 0; 767 ata_c->r_count = 0; 768 ata_c->r_sector = 0; 769 ata_c->r_cyl = 0; 770 if (chp->ch_status & WDCS_BSY) { 771 ata_c->flags |= AT_TIMEOU; 772 } else if (chp->ch_status & WDCS_ERR) { 773 ata_c->r_error = chp->ch_error; 774 ata_c->flags |= AT_ERROR; 775 } 776 } 777 ahci_cmd_done(chp, xfer, slot); 778 return 0; 779 } 780 781 void 782 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 783 { 784 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 785 struct ahci_channel *achp = (struct ahci_channel *)chp; 786 struct ata_command *ata_c = xfer->c_cmd; 787 788 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 789 DEBUG_FUNCS); 790 791 /* this comamnd is not active any more */ 792 achp->ahcic_cmds_active &= ~(1 << slot); 793 794 if (ata_c->flags & (AT_READ|AT_WRITE)) { 795 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 796 achp->ahcic_datad[slot]->dm_mapsize, 797 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 798 BUS_DMASYNC_POSTWRITE); 799 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 800 } 801 802 AHCI_CMDH_SYNC(sc, achp, slot, 803 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 804 805 ata_c->flags |= AT_DONE; 806 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 807 ata_c->flags |= AT_XFDONE; 808 809 ata_free_xfer(chp, xfer); 810 if (ata_c->flags & AT_WAIT) 811 wakeup(ata_c); 812 else if (ata_c->callback) 813 ata_c->callback(ata_c->callback_arg); 814 atastart(chp); 815 return; 816 } 817 818 int 819 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 820 { 821 struct ata_channel *chp = drvp->chnl_softc; 822 struct ata_xfer *xfer; 823 824 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 825 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 826 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 827 DEBUG_XFERS); 828 xfer = ata_get_xfer(ATAXF_NOSLEEP); 829 if (xfer == NULL) { 830 return ATACMD_TRY_AGAIN; 831 } 832 if (ata_bio->flags & ATA_POLL) 833 xfer->c_flags |= C_POLL; 834 xfer->c_drive = drvp->drive; 835 xfer->c_cmd = ata_bio; 836 xfer->c_databuf = ata_bio->databuf; 837 xfer->c_bcount = ata_bio->bcount; 838 xfer->c_start = ahci_bio_start; 839 xfer->c_intr = ahci_bio_complete; 840 xfer->c_kill_xfer = ahci_bio_kill_xfer; 841 ata_exec_xfer(chp, xfer); 842 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 843 } 844 845 void 846 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 847 { 848 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 849 struct ahci_channel *achp = (struct ahci_channel *)chp; 850 struct ata_bio *ata_bio = xfer->c_cmd; 851 int slot = 0 /* XXX slot */; 852 struct ahci_cmd_tbl *cmd_tbl; 853 struct ahci_cmd_header *cmd_h; 854 u_int8_t *fis; 855 int i, nblks; 856 int channel = chp->ch_channel; 857 858 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 859 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 860 861 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 862 863 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 864 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 865 cmd_tbl), DEBUG_XFERS); 866 fis = cmd_tbl->cmdt_cfis; 867 868 fis[0] = 0x27; /* host to device */ 869 fis[1] = 0x80; /* command FIS */ 870 if (ata_bio->flags & ATA_LBA48) { 871 fis[2] = (ata_bio->flags & ATA_READ) ? 872 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 873 } else { 874 fis[2] = 875 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 876 } 877 fis[3] = 0; /* features */ 878 fis[4] = ata_bio->blkno & 0xff; 879 fis[5] = (ata_bio->blkno >> 8) & 0xff; 880 fis[6] = (ata_bio->blkno >> 16) & 0xff; 881 if (ata_bio->flags & ATA_LBA48) { 882 fis[7] = WDSD_LBA; 883 fis[8] = (ata_bio->blkno >> 24) & 0xff; 884 fis[9] = (ata_bio->blkno >> 32) & 0xff; 885 fis[10] = (ata_bio->blkno >> 40) & 0xff; 886 } else { 887 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 888 fis[8] = 0; 889 fis[9] = 0; 890 fis[10] = 0; 891 } 892 fis[11] = 0; /* ext features */ 893 fis[12] = nblks & 0xff; 894 fis[13] = (ata_bio->flags & ATA_LBA48) ? 895 ((nblks >> 8) & 0xff) : 0; 896 fis[14] = 0; 897 fis[15] = WDCTL_4BIT; 898 fis[16] = 0; 899 fis[17] = 0; 900 fis[18] = 0; 901 fis[19] = 0; 902 903 cmd_h = &achp->ahcic_cmdh[slot]; 904 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 905 chp->ch_channel, cmd_h), DEBUG_XFERS); 906 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 907 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 908 ata_bio->error = ERR_DMA; 909 ata_bio->r_error = 0; 910 ahci_bio_complete(chp, xfer, slot); 911 return; 912 } 913 cmd_h->cmdh_flags = htole16( 914 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 915 20 /* fis lenght */ / 4); 916 cmd_h->cmdh_prdbc = 0; 917 AHCI_CMDH_SYNC(sc, achp, slot, 918 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 919 920 if (xfer->c_flags & C_POLL) { 921 /* polled command, disable interrupts */ 922 AHCI_WRITE(sc, AHCI_GHC, 923 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 924 } 925 chp->ch_flags |= ATACH_IRQ_WAIT; 926 chp->ch_status = 0; 927 /* start command */ 928 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 929 /* and says we started this command */ 930 achp->ahcic_cmds_active |= 1 << slot; 931 932 if ((xfer->c_flags & C_POLL) == 0) { 933 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 934 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 935 ahci_timeout, chp); 936 return; 937 } 938 /* 939 * Polled command. 940 */ 941 for (i = 0; i < ATA_DELAY / 10; i++) { 942 if (ata_bio->flags & ATA_ITSDONE) 943 break; 944 ahci_intr_port(sc, achp); 945 if (ata_bio->flags & ATA_NOSLEEP) 946 delay(10000); 947 else 948 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 949 } 950 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 951 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 952 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 953 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 954 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 955 DEBUG_XFERS); 956 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 957 ata_bio->error = TIMEOUT; 958 ahci_bio_complete(chp, xfer, slot); 959 } 960 /* reenable interrupts */ 961 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 962 } 963 964 void 965 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 966 { 967 int slot = 0; /* XXX slot */ 968 int drive = xfer->c_drive; 969 struct ata_bio *ata_bio = xfer->c_cmd; 970 struct ahci_channel *achp = (struct ahci_channel *)chp; 971 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 972 DEBUG_FUNCS); 973 974 achp->ahcic_cmds_active &= ~(1 << slot); 975 ata_free_xfer(chp, xfer); 976 ata_bio->flags |= ATA_ITSDONE; 977 switch (reason) { 978 case KILL_GONE: 979 ata_bio->error = ERR_NODEV; 980 break; 981 case KILL_RESET: 982 ata_bio->error = ERR_RESET; 983 break; 984 default: 985 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 986 panic("ahci_bio_kill_xfer"); 987 } 988 ata_bio->r_error = WDCE_ABRT; 989 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 990 } 991 992 int 993 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 994 { 995 int slot = 0; /* XXX slot */ 996 struct ata_bio *ata_bio = xfer->c_cmd; 997 int drive = xfer->c_drive; 998 struct ahci_channel *achp = (struct ahci_channel *)chp; 999 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1000 1001 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1002 DEBUG_FUNCS); 1003 1004 achp->ahcic_cmds_active &= ~(1 << slot); 1005 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1006 if (xfer->c_flags & C_TIMEOU) { 1007 ata_bio->error = TIMEOUT; 1008 } else { 1009 callout_stop(&chp->ch_callout); 1010 ata_bio->error = 0; 1011 } 1012 1013 chp->ch_queue->active_xfer = NULL; 1014 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1015 achp->ahcic_datad[slot]->dm_mapsize, 1016 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1017 BUS_DMASYNC_POSTWRITE); 1018 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1019 1020 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1021 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1022 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1023 wakeup(&chp->ch_queue->active_xfer); 1024 return 0; 1025 } 1026 ata_free_xfer(chp, xfer); 1027 ata_bio->flags |= ATA_ITSDONE; 1028 if (chp->ch_status & WDCS_DWF) { 1029 ata_bio->error = ERR_DF; 1030 } else if (chp->ch_status & WDCS_ERR) { 1031 ata_bio->error = ERROR; 1032 ata_bio->r_error = chp->ch_error; 1033 } else if (chp->ch_status & WDCS_CORR) 1034 ata_bio->flags |= ATA_CORR; 1035 1036 AHCI_CMDH_SYNC(sc, achp, slot, 1037 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1038 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1039 ata_bio->bcount), DEBUG_XFERS); 1040 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1041 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1042 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1043 atastart(chp); 1044 return 0; 1045 } 1046 1047 void 1048 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1049 { 1050 int i; 1051 /* stop channel */ 1052 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1053 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1054 /* wait 1s for channel to stop */ 1055 for (i = 0; i <100; i++) { 1056 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1057 == 0) 1058 break; 1059 if (flags & AT_WAIT) 1060 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1061 else 1062 delay(10000); 1063 } 1064 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1065 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1066 /* XXX controller reset ? */ 1067 return; 1068 } 1069 } 1070 1071 void 1072 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1073 { 1074 /* clear error */ 1075 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1076 1077 /* and start controller */ 1078 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1079 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1080 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1081 } 1082 1083 void 1084 ahci_timeout(void *v) 1085 { 1086 struct ata_channel *chp = (struct ata_channel *)v; 1087 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1088 int s = splbio(); 1089 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1090 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1091 xfer->c_flags |= C_TIMEOU; 1092 xfer->c_intr(chp, xfer, 0); 1093 } 1094 splx(s); 1095 } 1096 1097 int 1098 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1099 size_t count, int op) 1100 { 1101 int error, seg; 1102 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1103 struct ahci_channel *achp = (struct ahci_channel *)chp; 1104 struct ahci_cmd_tbl *cmd_tbl; 1105 struct ahci_cmd_header *cmd_h; 1106 1107 cmd_h = &achp->ahcic_cmdh[slot]; 1108 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1109 1110 if (data == NULL) { 1111 cmd_h->cmdh_prdtl = 0; 1112 goto end; 1113 } 1114 1115 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1116 data, count, NULL, 1117 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1118 if (error) { 1119 printf("%s port %d: failed to load xfer: %d\n", 1120 AHCINAME(sc), chp->ch_channel, error); 1121 return error; 1122 } 1123 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1124 achp->ahcic_datad[slot]->dm_mapsize, 1125 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1126 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1127 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1128 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1129 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1130 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1131 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1132 } 1133 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1134 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1135 end: 1136 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1137 return 0; 1138 } 1139
Indexes created Tue Sep 23 01:09:51 GMT 2025