ahcisata_core.c revision 1.70
1 /* $NetBSD: ahcisata_core.c,v 1.70 2018/11/20 08:47:55 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.70 2018/11/20 08:47:55 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 129 static void ahci_setup_port(struct ahci_softc *sc, int i); 130 131 static void 132 ahci_enable(struct ahci_softc *sc) 133 { 134 uint32_t ghc; 135 136 ghc = AHCI_READ(sc, AHCI_GHC); 137 if (!(ghc & AHCI_GHC_AE)) { 138 ghc |= AHCI_GHC_AE; 139 AHCI_WRITE(sc, AHCI_GHC, ghc); 140 } 141 } 142 143 static int 144 ahci_reset(struct ahci_softc *sc) 145 { 146 int i; 147 148 /* reset controller */ 149 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 150 /* wait up to 1s for reset to complete */ 151 for (i = 0; i < 1000; i++) { 152 delay(1000); 153 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 154 break; 155 } 156 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 157 aprint_error("%s: reset failed\n", AHCINAME(sc)); 158 return -1; 159 } 160 /* enable ahci mode */ 161 ahci_enable(sc); 162 163 if (sc->sc_save_init_data) { 164 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 165 if (sc->sc_init_data.cap2) 166 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 167 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 168 } 169 170 return 0; 171 } 172 173 static void 174 ahci_setup_ports(struct ahci_softc *sc) 175 { 176 int i, port; 177 178 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 179 if ((sc->sc_ahci_ports & (1U << i)) == 0) 180 continue; 181 if (port >= sc->sc_atac.atac_nchannels) { 182 aprint_error("%s: more ports than announced\n", 183 AHCINAME(sc)); 184 break; 185 } 186 ahci_setup_port(sc, i); 187 port++; 188 } 189 } 190 191 static void 192 ahci_reprobe_drives(struct ahci_softc *sc) 193 { 194 int i, port; 195 struct ahci_channel *achp; 196 struct ata_channel *chp; 197 198 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 199 if ((sc->sc_ahci_ports & (1U << i)) == 0) 200 continue; 201 if (port >= sc->sc_atac.atac_nchannels) { 202 aprint_error("%s: more ports than announced\n", 203 AHCINAME(sc)); 204 break; 205 } 206 achp = &sc->sc_channels[i]; 207 chp = &achp->ata_channel; 208 209 ahci_probe_drive(chp); 210 port++; 211 } 212 } 213 214 static void 215 ahci_setup_port(struct ahci_softc *sc, int i) 216 { 217 struct ahci_channel *achp; 218 219 achp = &sc->sc_channels[i]; 220 221 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 222 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 223 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 224 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 225 } 226 227 static void 228 ahci_enable_intrs(struct ahci_softc *sc) 229 { 230 231 /* clear interrupts */ 232 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 233 /* enable interrupts */ 234 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 235 } 236 237 void 238 ahci_attach(struct ahci_softc *sc) 239 { 240 uint32_t ahci_rev; 241 int i, j, port; 242 struct ahci_channel *achp; 243 struct ata_channel *chp; 244 int error; 245 int dmasize; 246 char buf[128]; 247 void *cmdhp; 248 void *cmdtblp; 249 250 if (sc->sc_save_init_data) { 251 ahci_enable(sc); 252 253 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 254 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 255 256 ahci_rev = AHCI_READ(sc, AHCI_VS); 257 if (AHCI_VS_MJR(ahci_rev) > 1 || 258 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 259 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 260 } else { 261 sc->sc_init_data.cap2 = 0; 262 } 263 if (sc->sc_init_data.ports == 0) { 264 sc->sc_init_data.ports = sc->sc_ahci_ports; 265 } 266 } 267 268 if (ahci_reset(sc) != 0) 269 return; 270 271 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 272 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 273 aprint_verbose_dev(sc->sc_atac.atac_dev, 274 "ignoring broken port multiplier support\n"); 275 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 276 } 277 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 278 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 279 ahci_rev = AHCI_READ(sc, AHCI_VS); 280 snprintb(buf, sizeof(buf), "\177\020" 281 /* "f\000\005NP\0" */ 282 "b\005SXS\0" 283 "b\006EMS\0" 284 "b\007CCCS\0" 285 /* "f\010\005NCS\0" */ 286 "b\015PSC\0" 287 "b\016SSC\0" 288 "b\017PMD\0" 289 "b\020FBSS\0" 290 "b\021SPM\0" 291 "b\022SAM\0" 292 "b\023SNZO\0" 293 "f\024\003ISS\0" 294 "=\001Gen1\0" 295 "=\002Gen2\0" 296 "=\003Gen3\0" 297 "b\030SCLO\0" 298 "b\031SAL\0" 299 "b\032SALP\0" 300 "b\033SSS\0" 301 "b\034SMPS\0" 302 "b\035SSNTF\0" 303 "b\036SNCQ\0" 304 "b\037S64A\0" 305 "\0", sc->sc_ahci_cap); 306 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 307 ", %d port%s, %d slot%s, CAP %s\n", 308 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 309 sc->sc_atac.atac_nchannels, 310 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 311 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 312 313 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 314 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 315 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 316 sc->sc_atac.atac_pio_cap = 4; 317 sc->sc_atac.atac_dma_cap = 2; 318 sc->sc_atac.atac_udma_cap = 6; 319 sc->sc_atac.atac_channels = sc->sc_chanarray; 320 sc->sc_atac.atac_probe = ahci_probe_drive; 321 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 322 sc->sc_atac.atac_set_modes = ahci_setup_channel; 323 #if NATAPIBUS > 0 324 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 325 #endif 326 327 dmasize = 328 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 329 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 330 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 331 if (error) { 332 aprint_error("%s: unable to allocate command header memory" 333 ", error=%d\n", AHCINAME(sc), error); 334 return; 335 } 336 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 337 sc->sc_cmd_hdr_nseg, dmasize, 338 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 339 if (error) { 340 aprint_error("%s: unable to map command header memory" 341 ", error=%d\n", AHCINAME(sc), error); 342 return; 343 } 344 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 345 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 346 if (error) { 347 aprint_error("%s: unable to create command header map" 348 ", error=%d\n", AHCINAME(sc), error); 349 return; 350 } 351 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 352 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 353 if (error) { 354 aprint_error("%s: unable to load command header map" 355 ", error=%d\n", AHCINAME(sc), error); 356 return; 357 } 358 sc->sc_cmd_hdr = cmdhp; 359 360 ahci_enable_intrs(sc); 361 362 if (sc->sc_ahci_ports == 0) { 363 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 364 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 365 DEBUG_PROBE); 366 } 367 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 368 if ((sc->sc_ahci_ports & (1U << i)) == 0) 369 continue; 370 if (port >= sc->sc_atac.atac_nchannels) { 371 aprint_error("%s: more ports than announced\n", 372 AHCINAME(sc)); 373 break; 374 } 375 achp = &sc->sc_channels[i]; 376 chp = &achp->ata_channel; 377 sc->sc_chanarray[i] = chp; 378 chp->ch_channel = i; 379 chp->ch_atac = &sc->sc_atac; 380 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 381 if (chp->ch_queue == NULL) { 382 aprint_error("%s port %d: can't allocate memory for " 383 "command queue", AHCINAME(sc), i); 384 break; 385 } 386 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 387 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 388 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 389 BUS_DMA_NOWAIT); 390 if (error) { 391 aprint_error("%s: unable to allocate command table " 392 "memory, error=%d\n", AHCINAME(sc), error); 393 break; 394 } 395 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 396 achp->ahcic_cmd_tbl_nseg, dmasize, 397 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 398 if (error) { 399 aprint_error("%s: unable to map command table memory" 400 ", error=%d\n", AHCINAME(sc), error); 401 break; 402 } 403 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 404 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 405 if (error) { 406 aprint_error("%s: unable to create command table map" 407 ", error=%d\n", AHCINAME(sc), error); 408 break; 409 } 410 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 411 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 412 if (error) { 413 aprint_error("%s: unable to load command table map" 414 ", error=%d\n", AHCINAME(sc), error); 415 break; 416 } 417 achp->ahcic_cmdh = (struct ahci_cmd_header *) 418 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 419 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 420 AHCI_CMDH_SIZE * port; 421 achp->ahcic_rfis = (struct ahci_r_fis *) 422 ((char *)cmdhp + 423 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 424 AHCI_RFIS_SIZE * port); 425 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 426 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 427 AHCI_RFIS_SIZE * port; 428 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 429 "rfis %p (0x%" PRIx64 ")\n", i, 430 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 431 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 432 DEBUG_PROBE); 433 434 for (j = 0; j < sc->sc_ncmds; j++) { 435 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 436 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 437 achp->ahcic_bus_cmd_tbl[j] = 438 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 439 AHCI_CMDTBL_SIZE * j; 440 achp->ahcic_cmdh[j].cmdh_cmdtba = 441 htole64(achp->ahcic_bus_cmd_tbl[j]); 442 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 443 achp->ahcic_cmd_tbl[j], 444 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 445 /* The xfer DMA map */ 446 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 447 AHCI_NPRD, 0x400000 /* 4MB */, 0, 448 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 449 &achp->ahcic_datad[j]); 450 if (error) { 451 aprint_error("%s: couldn't alloc xfer DMA map, " 452 "error=%d\n", AHCINAME(sc), error); 453 goto end; 454 } 455 } 456 ahci_setup_port(sc, i); 457 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 458 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 459 aprint_error("%s: couldn't map port %d " 460 "sata_status regs\n", AHCINAME(sc), i); 461 break; 462 } 463 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 464 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 465 aprint_error("%s: couldn't map port %d " 466 "sata_control regs\n", AHCINAME(sc), i); 467 break; 468 } 469 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 470 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 471 aprint_error("%s: couldn't map port %d " 472 "sata_error regs\n", AHCINAME(sc), i); 473 break; 474 } 475 ata_channel_attach(chp); 476 port++; 477 end: 478 continue; 479 } 480 } 481 482 void 483 ahci_childdetached(struct ahci_softc *sc, device_t child) 484 { 485 struct ahci_channel *achp; 486 struct ata_channel *chp; 487 488 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 489 achp = &sc->sc_channels[i]; 490 chp = &achp->ata_channel; 491 492 if ((sc->sc_ahci_ports & (1U << i)) == 0) 493 continue; 494 495 if (child == chp->atabus) 496 chp->atabus = NULL; 497 } 498 } 499 500 int 501 ahci_detach(struct ahci_softc *sc, int flags) 502 { 503 struct atac_softc *atac; 504 struct ahci_channel *achp; 505 struct ata_channel *chp; 506 struct scsipi_adapter *adapt; 507 int i, j, port; 508 int error; 509 510 atac = &sc->sc_atac; 511 adapt = &atac->atac_atapi_adapter._generic; 512 513 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 514 achp = &sc->sc_channels[i]; 515 chp = &achp->ata_channel; 516 517 if ((sc->sc_ahci_ports & (1U << i)) == 0) 518 continue; 519 if (port >= sc->sc_atac.atac_nchannels) { 520 aprint_error("%s: more ports than announced\n", 521 AHCINAME(sc)); 522 break; 523 } 524 525 if (chp->atabus != NULL) { 526 if ((error = config_detach(chp->atabus, flags)) != 0) 527 return error; 528 529 KASSERT(chp->atabus == NULL); 530 } 531 532 if (chp->ch_flags & ATACH_DETACHED) 533 continue; 534 535 for (j = 0; j < sc->sc_ncmds; j++) 536 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 537 538 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 539 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 540 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 541 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 542 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 543 achp->ahcic_cmd_tbl_nseg); 544 545 ata_channel_detach(chp); 546 port++; 547 } 548 549 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 550 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 551 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 552 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 553 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 554 555 if (adapt->adapt_refcnt != 0) 556 return EBUSY; 557 558 return 0; 559 } 560 561 void 562 ahci_resume(struct ahci_softc *sc) 563 { 564 ahci_reset(sc); 565 ahci_setup_ports(sc); 566 ahci_reprobe_drives(sc); 567 ahci_enable_intrs(sc); 568 } 569 570 int 571 ahci_intr(void *v) 572 { 573 struct ahci_softc *sc = v; 574 uint32_t is; 575 int i, r = 0; 576 577 while ((is = AHCI_READ(sc, AHCI_IS))) { 578 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 579 DEBUG_INTR); 580 r = 1; 581 AHCI_WRITE(sc, AHCI_IS, is); 582 for (i = 0; i < AHCI_MAX_PORTS; i++) 583 if (is & (1U << i)) 584 ahci_intr_port(sc, &sc->sc_channels[i]); 585 } 586 return r; 587 } 588 589 static void 590 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 591 { 592 uint32_t is, tfd, sact; 593 struct ata_channel *chp = &achp->ata_channel; 594 struct ata_xfer *xfer; 595 int slot = -1; 596 bool recover = false; 597 uint32_t aslots; 598 599 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 600 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 601 602 AHCIDEBUG_PRINT(( 603 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 604 AHCINAME(sc), 605 chp->ch_channel, is, 606 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 607 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 608 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 609 DEBUG_INTR); 610 611 if ((chp->ch_flags & ATACH_NCQ) == 0) { 612 /* Non-NCQ operation */ 613 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 614 } else { 615 /* NCQ operation */ 616 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 617 } 618 619 /* Handle errors */ 620 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 621 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 622 /* Fatal errors */ 623 if (is & AHCI_P_IX_TFES) { 624 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 625 626 if ((chp->ch_flags & ATACH_NCQ) == 0) { 627 /* Slot valid only for Non-NCQ operation */ 628 slot = (AHCI_READ(sc, 629 AHCI_P_CMD(chp->ch_channel)) 630 & AHCI_P_CMD_CCS_MASK) 631 >> AHCI_P_CMD_CCS_SHIFT; 632 } 633 634 AHCIDEBUG_PRINT(( 635 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 636 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 637 DEBUG_INTR); 638 } else { 639 /* mark an error, and set BSY */ 640 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 641 WDCS_ERR | WDCS_BSY; 642 } 643 644 if (is & AHCI_P_IX_IFS) { 645 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 646 AHCINAME(sc), chp->ch_channel, 647 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 648 DEBUG_INTR); 649 } 650 651 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 652 recover = true; 653 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 654 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 655 656 /* D2H Register FIS or Set Device Bits */ 657 if ((tfd & WDCS_ERR) != 0) { 658 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 659 recover = true; 660 661 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 662 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 663 664 } 665 } else { 666 tfd = 0; 667 } 668 669 if (__predict_false(recover)) 670 ata_channel_freeze(chp); 671 672 aslots = ata_queue_active(chp); 673 674 if (slot >= 0) { 675 if ((aslots & __BIT(slot)) != 0 && 676 (sact & __BIT(slot)) == 0) { 677 xfer = ata_queue_hwslot_to_xfer(chp, slot); 678 xfer->ops->c_intr(chp, xfer, tfd); 679 } 680 } else { 681 /* 682 * For NCQ, HBA halts processing when error is notified, 683 * and any further D2H FISes are ignored until the error 684 * condition is cleared. Hence if a command is inactive, 685 * it means it actually already finished successfully. 686 * Note: active slots can change as c_intr() callback 687 * can activate another command(s), so must only process 688 * commands active before we start processing. 689 */ 690 691 for (slot=0; slot < sc->sc_ncmds; slot++) { 692 if ((aslots & __BIT(slot)) != 0 && 693 (sact & __BIT(slot)) == 0) { 694 xfer = ata_queue_hwslot_to_xfer(chp, slot); 695 xfer->ops->c_intr(chp, xfer, tfd); 696 } 697 } 698 } 699 700 if (__predict_false(recover)) { 701 ata_channel_lock(chp); 702 ata_channel_thaw_locked(chp); 703 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 704 ata_channel_unlock(chp); 705 } 706 } 707 708 static void 709 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 710 { 711 struct ata_channel *chp = drvp->chnl_softc; 712 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 713 uint8_t c_slot; 714 715 ata_channel_lock_owned(chp); 716 717 /* get a slot for running the command on */ 718 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 719 panic("%s: %s: failed to get xfer for reset, port %d\n", 720 device_xname(sc->sc_atac.atac_dev), 721 __func__, chp->ch_channel); 722 /* NOTREACHED */ 723 } 724 725 AHCI_WRITE(sc, AHCI_GHC, 726 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 727 ahci_channel_stop(sc, chp, flags); 728 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 729 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 730 731 ata_queue_free_slot(chp, c_slot); 732 } 733 734 /* return error code from ata_bio */ 735 static int 736 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 737 { 738 struct ahci_channel *achp = (struct ahci_channel *)chp; 739 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 740 int i; 741 uint32_t is; 742 743 /* 744 * Base timeout is specified in ms. 745 * If we are allowed to sleep, wait a tick each round. 746 * Otherwise delay for 10ms on each round. 747 */ 748 if (flags & AT_WAIT) 749 timeout = MAX(1, mstohz(timeout)); 750 else 751 timeout = timeout / 10; 752 753 AHCI_CMDH_SYNC(sc, achp, slot, 754 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 755 /* start command */ 756 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 757 for (i = 0; i < timeout; i++) { 758 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 759 0) 760 return 0; 761 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 762 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 763 AHCI_P_IX_IFS | 764 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 765 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 766 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 767 /* 768 * we got the D2H FIS anyway, 769 * assume sig is valid. 770 * channel is restarted later 771 */ 772 return ERROR; 773 } 774 aprint_debug("%s port %d: error 0x%x sending FIS\n", 775 AHCINAME(sc), chp->ch_channel, is); 776 return ERR_DF; 777 } 778 ata_delay(chp, 10, "ahcifis", flags); 779 } 780 781 aprint_debug("%s port %d: timeout sending FIS\n", 782 AHCINAME(sc), chp->ch_channel); 783 return TIMEOUT; 784 } 785 786 static int 787 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 788 uint32_t *sigp, uint8_t c_slot) 789 { 790 struct ahci_channel *achp = (struct ahci_channel *)chp; 791 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 792 struct ahci_cmd_tbl *cmd_tbl; 793 struct ahci_cmd_header *cmd_h; 794 int i, error = 0; 795 uint32_t sig; 796 797 ata_channel_lock_owned(chp); 798 799 /* clear port interrupt register */ 800 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 801 /* clear SErrors and start operations */ 802 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 803 /* 804 * issue a command list override to clear BSY. 805 * This is needed if there's a PMP with no drive 806 * on port 0 807 */ 808 ahci_channel_start(sc, chp, flags, 1); 809 } else { 810 /* Can't handle command still running without CLO */ 811 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 812 813 ahci_channel_start(sc, chp, flags, 0); 814 } 815 if (drive > 0) { 816 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 817 } 818 819 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 820 goto skip_reset; 821 822 /* polled command, assume interrupts are disabled */ 823 824 cmd_h = &achp->ahcic_cmdh[c_slot]; 825 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 826 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 827 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 828 cmd_h->cmdh_prdbc = 0; 829 memset(cmd_tbl->cmdt_cfis, 0, 64); 830 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 831 cmd_tbl->cmdt_cfis[rhd_c] = drive; 832 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 833 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 834 case ERR_DF: 835 case TIMEOUT: 836 aprint_error("%s port %d: setting WDCTL_RST failed " 837 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 838 error = EBUSY; 839 goto end; 840 default: 841 break; 842 } 843 844 /* 845 * SATA specification has toggle period for SRST bit of 5 usec. Some 846 * controllers fail to process the SRST clear operation unless 847 * we wait for at least this period between the set and clear commands. 848 */ 849 ata_delay(chp, 10, "ahcirstw", flags); 850 851 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 852 (drive << AHCI_CMDH_F_PMP_SHIFT)); 853 cmd_h->cmdh_prdbc = 0; 854 memset(cmd_tbl->cmdt_cfis, 0, 64); 855 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 856 cmd_tbl->cmdt_cfis[rhd_c] = drive; 857 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 858 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 859 case ERR_DF: 860 case TIMEOUT: 861 aprint_error("%s port %d: clearing WDCTL_RST failed " 862 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 863 error = EBUSY; 864 goto end; 865 default: 866 break; 867 } 868 869 skip_reset: 870 /* 871 * wait 31s for BSY to clear 872 * This should not be needed, but some controllers clear the 873 * command slot before receiving the D2H FIS ... 874 */ 875 for (i = 0; i < AHCI_RST_WAIT; i++) { 876 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 877 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 878 break; 879 ata_delay(chp, 10, "ahcid2h", flags); 880 } 881 if (i == AHCI_RST_WAIT) { 882 aprint_error("%s: BSY never cleared, TD 0x%x\n", 883 AHCINAME(sc), sig); 884 goto end; 885 } 886 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 887 DEBUG_PROBE); 888 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 889 if (sigp) 890 *sigp = sig; 891 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 892 AHCINAME(sc), chp->ch_channel, sig, 893 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 894 end: 895 ahci_channel_stop(sc, chp, flags); 896 ata_delay(chp, 500, "ahcirst", flags); 897 /* clear port interrupt register */ 898 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 899 ahci_channel_start(sc, chp, flags, 900 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 901 return error; 902 } 903 904 static void 905 ahci_reset_channel(struct ata_channel *chp, int flags) 906 { 907 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 908 struct ahci_channel *achp = (struct ahci_channel *)chp; 909 int i, tfd; 910 911 ata_channel_lock_owned(chp); 912 913 ahci_channel_stop(sc, chp, flags); 914 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 915 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 916 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 917 /* XXX and then ? */ 918 } 919 ata_kill_active(chp, KILL_RESET, flags); 920 ata_delay(chp, 500, "ahcirst", flags); 921 /* clear port interrupt register */ 922 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 923 /* clear SErrors and start operations */ 924 ahci_channel_start(sc, chp, flags, 925 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 926 /* wait 31s for BSY to clear */ 927 for (i = 0; i < AHCI_RST_WAIT; i++) { 928 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 929 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 930 break; 931 ata_delay(chp, 10, "ahcid2h", flags); 932 } 933 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 934 aprint_error("%s: BSY never cleared, TD 0x%x\n", 935 AHCINAME(sc), tfd); 936 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 937 DEBUG_PROBE); 938 /* clear port interrupt register */ 939 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 940 941 return; 942 } 943 944 static int 945 ahci_ata_addref(struct ata_drive_datas *drvp) 946 { 947 return 0; 948 } 949 950 static void 951 ahci_ata_delref(struct ata_drive_datas *drvp) 952 { 953 return; 954 } 955 956 static void 957 ahci_killpending(struct ata_drive_datas *drvp) 958 { 959 return; 960 } 961 962 static void 963 ahci_probe_drive(struct ata_channel *chp) 964 { 965 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 966 struct ahci_channel *achp = (struct ahci_channel *)chp; 967 uint32_t sig; 968 uint8_t c_slot; 969 int error; 970 971 ata_channel_lock(chp); 972 973 /* get a slot for running the command on */ 974 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 975 aprint_error_dev(sc->sc_atac.atac_dev, 976 "%s: failed to get xfer port %d\n", 977 __func__, chp->ch_channel); 978 ata_channel_unlock(chp); 979 return; 980 } 981 982 /* bring interface up, accept FISs, power up and spin up device */ 983 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 984 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 985 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 986 /* reset the PHY and bring online */ 987 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 988 achp->ahcic_sstatus, AT_WAIT)) { 989 case SStatus_DET_DEV: 990 ata_delay(chp, 500, "ahcidv", AT_WAIT); 991 992 /* Initial value, used in case the soft reset fails */ 993 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 994 995 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 996 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 997 &sig, c_slot); 998 999 /* If probe for PMP failed, just fallback to drive 0 */ 1000 if (error) { 1001 aprint_error("%s port %d: drive %d reset " 1002 "failing, disabling PMP\n", 1003 AHCINAME(sc), chp->ch_channel, 1004 PMP_PORT_CTL); 1005 1006 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1007 ahci_reset_channel(chp, AT_WAIT); 1008 } 1009 } else { 1010 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1011 } 1012 sata_interpret_sig(chp, 0, sig); 1013 /* if we have a PMP attached, inform the controller */ 1014 if (chp->ch_ndrives > PMP_PORT_CTL && 1015 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1016 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1017 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1018 AHCI_P_CMD_PMA); 1019 } 1020 /* clear port interrupt register */ 1021 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1022 1023 /* and enable interrupts */ 1024 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1025 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1026 AHCI_P_IX_IFS | 1027 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1028 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1029 /* wait 500ms before actually starting operations */ 1030 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1031 break; 1032 1033 default: 1034 break; 1035 } 1036 1037 ata_queue_free_slot(chp, c_slot); 1038 1039 ata_channel_unlock(chp); 1040 } 1041 1042 static void 1043 ahci_setup_channel(struct ata_channel *chp) 1044 { 1045 return; 1046 } 1047 1048 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1049 .c_start = ahci_cmd_start, 1050 .c_poll = ahci_cmd_poll, 1051 .c_abort = ahci_cmd_abort, 1052 .c_intr = ahci_cmd_complete, 1053 .c_kill_xfer = ahci_cmd_kill_xfer, 1054 }; 1055 1056 static int 1057 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1058 { 1059 struct ata_channel *chp = drvp->chnl_softc; 1060 struct ata_command *ata_c = &xfer->c_ata_c; 1061 int ret; 1062 int s; 1063 1064 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1065 chp->ch_channel, 1066 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1067 DEBUG_XFERS); 1068 if (ata_c->flags & AT_POLL) 1069 xfer->c_flags |= C_POLL; 1070 if (ata_c->flags & AT_WAIT) 1071 xfer->c_flags |= C_WAIT; 1072 xfer->c_drive = drvp->drive; 1073 xfer->c_databuf = ata_c->data; 1074 xfer->c_bcount = ata_c->bcount; 1075 xfer->ops = &ahci_cmd_xfer_ops; 1076 s = splbio(); 1077 ata_exec_xfer(chp, xfer); 1078 #ifdef DIAGNOSTIC 1079 if ((ata_c->flags & AT_POLL) != 0 && 1080 (ata_c->flags & AT_DONE) == 0) 1081 panic("ahci_exec_command: polled command not done"); 1082 #endif 1083 if (ata_c->flags & AT_DONE) { 1084 ret = ATACMD_COMPLETE; 1085 } else { 1086 if (ata_c->flags & AT_WAIT) { 1087 ata_wait_cmd(chp, xfer); 1088 ret = ATACMD_COMPLETE; 1089 } else { 1090 ret = ATACMD_QUEUED; 1091 } 1092 } 1093 splx(s); 1094 return ret; 1095 } 1096 1097 static int 1098 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1099 { 1100 struct ahci_softc *sc = AHCI_CH2SC(chp); 1101 struct ahci_channel *achp = (struct ahci_channel *)chp; 1102 struct ata_command *ata_c = &xfer->c_ata_c; 1103 int slot = xfer->c_slot; 1104 struct ahci_cmd_tbl *cmd_tbl; 1105 struct ahci_cmd_header *cmd_h; 1106 1107 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1108 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1109 ata_c->timeout, slot), 1110 DEBUG_XFERS); 1111 1112 ata_channel_lock_owned(chp); 1113 1114 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1115 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1116 cmd_tbl), DEBUG_XFERS); 1117 1118 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1119 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1120 1121 cmd_h = &achp->ahcic_cmdh[slot]; 1122 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1123 chp->ch_channel, cmd_h), DEBUG_XFERS); 1124 if (ahci_dma_setup(chp, slot, 1125 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1126 ata_c->data : NULL, 1127 ata_c->bcount, 1128 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1129 ata_c->flags |= AT_DF; 1130 return ATASTART_ABORT; 1131 } 1132 cmd_h->cmdh_flags = htole16( 1133 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1134 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1135 cmd_h->cmdh_prdbc = 0; 1136 AHCI_CMDH_SYNC(sc, achp, slot, 1137 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1138 1139 if (ata_c->flags & AT_POLL) { 1140 /* polled command, disable interrupts */ 1141 AHCI_WRITE(sc, AHCI_GHC, 1142 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1143 } 1144 /* start command */ 1145 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1146 1147 if ((ata_c->flags & AT_POLL) == 0) { 1148 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1149 ata_timeout, chp); 1150 return ATASTART_STARTED; 1151 } else 1152 return ATASTART_POLL; 1153 } 1154 1155 static void 1156 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1157 { 1158 struct ahci_softc *sc = AHCI_CH2SC(chp); 1159 struct ahci_channel *achp = (struct ahci_channel *)chp; 1160 1161 ata_channel_lock(chp); 1162 1163 /* 1164 * Polled command. 1165 */ 1166 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1167 if (xfer->c_ata_c.flags & AT_DONE) 1168 break; 1169 ata_channel_unlock(chp); 1170 ahci_intr_port(sc, achp); 1171 ata_channel_lock(chp); 1172 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1173 } 1174 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1175 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1176 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1177 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1178 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1179 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1180 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1181 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1182 DEBUG_XFERS); 1183 1184 ata_channel_unlock(chp); 1185 1186 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1187 xfer->c_ata_c.flags |= AT_TIMEOU; 1188 xfer->ops->c_intr(chp, xfer, 0); 1189 } 1190 /* reenable interrupts */ 1191 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1192 } 1193 1194 static void 1195 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1196 { 1197 ahci_cmd_complete(chp, xfer, 0); 1198 } 1199 1200 static void 1201 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1202 { 1203 struct ata_command *ata_c = &xfer->c_ata_c; 1204 bool deactivate = true; 1205 1206 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1207 DEBUG_FUNCS); 1208 1209 switch (reason) { 1210 case KILL_GONE_INACTIVE: 1211 deactivate = false; 1212 /* FALLTHROUGH */ 1213 case KILL_GONE: 1214 ata_c->flags |= AT_GONE; 1215 break; 1216 case KILL_RESET: 1217 ata_c->flags |= AT_RESET; 1218 break; 1219 case KILL_REQUEUE: 1220 panic("%s: not supposed to be requeued\n", __func__); 1221 break; 1222 default: 1223 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1224 panic("ahci_cmd_kill_xfer"); 1225 } 1226 1227 ahci_cmd_done_end(chp, xfer); 1228 1229 if (deactivate) 1230 ata_deactivate_xfer(chp, xfer); 1231 } 1232 1233 static int 1234 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1235 { 1236 struct ata_command *ata_c = &xfer->c_ata_c; 1237 struct ahci_channel *achp = (struct ahci_channel *)chp; 1238 1239 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1240 chp->ch_channel, 1241 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1242 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1243 DEBUG_FUNCS); 1244 1245 if (ata_waitdrain_xfer_check(chp, xfer)) 1246 return 0; 1247 1248 if (xfer->c_flags & C_TIMEOU) { 1249 ata_c->flags |= AT_TIMEOU; 1250 } 1251 1252 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1253 ata_c->flags |= AT_TIMEOU; 1254 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1255 ata_c->r_error = AHCI_TFD_ERR(tfd); 1256 ata_c->flags |= AT_ERROR; 1257 } 1258 1259 if (ata_c->flags & AT_READREG) 1260 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1261 1262 ahci_cmd_done(chp, xfer); 1263 1264 ata_deactivate_xfer(chp, xfer); 1265 1266 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1267 atastart(chp); 1268 1269 return 0; 1270 } 1271 1272 static void 1273 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1274 { 1275 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1276 struct ahci_channel *achp = (struct ahci_channel *)chp; 1277 struct ata_command *ata_c = &xfer->c_ata_c; 1278 uint16_t *idwordbuf; 1279 int i; 1280 1281 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1282 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1283 1284 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1285 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1286 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1287 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1288 BUS_DMASYNC_POSTWRITE); 1289 bus_dmamap_unload(sc->sc_dmat, map); 1290 } 1291 1292 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1293 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1294 1295 /* ata(4) expects IDENTIFY data to be in host endianess */ 1296 if (ata_c->r_command == WDCC_IDENTIFY || 1297 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1298 idwordbuf = xfer->c_databuf; 1299 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1300 idwordbuf[i] = le16toh(idwordbuf[i]); 1301 } 1302 } 1303 1304 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1305 ata_c->flags |= AT_XFDONE; 1306 1307 ahci_cmd_done_end(chp, xfer); 1308 } 1309 1310 static void 1311 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1312 { 1313 struct ata_command *ata_c = &xfer->c_ata_c; 1314 1315 ata_c->flags |= AT_DONE; 1316 } 1317 1318 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1319 .c_start = ahci_bio_start, 1320 .c_poll = ahci_bio_poll, 1321 .c_abort = ahci_bio_abort, 1322 .c_intr = ahci_bio_complete, 1323 .c_kill_xfer = ahci_bio_kill_xfer, 1324 }; 1325 1326 static int 1327 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1328 { 1329 struct ata_channel *chp = drvp->chnl_softc; 1330 struct ata_bio *ata_bio = &xfer->c_bio; 1331 1332 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1333 chp->ch_channel, 1334 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1335 DEBUG_XFERS); 1336 if (ata_bio->flags & ATA_POLL) 1337 xfer->c_flags |= C_POLL; 1338 xfer->c_drive = drvp->drive; 1339 xfer->c_databuf = ata_bio->databuf; 1340 xfer->c_bcount = ata_bio->bcount; 1341 xfer->ops = &ahci_bio_xfer_ops; 1342 ata_exec_xfer(chp, xfer); 1343 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1344 } 1345 1346 static int 1347 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1348 { 1349 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1350 struct ahci_channel *achp = (struct ahci_channel *)chp; 1351 struct ata_bio *ata_bio = &xfer->c_bio; 1352 struct ahci_cmd_tbl *cmd_tbl; 1353 struct ahci_cmd_header *cmd_h; 1354 1355 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1356 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1357 1358 ata_channel_lock_owned(chp); 1359 1360 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1361 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1362 cmd_tbl), DEBUG_XFERS); 1363 1364 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1365 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1366 1367 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1368 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1369 chp->ch_channel, cmd_h), DEBUG_XFERS); 1370 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1371 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1372 ata_bio->error = ERR_DMA; 1373 ata_bio->r_error = 0; 1374 return ATASTART_ABORT; 1375 } 1376 cmd_h->cmdh_flags = htole16( 1377 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1378 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1379 cmd_h->cmdh_prdbc = 0; 1380 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1381 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1382 1383 if (xfer->c_flags & C_POLL) { 1384 /* polled command, disable interrupts */ 1385 AHCI_WRITE(sc, AHCI_GHC, 1386 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1387 } 1388 if (xfer->c_flags & C_NCQ) 1389 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1390 /* start command */ 1391 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1392 1393 if ((xfer->c_flags & C_POLL) == 0) { 1394 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1395 ata_timeout, chp); 1396 return ATASTART_STARTED; 1397 } else 1398 return ATASTART_POLL; 1399 } 1400 1401 static void 1402 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1403 { 1404 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1405 struct ahci_channel *achp = (struct ahci_channel *)chp; 1406 1407 /* 1408 * Polled command. 1409 */ 1410 for (int i = 0; i < ATA_DELAY * 10; i++) { 1411 if (xfer->c_bio.flags & ATA_ITSDONE) 1412 break; 1413 ahci_intr_port(sc, achp); 1414 delay(100); 1415 } 1416 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1417 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1418 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1419 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1420 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1421 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1422 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1423 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1424 DEBUG_XFERS); 1425 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1426 xfer->c_bio.error = TIMEOUT; 1427 xfer->ops->c_intr(chp, xfer, 0); 1428 } 1429 /* reenable interrupts */ 1430 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1431 } 1432 1433 static void 1434 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1435 { 1436 ahci_bio_complete(chp, xfer, 0); 1437 } 1438 1439 static void 1440 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1441 { 1442 int drive = xfer->c_drive; 1443 struct ata_bio *ata_bio = &xfer->c_bio; 1444 bool deactivate = true; 1445 1446 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1447 DEBUG_FUNCS); 1448 1449 ata_bio->flags |= ATA_ITSDONE; 1450 switch (reason) { 1451 case KILL_GONE_INACTIVE: 1452 deactivate = false; 1453 /* FALLTHROUGH */ 1454 case KILL_GONE: 1455 ata_bio->error = ERR_NODEV; 1456 break; 1457 case KILL_RESET: 1458 ata_bio->error = ERR_RESET; 1459 break; 1460 case KILL_REQUEUE: 1461 ata_bio->error = REQUEUE; 1462 break; 1463 default: 1464 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1465 panic("ahci_bio_kill_xfer"); 1466 } 1467 ata_bio->r_error = WDCE_ABRT; 1468 1469 if (deactivate) 1470 ata_deactivate_xfer(chp, xfer); 1471 1472 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1473 } 1474 1475 static int 1476 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1477 { 1478 struct ata_bio *ata_bio = &xfer->c_bio; 1479 int drive = xfer->c_drive; 1480 struct ahci_channel *achp = (struct ahci_channel *)chp; 1481 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1482 1483 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1484 DEBUG_FUNCS); 1485 1486 if (ata_waitdrain_xfer_check(chp, xfer)) 1487 return 0; 1488 1489 if (xfer->c_flags & C_TIMEOU) { 1490 ata_bio->error = TIMEOUT; 1491 } 1492 1493 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1494 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1495 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1496 BUS_DMASYNC_POSTWRITE); 1497 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1498 1499 ata_bio->flags |= ATA_ITSDONE; 1500 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1501 ata_bio->error = ERR_DF; 1502 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1503 ata_bio->error = ERROR; 1504 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1505 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1506 ata_bio->flags |= ATA_CORR; 1507 1508 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1509 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1510 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1511 ata_bio->bcount), DEBUG_XFERS); 1512 /* 1513 * If it was a write, complete data buffer may have been transfered 1514 * before error detection; in this case don't use cmdh_prdbc 1515 * as it won't reflect what was written to media. Assume nothing 1516 * was transfered and leave bcount as-is. 1517 * For queued commands, PRD Byte Count should not be used, and is 1518 * not required to be valid; in that case underflow is always illegal. 1519 */ 1520 if ((xfer->c_flags & C_NCQ) != 0) { 1521 if (ata_bio->error == NOERROR) 1522 ata_bio->bcount = 0; 1523 } else { 1524 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1525 ata_bio->bcount -= 1526 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1527 } 1528 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1529 1530 ata_deactivate_xfer(chp, xfer); 1531 1532 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1533 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1534 atastart(chp); 1535 return 0; 1536 } 1537 1538 static void 1539 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1540 { 1541 int i; 1542 /* stop channel */ 1543 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1544 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1545 /* wait 1s for channel to stop */ 1546 for (i = 0; i <100; i++) { 1547 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1548 == 0) 1549 break; 1550 ata_delay(chp, 10, "ahcistop", flags); 1551 } 1552 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1553 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1554 /* XXX controller reset ? */ 1555 return; 1556 } 1557 1558 if (sc->sc_channel_stop) 1559 sc->sc_channel_stop(sc, chp); 1560 } 1561 1562 static void 1563 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1564 int flags, int clo) 1565 { 1566 int i; 1567 uint32_t p_cmd; 1568 /* clear error */ 1569 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1570 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1571 1572 if (clo) { 1573 /* issue command list override */ 1574 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1575 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1576 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1577 /* wait 1s for AHCI_CAP_CLO to clear */ 1578 for (i = 0; i <100; i++) { 1579 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1580 AHCI_P_CMD_CLO) == 0) 1581 break; 1582 ata_delay(chp, 10, "ahciclo", flags); 1583 } 1584 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1585 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1586 /* XXX controller reset ? */ 1587 return; 1588 } 1589 } 1590 1591 if (sc->sc_channel_start) 1592 sc->sc_channel_start(sc, chp); 1593 1594 /* and start controller */ 1595 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1596 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1597 if (chp->ch_ndrives > PMP_PORT_CTL && 1598 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1599 p_cmd |= AHCI_P_CMD_PMA; 1600 } 1601 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1602 } 1603 1604 /* Recover channel after command failure */ 1605 static void 1606 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1607 { 1608 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1609 int drive = ATACH_NODRIVE; 1610 bool reset = false; 1611 1612 ata_channel_lock_owned(chp); 1613 1614 /* 1615 * Read FBS to get the drive which caused the error, if PM is in use. 1616 * According to AHCI 1.3 spec, this register is available regardless 1617 * if FIS-based switching (FBSS) feature is supported, or disabled. 1618 * If FIS-based switching is not in use, it merely maintains single 1619 * pair of DRQ/BSY state, but it is enough since in that case we 1620 * never issue commands for more than one device at the time anyway. 1621 * XXX untested 1622 */ 1623 if (chp->ch_ndrives > PMP_PORT_CTL) { 1624 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1625 if (fbs & AHCI_P_FBS_SDE) { 1626 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1627 1628 /* 1629 * Tell HBA to reset PM port X (value in DWE) state, 1630 * and resume processing commands for other ports. 1631 */ 1632 fbs |= AHCI_P_FBS_DEC; 1633 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1634 for (int i = 0; i < 1000; i++) { 1635 fbs = AHCI_READ(sc, 1636 AHCI_P_FBS(chp->ch_channel)); 1637 if ((fbs & AHCI_P_FBS_DEC) == 0) 1638 break; 1639 DELAY(1000); 1640 } 1641 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1642 /* follow non-device specific recovery */ 1643 drive = ATACH_NODRIVE; 1644 reset = true; 1645 } 1646 } else { 1647 /* not device specific, reset channel */ 1648 drive = ATACH_NODRIVE; 1649 reset = true; 1650 } 1651 } else 1652 drive = 0; 1653 1654 /* 1655 * If BSY or DRQ bits are set, must execute COMRESET to return 1656 * device to idle state. If drive is idle, it's enough to just 1657 * reset CMD.ST, it's not necessary to do software reset. 1658 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1659 * to unblock device processing if COMRESET was not done. 1660 */ 1661 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1662 ahci_reset_channel(chp, flags); 1663 goto out; 1664 } 1665 1666 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1667 ahci_channel_stop(sc, chp, flags); 1668 ahci_channel_start(sc, chp, flags, 1669 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1670 1671 ata_recovery_resume(chp, drive, tfd, flags); 1672 1673 out: 1674 /* Drive unblocked, back to normal operation */ 1675 return; 1676 } 1677 1678 static int 1679 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1680 size_t count, int op) 1681 { 1682 int error, seg; 1683 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1684 struct ahci_channel *achp = (struct ahci_channel *)chp; 1685 struct ahci_cmd_tbl *cmd_tbl; 1686 struct ahci_cmd_header *cmd_h; 1687 1688 cmd_h = &achp->ahcic_cmdh[slot]; 1689 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1690 1691 if (data == NULL) { 1692 cmd_h->cmdh_prdtl = 0; 1693 goto end; 1694 } 1695 1696 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1697 data, count, NULL, 1698 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1699 if (error) { 1700 printf("%s port %d: failed to load xfer: %d\n", 1701 AHCINAME(sc), chp->ch_channel, error); 1702 return error; 1703 } 1704 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1705 achp->ahcic_datad[slot]->dm_mapsize, 1706 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1707 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1708 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1709 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1710 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1711 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1712 } 1713 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1714 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1715 end: 1716 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1717 return 0; 1718 } 1719 1720 #if NATAPIBUS > 0 1721 static void 1722 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1723 { 1724 struct ata_channel *chp = ata_sc->sc_chan; 1725 struct atac_softc *atac = chp->ch_atac; 1726 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1727 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1728 /* 1729 * Fill in the scsipi_adapter. 1730 */ 1731 adapt->adapt_dev = atac->atac_dev; 1732 adapt->adapt_nchannels = atac->atac_nchannels; 1733 adapt->adapt_request = ahci_atapi_scsipi_request; 1734 adapt->adapt_minphys = ahci_atapi_minphys; 1735 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1736 1737 /* 1738 * Fill in the scsipi_channel. 1739 */ 1740 memset(chan, 0, sizeof(*chan)); 1741 chan->chan_adapter = adapt; 1742 chan->chan_bustype = &ahci_atapi_bustype; 1743 chan->chan_channel = chp->ch_channel; 1744 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1745 chan->chan_openings = 1; 1746 chan->chan_max_periph = 1; 1747 chan->chan_ntargets = 1; 1748 chan->chan_nluns = 1; 1749 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1750 atapiprint); 1751 } 1752 1753 static void 1754 ahci_atapi_minphys(struct buf *bp) 1755 { 1756 if (bp->b_bcount > MAXPHYS) 1757 bp->b_bcount = MAXPHYS; 1758 minphys(bp); 1759 } 1760 1761 /* 1762 * Kill off all pending xfers for a periph. 1763 * 1764 * Must be called at splbio(). 1765 */ 1766 static void 1767 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1768 { 1769 struct atac_softc *atac = 1770 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1771 struct ata_channel *chp = 1772 atac->atac_channels[periph->periph_channel->chan_channel]; 1773 1774 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1775 } 1776 1777 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1778 .c_start = ahci_atapi_start, 1779 .c_poll = ahci_atapi_poll, 1780 .c_abort = ahci_atapi_abort, 1781 .c_intr = ahci_atapi_complete, 1782 .c_kill_xfer = ahci_atapi_kill_xfer, 1783 }; 1784 1785 static void 1786 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1787 scsipi_adapter_req_t req, void *arg) 1788 { 1789 struct scsipi_adapter *adapt = chan->chan_adapter; 1790 struct scsipi_periph *periph; 1791 struct scsipi_xfer *sc_xfer; 1792 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1793 struct atac_softc *atac = &sc->sc_atac; 1794 struct ata_xfer *xfer; 1795 int channel = chan->chan_channel; 1796 int drive, s; 1797 1798 switch (req) { 1799 case ADAPTER_REQ_RUN_XFER: 1800 sc_xfer = arg; 1801 periph = sc_xfer->xs_periph; 1802 drive = periph->periph_target; 1803 if (!device_is_active(atac->atac_dev)) { 1804 sc_xfer->error = XS_DRIVER_STUFFUP; 1805 scsipi_done(sc_xfer); 1806 return; 1807 } 1808 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1809 if (xfer == NULL) { 1810 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1811 scsipi_done(sc_xfer); 1812 return; 1813 } 1814 1815 if (sc_xfer->xs_control & XS_CTL_POLL) 1816 xfer->c_flags |= C_POLL; 1817 xfer->c_drive = drive; 1818 xfer->c_flags |= C_ATAPI; 1819 xfer->c_databuf = sc_xfer->data; 1820 xfer->c_bcount = sc_xfer->datalen; 1821 xfer->ops = &ahci_atapi_xfer_ops; 1822 xfer->c_scsipi = sc_xfer; 1823 xfer->c_atapi.c_dscpoll = 0; 1824 s = splbio(); 1825 ata_exec_xfer(atac->atac_channels[channel], xfer); 1826 #ifdef DIAGNOSTIC 1827 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1828 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1829 panic("ahci_atapi_scsipi_request: polled command " 1830 "not done"); 1831 #endif 1832 splx(s); 1833 return; 1834 default: 1835 /* Not supported, nothing to do. */ 1836 ; 1837 } 1838 } 1839 1840 static int 1841 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1842 { 1843 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1844 struct ahci_channel *achp = (struct ahci_channel *)chp; 1845 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1846 struct ahci_cmd_tbl *cmd_tbl; 1847 struct ahci_cmd_header *cmd_h; 1848 1849 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1850 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1851 1852 ata_channel_lock_owned(chp); 1853 1854 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1855 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1856 cmd_tbl), DEBUG_XFERS); 1857 1858 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1859 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1860 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1861 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1862 1863 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1864 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1865 chp->ch_channel, cmd_h), DEBUG_XFERS); 1866 if (ahci_dma_setup(chp, xfer->c_slot, 1867 sc_xfer->datalen ? sc_xfer->data : NULL, 1868 sc_xfer->datalen, 1869 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1870 BUS_DMA_READ : BUS_DMA_WRITE)) { 1871 sc_xfer->error = XS_DRIVER_STUFFUP; 1872 return ATASTART_ABORT; 1873 } 1874 cmd_h->cmdh_flags = htole16( 1875 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1876 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1877 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1878 cmd_h->cmdh_prdbc = 0; 1879 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1881 1882 if (xfer->c_flags & C_POLL) { 1883 /* polled command, disable interrupts */ 1884 AHCI_WRITE(sc, AHCI_GHC, 1885 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1886 } 1887 /* start command */ 1888 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1889 1890 if ((xfer->c_flags & C_POLL) == 0) { 1891 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1892 ata_timeout, chp); 1893 return ATASTART_STARTED; 1894 } else 1895 return ATASTART_POLL; 1896 } 1897 1898 static void 1899 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1900 { 1901 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1902 struct ahci_channel *achp = (struct ahci_channel *)chp; 1903 1904 /* 1905 * Polled command. 1906 */ 1907 for (int i = 0; i < ATA_DELAY / 10; i++) { 1908 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1909 break; 1910 ahci_intr_port(sc, achp); 1911 delay(10000); 1912 } 1913 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1914 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1915 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1916 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1917 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1918 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1919 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1920 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1921 DEBUG_XFERS); 1922 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1923 xfer->c_scsipi->error = XS_TIMEOUT; 1924 xfer->ops->c_intr(chp, xfer, 0); 1925 } 1926 /* reenable interrupts */ 1927 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1928 } 1929 1930 static void 1931 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1932 { 1933 ahci_atapi_complete(chp, xfer, 0); 1934 } 1935 1936 static int 1937 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1938 { 1939 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1940 struct ahci_channel *achp = (struct ahci_channel *)chp; 1941 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1942 1943 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1944 DEBUG_FUNCS); 1945 1946 if (ata_waitdrain_xfer_check(chp, xfer)) 1947 return 0; 1948 1949 if (xfer->c_flags & C_TIMEOU) { 1950 sc_xfer->error = XS_TIMEOUT; 1951 } 1952 1953 if (xfer->c_bcount > 0) { 1954 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1955 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1956 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1957 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1958 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1959 } 1960 1961 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1962 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1963 sc_xfer->resid = sc_xfer->datalen; 1964 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1965 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1966 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1967 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1968 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1969 sc_xfer->resid == sc_xfer->datalen)) { 1970 sc_xfer->error = XS_SHORTSENSE; 1971 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 1972 if ((sc_xfer->xs_periph->periph_quirks & 1973 PQUIRK_NOSENSE) == 0) { 1974 /* ask scsipi to send a REQUEST_SENSE */ 1975 sc_xfer->error = XS_BUSY; 1976 sc_xfer->status = SCSI_CHECK; 1977 } 1978 } 1979 1980 ata_deactivate_xfer(chp, xfer); 1981 1982 ata_free_xfer(chp, xfer); 1983 scsipi_done(sc_xfer); 1984 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1985 atastart(chp); 1986 return 0; 1987 } 1988 1989 static void 1990 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1991 { 1992 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1993 bool deactivate = true; 1994 1995 /* remove this command from xfer queue */ 1996 switch (reason) { 1997 case KILL_GONE_INACTIVE: 1998 deactivate = false; 1999 /* FALLTHROUGH */ 2000 case KILL_GONE: 2001 sc_xfer->error = XS_DRIVER_STUFFUP; 2002 break; 2003 case KILL_RESET: 2004 sc_xfer->error = XS_RESET; 2005 break; 2006 case KILL_REQUEUE: 2007 sc_xfer->error = XS_REQUEUE; 2008 break; 2009 default: 2010 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2011 panic("ahci_ata_atapi_kill_xfer"); 2012 } 2013 2014 if (deactivate) 2015 ata_deactivate_xfer(chp, xfer); 2016 2017 ata_free_xfer(chp, xfer); 2018 scsipi_done(sc_xfer); 2019 } 2020 2021 static void 2022 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2023 { 2024 struct scsipi_channel *chan = sc->sc_channel; 2025 struct scsipi_periph *periph; 2026 struct ataparams ids; 2027 struct ataparams *id = &ids; 2028 struct ahci_softc *ahcic = 2029 device_private(chan->chan_adapter->adapt_dev); 2030 struct atac_softc *atac = &ahcic->sc_atac; 2031 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2032 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2033 struct scsipibus_attach_args sa; 2034 char serial_number[21], model[41], firmware_revision[9]; 2035 int s; 2036 2037 /* skip if already attached */ 2038 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2039 return; 2040 2041 /* if no ATAPI device detected at attach time, skip */ 2042 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2043 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2044 "not present\n", target), DEBUG_PROBE); 2045 return; 2046 } 2047 2048 /* Some ATAPI devices need a bit more time after software reset. */ 2049 delay(5000); 2050 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2051 #ifdef ATAPI_DEBUG_PROBE 2052 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2053 AHCINAME(ahcic), target, 2054 id->atap_config & ATAPI_CFG_CMD_MASK, 2055 id->atap_config & ATAPI_CFG_DRQ_MASK); 2056 #endif 2057 periph = scsipi_alloc_periph(M_NOWAIT); 2058 if (periph == NULL) { 2059 aprint_error_dev(sc->sc_dev, 2060 "unable to allocate periph for drive %d\n", 2061 target); 2062 return; 2063 } 2064 periph->periph_dev = NULL; 2065 periph->periph_channel = chan; 2066 periph->periph_switch = &atapi_probe_periphsw; 2067 periph->periph_target = target; 2068 periph->periph_lun = 0; 2069 periph->periph_quirks = PQUIRK_ONLYBIG; 2070 2071 #ifdef SCSIPI_DEBUG 2072 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2073 SCSIPI_DEBUG_TARGET == target) 2074 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2075 #endif 2076 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2077 if (id->atap_config & ATAPI_CFG_REMOV) 2078 periph->periph_flags |= PERIPH_REMOVABLE; 2079 if (periph->periph_type == T_SEQUENTIAL) { 2080 s = splbio(); 2081 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2082 splx(s); 2083 } 2084 2085 sa.sa_periph = periph; 2086 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2087 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2088 T_REMOV : T_FIXED; 2089 strnvisx(model, sizeof(model), id->atap_model, 40, 2090 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2091 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2092 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2093 strnvisx(firmware_revision, sizeof(firmware_revision), 2094 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2095 sa.sa_inqbuf.vendor = model; 2096 sa.sa_inqbuf.product = serial_number; 2097 sa.sa_inqbuf.revision = firmware_revision; 2098 2099 /* 2100 * Determine the operating mode capabilities of the device. 2101 */ 2102 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2103 periph->periph_cap |= PERIPH_CAP_CMD16; 2104 /* XXX This is gross. */ 2105 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2106 2107 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2108 2109 if (drvp->drv_softc) 2110 ata_probe_caps(drvp); 2111 else { 2112 s = splbio(); 2113 drvp->drive_type = ATA_DRIVET_NONE; 2114 splx(s); 2115 } 2116 } else { 2117 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2118 "failed for drive %s:%d:%d\n", 2119 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2120 s = splbio(); 2121 drvp->drive_type = ATA_DRIVET_NONE; 2122 splx(s); 2123 } 2124 } 2125 #endif /* NATAPIBUS */ 2126
Indexes created Wed Sep 24 22:09:59 GMT 2025