ahcisata_core.c revision 1.72
1 /* $NetBSD: ahcisata_core.c,v 1.72 2018/12/07 22:22:12 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.72 2018/12/07 22:22:12 jdolecek Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 280 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 281 ahci_rev = AHCI_READ(sc, AHCI_VS); 282 snprintb(buf, sizeof(buf), "\177\020" 283 /* "f\000\005NP\0" */ 284 "b\005SXS\0" 285 "b\006EMS\0" 286 "b\007CCCS\0" 287 /* "f\010\005NCS\0" */ 288 "b\015PSC\0" 289 "b\016SSC\0" 290 "b\017PMD\0" 291 "b\020FBSS\0" 292 "b\021SPM\0" 293 "b\022SAM\0" 294 "b\023SNZO\0" 295 "f\024\003ISS\0" 296 "=\001Gen1\0" 297 "=\002Gen2\0" 298 "=\003Gen3\0" 299 "b\030SCLO\0" 300 "b\031SAL\0" 301 "b\032SALP\0" 302 "b\033SSS\0" 303 "b\034SMPS\0" 304 "b\035SSNTF\0" 305 "b\036SNCQ\0" 306 "b\037S64A\0" 307 "\0", sc->sc_ahci_cap); 308 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 309 ", %d port%s, %d slot%s, CAP %s\n", 310 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 311 sc->sc_atac.atac_nchannels, 312 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 313 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 314 315 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 316 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 317 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 318 sc->sc_atac.atac_pio_cap = 4; 319 sc->sc_atac.atac_dma_cap = 2; 320 sc->sc_atac.atac_udma_cap = 6; 321 sc->sc_atac.atac_channels = sc->sc_chanarray; 322 sc->sc_atac.atac_probe = ahci_probe_drive; 323 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 324 sc->sc_atac.atac_set_modes = ahci_setup_channel; 325 #if NATAPIBUS > 0 326 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 327 #endif 328 329 dmasize = 330 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 331 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 332 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 333 if (error) { 334 aprint_error("%s: unable to allocate command header memory" 335 ", error=%d\n", AHCINAME(sc), error); 336 return; 337 } 338 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 339 sc->sc_cmd_hdr_nseg, dmasize, 340 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 341 if (error) { 342 aprint_error("%s: unable to map command header memory" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 347 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 348 if (error) { 349 aprint_error("%s: unable to create command header map" 350 ", error=%d\n", AHCINAME(sc), error); 351 return; 352 } 353 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 354 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 355 if (error) { 356 aprint_error("%s: unable to load command header map" 357 ", error=%d\n", AHCINAME(sc), error); 358 return; 359 } 360 sc->sc_cmd_hdr = cmdhp; 361 362 ahci_enable_intrs(sc); 363 364 if (sc->sc_ahci_ports == 0) { 365 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 366 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 367 DEBUG_PROBE); 368 } 369 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 370 if ((sc->sc_ahci_ports & (1U << i)) == 0) 371 continue; 372 if (port >= sc->sc_atac.atac_nchannels) { 373 aprint_error("%s: more ports than announced\n", 374 AHCINAME(sc)); 375 break; 376 } 377 378 /* Optional intr establish per active port */ 379 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 380 aprint_error("%s: intr establish hook failed\n", 381 AHCINAME(sc)); 382 break; 383 } 384 385 achp = &sc->sc_channels[i]; 386 chp = &achp->ata_channel; 387 sc->sc_chanarray[i] = chp; 388 chp->ch_channel = i; 389 chp->ch_atac = &sc->sc_atac; 390 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 391 if (chp->ch_queue == NULL) { 392 aprint_error("%s port %d: can't allocate memory for " 393 "command queue", AHCINAME(sc), i); 394 break; 395 } 396 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 397 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 398 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 399 BUS_DMA_NOWAIT); 400 if (error) { 401 aprint_error("%s: unable to allocate command table " 402 "memory, error=%d\n", AHCINAME(sc), error); 403 break; 404 } 405 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 406 achp->ahcic_cmd_tbl_nseg, dmasize, 407 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 408 if (error) { 409 aprint_error("%s: unable to map command table memory" 410 ", error=%d\n", AHCINAME(sc), error); 411 break; 412 } 413 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 414 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 415 if (error) { 416 aprint_error("%s: unable to create command table map" 417 ", error=%d\n", AHCINAME(sc), error); 418 break; 419 } 420 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 421 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 422 if (error) { 423 aprint_error("%s: unable to load command table map" 424 ", error=%d\n", AHCINAME(sc), error); 425 break; 426 } 427 achp->ahcic_cmdh = (struct ahci_cmd_header *) 428 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 429 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 430 AHCI_CMDH_SIZE * port; 431 achp->ahcic_rfis = (struct ahci_r_fis *) 432 ((char *)cmdhp + 433 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 434 AHCI_RFIS_SIZE * port); 435 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 436 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 437 AHCI_RFIS_SIZE * port; 438 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 439 "rfis %p (0x%" PRIx64 ")\n", i, 440 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 441 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 442 DEBUG_PROBE); 443 444 for (j = 0; j < sc->sc_ncmds; j++) { 445 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 446 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 447 achp->ahcic_bus_cmd_tbl[j] = 448 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 449 AHCI_CMDTBL_SIZE * j; 450 achp->ahcic_cmdh[j].cmdh_cmdtba = 451 htole64(achp->ahcic_bus_cmd_tbl[j]); 452 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 453 achp->ahcic_cmd_tbl[j], 454 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 455 /* The xfer DMA map */ 456 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 457 AHCI_NPRD, 0x400000 /* 4MB */, 0, 458 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 459 &achp->ahcic_datad[j]); 460 if (error) { 461 aprint_error("%s: couldn't alloc xfer DMA map, " 462 "error=%d\n", AHCINAME(sc), error); 463 goto end; 464 } 465 } 466 ahci_setup_port(sc, i); 467 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 468 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 469 aprint_error("%s: couldn't map port %d " 470 "sata_status regs\n", AHCINAME(sc), i); 471 break; 472 } 473 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 474 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 475 aprint_error("%s: couldn't map port %d " 476 "sata_control regs\n", AHCINAME(sc), i); 477 break; 478 } 479 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 480 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 481 aprint_error("%s: couldn't map port %d " 482 "sata_error regs\n", AHCINAME(sc), i); 483 break; 484 } 485 ata_channel_attach(chp); 486 port++; 487 end: 488 continue; 489 } 490 } 491 492 void 493 ahci_childdetached(struct ahci_softc *sc, device_t child) 494 { 495 struct ahci_channel *achp; 496 struct ata_channel *chp; 497 498 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 499 achp = &sc->sc_channels[i]; 500 chp = &achp->ata_channel; 501 502 if ((sc->sc_ahci_ports & (1U << i)) == 0) 503 continue; 504 505 if (child == chp->atabus) 506 chp->atabus = NULL; 507 } 508 } 509 510 int 511 ahci_detach(struct ahci_softc *sc, int flags) 512 { 513 struct atac_softc *atac; 514 struct ahci_channel *achp; 515 struct ata_channel *chp; 516 struct scsipi_adapter *adapt; 517 int i, j, port; 518 int error; 519 520 atac = &sc->sc_atac; 521 adapt = &atac->atac_atapi_adapter._generic; 522 523 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 524 achp = &sc->sc_channels[i]; 525 chp = &achp->ata_channel; 526 527 if ((sc->sc_ahci_ports & (1U << i)) == 0) 528 continue; 529 if (port >= sc->sc_atac.atac_nchannels) { 530 aprint_error("%s: more ports than announced\n", 531 AHCINAME(sc)); 532 break; 533 } 534 535 if (chp->atabus != NULL) { 536 if ((error = config_detach(chp->atabus, flags)) != 0) 537 return error; 538 539 KASSERT(chp->atabus == NULL); 540 } 541 542 if (chp->ch_flags & ATACH_DETACHED) 543 continue; 544 545 for (j = 0; j < sc->sc_ncmds; j++) 546 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 547 548 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 549 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 550 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 551 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 552 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 553 achp->ahcic_cmd_tbl_nseg); 554 555 ata_channel_detach(chp); 556 port++; 557 } 558 559 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 560 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 561 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 562 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 563 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 564 565 if (adapt->adapt_refcnt != 0) 566 return EBUSY; 567 568 return 0; 569 } 570 571 void 572 ahci_resume(struct ahci_softc *sc) 573 { 574 ahci_reset(sc); 575 ahci_setup_ports(sc); 576 ahci_reprobe_drives(sc); 577 ahci_enable_intrs(sc); 578 } 579 580 int 581 ahci_intr(void *v) 582 { 583 struct ahci_softc *sc = v; 584 uint32_t is; 585 int i, r = 0; 586 587 while ((is = AHCI_READ(sc, AHCI_IS))) { 588 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 589 DEBUG_INTR); 590 r = 1; 591 AHCI_WRITE(sc, AHCI_IS, is); 592 for (i = 0; i < AHCI_MAX_PORTS; i++) 593 if (is & (1U << i)) 594 ahci_intr_port(&sc->sc_channels[i]); 595 } 596 597 return r; 598 } 599 600 int 601 ahci_intr_port(void *v) 602 { 603 struct ahci_channel *achp = v; 604 struct ata_channel *chp = &achp->ata_channel; 605 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 606 uint32_t is, tfd, sact; 607 struct ata_xfer *xfer; 608 int slot = -1; 609 bool recover = false; 610 uint32_t aslots; 611 612 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 613 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 614 615 AHCIDEBUG_PRINT(( 616 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 617 AHCINAME(sc), 618 chp->ch_channel, is, 619 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 620 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 621 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 622 DEBUG_INTR); 623 624 if ((chp->ch_flags & ATACH_NCQ) == 0) { 625 /* Non-NCQ operation */ 626 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 627 } else { 628 /* NCQ operation */ 629 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 630 } 631 632 /* Handle errors */ 633 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 634 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 635 /* Fatal errors */ 636 if (is & AHCI_P_IX_TFES) { 637 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 638 639 if ((chp->ch_flags & ATACH_NCQ) == 0) { 640 /* Slot valid only for Non-NCQ operation */ 641 slot = (AHCI_READ(sc, 642 AHCI_P_CMD(chp->ch_channel)) 643 & AHCI_P_CMD_CCS_MASK) 644 >> AHCI_P_CMD_CCS_SHIFT; 645 } 646 647 AHCIDEBUG_PRINT(( 648 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 649 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 650 DEBUG_INTR); 651 } else { 652 /* mark an error, and set BSY */ 653 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 654 WDCS_ERR | WDCS_BSY; 655 } 656 657 if (is & AHCI_P_IX_IFS) { 658 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 659 AHCINAME(sc), chp->ch_channel, 660 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 661 DEBUG_INTR); 662 } 663 664 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 665 recover = true; 666 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 667 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 668 669 /* D2H Register FIS or Set Device Bits */ 670 if ((tfd & WDCS_ERR) != 0) { 671 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 672 recover = true; 673 674 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 675 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 676 677 } 678 } else { 679 tfd = 0; 680 } 681 682 if (__predict_false(recover)) 683 ata_channel_freeze(chp); 684 685 aslots = ata_queue_active(chp); 686 687 if (slot >= 0) { 688 if ((aslots & __BIT(slot)) != 0 && 689 (sact & __BIT(slot)) == 0) { 690 xfer = ata_queue_hwslot_to_xfer(chp, slot); 691 xfer->ops->c_intr(chp, xfer, tfd); 692 } 693 } else { 694 /* 695 * For NCQ, HBA halts processing when error is notified, 696 * and any further D2H FISes are ignored until the error 697 * condition is cleared. Hence if a command is inactive, 698 * it means it actually already finished successfully. 699 * Note: active slots can change as c_intr() callback 700 * can activate another command(s), so must only process 701 * commands active before we start processing. 702 */ 703 704 for (slot=0; slot < sc->sc_ncmds; slot++) { 705 if ((aslots & __BIT(slot)) != 0 && 706 (sact & __BIT(slot)) == 0) { 707 xfer = ata_queue_hwslot_to_xfer(chp, slot); 708 xfer->ops->c_intr(chp, xfer, tfd); 709 } 710 } 711 } 712 713 if (__predict_false(recover)) { 714 ata_channel_lock(chp); 715 ata_channel_thaw_locked(chp); 716 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 717 ata_channel_unlock(chp); 718 } 719 720 return 1; 721 } 722 723 static void 724 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 725 { 726 struct ata_channel *chp = drvp->chnl_softc; 727 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 728 uint8_t c_slot; 729 730 ata_channel_lock_owned(chp); 731 732 /* get a slot for running the command on */ 733 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 734 panic("%s: %s: failed to get xfer for reset, port %d\n", 735 device_xname(sc->sc_atac.atac_dev), 736 __func__, chp->ch_channel); 737 /* NOTREACHED */ 738 } 739 740 AHCI_WRITE(sc, AHCI_GHC, 741 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 742 ahci_channel_stop(sc, chp, flags); 743 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 744 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 745 746 ata_queue_free_slot(chp, c_slot); 747 } 748 749 /* return error code from ata_bio */ 750 static int 751 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 752 { 753 struct ahci_channel *achp = (struct ahci_channel *)chp; 754 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 755 int i; 756 uint32_t is; 757 758 /* 759 * Base timeout is specified in ms. 760 * If we are allowed to sleep, wait a tick each round. 761 * Otherwise delay for 10ms on each round. 762 */ 763 if (flags & AT_WAIT) 764 timeout = MAX(1, mstohz(timeout)); 765 else 766 timeout = timeout / 10; 767 768 AHCI_CMDH_SYNC(sc, achp, slot, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 /* start command */ 771 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 772 for (i = 0; i < timeout; i++) { 773 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 774 0) 775 return 0; 776 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 777 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 778 AHCI_P_IX_IFS | 779 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 780 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 781 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 782 /* 783 * we got the D2H FIS anyway, 784 * assume sig is valid. 785 * channel is restarted later 786 */ 787 return ERROR; 788 } 789 aprint_debug("%s port %d: error 0x%x sending FIS\n", 790 AHCINAME(sc), chp->ch_channel, is); 791 return ERR_DF; 792 } 793 ata_delay(chp, 10, "ahcifis", flags); 794 } 795 796 aprint_debug("%s port %d: timeout sending FIS\n", 797 AHCINAME(sc), chp->ch_channel); 798 return TIMEOUT; 799 } 800 801 static int 802 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 803 uint32_t *sigp, uint8_t c_slot) 804 { 805 struct ahci_channel *achp = (struct ahci_channel *)chp; 806 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 807 struct ahci_cmd_tbl *cmd_tbl; 808 struct ahci_cmd_header *cmd_h; 809 int i, error = 0; 810 uint32_t sig; 811 812 ata_channel_lock_owned(chp); 813 814 /* clear port interrupt register */ 815 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 816 /* clear SErrors and start operations */ 817 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 818 /* 819 * issue a command list override to clear BSY. 820 * This is needed if there's a PMP with no drive 821 * on port 0 822 */ 823 ahci_channel_start(sc, chp, flags, 1); 824 } else { 825 /* Can't handle command still running without CLO */ 826 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 827 828 ahci_channel_start(sc, chp, flags, 0); 829 } 830 if (drive > 0) { 831 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 832 } 833 834 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 835 goto skip_reset; 836 837 /* polled command, assume interrupts are disabled */ 838 839 cmd_h = &achp->ahcic_cmdh[c_slot]; 840 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 841 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 842 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 843 cmd_h->cmdh_prdbc = 0; 844 memset(cmd_tbl->cmdt_cfis, 0, 64); 845 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 846 cmd_tbl->cmdt_cfis[rhd_c] = drive; 847 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 848 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 849 case ERR_DF: 850 case TIMEOUT: 851 aprint_error("%s port %d: setting WDCTL_RST failed " 852 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 853 error = EBUSY; 854 goto end; 855 default: 856 break; 857 } 858 859 /* 860 * SATA specification has toggle period for SRST bit of 5 usec. Some 861 * controllers fail to process the SRST clear operation unless 862 * we wait for at least this period between the set and clear commands. 863 */ 864 ata_delay(chp, 10, "ahcirstw", flags); 865 866 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 867 (drive << AHCI_CMDH_F_PMP_SHIFT)); 868 cmd_h->cmdh_prdbc = 0; 869 memset(cmd_tbl->cmdt_cfis, 0, 64); 870 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 871 cmd_tbl->cmdt_cfis[rhd_c] = drive; 872 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 873 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 874 case ERR_DF: 875 case TIMEOUT: 876 aprint_error("%s port %d: clearing WDCTL_RST failed " 877 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 878 error = EBUSY; 879 goto end; 880 default: 881 break; 882 } 883 884 skip_reset: 885 /* 886 * wait 31s for BSY to clear 887 * This should not be needed, but some controllers clear the 888 * command slot before receiving the D2H FIS ... 889 */ 890 for (i = 0; i < AHCI_RST_WAIT; i++) { 891 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 892 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 893 break; 894 ata_delay(chp, 10, "ahcid2h", flags); 895 } 896 if (i == AHCI_RST_WAIT) { 897 aprint_error("%s: BSY never cleared, TD 0x%x\n", 898 AHCINAME(sc), sig); 899 goto end; 900 } 901 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 902 DEBUG_PROBE); 903 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 904 if (sigp) 905 *sigp = sig; 906 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 907 AHCINAME(sc), chp->ch_channel, sig, 908 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 909 end: 910 ahci_channel_stop(sc, chp, flags); 911 ata_delay(chp, 500, "ahcirst", flags); 912 /* clear port interrupt register */ 913 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 914 ahci_channel_start(sc, chp, flags, 915 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 916 return error; 917 } 918 919 static void 920 ahci_reset_channel(struct ata_channel *chp, int flags) 921 { 922 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 923 struct ahci_channel *achp = (struct ahci_channel *)chp; 924 int i, tfd; 925 926 ata_channel_lock_owned(chp); 927 928 ahci_channel_stop(sc, chp, flags); 929 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 930 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 931 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 932 /* XXX and then ? */ 933 } 934 ata_kill_active(chp, KILL_RESET, flags); 935 ata_delay(chp, 500, "ahcirst", flags); 936 /* clear port interrupt register */ 937 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 938 /* clear SErrors and start operations */ 939 ahci_channel_start(sc, chp, flags, 940 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 941 /* wait 31s for BSY to clear */ 942 for (i = 0; i < AHCI_RST_WAIT; i++) { 943 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 944 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 945 break; 946 ata_delay(chp, 10, "ahcid2h", flags); 947 } 948 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 949 aprint_error("%s: BSY never cleared, TD 0x%x\n", 950 AHCINAME(sc), tfd); 951 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 952 DEBUG_PROBE); 953 /* clear port interrupt register */ 954 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 955 956 return; 957 } 958 959 static int 960 ahci_ata_addref(struct ata_drive_datas *drvp) 961 { 962 return 0; 963 } 964 965 static void 966 ahci_ata_delref(struct ata_drive_datas *drvp) 967 { 968 return; 969 } 970 971 static void 972 ahci_killpending(struct ata_drive_datas *drvp) 973 { 974 return; 975 } 976 977 static void 978 ahci_probe_drive(struct ata_channel *chp) 979 { 980 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 981 struct ahci_channel *achp = (struct ahci_channel *)chp; 982 uint32_t sig; 983 uint8_t c_slot; 984 int error; 985 986 ata_channel_lock(chp); 987 988 /* get a slot for running the command on */ 989 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 990 aprint_error_dev(sc->sc_atac.atac_dev, 991 "%s: failed to get xfer port %d\n", 992 __func__, chp->ch_channel); 993 ata_channel_unlock(chp); 994 return; 995 } 996 997 /* bring interface up, accept FISs, power up and spin up device */ 998 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 999 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1000 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1001 /* reset the PHY and bring online */ 1002 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1003 achp->ahcic_sstatus, AT_WAIT)) { 1004 case SStatus_DET_DEV: 1005 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1006 1007 /* Initial value, used in case the soft reset fails */ 1008 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1009 1010 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1011 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1012 &sig, c_slot); 1013 1014 /* If probe for PMP failed, just fallback to drive 0 */ 1015 if (error) { 1016 aprint_error("%s port %d: drive %d reset " 1017 "failed, disabling PMP\n", 1018 AHCINAME(sc), chp->ch_channel, 1019 PMP_PORT_CTL); 1020 1021 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1022 ahci_reset_channel(chp, AT_WAIT); 1023 } 1024 } else { 1025 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1026 } 1027 sata_interpret_sig(chp, 0, sig); 1028 /* if we have a PMP attached, inform the controller */ 1029 if (chp->ch_ndrives > PMP_PORT_CTL && 1030 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1031 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1032 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1033 AHCI_P_CMD_PMA); 1034 } 1035 /* clear port interrupt register */ 1036 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1037 1038 /* and enable interrupts */ 1039 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1040 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1041 AHCI_P_IX_IFS | 1042 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1043 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1044 /* wait 500ms before actually starting operations */ 1045 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1046 break; 1047 1048 default: 1049 break; 1050 } 1051 1052 ata_queue_free_slot(chp, c_slot); 1053 1054 ata_channel_unlock(chp); 1055 } 1056 1057 static void 1058 ahci_setup_channel(struct ata_channel *chp) 1059 { 1060 return; 1061 } 1062 1063 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1064 .c_start = ahci_cmd_start, 1065 .c_poll = ahci_cmd_poll, 1066 .c_abort = ahci_cmd_abort, 1067 .c_intr = ahci_cmd_complete, 1068 .c_kill_xfer = ahci_cmd_kill_xfer, 1069 }; 1070 1071 static int 1072 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1073 { 1074 struct ata_channel *chp = drvp->chnl_softc; 1075 struct ata_command *ata_c = &xfer->c_ata_c; 1076 int ret; 1077 int s; 1078 1079 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1080 chp->ch_channel, 1081 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1082 DEBUG_XFERS); 1083 if (ata_c->flags & AT_POLL) 1084 xfer->c_flags |= C_POLL; 1085 if (ata_c->flags & AT_WAIT) 1086 xfer->c_flags |= C_WAIT; 1087 xfer->c_drive = drvp->drive; 1088 xfer->c_databuf = ata_c->data; 1089 xfer->c_bcount = ata_c->bcount; 1090 xfer->ops = &ahci_cmd_xfer_ops; 1091 s = splbio(); 1092 ata_exec_xfer(chp, xfer); 1093 #ifdef DIAGNOSTIC 1094 if ((ata_c->flags & AT_POLL) != 0 && 1095 (ata_c->flags & AT_DONE) == 0) 1096 panic("ahci_exec_command: polled command not done"); 1097 #endif 1098 if (ata_c->flags & AT_DONE) { 1099 ret = ATACMD_COMPLETE; 1100 } else { 1101 if (ata_c->flags & AT_WAIT) { 1102 ata_wait_cmd(chp, xfer); 1103 ret = ATACMD_COMPLETE; 1104 } else { 1105 ret = ATACMD_QUEUED; 1106 } 1107 } 1108 splx(s); 1109 return ret; 1110 } 1111 1112 static int 1113 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1114 { 1115 struct ahci_softc *sc = AHCI_CH2SC(chp); 1116 struct ahci_channel *achp = (struct ahci_channel *)chp; 1117 struct ata_command *ata_c = &xfer->c_ata_c; 1118 int slot = xfer->c_slot; 1119 struct ahci_cmd_tbl *cmd_tbl; 1120 struct ahci_cmd_header *cmd_h; 1121 1122 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1123 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1124 ata_c->timeout, slot), 1125 DEBUG_XFERS); 1126 1127 ata_channel_lock_owned(chp); 1128 1129 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1130 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1131 cmd_tbl), DEBUG_XFERS); 1132 1133 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1134 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1135 1136 cmd_h = &achp->ahcic_cmdh[slot]; 1137 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1138 chp->ch_channel, cmd_h), DEBUG_XFERS); 1139 if (ahci_dma_setup(chp, slot, 1140 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1141 ata_c->data : NULL, 1142 ata_c->bcount, 1143 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1144 ata_c->flags |= AT_DF; 1145 return ATASTART_ABORT; 1146 } 1147 cmd_h->cmdh_flags = htole16( 1148 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1149 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1150 cmd_h->cmdh_prdbc = 0; 1151 AHCI_CMDH_SYNC(sc, achp, slot, 1152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1153 1154 if (ata_c->flags & AT_POLL) { 1155 /* polled command, disable interrupts */ 1156 AHCI_WRITE(sc, AHCI_GHC, 1157 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1158 } 1159 /* start command */ 1160 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1161 1162 if ((ata_c->flags & AT_POLL) == 0) { 1163 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1164 ata_timeout, chp); 1165 return ATASTART_STARTED; 1166 } else 1167 return ATASTART_POLL; 1168 } 1169 1170 static void 1171 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1172 { 1173 struct ahci_softc *sc = AHCI_CH2SC(chp); 1174 struct ahci_channel *achp = (struct ahci_channel *)chp; 1175 1176 ata_channel_lock(chp); 1177 1178 /* 1179 * Polled command. 1180 */ 1181 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1182 if (xfer->c_ata_c.flags & AT_DONE) 1183 break; 1184 ata_channel_unlock(chp); 1185 ahci_intr_port(achp); 1186 ata_channel_lock(chp); 1187 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1188 } 1189 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1190 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1191 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1192 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1193 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1194 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1195 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1196 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1197 DEBUG_XFERS); 1198 1199 ata_channel_unlock(chp); 1200 1201 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1202 xfer->c_ata_c.flags |= AT_TIMEOU; 1203 xfer->ops->c_intr(chp, xfer, 0); 1204 } 1205 /* reenable interrupts */ 1206 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1207 } 1208 1209 static void 1210 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1211 { 1212 ahci_cmd_complete(chp, xfer, 0); 1213 } 1214 1215 static void 1216 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1217 { 1218 struct ata_command *ata_c = &xfer->c_ata_c; 1219 bool deactivate = true; 1220 1221 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1222 DEBUG_FUNCS); 1223 1224 switch (reason) { 1225 case KILL_GONE_INACTIVE: 1226 deactivate = false; 1227 /* FALLTHROUGH */ 1228 case KILL_GONE: 1229 ata_c->flags |= AT_GONE; 1230 break; 1231 case KILL_RESET: 1232 ata_c->flags |= AT_RESET; 1233 break; 1234 case KILL_REQUEUE: 1235 panic("%s: not supposed to be requeued\n", __func__); 1236 break; 1237 default: 1238 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1239 panic("ahci_cmd_kill_xfer"); 1240 } 1241 1242 ahci_cmd_done_end(chp, xfer); 1243 1244 if (deactivate) 1245 ata_deactivate_xfer(chp, xfer); 1246 } 1247 1248 static int 1249 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1250 { 1251 struct ata_command *ata_c = &xfer->c_ata_c; 1252 struct ahci_channel *achp = (struct ahci_channel *)chp; 1253 1254 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1255 chp->ch_channel, 1256 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1257 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1258 DEBUG_FUNCS); 1259 1260 if (ata_waitdrain_xfer_check(chp, xfer)) 1261 return 0; 1262 1263 if (xfer->c_flags & C_TIMEOU) { 1264 ata_c->flags |= AT_TIMEOU; 1265 } 1266 1267 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1268 ata_c->flags |= AT_TIMEOU; 1269 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1270 ata_c->r_error = AHCI_TFD_ERR(tfd); 1271 ata_c->flags |= AT_ERROR; 1272 } 1273 1274 if (ata_c->flags & AT_READREG) 1275 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1276 1277 ahci_cmd_done(chp, xfer); 1278 1279 ata_deactivate_xfer(chp, xfer); 1280 1281 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1282 atastart(chp); 1283 1284 return 0; 1285 } 1286 1287 static void 1288 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1289 { 1290 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1291 struct ahci_channel *achp = (struct ahci_channel *)chp; 1292 struct ata_command *ata_c = &xfer->c_ata_c; 1293 uint16_t *idwordbuf; 1294 int i; 1295 1296 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1297 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1298 1299 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1300 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1301 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1302 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1303 BUS_DMASYNC_POSTWRITE); 1304 bus_dmamap_unload(sc->sc_dmat, map); 1305 } 1306 1307 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1308 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1309 1310 /* ata(4) expects IDENTIFY data to be in host endianess */ 1311 if (ata_c->r_command == WDCC_IDENTIFY || 1312 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1313 idwordbuf = xfer->c_databuf; 1314 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1315 idwordbuf[i] = le16toh(idwordbuf[i]); 1316 } 1317 } 1318 1319 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1320 ata_c->flags |= AT_XFDONE; 1321 1322 ahci_cmd_done_end(chp, xfer); 1323 } 1324 1325 static void 1326 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1327 { 1328 struct ata_command *ata_c = &xfer->c_ata_c; 1329 1330 ata_c->flags |= AT_DONE; 1331 } 1332 1333 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1334 .c_start = ahci_bio_start, 1335 .c_poll = ahci_bio_poll, 1336 .c_abort = ahci_bio_abort, 1337 .c_intr = ahci_bio_complete, 1338 .c_kill_xfer = ahci_bio_kill_xfer, 1339 }; 1340 1341 static int 1342 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1343 { 1344 struct ata_channel *chp = drvp->chnl_softc; 1345 struct ata_bio *ata_bio = &xfer->c_bio; 1346 1347 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1348 chp->ch_channel, 1349 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1350 DEBUG_XFERS); 1351 if (ata_bio->flags & ATA_POLL) 1352 xfer->c_flags |= C_POLL; 1353 xfer->c_drive = drvp->drive; 1354 xfer->c_databuf = ata_bio->databuf; 1355 xfer->c_bcount = ata_bio->bcount; 1356 xfer->ops = &ahci_bio_xfer_ops; 1357 ata_exec_xfer(chp, xfer); 1358 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1359 } 1360 1361 static int 1362 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1363 { 1364 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1365 struct ahci_channel *achp = (struct ahci_channel *)chp; 1366 struct ata_bio *ata_bio = &xfer->c_bio; 1367 struct ahci_cmd_tbl *cmd_tbl; 1368 struct ahci_cmd_header *cmd_h; 1369 1370 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1371 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1372 1373 ata_channel_lock_owned(chp); 1374 1375 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1376 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1377 cmd_tbl), DEBUG_XFERS); 1378 1379 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1380 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1381 1382 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1383 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1384 chp->ch_channel, cmd_h), DEBUG_XFERS); 1385 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1386 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1387 ata_bio->error = ERR_DMA; 1388 ata_bio->r_error = 0; 1389 return ATASTART_ABORT; 1390 } 1391 cmd_h->cmdh_flags = htole16( 1392 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1393 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1394 cmd_h->cmdh_prdbc = 0; 1395 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1397 1398 if (xfer->c_flags & C_POLL) { 1399 /* polled command, disable interrupts */ 1400 AHCI_WRITE(sc, AHCI_GHC, 1401 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1402 } 1403 if (xfer->c_flags & C_NCQ) 1404 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1405 /* start command */ 1406 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1407 1408 if ((xfer->c_flags & C_POLL) == 0) { 1409 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1410 ata_timeout, chp); 1411 return ATASTART_STARTED; 1412 } else 1413 return ATASTART_POLL; 1414 } 1415 1416 static void 1417 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1418 { 1419 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1420 struct ahci_channel *achp = (struct ahci_channel *)chp; 1421 1422 /* 1423 * Polled command. 1424 */ 1425 for (int i = 0; i < ATA_DELAY * 10; i++) { 1426 if (xfer->c_bio.flags & ATA_ITSDONE) 1427 break; 1428 ahci_intr_port(achp); 1429 delay(100); 1430 } 1431 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1432 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1433 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1434 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1435 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1436 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1437 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1438 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1439 DEBUG_XFERS); 1440 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1441 xfer->c_bio.error = TIMEOUT; 1442 xfer->ops->c_intr(chp, xfer, 0); 1443 } 1444 /* reenable interrupts */ 1445 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1446 } 1447 1448 static void 1449 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1450 { 1451 ahci_bio_complete(chp, xfer, 0); 1452 } 1453 1454 static void 1455 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1456 { 1457 int drive = xfer->c_drive; 1458 struct ata_bio *ata_bio = &xfer->c_bio; 1459 bool deactivate = true; 1460 1461 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1462 DEBUG_FUNCS); 1463 1464 ata_bio->flags |= ATA_ITSDONE; 1465 switch (reason) { 1466 case KILL_GONE_INACTIVE: 1467 deactivate = false; 1468 /* FALLTHROUGH */ 1469 case KILL_GONE: 1470 ata_bio->error = ERR_NODEV; 1471 break; 1472 case KILL_RESET: 1473 ata_bio->error = ERR_RESET; 1474 break; 1475 case KILL_REQUEUE: 1476 ata_bio->error = REQUEUE; 1477 break; 1478 default: 1479 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1480 panic("ahci_bio_kill_xfer"); 1481 } 1482 ata_bio->r_error = WDCE_ABRT; 1483 1484 if (deactivate) 1485 ata_deactivate_xfer(chp, xfer); 1486 1487 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1488 } 1489 1490 static int 1491 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1492 { 1493 struct ata_bio *ata_bio = &xfer->c_bio; 1494 int drive = xfer->c_drive; 1495 struct ahci_channel *achp = (struct ahci_channel *)chp; 1496 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1497 1498 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1499 DEBUG_FUNCS); 1500 1501 if (ata_waitdrain_xfer_check(chp, xfer)) 1502 return 0; 1503 1504 if (xfer->c_flags & C_TIMEOU) { 1505 ata_bio->error = TIMEOUT; 1506 } 1507 1508 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1509 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1510 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1511 BUS_DMASYNC_POSTWRITE); 1512 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1513 1514 ata_bio->flags |= ATA_ITSDONE; 1515 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1516 ata_bio->error = ERR_DF; 1517 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1518 ata_bio->error = ERROR; 1519 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1520 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1521 ata_bio->flags |= ATA_CORR; 1522 1523 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1524 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1525 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1526 ata_bio->bcount), DEBUG_XFERS); 1527 /* 1528 * If it was a write, complete data buffer may have been transfered 1529 * before error detection; in this case don't use cmdh_prdbc 1530 * as it won't reflect what was written to media. Assume nothing 1531 * was transfered and leave bcount as-is. 1532 * For queued commands, PRD Byte Count should not be used, and is 1533 * not required to be valid; in that case underflow is always illegal. 1534 */ 1535 if ((xfer->c_flags & C_NCQ) != 0) { 1536 if (ata_bio->error == NOERROR) 1537 ata_bio->bcount = 0; 1538 } else { 1539 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1540 ata_bio->bcount -= 1541 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1542 } 1543 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1544 1545 ata_deactivate_xfer(chp, xfer); 1546 1547 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1548 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1549 atastart(chp); 1550 return 0; 1551 } 1552 1553 static void 1554 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1555 { 1556 int i; 1557 /* stop channel */ 1558 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1559 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1560 /* wait 1s for channel to stop */ 1561 for (i = 0; i <100; i++) { 1562 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1563 == 0) 1564 break; 1565 ata_delay(chp, 10, "ahcistop", flags); 1566 } 1567 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1568 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1569 /* XXX controller reset ? */ 1570 return; 1571 } 1572 1573 if (sc->sc_channel_stop) 1574 sc->sc_channel_stop(sc, chp); 1575 } 1576 1577 static void 1578 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1579 int flags, int clo) 1580 { 1581 int i; 1582 uint32_t p_cmd; 1583 /* clear error */ 1584 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1585 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1586 1587 if (clo) { 1588 /* issue command list override */ 1589 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1590 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1591 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1592 /* wait 1s for AHCI_CAP_CLO to clear */ 1593 for (i = 0; i <100; i++) { 1594 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1595 AHCI_P_CMD_CLO) == 0) 1596 break; 1597 ata_delay(chp, 10, "ahciclo", flags); 1598 } 1599 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1600 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1601 /* XXX controller reset ? */ 1602 return; 1603 } 1604 } 1605 1606 if (sc->sc_channel_start) 1607 sc->sc_channel_start(sc, chp); 1608 1609 /* and start controller */ 1610 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1611 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1612 if (chp->ch_ndrives > PMP_PORT_CTL && 1613 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1614 p_cmd |= AHCI_P_CMD_PMA; 1615 } 1616 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1617 } 1618 1619 /* Recover channel after command failure */ 1620 static void 1621 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1622 { 1623 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1624 int drive = ATACH_NODRIVE; 1625 bool reset = false; 1626 1627 ata_channel_lock_owned(chp); 1628 1629 /* 1630 * Read FBS to get the drive which caused the error, if PM is in use. 1631 * According to AHCI 1.3 spec, this register is available regardless 1632 * if FIS-based switching (FBSS) feature is supported, or disabled. 1633 * If FIS-based switching is not in use, it merely maintains single 1634 * pair of DRQ/BSY state, but it is enough since in that case we 1635 * never issue commands for more than one device at the time anyway. 1636 * XXX untested 1637 */ 1638 if (chp->ch_ndrives > PMP_PORT_CTL) { 1639 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1640 if (fbs & AHCI_P_FBS_SDE) { 1641 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1642 1643 /* 1644 * Tell HBA to reset PM port X (value in DWE) state, 1645 * and resume processing commands for other ports. 1646 */ 1647 fbs |= AHCI_P_FBS_DEC; 1648 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1649 for (int i = 0; i < 1000; i++) { 1650 fbs = AHCI_READ(sc, 1651 AHCI_P_FBS(chp->ch_channel)); 1652 if ((fbs & AHCI_P_FBS_DEC) == 0) 1653 break; 1654 DELAY(1000); 1655 } 1656 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1657 /* follow non-device specific recovery */ 1658 drive = ATACH_NODRIVE; 1659 reset = true; 1660 } 1661 } else { 1662 /* not device specific, reset channel */ 1663 drive = ATACH_NODRIVE; 1664 reset = true; 1665 } 1666 } else 1667 drive = 0; 1668 1669 /* 1670 * If BSY or DRQ bits are set, must execute COMRESET to return 1671 * device to idle state. If drive is idle, it's enough to just 1672 * reset CMD.ST, it's not necessary to do software reset. 1673 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1674 * to unblock device processing if COMRESET was not done. 1675 */ 1676 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1677 ahci_reset_channel(chp, flags); 1678 goto out; 1679 } 1680 1681 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1682 ahci_channel_stop(sc, chp, flags); 1683 ahci_channel_start(sc, chp, flags, 1684 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1685 1686 ata_recovery_resume(chp, drive, tfd, flags); 1687 1688 out: 1689 /* Drive unblocked, back to normal operation */ 1690 return; 1691 } 1692 1693 static int 1694 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1695 size_t count, int op) 1696 { 1697 int error, seg; 1698 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1699 struct ahci_channel *achp = (struct ahci_channel *)chp; 1700 struct ahci_cmd_tbl *cmd_tbl; 1701 struct ahci_cmd_header *cmd_h; 1702 1703 cmd_h = &achp->ahcic_cmdh[slot]; 1704 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1705 1706 if (data == NULL) { 1707 cmd_h->cmdh_prdtl = 0; 1708 goto end; 1709 } 1710 1711 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1712 data, count, NULL, 1713 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1714 if (error) { 1715 printf("%s port %d: failed to load xfer: %d\n", 1716 AHCINAME(sc), chp->ch_channel, error); 1717 return error; 1718 } 1719 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1720 achp->ahcic_datad[slot]->dm_mapsize, 1721 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1722 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1723 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1724 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1725 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1726 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1727 } 1728 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1729 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1730 end: 1731 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1732 return 0; 1733 } 1734 1735 #if NATAPIBUS > 0 1736 static void 1737 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1738 { 1739 struct ata_channel *chp = ata_sc->sc_chan; 1740 struct atac_softc *atac = chp->ch_atac; 1741 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1742 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1743 /* 1744 * Fill in the scsipi_adapter. 1745 */ 1746 adapt->adapt_dev = atac->atac_dev; 1747 adapt->adapt_nchannels = atac->atac_nchannels; 1748 adapt->adapt_request = ahci_atapi_scsipi_request; 1749 adapt->adapt_minphys = ahci_atapi_minphys; 1750 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1751 1752 /* 1753 * Fill in the scsipi_channel. 1754 */ 1755 memset(chan, 0, sizeof(*chan)); 1756 chan->chan_adapter = adapt; 1757 chan->chan_bustype = &ahci_atapi_bustype; 1758 chan->chan_channel = chp->ch_channel; 1759 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1760 chan->chan_openings = 1; 1761 chan->chan_max_periph = 1; 1762 chan->chan_ntargets = 1; 1763 chan->chan_nluns = 1; 1764 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1765 atapiprint); 1766 } 1767 1768 static void 1769 ahci_atapi_minphys(struct buf *bp) 1770 { 1771 if (bp->b_bcount > MAXPHYS) 1772 bp->b_bcount = MAXPHYS; 1773 minphys(bp); 1774 } 1775 1776 /* 1777 * Kill off all pending xfers for a periph. 1778 * 1779 * Must be called at splbio(). 1780 */ 1781 static void 1782 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1783 { 1784 struct atac_softc *atac = 1785 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1786 struct ata_channel *chp = 1787 atac->atac_channels[periph->periph_channel->chan_channel]; 1788 1789 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1790 } 1791 1792 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1793 .c_start = ahci_atapi_start, 1794 .c_poll = ahci_atapi_poll, 1795 .c_abort = ahci_atapi_abort, 1796 .c_intr = ahci_atapi_complete, 1797 .c_kill_xfer = ahci_atapi_kill_xfer, 1798 }; 1799 1800 static void 1801 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1802 scsipi_adapter_req_t req, void *arg) 1803 { 1804 struct scsipi_adapter *adapt = chan->chan_adapter; 1805 struct scsipi_periph *periph; 1806 struct scsipi_xfer *sc_xfer; 1807 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1808 struct atac_softc *atac = &sc->sc_atac; 1809 struct ata_xfer *xfer; 1810 int channel = chan->chan_channel; 1811 int drive, s; 1812 1813 switch (req) { 1814 case ADAPTER_REQ_RUN_XFER: 1815 sc_xfer = arg; 1816 periph = sc_xfer->xs_periph; 1817 drive = periph->periph_target; 1818 if (!device_is_active(atac->atac_dev)) { 1819 sc_xfer->error = XS_DRIVER_STUFFUP; 1820 scsipi_done(sc_xfer); 1821 return; 1822 } 1823 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1824 if (xfer == NULL) { 1825 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1826 scsipi_done(sc_xfer); 1827 return; 1828 } 1829 1830 if (sc_xfer->xs_control & XS_CTL_POLL) 1831 xfer->c_flags |= C_POLL; 1832 xfer->c_drive = drive; 1833 xfer->c_flags |= C_ATAPI; 1834 xfer->c_databuf = sc_xfer->data; 1835 xfer->c_bcount = sc_xfer->datalen; 1836 xfer->ops = &ahci_atapi_xfer_ops; 1837 xfer->c_scsipi = sc_xfer; 1838 xfer->c_atapi.c_dscpoll = 0; 1839 s = splbio(); 1840 ata_exec_xfer(atac->atac_channels[channel], xfer); 1841 #ifdef DIAGNOSTIC 1842 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1843 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1844 panic("ahci_atapi_scsipi_request: polled command " 1845 "not done"); 1846 #endif 1847 splx(s); 1848 return; 1849 default: 1850 /* Not supported, nothing to do. */ 1851 ; 1852 } 1853 } 1854 1855 static int 1856 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1857 { 1858 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1859 struct ahci_channel *achp = (struct ahci_channel *)chp; 1860 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1861 struct ahci_cmd_tbl *cmd_tbl; 1862 struct ahci_cmd_header *cmd_h; 1863 1864 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1865 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1866 1867 ata_channel_lock_owned(chp); 1868 1869 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1870 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1871 cmd_tbl), DEBUG_XFERS); 1872 1873 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1874 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1875 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1876 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1877 1878 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1879 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1880 chp->ch_channel, cmd_h), DEBUG_XFERS); 1881 if (ahci_dma_setup(chp, xfer->c_slot, 1882 sc_xfer->datalen ? sc_xfer->data : NULL, 1883 sc_xfer->datalen, 1884 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1885 BUS_DMA_READ : BUS_DMA_WRITE)) { 1886 sc_xfer->error = XS_DRIVER_STUFFUP; 1887 return ATASTART_ABORT; 1888 } 1889 cmd_h->cmdh_flags = htole16( 1890 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1891 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1892 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1893 cmd_h->cmdh_prdbc = 0; 1894 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1895 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1896 1897 if (xfer->c_flags & C_POLL) { 1898 /* polled command, disable interrupts */ 1899 AHCI_WRITE(sc, AHCI_GHC, 1900 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1901 } 1902 /* start command */ 1903 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1904 1905 if ((xfer->c_flags & C_POLL) == 0) { 1906 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1907 ata_timeout, chp); 1908 return ATASTART_STARTED; 1909 } else 1910 return ATASTART_POLL; 1911 } 1912 1913 static void 1914 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1915 { 1916 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1917 struct ahci_channel *achp = (struct ahci_channel *)chp; 1918 1919 /* 1920 * Polled command. 1921 */ 1922 for (int i = 0; i < ATA_DELAY / 10; i++) { 1923 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1924 break; 1925 ahci_intr_port(achp); 1926 delay(10000); 1927 } 1928 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1929 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1930 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1931 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1932 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1933 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1934 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1935 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1936 DEBUG_XFERS); 1937 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1938 xfer->c_scsipi->error = XS_TIMEOUT; 1939 xfer->ops->c_intr(chp, xfer, 0); 1940 } 1941 /* reenable interrupts */ 1942 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1943 } 1944 1945 static void 1946 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1947 { 1948 ahci_atapi_complete(chp, xfer, 0); 1949 } 1950 1951 static int 1952 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1953 { 1954 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1955 struct ahci_channel *achp = (struct ahci_channel *)chp; 1956 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1957 1958 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1959 DEBUG_FUNCS); 1960 1961 if (ata_waitdrain_xfer_check(chp, xfer)) 1962 return 0; 1963 1964 if (xfer->c_flags & C_TIMEOU) { 1965 sc_xfer->error = XS_TIMEOUT; 1966 } 1967 1968 if (xfer->c_bcount > 0) { 1969 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1970 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1971 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1972 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1973 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1974 } 1975 1976 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1977 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1978 sc_xfer->resid = sc_xfer->datalen; 1979 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1980 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1981 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1982 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1983 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1984 sc_xfer->resid == sc_xfer->datalen)) { 1985 sc_xfer->error = XS_SHORTSENSE; 1986 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 1987 if ((sc_xfer->xs_periph->periph_quirks & 1988 PQUIRK_NOSENSE) == 0) { 1989 /* ask scsipi to send a REQUEST_SENSE */ 1990 sc_xfer->error = XS_BUSY; 1991 sc_xfer->status = SCSI_CHECK; 1992 } 1993 } 1994 1995 ata_deactivate_xfer(chp, xfer); 1996 1997 ata_free_xfer(chp, xfer); 1998 scsipi_done(sc_xfer); 1999 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2000 atastart(chp); 2001 return 0; 2002 } 2003 2004 static void 2005 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2006 { 2007 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2008 bool deactivate = true; 2009 2010 /* remove this command from xfer queue */ 2011 switch (reason) { 2012 case KILL_GONE_INACTIVE: 2013 deactivate = false; 2014 /* FALLTHROUGH */ 2015 case KILL_GONE: 2016 sc_xfer->error = XS_DRIVER_STUFFUP; 2017 break; 2018 case KILL_RESET: 2019 sc_xfer->error = XS_RESET; 2020 break; 2021 case KILL_REQUEUE: 2022 sc_xfer->error = XS_REQUEUE; 2023 break; 2024 default: 2025 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2026 panic("ahci_ata_atapi_kill_xfer"); 2027 } 2028 2029 if (deactivate) 2030 ata_deactivate_xfer(chp, xfer); 2031 2032 ata_free_xfer(chp, xfer); 2033 scsipi_done(sc_xfer); 2034 } 2035 2036 static void 2037 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2038 { 2039 struct scsipi_channel *chan = sc->sc_channel; 2040 struct scsipi_periph *periph; 2041 struct ataparams ids; 2042 struct ataparams *id = &ids; 2043 struct ahci_softc *ahcic = 2044 device_private(chan->chan_adapter->adapt_dev); 2045 struct atac_softc *atac = &ahcic->sc_atac; 2046 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2047 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2048 struct scsipibus_attach_args sa; 2049 char serial_number[21], model[41], firmware_revision[9]; 2050 int s; 2051 2052 /* skip if already attached */ 2053 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2054 return; 2055 2056 /* if no ATAPI device detected at attach time, skip */ 2057 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2058 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2059 "not present\n", target), DEBUG_PROBE); 2060 return; 2061 } 2062 2063 /* Some ATAPI devices need a bit more time after software reset. */ 2064 delay(5000); 2065 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2066 #ifdef ATAPI_DEBUG_PROBE 2067 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2068 AHCINAME(ahcic), target, 2069 id->atap_config & ATAPI_CFG_CMD_MASK, 2070 id->atap_config & ATAPI_CFG_DRQ_MASK); 2071 #endif 2072 periph = scsipi_alloc_periph(M_NOWAIT); 2073 if (periph == NULL) { 2074 aprint_error_dev(sc->sc_dev, 2075 "unable to allocate periph for drive %d\n", 2076 target); 2077 return; 2078 } 2079 periph->periph_dev = NULL; 2080 periph->periph_channel = chan; 2081 periph->periph_switch = &atapi_probe_periphsw; 2082 periph->periph_target = target; 2083 periph->periph_lun = 0; 2084 periph->periph_quirks = PQUIRK_ONLYBIG; 2085 2086 #ifdef SCSIPI_DEBUG 2087 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2088 SCSIPI_DEBUG_TARGET == target) 2089 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2090 #endif 2091 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2092 if (id->atap_config & ATAPI_CFG_REMOV) 2093 periph->periph_flags |= PERIPH_REMOVABLE; 2094 if (periph->periph_type == T_SEQUENTIAL) { 2095 s = splbio(); 2096 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2097 splx(s); 2098 } 2099 2100 sa.sa_periph = periph; 2101 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2102 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2103 T_REMOV : T_FIXED; 2104 strnvisx(model, sizeof(model), id->atap_model, 40, 2105 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2106 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2107 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2108 strnvisx(firmware_revision, sizeof(firmware_revision), 2109 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2110 sa.sa_inqbuf.vendor = model; 2111 sa.sa_inqbuf.product = serial_number; 2112 sa.sa_inqbuf.revision = firmware_revision; 2113 2114 /* 2115 * Determine the operating mode capabilities of the device. 2116 */ 2117 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2118 periph->periph_cap |= PERIPH_CAP_CMD16; 2119 /* XXX This is gross. */ 2120 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2121 2122 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2123 2124 if (drvp->drv_softc) 2125 ata_probe_caps(drvp); 2126 else { 2127 s = splbio(); 2128 drvp->drive_type = ATA_DRIVET_NONE; 2129 splx(s); 2130 } 2131 } else { 2132 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2133 "failed for drive %s:%d:%d\n", 2134 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2135 s = splbio(); 2136 drvp->drive_type = ATA_DRIVET_NONE; 2137 splx(s); 2138 } 2139 } 2140 #endif /* NATAPIBUS */ 2141
Indexes created Fri Sep 26 08:10:20 GMT 2025