ahcisata_core.c revision 1.75
1 /* $NetBSD: ahcisata_core.c,v 1.75 2019/04/07 17:46:49 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.75 2019/04/07 17:46:49 bouyer Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 280 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 281 ahci_rev = AHCI_READ(sc, AHCI_VS); 282 snprintb(buf, sizeof(buf), "\177\020" 283 /* "f\000\005NP\0" */ 284 "b\005SXS\0" 285 "b\006EMS\0" 286 "b\007CCCS\0" 287 /* "f\010\005NCS\0" */ 288 "b\015PSC\0" 289 "b\016SSC\0" 290 "b\017PMD\0" 291 "b\020FBSS\0" 292 "b\021SPM\0" 293 "b\022SAM\0" 294 "b\023SNZO\0" 295 "f\024\003ISS\0" 296 "=\001Gen1\0" 297 "=\002Gen2\0" 298 "=\003Gen3\0" 299 "b\030SCLO\0" 300 "b\031SAL\0" 301 "b\032SALP\0" 302 "b\033SSS\0" 303 "b\034SMPS\0" 304 "b\035SSNTF\0" 305 "b\036SNCQ\0" 306 "b\037S64A\0" 307 "\0", sc->sc_ahci_cap); 308 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 309 ", %d port%s, %d slot%s, CAP %s\n", 310 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 311 sc->sc_atac.atac_nchannels, 312 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 313 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 314 315 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 316 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 317 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 318 sc->sc_atac.atac_pio_cap = 4; 319 sc->sc_atac.atac_dma_cap = 2; 320 sc->sc_atac.atac_udma_cap = 6; 321 sc->sc_atac.atac_channels = sc->sc_chanarray; 322 sc->sc_atac.atac_probe = ahci_probe_drive; 323 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 324 sc->sc_atac.atac_set_modes = ahci_setup_channel; 325 #if NATAPIBUS > 0 326 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 327 #endif 328 329 dmasize = 330 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 331 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 332 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 333 if (error) { 334 aprint_error("%s: unable to allocate command header memory" 335 ", error=%d\n", AHCINAME(sc), error); 336 return; 337 } 338 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 339 sc->sc_cmd_hdr_nseg, dmasize, 340 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 341 if (error) { 342 aprint_error("%s: unable to map command header memory" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 347 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 348 if (error) { 349 aprint_error("%s: unable to create command header map" 350 ", error=%d\n", AHCINAME(sc), error); 351 return; 352 } 353 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 354 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 355 if (error) { 356 aprint_error("%s: unable to load command header map" 357 ", error=%d\n", AHCINAME(sc), error); 358 return; 359 } 360 sc->sc_cmd_hdr = cmdhp; 361 362 ahci_enable_intrs(sc); 363 364 if (sc->sc_ahci_ports == 0) { 365 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 366 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 367 DEBUG_PROBE); 368 } 369 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 370 if ((sc->sc_ahci_ports & (1U << i)) == 0) 371 continue; 372 if (port >= sc->sc_atac.atac_nchannels) { 373 aprint_error("%s: more ports than announced\n", 374 AHCINAME(sc)); 375 break; 376 } 377 378 /* Optional intr establish per active port */ 379 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 380 aprint_error("%s: intr establish hook failed\n", 381 AHCINAME(sc)); 382 break; 383 } 384 385 achp = &sc->sc_channels[i]; 386 chp = &achp->ata_channel; 387 sc->sc_chanarray[i] = chp; 388 chp->ch_channel = i; 389 chp->ch_atac = &sc->sc_atac; 390 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 391 if (chp->ch_queue == NULL) { 392 aprint_error("%s port %d: can't allocate memory for " 393 "command queue", AHCINAME(sc), i); 394 break; 395 } 396 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 397 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 398 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 399 BUS_DMA_NOWAIT); 400 if (error) { 401 aprint_error("%s: unable to allocate command table " 402 "memory, error=%d\n", AHCINAME(sc), error); 403 break; 404 } 405 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 406 achp->ahcic_cmd_tbl_nseg, dmasize, 407 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 408 if (error) { 409 aprint_error("%s: unable to map command table memory" 410 ", error=%d\n", AHCINAME(sc), error); 411 break; 412 } 413 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 414 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 415 if (error) { 416 aprint_error("%s: unable to create command table map" 417 ", error=%d\n", AHCINAME(sc), error); 418 break; 419 } 420 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 421 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 422 if (error) { 423 aprint_error("%s: unable to load command table map" 424 ", error=%d\n", AHCINAME(sc), error); 425 break; 426 } 427 achp->ahcic_cmdh = (struct ahci_cmd_header *) 428 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 429 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 430 AHCI_CMDH_SIZE * port; 431 achp->ahcic_rfis = (struct ahci_r_fis *) 432 ((char *)cmdhp + 433 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 434 AHCI_RFIS_SIZE * port); 435 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 436 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 437 AHCI_RFIS_SIZE * port; 438 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 439 "rfis %p (0x%" PRIx64 ")\n", i, 440 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 441 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 442 DEBUG_PROBE); 443 444 for (j = 0; j < sc->sc_ncmds; j++) { 445 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 446 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 447 achp->ahcic_bus_cmd_tbl[j] = 448 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 449 AHCI_CMDTBL_SIZE * j; 450 achp->ahcic_cmdh[j].cmdh_cmdtba = 451 htole64(achp->ahcic_bus_cmd_tbl[j]); 452 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 453 achp->ahcic_cmd_tbl[j], 454 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 455 /* The xfer DMA map */ 456 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 457 AHCI_NPRD, 0x400000 /* 4MB */, 0, 458 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 459 &achp->ahcic_datad[j]); 460 if (error) { 461 aprint_error("%s: couldn't alloc xfer DMA map, " 462 "error=%d\n", AHCINAME(sc), error); 463 goto end; 464 } 465 } 466 ahci_setup_port(sc, i); 467 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 468 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 469 aprint_error("%s: couldn't map port %d " 470 "sata_status regs\n", AHCINAME(sc), i); 471 break; 472 } 473 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 474 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 475 aprint_error("%s: couldn't map port %d " 476 "sata_control regs\n", AHCINAME(sc), i); 477 break; 478 } 479 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 480 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 481 aprint_error("%s: couldn't map port %d " 482 "sata_error regs\n", AHCINAME(sc), i); 483 break; 484 } 485 ata_channel_attach(chp); 486 port++; 487 end: 488 continue; 489 } 490 } 491 492 void 493 ahci_childdetached(struct ahci_softc *sc, device_t child) 494 { 495 struct ahci_channel *achp; 496 struct ata_channel *chp; 497 498 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 499 achp = &sc->sc_channels[i]; 500 chp = &achp->ata_channel; 501 502 if ((sc->sc_ahci_ports & (1U << i)) == 0) 503 continue; 504 505 if (child == chp->atabus) 506 chp->atabus = NULL; 507 } 508 } 509 510 int 511 ahci_detach(struct ahci_softc *sc, int flags) 512 { 513 struct atac_softc *atac; 514 struct ahci_channel *achp; 515 struct ata_channel *chp; 516 struct scsipi_adapter *adapt; 517 int i, j, port; 518 int error; 519 520 atac = &sc->sc_atac; 521 adapt = &atac->atac_atapi_adapter._generic; 522 523 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 524 achp = &sc->sc_channels[i]; 525 chp = &achp->ata_channel; 526 527 if ((sc->sc_ahci_ports & (1U << i)) == 0) 528 continue; 529 if (port >= sc->sc_atac.atac_nchannels) { 530 aprint_error("%s: more ports than announced\n", 531 AHCINAME(sc)); 532 break; 533 } 534 535 if (chp->atabus != NULL) { 536 if ((error = config_detach(chp->atabus, flags)) != 0) 537 return error; 538 539 KASSERT(chp->atabus == NULL); 540 } 541 542 if (chp->ch_flags & ATACH_DETACHED) 543 continue; 544 545 for (j = 0; j < sc->sc_ncmds; j++) 546 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 547 548 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 549 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 550 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 551 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 552 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 553 achp->ahcic_cmd_tbl_nseg); 554 555 ata_channel_detach(chp); 556 port++; 557 } 558 559 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 560 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 561 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 562 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 563 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 564 565 if (adapt->adapt_refcnt != 0) 566 return EBUSY; 567 568 return 0; 569 } 570 571 void 572 ahci_resume(struct ahci_softc *sc) 573 { 574 ahci_reset(sc); 575 ahci_setup_ports(sc); 576 ahci_reprobe_drives(sc); 577 ahci_enable_intrs(sc); 578 } 579 580 int 581 ahci_intr(void *v) 582 { 583 struct ahci_softc *sc = v; 584 uint32_t is; 585 int i, r = 0; 586 587 while ((is = AHCI_READ(sc, AHCI_IS))) { 588 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 589 DEBUG_INTR); 590 r = 1; 591 AHCI_WRITE(sc, AHCI_IS, is); 592 for (i = 0; i < AHCI_MAX_PORTS; i++) 593 if (is & (1U << i)) 594 ahci_intr_port(&sc->sc_channels[i]); 595 } 596 597 return r; 598 } 599 600 int 601 ahci_intr_port(void *v) 602 { 603 struct ahci_channel *achp = v; 604 struct ata_channel *chp = &achp->ata_channel; 605 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 606 uint32_t is, tfd, sact; 607 struct ata_xfer *xfer; 608 int slot = -1; 609 bool recover = false; 610 uint32_t aslots; 611 612 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 613 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 614 615 AHCIDEBUG_PRINT(( 616 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 617 AHCINAME(sc), 618 chp->ch_channel, is, 619 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 620 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 621 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 622 DEBUG_INTR); 623 624 if ((chp->ch_flags & ATACH_NCQ) == 0) { 625 /* Non-NCQ operation */ 626 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 627 } else { 628 /* NCQ operation */ 629 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 630 } 631 632 /* Handle errors */ 633 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 634 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 635 /* Fatal errors */ 636 if (is & AHCI_P_IX_TFES) { 637 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 638 639 if ((chp->ch_flags & ATACH_NCQ) == 0) { 640 /* Slot valid only for Non-NCQ operation */ 641 slot = (AHCI_READ(sc, 642 AHCI_P_CMD(chp->ch_channel)) 643 & AHCI_P_CMD_CCS_MASK) 644 >> AHCI_P_CMD_CCS_SHIFT; 645 } 646 647 AHCIDEBUG_PRINT(( 648 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 649 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 650 DEBUG_INTR); 651 } else { 652 /* mark an error, and set BSY */ 653 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 654 WDCS_ERR | WDCS_BSY; 655 } 656 657 if (is & AHCI_P_IX_IFS) { 658 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 659 AHCINAME(sc), chp->ch_channel, 660 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 661 DEBUG_INTR); 662 } 663 664 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 665 recover = true; 666 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 667 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 668 669 /* D2H Register FIS or Set Device Bits */ 670 if ((tfd & WDCS_ERR) != 0) { 671 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 672 recover = true; 673 674 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 675 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 676 677 } 678 } else { 679 tfd = 0; 680 } 681 682 if (__predict_false(recover)) 683 ata_channel_freeze(chp); 684 685 aslots = ata_queue_active(chp); 686 687 if (slot >= 0) { 688 if ((aslots & __BIT(slot)) != 0 && 689 (sact & __BIT(slot)) == 0) { 690 xfer = ata_queue_hwslot_to_xfer(chp, slot); 691 xfer->ops->c_intr(chp, xfer, tfd); 692 } 693 } else { 694 /* 695 * For NCQ, HBA halts processing when error is notified, 696 * and any further D2H FISes are ignored until the error 697 * condition is cleared. Hence if a command is inactive, 698 * it means it actually already finished successfully. 699 * Note: active slots can change as c_intr() callback 700 * can activate another command(s), so must only process 701 * commands active before we start processing. 702 */ 703 704 for (slot=0; slot < sc->sc_ncmds; slot++) { 705 if ((aslots & __BIT(slot)) != 0 && 706 (sact & __BIT(slot)) == 0) { 707 xfer = ata_queue_hwslot_to_xfer(chp, slot); 708 xfer->ops->c_intr(chp, xfer, tfd); 709 } 710 } 711 } 712 713 if (__predict_false(recover)) { 714 ata_channel_lock(chp); 715 ata_channel_thaw_locked(chp); 716 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 717 ata_channel_unlock(chp); 718 } 719 720 return 1; 721 } 722 723 static void 724 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 725 { 726 struct ata_channel *chp = drvp->chnl_softc; 727 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 728 uint8_t c_slot; 729 730 ata_channel_lock_owned(chp); 731 732 /* get a slot for running the command on */ 733 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 734 panic("%s: %s: failed to get xfer for reset, port %d\n", 735 device_xname(sc->sc_atac.atac_dev), 736 __func__, chp->ch_channel); 737 /* NOTREACHED */ 738 } 739 740 AHCI_WRITE(sc, AHCI_GHC, 741 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 742 ahci_channel_stop(sc, chp, flags); 743 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 744 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 745 746 ata_queue_free_slot(chp, c_slot); 747 } 748 749 /* return error code from ata_bio */ 750 static int 751 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 752 { 753 struct ahci_channel *achp = (struct ahci_channel *)chp; 754 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 755 int i; 756 uint32_t is; 757 758 /* 759 * Base timeout is specified in ms. 760 * If we are allowed to sleep, wait a tick each round. 761 * Otherwise delay for 10ms on each round. 762 */ 763 if (flags & AT_WAIT) 764 timeout = MAX(1, mstohz(timeout)); 765 else 766 timeout = timeout / 10; 767 768 AHCI_CMDH_SYNC(sc, achp, slot, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 /* start command */ 771 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 772 for (i = 0; i < timeout; i++) { 773 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 774 0) 775 return 0; 776 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 777 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 778 AHCI_P_IX_IFS | 779 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 780 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 781 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 782 /* 783 * we got the D2H FIS anyway, 784 * assume sig is valid. 785 * channel is restarted later 786 */ 787 return ERROR; 788 } 789 aprint_debug("%s port %d: error 0x%x sending FIS\n", 790 AHCINAME(sc), chp->ch_channel, is); 791 return ERR_DF; 792 } 793 ata_delay(chp, 10, "ahcifis", flags); 794 } 795 796 aprint_debug("%s port %d: timeout sending FIS\n", 797 AHCINAME(sc), chp->ch_channel); 798 return TIMEOUT; 799 } 800 801 static int 802 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 803 uint32_t *sigp, uint8_t c_slot) 804 { 805 struct ahci_channel *achp = (struct ahci_channel *)chp; 806 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 807 struct ahci_cmd_tbl *cmd_tbl; 808 struct ahci_cmd_header *cmd_h; 809 int i, error = 0; 810 uint32_t sig; 811 int noclo_retry = 0; 812 813 ata_channel_lock_owned(chp); 814 815 again: 816 /* clear port interrupt register */ 817 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 818 /* clear SErrors and start operations */ 819 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 820 /* 821 * issue a command list override to clear BSY. 822 * This is needed if there's a PMP with no drive 823 * on port 0 824 */ 825 ahci_channel_start(sc, chp, flags, 1); 826 } else { 827 /* Can't handle command still running without CLO */ 828 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 829 830 ahci_channel_start(sc, chp, flags, 0); 831 } 832 if (drive > 0) { 833 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 834 } 835 836 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 837 goto skip_reset; 838 839 /* polled command, assume interrupts are disabled */ 840 841 cmd_h = &achp->ahcic_cmdh[c_slot]; 842 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 843 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 844 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 845 cmd_h->cmdh_prdbc = 0; 846 memset(cmd_tbl->cmdt_cfis, 0, 64); 847 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 848 cmd_tbl->cmdt_cfis[rhd_c] = drive; 849 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 850 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 851 case ERR_DF: 852 case TIMEOUT: 853 /* 854 * without CLO we can't make sure a software reset will 855 * success, as the drive may still have BSY or DRQ set. 856 * in this case, reset the whole channel and retry the 857 * drive reset. The channel reset should clear BSY and DRQ 858 */ 859 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 860 noclo_retry++; 861 ahci_reset_channel(chp, flags); 862 goto again; 863 } 864 aprint_error("%s port %d: setting WDCTL_RST failed " 865 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 866 error = EBUSY; 867 goto end; 868 default: 869 break; 870 } 871 872 /* 873 * SATA specification has toggle period for SRST bit of 5 usec. Some 874 * controllers fail to process the SRST clear operation unless 875 * we wait for at least this period between the set and clear commands. 876 */ 877 ata_delay(chp, 10, "ahcirstw", flags); 878 879 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 880 (drive << AHCI_CMDH_F_PMP_SHIFT)); 881 cmd_h->cmdh_prdbc = 0; 882 memset(cmd_tbl->cmdt_cfis, 0, 64); 883 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 884 cmd_tbl->cmdt_cfis[rhd_c] = drive; 885 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 886 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 887 case ERR_DF: 888 case TIMEOUT: 889 aprint_error("%s port %d: clearing WDCTL_RST failed " 890 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 891 error = EBUSY; 892 goto end; 893 default: 894 break; 895 } 896 897 skip_reset: 898 /* 899 * wait 31s for BSY to clear 900 * This should not be needed, but some controllers clear the 901 * command slot before receiving the D2H FIS ... 902 */ 903 for (i = 0; i < AHCI_RST_WAIT; i++) { 904 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 905 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 906 break; 907 ata_delay(chp, 10, "ahcid2h", flags); 908 } 909 if (i == AHCI_RST_WAIT) { 910 aprint_error("%s: BSY never cleared, TD 0x%x\n", 911 AHCINAME(sc), sig); 912 goto end; 913 } 914 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 915 DEBUG_PROBE); 916 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 917 if (sigp) 918 *sigp = sig; 919 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 920 AHCINAME(sc), chp->ch_channel, sig, 921 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 922 end: 923 ahci_channel_stop(sc, chp, flags); 924 ata_delay(chp, 500, "ahcirst", flags); 925 /* clear port interrupt register */ 926 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 927 ahci_channel_start(sc, chp, flags, 928 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 929 return error; 930 } 931 932 static void 933 ahci_reset_channel(struct ata_channel *chp, int flags) 934 { 935 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 936 struct ahci_channel *achp = (struct ahci_channel *)chp; 937 int i, tfd; 938 939 ata_channel_lock_owned(chp); 940 941 ahci_channel_stop(sc, chp, flags); 942 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 943 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 944 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 945 /* XXX and then ? */ 946 } 947 ata_kill_active(chp, KILL_RESET, flags); 948 ata_delay(chp, 500, "ahcirst", flags); 949 /* clear port interrupt register */ 950 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 951 /* clear SErrors and start operations */ 952 ahci_channel_start(sc, chp, flags, 953 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 954 /* wait 31s for BSY to clear */ 955 for (i = 0; i < AHCI_RST_WAIT; i++) { 956 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 957 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 958 break; 959 ata_delay(chp, 10, "ahcid2h", flags); 960 } 961 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 962 aprint_error("%s: BSY never cleared, TD 0x%x\n", 963 AHCINAME(sc), tfd); 964 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 965 DEBUG_PROBE); 966 /* clear port interrupt register */ 967 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 968 969 return; 970 } 971 972 static int 973 ahci_ata_addref(struct ata_drive_datas *drvp) 974 { 975 return 0; 976 } 977 978 static void 979 ahci_ata_delref(struct ata_drive_datas *drvp) 980 { 981 return; 982 } 983 984 static void 985 ahci_killpending(struct ata_drive_datas *drvp) 986 { 987 return; 988 } 989 990 static void 991 ahci_probe_drive(struct ata_channel *chp) 992 { 993 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 994 struct ahci_channel *achp = (struct ahci_channel *)chp; 995 uint32_t sig; 996 uint8_t c_slot; 997 int error; 998 999 ata_channel_lock(chp); 1000 1001 /* get a slot for running the command on */ 1002 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1003 aprint_error_dev(sc->sc_atac.atac_dev, 1004 "%s: failed to get xfer port %d\n", 1005 __func__, chp->ch_channel); 1006 ata_channel_unlock(chp); 1007 return; 1008 } 1009 1010 /* bring interface up, accept FISs, power up and spin up device */ 1011 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1012 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1013 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1014 /* reset the PHY and bring online */ 1015 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1016 achp->ahcic_sstatus, AT_WAIT)) { 1017 case SStatus_DET_DEV: 1018 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1019 1020 /* Initial value, used in case the soft reset fails */ 1021 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1022 1023 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1024 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1025 &sig, c_slot); 1026 1027 /* If probe for PMP failed, just fallback to drive 0 */ 1028 if (error) { 1029 aprint_error("%s port %d: drive %d reset " 1030 "failed, disabling PMP\n", 1031 AHCINAME(sc), chp->ch_channel, 1032 PMP_PORT_CTL); 1033 1034 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1035 ahci_reset_channel(chp, AT_WAIT); 1036 } 1037 } else { 1038 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1039 } 1040 sata_interpret_sig(chp, 0, sig); 1041 /* if we have a PMP attached, inform the controller */ 1042 if (chp->ch_ndrives > PMP_PORT_CTL && 1043 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1044 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1045 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1046 AHCI_P_CMD_PMA); 1047 } 1048 /* clear port interrupt register */ 1049 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1050 1051 /* and enable interrupts */ 1052 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1053 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1054 AHCI_P_IX_IFS | 1055 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1056 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1057 /* wait 500ms before actually starting operations */ 1058 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1059 break; 1060 1061 default: 1062 break; 1063 } 1064 1065 ata_queue_free_slot(chp, c_slot); 1066 1067 ata_channel_unlock(chp); 1068 } 1069 1070 static void 1071 ahci_setup_channel(struct ata_channel *chp) 1072 { 1073 return; 1074 } 1075 1076 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1077 .c_start = ahci_cmd_start, 1078 .c_poll = ahci_cmd_poll, 1079 .c_abort = ahci_cmd_abort, 1080 .c_intr = ahci_cmd_complete, 1081 .c_kill_xfer = ahci_cmd_kill_xfer, 1082 }; 1083 1084 static int 1085 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1086 { 1087 struct ata_channel *chp = drvp->chnl_softc; 1088 struct ata_command *ata_c = &xfer->c_ata_c; 1089 int ret; 1090 int s; 1091 1092 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1093 chp->ch_channel, 1094 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1095 DEBUG_XFERS); 1096 if (ata_c->flags & AT_POLL) 1097 xfer->c_flags |= C_POLL; 1098 if (ata_c->flags & AT_WAIT) 1099 xfer->c_flags |= C_WAIT; 1100 xfer->c_drive = drvp->drive; 1101 xfer->c_databuf = ata_c->data; 1102 xfer->c_bcount = ata_c->bcount; 1103 xfer->ops = &ahci_cmd_xfer_ops; 1104 s = splbio(); 1105 ata_exec_xfer(chp, xfer); 1106 #ifdef DIAGNOSTIC 1107 if ((ata_c->flags & AT_POLL) != 0 && 1108 (ata_c->flags & AT_DONE) == 0) 1109 panic("ahci_exec_command: polled command not done"); 1110 #endif 1111 if (ata_c->flags & AT_DONE) { 1112 ret = ATACMD_COMPLETE; 1113 } else { 1114 if (ata_c->flags & AT_WAIT) { 1115 ata_wait_cmd(chp, xfer); 1116 ret = ATACMD_COMPLETE; 1117 } else { 1118 ret = ATACMD_QUEUED; 1119 } 1120 } 1121 splx(s); 1122 return ret; 1123 } 1124 1125 static int 1126 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1127 { 1128 struct ahci_softc *sc = AHCI_CH2SC(chp); 1129 struct ahci_channel *achp = (struct ahci_channel *)chp; 1130 struct ata_command *ata_c = &xfer->c_ata_c; 1131 int slot = xfer->c_slot; 1132 struct ahci_cmd_tbl *cmd_tbl; 1133 struct ahci_cmd_header *cmd_h; 1134 1135 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1136 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1137 ata_c->timeout, slot), 1138 DEBUG_XFERS); 1139 1140 ata_channel_lock_owned(chp); 1141 1142 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1143 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1144 cmd_tbl), DEBUG_XFERS); 1145 1146 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1147 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1148 1149 cmd_h = &achp->ahcic_cmdh[slot]; 1150 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1151 chp->ch_channel, cmd_h), DEBUG_XFERS); 1152 if (ahci_dma_setup(chp, slot, 1153 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1154 ata_c->data : NULL, 1155 ata_c->bcount, 1156 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1157 ata_c->flags |= AT_DF; 1158 return ATASTART_ABORT; 1159 } 1160 cmd_h->cmdh_flags = htole16( 1161 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1162 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1163 cmd_h->cmdh_prdbc = 0; 1164 AHCI_CMDH_SYNC(sc, achp, slot, 1165 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1166 1167 if (ata_c->flags & AT_POLL) { 1168 /* polled command, disable interrupts */ 1169 AHCI_WRITE(sc, AHCI_GHC, 1170 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1171 } 1172 /* start command */ 1173 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1174 1175 if ((ata_c->flags & AT_POLL) == 0) { 1176 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1177 ata_timeout, chp); 1178 return ATASTART_STARTED; 1179 } else 1180 return ATASTART_POLL; 1181 } 1182 1183 static void 1184 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1185 { 1186 struct ahci_softc *sc = AHCI_CH2SC(chp); 1187 struct ahci_channel *achp = (struct ahci_channel *)chp; 1188 1189 ata_channel_lock(chp); 1190 1191 /* 1192 * Polled command. 1193 */ 1194 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1195 if (xfer->c_ata_c.flags & AT_DONE) 1196 break; 1197 ata_channel_unlock(chp); 1198 ahci_intr_port(achp); 1199 ata_channel_lock(chp); 1200 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1201 } 1202 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1203 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1204 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1205 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1206 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1207 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1208 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1209 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1210 DEBUG_XFERS); 1211 1212 ata_channel_unlock(chp); 1213 1214 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1215 xfer->c_ata_c.flags |= AT_TIMEOU; 1216 xfer->ops->c_intr(chp, xfer, 0); 1217 } 1218 /* reenable interrupts */ 1219 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1220 } 1221 1222 static void 1223 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1224 { 1225 ahci_cmd_complete(chp, xfer, 0); 1226 } 1227 1228 static void 1229 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1230 { 1231 struct ata_command *ata_c = &xfer->c_ata_c; 1232 bool deactivate = true; 1233 1234 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1235 DEBUG_FUNCS); 1236 1237 switch (reason) { 1238 case KILL_GONE_INACTIVE: 1239 deactivate = false; 1240 /* FALLTHROUGH */ 1241 case KILL_GONE: 1242 ata_c->flags |= AT_GONE; 1243 break; 1244 case KILL_RESET: 1245 ata_c->flags |= AT_RESET; 1246 break; 1247 case KILL_REQUEUE: 1248 panic("%s: not supposed to be requeued\n", __func__); 1249 break; 1250 default: 1251 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1252 panic("ahci_cmd_kill_xfer"); 1253 } 1254 1255 ahci_cmd_done_end(chp, xfer); 1256 1257 if (deactivate) 1258 ata_deactivate_xfer(chp, xfer); 1259 } 1260 1261 static int 1262 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1263 { 1264 struct ata_command *ata_c = &xfer->c_ata_c; 1265 struct ahci_channel *achp = (struct ahci_channel *)chp; 1266 1267 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1268 chp->ch_channel, 1269 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1270 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1271 DEBUG_FUNCS); 1272 1273 if (ata_waitdrain_xfer_check(chp, xfer)) 1274 return 0; 1275 1276 if (xfer->c_flags & C_TIMEOU) { 1277 ata_c->flags |= AT_TIMEOU; 1278 } 1279 1280 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1281 ata_c->flags |= AT_TIMEOU; 1282 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1283 ata_c->r_error = AHCI_TFD_ERR(tfd); 1284 ata_c->flags |= AT_ERROR; 1285 } 1286 1287 if (ata_c->flags & AT_READREG) 1288 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1289 1290 ahci_cmd_done(chp, xfer); 1291 1292 ata_deactivate_xfer(chp, xfer); 1293 1294 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1295 atastart(chp); 1296 1297 return 0; 1298 } 1299 1300 static void 1301 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1302 { 1303 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1304 struct ahci_channel *achp = (struct ahci_channel *)chp; 1305 struct ata_command *ata_c = &xfer->c_ata_c; 1306 uint16_t *idwordbuf; 1307 int i; 1308 1309 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1310 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1311 1312 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1313 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1314 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1315 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1316 BUS_DMASYNC_POSTWRITE); 1317 bus_dmamap_unload(sc->sc_dmat, map); 1318 } 1319 1320 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1321 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1322 1323 /* ata(4) expects IDENTIFY data to be in host endianess */ 1324 if (ata_c->r_command == WDCC_IDENTIFY || 1325 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1326 idwordbuf = xfer->c_databuf; 1327 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1328 idwordbuf[i] = le16toh(idwordbuf[i]); 1329 } 1330 } 1331 1332 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1333 ata_c->flags |= AT_XFDONE; 1334 1335 ahci_cmd_done_end(chp, xfer); 1336 } 1337 1338 static void 1339 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1340 { 1341 struct ata_command *ata_c = &xfer->c_ata_c; 1342 1343 ata_c->flags |= AT_DONE; 1344 } 1345 1346 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1347 .c_start = ahci_bio_start, 1348 .c_poll = ahci_bio_poll, 1349 .c_abort = ahci_bio_abort, 1350 .c_intr = ahci_bio_complete, 1351 .c_kill_xfer = ahci_bio_kill_xfer, 1352 }; 1353 1354 static int 1355 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1356 { 1357 struct ata_channel *chp = drvp->chnl_softc; 1358 struct ata_bio *ata_bio = &xfer->c_bio; 1359 1360 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1361 chp->ch_channel, 1362 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1363 DEBUG_XFERS); 1364 if (ata_bio->flags & ATA_POLL) 1365 xfer->c_flags |= C_POLL; 1366 xfer->c_drive = drvp->drive; 1367 xfer->c_databuf = ata_bio->databuf; 1368 xfer->c_bcount = ata_bio->bcount; 1369 xfer->ops = &ahci_bio_xfer_ops; 1370 ata_exec_xfer(chp, xfer); 1371 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1372 } 1373 1374 static int 1375 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1376 { 1377 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1378 struct ahci_channel *achp = (struct ahci_channel *)chp; 1379 struct ata_bio *ata_bio = &xfer->c_bio; 1380 struct ahci_cmd_tbl *cmd_tbl; 1381 struct ahci_cmd_header *cmd_h; 1382 1383 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1384 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1385 1386 ata_channel_lock_owned(chp); 1387 1388 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1389 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1390 cmd_tbl), DEBUG_XFERS); 1391 1392 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1393 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1394 1395 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1396 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1397 chp->ch_channel, cmd_h), DEBUG_XFERS); 1398 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1399 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1400 ata_bio->error = ERR_DMA; 1401 ata_bio->r_error = 0; 1402 return ATASTART_ABORT; 1403 } 1404 cmd_h->cmdh_flags = htole16( 1405 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1406 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1407 cmd_h->cmdh_prdbc = 0; 1408 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1410 1411 if (xfer->c_flags & C_POLL) { 1412 /* polled command, disable interrupts */ 1413 AHCI_WRITE(sc, AHCI_GHC, 1414 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1415 } 1416 if (xfer->c_flags & C_NCQ) 1417 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1418 /* start command */ 1419 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1420 1421 if ((xfer->c_flags & C_POLL) == 0) { 1422 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1423 ata_timeout, chp); 1424 return ATASTART_STARTED; 1425 } else 1426 return ATASTART_POLL; 1427 } 1428 1429 static void 1430 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1431 { 1432 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1433 struct ahci_channel *achp = (struct ahci_channel *)chp; 1434 1435 /* 1436 * Polled command. 1437 */ 1438 for (int i = 0; i < ATA_DELAY * 10; i++) { 1439 if (xfer->c_bio.flags & ATA_ITSDONE) 1440 break; 1441 ahci_intr_port(achp); 1442 delay(100); 1443 } 1444 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1445 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1446 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1447 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1448 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1449 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1450 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1451 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1452 DEBUG_XFERS); 1453 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1454 xfer->c_bio.error = TIMEOUT; 1455 xfer->ops->c_intr(chp, xfer, 0); 1456 } 1457 /* reenable interrupts */ 1458 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1459 } 1460 1461 static void 1462 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1463 { 1464 ahci_bio_complete(chp, xfer, 0); 1465 } 1466 1467 static void 1468 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1469 { 1470 int drive = xfer->c_drive; 1471 struct ata_bio *ata_bio = &xfer->c_bio; 1472 bool deactivate = true; 1473 1474 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1475 DEBUG_FUNCS); 1476 1477 ata_bio->flags |= ATA_ITSDONE; 1478 switch (reason) { 1479 case KILL_GONE_INACTIVE: 1480 deactivate = false; 1481 /* FALLTHROUGH */ 1482 case KILL_GONE: 1483 ata_bio->error = ERR_NODEV; 1484 break; 1485 case KILL_RESET: 1486 ata_bio->error = ERR_RESET; 1487 break; 1488 case KILL_REQUEUE: 1489 ata_bio->error = REQUEUE; 1490 break; 1491 default: 1492 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1493 panic("ahci_bio_kill_xfer"); 1494 } 1495 ata_bio->r_error = WDCE_ABRT; 1496 1497 if (deactivate) 1498 ata_deactivate_xfer(chp, xfer); 1499 1500 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1501 } 1502 1503 static int 1504 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1505 { 1506 struct ata_bio *ata_bio = &xfer->c_bio; 1507 int drive = xfer->c_drive; 1508 struct ahci_channel *achp = (struct ahci_channel *)chp; 1509 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1510 1511 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1512 DEBUG_FUNCS); 1513 1514 if (ata_waitdrain_xfer_check(chp, xfer)) 1515 return 0; 1516 1517 if (xfer->c_flags & C_TIMEOU) { 1518 ata_bio->error = TIMEOUT; 1519 } 1520 1521 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1522 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1523 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1524 BUS_DMASYNC_POSTWRITE); 1525 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1526 1527 ata_bio->flags |= ATA_ITSDONE; 1528 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1529 ata_bio->error = ERR_DF; 1530 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1531 ata_bio->error = ERROR; 1532 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1533 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1534 ata_bio->flags |= ATA_CORR; 1535 1536 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1537 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1538 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1539 ata_bio->bcount), DEBUG_XFERS); 1540 /* 1541 * If it was a write, complete data buffer may have been transfered 1542 * before error detection; in this case don't use cmdh_prdbc 1543 * as it won't reflect what was written to media. Assume nothing 1544 * was transfered and leave bcount as-is. 1545 * For queued commands, PRD Byte Count should not be used, and is 1546 * not required to be valid; in that case underflow is always illegal. 1547 */ 1548 if ((xfer->c_flags & C_NCQ) != 0) { 1549 if (ata_bio->error == NOERROR) 1550 ata_bio->bcount = 0; 1551 } else { 1552 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1553 ata_bio->bcount -= 1554 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1555 } 1556 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1557 1558 ata_deactivate_xfer(chp, xfer); 1559 1560 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1561 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1562 atastart(chp); 1563 return 0; 1564 } 1565 1566 static void 1567 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1568 { 1569 int i; 1570 /* stop channel */ 1571 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1572 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1573 /* wait 1s for channel to stop */ 1574 for (i = 0; i <100; i++) { 1575 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1576 == 0) 1577 break; 1578 ata_delay(chp, 10, "ahcistop", flags); 1579 } 1580 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1581 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1582 /* XXX controller reset ? */ 1583 return; 1584 } 1585 1586 if (sc->sc_channel_stop) 1587 sc->sc_channel_stop(sc, chp); 1588 } 1589 1590 static void 1591 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1592 int flags, int clo) 1593 { 1594 int i; 1595 uint32_t p_cmd; 1596 /* clear error */ 1597 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1598 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1599 1600 if (clo) { 1601 /* issue command list override */ 1602 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1603 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1604 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1605 /* wait 1s for AHCI_CAP_CLO to clear */ 1606 for (i = 0; i <100; i++) { 1607 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1608 AHCI_P_CMD_CLO) == 0) 1609 break; 1610 ata_delay(chp, 10, "ahciclo", flags); 1611 } 1612 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1613 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1614 /* XXX controller reset ? */ 1615 return; 1616 } 1617 } 1618 1619 if (sc->sc_channel_start) 1620 sc->sc_channel_start(sc, chp); 1621 1622 /* and start controller */ 1623 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1624 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1625 if (chp->ch_ndrives > PMP_PORT_CTL && 1626 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1627 p_cmd |= AHCI_P_CMD_PMA; 1628 } 1629 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1630 } 1631 1632 /* Recover channel after command failure */ 1633 static void 1634 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1635 { 1636 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1637 int drive = ATACH_NODRIVE; 1638 bool reset = false; 1639 1640 ata_channel_lock_owned(chp); 1641 1642 /* 1643 * Read FBS to get the drive which caused the error, if PM is in use. 1644 * According to AHCI 1.3 spec, this register is available regardless 1645 * if FIS-based switching (FBSS) feature is supported, or disabled. 1646 * If FIS-based switching is not in use, it merely maintains single 1647 * pair of DRQ/BSY state, but it is enough since in that case we 1648 * never issue commands for more than one device at the time anyway. 1649 * XXX untested 1650 */ 1651 if (chp->ch_ndrives > PMP_PORT_CTL) { 1652 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1653 if (fbs & AHCI_P_FBS_SDE) { 1654 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1655 1656 /* 1657 * Tell HBA to reset PM port X (value in DWE) state, 1658 * and resume processing commands for other ports. 1659 */ 1660 fbs |= AHCI_P_FBS_DEC; 1661 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1662 for (int i = 0; i < 1000; i++) { 1663 fbs = AHCI_READ(sc, 1664 AHCI_P_FBS(chp->ch_channel)); 1665 if ((fbs & AHCI_P_FBS_DEC) == 0) 1666 break; 1667 DELAY(1000); 1668 } 1669 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1670 /* follow non-device specific recovery */ 1671 drive = ATACH_NODRIVE; 1672 reset = true; 1673 } 1674 } else { 1675 /* not device specific, reset channel */ 1676 drive = ATACH_NODRIVE; 1677 reset = true; 1678 } 1679 } else 1680 drive = 0; 1681 1682 /* 1683 * If BSY or DRQ bits are set, must execute COMRESET to return 1684 * device to idle state. If drive is idle, it's enough to just 1685 * reset CMD.ST, it's not necessary to do software reset. 1686 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1687 * to unblock device processing if COMRESET was not done. 1688 */ 1689 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1690 ahci_reset_channel(chp, flags); 1691 goto out; 1692 } 1693 1694 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1695 ahci_channel_stop(sc, chp, flags); 1696 ahci_channel_start(sc, chp, flags, 1697 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1698 1699 ata_recovery_resume(chp, drive, tfd, flags); 1700 1701 out: 1702 /* Drive unblocked, back to normal operation */ 1703 return; 1704 } 1705 1706 static int 1707 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1708 size_t count, int op) 1709 { 1710 int error, seg; 1711 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1712 struct ahci_channel *achp = (struct ahci_channel *)chp; 1713 struct ahci_cmd_tbl *cmd_tbl; 1714 struct ahci_cmd_header *cmd_h; 1715 1716 cmd_h = &achp->ahcic_cmdh[slot]; 1717 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1718 1719 if (data == NULL) { 1720 cmd_h->cmdh_prdtl = 0; 1721 goto end; 1722 } 1723 1724 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1725 data, count, NULL, 1726 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1727 if (error) { 1728 printf("%s port %d: failed to load xfer: %d\n", 1729 AHCINAME(sc), chp->ch_channel, error); 1730 return error; 1731 } 1732 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1733 achp->ahcic_datad[slot]->dm_mapsize, 1734 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1735 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1736 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1737 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1738 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1739 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1740 } 1741 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1742 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1743 end: 1744 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1745 return 0; 1746 } 1747 1748 #if NATAPIBUS > 0 1749 static void 1750 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1751 { 1752 struct ata_channel *chp = ata_sc->sc_chan; 1753 struct atac_softc *atac = chp->ch_atac; 1754 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1755 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1756 /* 1757 * Fill in the scsipi_adapter. 1758 */ 1759 adapt->adapt_dev = atac->atac_dev; 1760 adapt->adapt_nchannels = atac->atac_nchannels; 1761 adapt->adapt_request = ahci_atapi_scsipi_request; 1762 adapt->adapt_minphys = ahci_atapi_minphys; 1763 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1764 1765 /* 1766 * Fill in the scsipi_channel. 1767 */ 1768 memset(chan, 0, sizeof(*chan)); 1769 chan->chan_adapter = adapt; 1770 chan->chan_bustype = &ahci_atapi_bustype; 1771 chan->chan_channel = chp->ch_channel; 1772 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1773 chan->chan_openings = 1; 1774 chan->chan_max_periph = 1; 1775 chan->chan_ntargets = 1; 1776 chan->chan_nluns = 1; 1777 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1778 atapiprint); 1779 } 1780 1781 static void 1782 ahci_atapi_minphys(struct buf *bp) 1783 { 1784 if (bp->b_bcount > MAXPHYS) 1785 bp->b_bcount = MAXPHYS; 1786 minphys(bp); 1787 } 1788 1789 /* 1790 * Kill off all pending xfers for a periph. 1791 * 1792 * Must be called at splbio(). 1793 */ 1794 static void 1795 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1796 { 1797 struct atac_softc *atac = 1798 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1799 struct ata_channel *chp = 1800 atac->atac_channels[periph->periph_channel->chan_channel]; 1801 1802 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1803 } 1804 1805 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1806 .c_start = ahci_atapi_start, 1807 .c_poll = ahci_atapi_poll, 1808 .c_abort = ahci_atapi_abort, 1809 .c_intr = ahci_atapi_complete, 1810 .c_kill_xfer = ahci_atapi_kill_xfer, 1811 }; 1812 1813 static void 1814 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1815 scsipi_adapter_req_t req, void *arg) 1816 { 1817 struct scsipi_adapter *adapt = chan->chan_adapter; 1818 struct scsipi_periph *periph; 1819 struct scsipi_xfer *sc_xfer; 1820 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1821 struct atac_softc *atac = &sc->sc_atac; 1822 struct ata_xfer *xfer; 1823 int channel = chan->chan_channel; 1824 int drive, s; 1825 1826 switch (req) { 1827 case ADAPTER_REQ_RUN_XFER: 1828 sc_xfer = arg; 1829 periph = sc_xfer->xs_periph; 1830 drive = periph->periph_target; 1831 if (!device_is_active(atac->atac_dev)) { 1832 sc_xfer->error = XS_DRIVER_STUFFUP; 1833 scsipi_done(sc_xfer); 1834 return; 1835 } 1836 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1837 if (xfer == NULL) { 1838 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1839 scsipi_done(sc_xfer); 1840 return; 1841 } 1842 1843 if (sc_xfer->xs_control & XS_CTL_POLL) 1844 xfer->c_flags |= C_POLL; 1845 xfer->c_drive = drive; 1846 xfer->c_flags |= C_ATAPI; 1847 xfer->c_databuf = sc_xfer->data; 1848 xfer->c_bcount = sc_xfer->datalen; 1849 xfer->ops = &ahci_atapi_xfer_ops; 1850 xfer->c_scsipi = sc_xfer; 1851 xfer->c_atapi.c_dscpoll = 0; 1852 s = splbio(); 1853 ata_exec_xfer(atac->atac_channels[channel], xfer); 1854 #ifdef DIAGNOSTIC 1855 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1856 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1857 panic("ahci_atapi_scsipi_request: polled command " 1858 "not done"); 1859 #endif 1860 splx(s); 1861 return; 1862 default: 1863 /* Not supported, nothing to do. */ 1864 ; 1865 } 1866 } 1867 1868 static int 1869 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1870 { 1871 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1872 struct ahci_channel *achp = (struct ahci_channel *)chp; 1873 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1874 struct ahci_cmd_tbl *cmd_tbl; 1875 struct ahci_cmd_header *cmd_h; 1876 1877 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1878 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1879 1880 ata_channel_lock_owned(chp); 1881 1882 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1883 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1884 cmd_tbl), DEBUG_XFERS); 1885 1886 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1887 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1888 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1889 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1890 1891 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1892 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1893 chp->ch_channel, cmd_h), DEBUG_XFERS); 1894 if (ahci_dma_setup(chp, xfer->c_slot, 1895 sc_xfer->datalen ? sc_xfer->data : NULL, 1896 sc_xfer->datalen, 1897 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1898 BUS_DMA_READ : BUS_DMA_WRITE)) { 1899 sc_xfer->error = XS_DRIVER_STUFFUP; 1900 return ATASTART_ABORT; 1901 } 1902 cmd_h->cmdh_flags = htole16( 1903 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1904 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1905 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1906 cmd_h->cmdh_prdbc = 0; 1907 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1908 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1909 1910 if (xfer->c_flags & C_POLL) { 1911 /* polled command, disable interrupts */ 1912 AHCI_WRITE(sc, AHCI_GHC, 1913 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1914 } 1915 /* start command */ 1916 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1917 1918 if ((xfer->c_flags & C_POLL) == 0) { 1919 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1920 ata_timeout, chp); 1921 return ATASTART_STARTED; 1922 } else 1923 return ATASTART_POLL; 1924 } 1925 1926 static void 1927 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1928 { 1929 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1930 struct ahci_channel *achp = (struct ahci_channel *)chp; 1931 1932 /* 1933 * Polled command. 1934 */ 1935 for (int i = 0; i < ATA_DELAY / 10; i++) { 1936 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1937 break; 1938 ahci_intr_port(achp); 1939 delay(10000); 1940 } 1941 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1942 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1943 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1944 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1945 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1946 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1947 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1948 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1949 DEBUG_XFERS); 1950 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1951 xfer->c_scsipi->error = XS_TIMEOUT; 1952 xfer->ops->c_intr(chp, xfer, 0); 1953 } 1954 /* reenable interrupts */ 1955 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1956 } 1957 1958 static void 1959 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1960 { 1961 ahci_atapi_complete(chp, xfer, 0); 1962 } 1963 1964 static int 1965 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1966 { 1967 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1968 struct ahci_channel *achp = (struct ahci_channel *)chp; 1969 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1970 1971 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1972 DEBUG_FUNCS); 1973 1974 if (ata_waitdrain_xfer_check(chp, xfer)) 1975 return 0; 1976 1977 if (xfer->c_flags & C_TIMEOU) { 1978 sc_xfer->error = XS_TIMEOUT; 1979 } 1980 1981 if (xfer->c_bcount > 0) { 1982 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1983 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1984 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1985 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1986 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1987 } 1988 1989 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1990 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1991 sc_xfer->resid = sc_xfer->datalen; 1992 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1993 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1994 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1995 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1996 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1997 sc_xfer->resid == sc_xfer->datalen)) { 1998 sc_xfer->error = XS_SHORTSENSE; 1999 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2000 if ((sc_xfer->xs_periph->periph_quirks & 2001 PQUIRK_NOSENSE) == 0) { 2002 /* ask scsipi to send a REQUEST_SENSE */ 2003 sc_xfer->error = XS_BUSY; 2004 sc_xfer->status = SCSI_CHECK; 2005 } 2006 } 2007 2008 ata_deactivate_xfer(chp, xfer); 2009 2010 ata_free_xfer(chp, xfer); 2011 scsipi_done(sc_xfer); 2012 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2013 atastart(chp); 2014 return 0; 2015 } 2016 2017 static void 2018 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2019 { 2020 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2021 bool deactivate = true; 2022 2023 /* remove this command from xfer queue */ 2024 switch (reason) { 2025 case KILL_GONE_INACTIVE: 2026 deactivate = false; 2027 /* FALLTHROUGH */ 2028 case KILL_GONE: 2029 sc_xfer->error = XS_DRIVER_STUFFUP; 2030 break; 2031 case KILL_RESET: 2032 sc_xfer->error = XS_RESET; 2033 break; 2034 case KILL_REQUEUE: 2035 sc_xfer->error = XS_REQUEUE; 2036 break; 2037 default: 2038 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2039 panic("ahci_ata_atapi_kill_xfer"); 2040 } 2041 2042 if (deactivate) 2043 ata_deactivate_xfer(chp, xfer); 2044 2045 ata_free_xfer(chp, xfer); 2046 scsipi_done(sc_xfer); 2047 } 2048 2049 static void 2050 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2051 { 2052 struct scsipi_channel *chan = sc->sc_channel; 2053 struct scsipi_periph *periph; 2054 struct ataparams ids; 2055 struct ataparams *id = &ids; 2056 struct ahci_softc *ahcic = 2057 device_private(chan->chan_adapter->adapt_dev); 2058 struct atac_softc *atac = &ahcic->sc_atac; 2059 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2060 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2061 struct scsipibus_attach_args sa; 2062 char serial_number[21], model[41], firmware_revision[9]; 2063 int s; 2064 2065 /* skip if already attached */ 2066 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2067 return; 2068 2069 /* if no ATAPI device detected at attach time, skip */ 2070 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2071 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2072 "not present\n", target), DEBUG_PROBE); 2073 return; 2074 } 2075 2076 /* Some ATAPI devices need a bit more time after software reset. */ 2077 delay(5000); 2078 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2079 #ifdef ATAPI_DEBUG_PROBE 2080 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2081 AHCINAME(ahcic), target, 2082 id->atap_config & ATAPI_CFG_CMD_MASK, 2083 id->atap_config & ATAPI_CFG_DRQ_MASK); 2084 #endif 2085 periph = scsipi_alloc_periph(M_NOWAIT); 2086 if (periph == NULL) { 2087 aprint_error_dev(sc->sc_dev, 2088 "unable to allocate periph for drive %d\n", 2089 target); 2090 return; 2091 } 2092 periph->periph_dev = NULL; 2093 periph->periph_channel = chan; 2094 periph->periph_switch = &atapi_probe_periphsw; 2095 periph->periph_target = target; 2096 periph->periph_lun = 0; 2097 periph->periph_quirks = PQUIRK_ONLYBIG; 2098 2099 #ifdef SCSIPI_DEBUG 2100 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2101 SCSIPI_DEBUG_TARGET == target) 2102 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2103 #endif 2104 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2105 if (id->atap_config & ATAPI_CFG_REMOV) 2106 periph->periph_flags |= PERIPH_REMOVABLE; 2107 if (periph->periph_type == T_SEQUENTIAL) { 2108 s = splbio(); 2109 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2110 splx(s); 2111 } 2112 2113 sa.sa_periph = periph; 2114 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2115 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2116 T_REMOV : T_FIXED; 2117 strnvisx(model, sizeof(model), id->atap_model, 40, 2118 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2119 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2120 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2121 strnvisx(firmware_revision, sizeof(firmware_revision), 2122 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2123 sa.sa_inqbuf.vendor = model; 2124 sa.sa_inqbuf.product = serial_number; 2125 sa.sa_inqbuf.revision = firmware_revision; 2126 2127 /* 2128 * Determine the operating mode capabilities of the device. 2129 */ 2130 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2131 periph->periph_cap |= PERIPH_CAP_CMD16; 2132 /* XXX This is gross. */ 2133 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2134 2135 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2136 2137 if (drvp->drv_softc) 2138 ata_probe_caps(drvp); 2139 else { 2140 s = splbio(); 2141 drvp->drive_type = ATA_DRIVET_NONE; 2142 splx(s); 2143 } 2144 } else { 2145 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2146 "failed for drive %s:%d:%d\n", 2147 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2148 s = splbio(); 2149 drvp->drive_type = ATA_DRIVET_NONE; 2150 splx(s); 2151 } 2152 } 2153 #endif /* NATAPIBUS */ 2154
Indexes created Wed Sep 24 14:09:57 GMT 2025