ahcisata_core.c revision 1.76
1 /* $NetBSD: ahcisata_core.c,v 1.76 2019/09/29 21:21:41 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.76 2019/09/29 21:21:41 jakllsch Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 280 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 281 ahci_rev = AHCI_READ(sc, AHCI_VS); 282 snprintb(buf, sizeof(buf), "\177\020" 283 /* "f\000\005NP\0" */ 284 "b\005SXS\0" 285 "b\006EMS\0" 286 "b\007CCCS\0" 287 /* "f\010\005NCS\0" */ 288 "b\015PSC\0" 289 "b\016SSC\0" 290 "b\017PMD\0" 291 "b\020FBSS\0" 292 "b\021SPM\0" 293 "b\022SAM\0" 294 "b\023SNZO\0" 295 "f\024\003ISS\0" 296 "=\001Gen1\0" 297 "=\002Gen2\0" 298 "=\003Gen3\0" 299 "b\030SCLO\0" 300 "b\031SAL\0" 301 "b\032SALP\0" 302 "b\033SSS\0" 303 "b\034SMPS\0" 304 "b\035SSNTF\0" 305 "b\036SNCQ\0" 306 "b\037S64A\0" 307 "\0", sc->sc_ahci_cap); 308 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 309 ", %d port%s, %d slot%s, CAP %s\n", 310 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 311 sc->sc_atac.atac_nchannels, 312 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 313 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 314 315 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 316 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 317 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 318 sc->sc_atac.atac_pio_cap = 4; 319 sc->sc_atac.atac_dma_cap = 2; 320 sc->sc_atac.atac_udma_cap = 6; 321 sc->sc_atac.atac_channels = sc->sc_chanarray; 322 sc->sc_atac.atac_probe = ahci_probe_drive; 323 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 324 sc->sc_atac.atac_set_modes = ahci_setup_channel; 325 #if NATAPIBUS > 0 326 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 327 #endif 328 329 dmasize = 330 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 331 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 332 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 333 if (error) { 334 aprint_error("%s: unable to allocate command header memory" 335 ", error=%d\n", AHCINAME(sc), error); 336 return; 337 } 338 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 339 sc->sc_cmd_hdr_nseg, dmasize, 340 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 341 if (error) { 342 aprint_error("%s: unable to map command header memory" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 347 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 348 if (error) { 349 aprint_error("%s: unable to create command header map" 350 ", error=%d\n", AHCINAME(sc), error); 351 return; 352 } 353 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 354 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 355 if (error) { 356 aprint_error("%s: unable to load command header map" 357 ", error=%d\n", AHCINAME(sc), error); 358 return; 359 } 360 sc->sc_cmd_hdr = cmdhp; 361 362 ahci_enable_intrs(sc); 363 364 if (sc->sc_ahci_ports == 0) { 365 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 366 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 367 DEBUG_PROBE); 368 } 369 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 370 if ((sc->sc_ahci_ports & (1U << i)) == 0) 371 continue; 372 if (port >= sc->sc_atac.atac_nchannels) { 373 aprint_error("%s: more ports than announced\n", 374 AHCINAME(sc)); 375 break; 376 } 377 378 /* Optional intr establish per active port */ 379 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 380 aprint_error("%s: intr establish hook failed\n", 381 AHCINAME(sc)); 382 break; 383 } 384 385 achp = &sc->sc_channels[i]; 386 chp = &achp->ata_channel; 387 sc->sc_chanarray[i] = chp; 388 chp->ch_channel = i; 389 chp->ch_atac = &sc->sc_atac; 390 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 391 if (chp->ch_queue == NULL) { 392 aprint_error("%s port %d: can't allocate memory for " 393 "command queue", AHCINAME(sc), i); 394 break; 395 } 396 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 397 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 398 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 399 BUS_DMA_NOWAIT); 400 if (error) { 401 aprint_error("%s: unable to allocate command table " 402 "memory, error=%d\n", AHCINAME(sc), error); 403 break; 404 } 405 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 406 achp->ahcic_cmd_tbl_nseg, dmasize, 407 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 408 if (error) { 409 aprint_error("%s: unable to map command table memory" 410 ", error=%d\n", AHCINAME(sc), error); 411 break; 412 } 413 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 414 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 415 if (error) { 416 aprint_error("%s: unable to create command table map" 417 ", error=%d\n", AHCINAME(sc), error); 418 break; 419 } 420 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 421 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 422 if (error) { 423 aprint_error("%s: unable to load command table map" 424 ", error=%d\n", AHCINAME(sc), error); 425 break; 426 } 427 achp->ahcic_cmdh = (struct ahci_cmd_header *) 428 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 429 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 430 AHCI_CMDH_SIZE * port; 431 achp->ahcic_rfis = (struct ahci_r_fis *) 432 ((char *)cmdhp + 433 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 434 AHCI_RFIS_SIZE * port); 435 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 436 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 437 AHCI_RFIS_SIZE * port; 438 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 439 "rfis %p (0x%" PRIx64 ")\n", i, 440 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 441 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 442 DEBUG_PROBE); 443 444 for (j = 0; j < sc->sc_ncmds; j++) { 445 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 446 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 447 achp->ahcic_bus_cmd_tbl[j] = 448 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 449 AHCI_CMDTBL_SIZE * j; 450 achp->ahcic_cmdh[j].cmdh_cmdtba = 451 htole64(achp->ahcic_bus_cmd_tbl[j]); 452 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 453 achp->ahcic_cmd_tbl[j], 454 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 455 /* The xfer DMA map */ 456 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 457 AHCI_NPRD, 0x400000 /* 4MB */, 0, 458 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 459 &achp->ahcic_datad[j]); 460 if (error) { 461 aprint_error("%s: couldn't alloc xfer DMA map, " 462 "error=%d\n", AHCINAME(sc), error); 463 goto end; 464 } 465 } 466 ahci_setup_port(sc, i); 467 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 468 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 469 aprint_error("%s: couldn't map port %d " 470 "sata_status regs\n", AHCINAME(sc), i); 471 break; 472 } 473 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 474 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 475 aprint_error("%s: couldn't map port %d " 476 "sata_control regs\n", AHCINAME(sc), i); 477 break; 478 } 479 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 480 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 481 aprint_error("%s: couldn't map port %d " 482 "sata_error regs\n", AHCINAME(sc), i); 483 break; 484 } 485 ata_channel_attach(chp); 486 port++; 487 end: 488 continue; 489 } 490 } 491 492 void 493 ahci_childdetached(struct ahci_softc *sc, device_t child) 494 { 495 struct ahci_channel *achp; 496 struct ata_channel *chp; 497 498 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 499 achp = &sc->sc_channels[i]; 500 chp = &achp->ata_channel; 501 502 if ((sc->sc_ahci_ports & (1U << i)) == 0) 503 continue; 504 505 if (child == chp->atabus) 506 chp->atabus = NULL; 507 } 508 } 509 510 int 511 ahci_detach(struct ahci_softc *sc, int flags) 512 { 513 struct atac_softc *atac; 514 struct ahci_channel *achp; 515 struct ata_channel *chp; 516 struct scsipi_adapter *adapt; 517 int i, j, port; 518 int error; 519 520 atac = &sc->sc_atac; 521 adapt = &atac->atac_atapi_adapter._generic; 522 523 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 524 achp = &sc->sc_channels[i]; 525 chp = &achp->ata_channel; 526 527 if ((sc->sc_ahci_ports & (1U << i)) == 0) 528 continue; 529 if (port >= sc->sc_atac.atac_nchannels) { 530 aprint_error("%s: more ports than announced\n", 531 AHCINAME(sc)); 532 break; 533 } 534 535 if (chp->atabus != NULL) { 536 if ((error = config_detach(chp->atabus, flags)) != 0) 537 return error; 538 539 KASSERT(chp->atabus == NULL); 540 } 541 542 if (chp->ch_flags & ATACH_DETACHED) 543 continue; 544 545 for (j = 0; j < sc->sc_ncmds; j++) 546 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 547 548 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 549 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 550 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 551 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 552 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 553 achp->ahcic_cmd_tbl_nseg); 554 555 ata_channel_detach(chp); 556 port++; 557 } 558 559 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 560 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 561 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 562 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 563 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 564 565 if (adapt->adapt_refcnt != 0) 566 return EBUSY; 567 568 return 0; 569 } 570 571 void 572 ahci_resume(struct ahci_softc *sc) 573 { 574 ahci_reset(sc); 575 ahci_setup_ports(sc); 576 ahci_reprobe_drives(sc); 577 ahci_enable_intrs(sc); 578 } 579 580 int 581 ahci_intr(void *v) 582 { 583 struct ahci_softc *sc = v; 584 uint32_t is; 585 int i, r = 0; 586 587 while ((is = AHCI_READ(sc, AHCI_IS))) { 588 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 589 DEBUG_INTR); 590 r = 1; 591 AHCI_WRITE(sc, AHCI_IS, is); 592 for (i = 0; i < AHCI_MAX_PORTS; i++) 593 if (is & (1U << i)) 594 ahci_intr_port(&sc->sc_channels[i]); 595 } 596 597 return r; 598 } 599 600 int 601 ahci_intr_port(void *v) 602 { 603 struct ahci_channel *achp = v; 604 struct ata_channel *chp = &achp->ata_channel; 605 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 606 uint32_t is, tfd, sact; 607 struct ata_xfer *xfer; 608 int slot = -1; 609 bool recover = false; 610 uint32_t aslots; 611 612 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 613 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 614 615 AHCIDEBUG_PRINT(( 616 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 617 AHCINAME(sc), 618 chp->ch_channel, is, 619 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 620 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 621 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 622 DEBUG_INTR); 623 624 if ((chp->ch_flags & ATACH_NCQ) == 0) { 625 /* Non-NCQ operation */ 626 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 627 } else { 628 /* NCQ operation */ 629 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 630 } 631 632 /* Handle errors */ 633 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 634 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 635 /* Fatal errors */ 636 if (is & AHCI_P_IX_TFES) { 637 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 638 639 if ((chp->ch_flags & ATACH_NCQ) == 0) { 640 /* Slot valid only for Non-NCQ operation */ 641 slot = (AHCI_READ(sc, 642 AHCI_P_CMD(chp->ch_channel)) 643 & AHCI_P_CMD_CCS_MASK) 644 >> AHCI_P_CMD_CCS_SHIFT; 645 } 646 647 AHCIDEBUG_PRINT(( 648 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 649 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 650 DEBUG_INTR); 651 } else { 652 /* mark an error, and set BSY */ 653 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 654 WDCS_ERR | WDCS_BSY; 655 } 656 657 if (is & AHCI_P_IX_IFS) { 658 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 659 AHCINAME(sc), chp->ch_channel, 660 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 661 DEBUG_INTR); 662 } 663 664 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 665 recover = true; 666 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 667 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 668 669 /* D2H Register FIS or Set Device Bits */ 670 if ((tfd & WDCS_ERR) != 0) { 671 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 672 recover = true; 673 674 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 675 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 676 677 } 678 } else { 679 tfd = 0; 680 } 681 682 if (__predict_false(recover)) 683 ata_channel_freeze(chp); 684 685 aslots = ata_queue_active(chp); 686 687 if (slot >= 0) { 688 if ((aslots & __BIT(slot)) != 0 && 689 (sact & __BIT(slot)) == 0) { 690 xfer = ata_queue_hwslot_to_xfer(chp, slot); 691 xfer->ops->c_intr(chp, xfer, tfd); 692 } 693 } else { 694 /* 695 * For NCQ, HBA halts processing when error is notified, 696 * and any further D2H FISes are ignored until the error 697 * condition is cleared. Hence if a command is inactive, 698 * it means it actually already finished successfully. 699 * Note: active slots can change as c_intr() callback 700 * can activate another command(s), so must only process 701 * commands active before we start processing. 702 */ 703 704 for (slot=0; slot < sc->sc_ncmds; slot++) { 705 if ((aslots & __BIT(slot)) != 0 && 706 (sact & __BIT(slot)) == 0) { 707 xfer = ata_queue_hwslot_to_xfer(chp, slot); 708 xfer->ops->c_intr(chp, xfer, tfd); 709 } 710 } 711 } 712 713 if (__predict_false(recover)) { 714 ata_channel_lock(chp); 715 ata_channel_thaw_locked(chp); 716 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 717 ata_channel_unlock(chp); 718 } 719 720 return 1; 721 } 722 723 static void 724 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 725 { 726 struct ata_channel *chp = drvp->chnl_softc; 727 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 728 uint8_t c_slot; 729 730 ata_channel_lock_owned(chp); 731 732 /* get a slot for running the command on */ 733 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 734 panic("%s: %s: failed to get xfer for reset, port %d\n", 735 device_xname(sc->sc_atac.atac_dev), 736 __func__, chp->ch_channel); 737 /* NOTREACHED */ 738 } 739 740 AHCI_WRITE(sc, AHCI_GHC, 741 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 742 ahci_channel_stop(sc, chp, flags); 743 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 744 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 745 746 ata_queue_free_slot(chp, c_slot); 747 } 748 749 /* return error code from ata_bio */ 750 static int 751 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 752 { 753 struct ahci_channel *achp = (struct ahci_channel *)chp; 754 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 755 int i; 756 uint32_t is; 757 758 /* 759 * Base timeout is specified in ms. 760 * If we are allowed to sleep, wait a tick each round. 761 * Otherwise delay for 10ms on each round. 762 */ 763 if (flags & AT_WAIT) 764 timeout = MAX(1, mstohz(timeout)); 765 else 766 timeout = timeout / 10; 767 768 AHCI_CMDH_SYNC(sc, achp, slot, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 /* start command */ 771 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 772 for (i = 0; i < timeout; i++) { 773 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 774 0) 775 return 0; 776 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 777 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 778 AHCI_P_IX_IFS | 779 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 780 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 781 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 782 /* 783 * we got the D2H FIS anyway, 784 * assume sig is valid. 785 * channel is restarted later 786 */ 787 return ERROR; 788 } 789 aprint_debug("%s port %d: error 0x%x sending FIS\n", 790 AHCINAME(sc), chp->ch_channel, is); 791 return ERR_DF; 792 } 793 ata_delay(chp, 10, "ahcifis", flags); 794 } 795 796 aprint_debug("%s port %d: timeout sending FIS\n", 797 AHCINAME(sc), chp->ch_channel); 798 return TIMEOUT; 799 } 800 801 static int 802 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 803 uint32_t *sigp, uint8_t c_slot) 804 { 805 struct ahci_channel *achp = (struct ahci_channel *)chp; 806 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 807 struct ahci_cmd_tbl *cmd_tbl; 808 struct ahci_cmd_header *cmd_h; 809 int i, error = 0; 810 uint32_t sig; 811 int noclo_retry = 0; 812 813 ata_channel_lock_owned(chp); 814 815 again: 816 /* clear port interrupt register */ 817 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 818 /* clear SErrors and start operations */ 819 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 820 /* 821 * issue a command list override to clear BSY. 822 * This is needed if there's a PMP with no drive 823 * on port 0 824 */ 825 ahci_channel_start(sc, chp, flags, 1); 826 } else { 827 /* Can't handle command still running without CLO */ 828 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 829 830 ahci_channel_start(sc, chp, flags, 0); 831 } 832 if (drive > 0) { 833 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 834 } 835 836 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 837 goto skip_reset; 838 839 /* polled command, assume interrupts are disabled */ 840 841 cmd_h = &achp->ahcic_cmdh[c_slot]; 842 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 843 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 844 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 845 cmd_h->cmdh_prdtl = 0; 846 cmd_h->cmdh_prdbc = 0; 847 memset(cmd_tbl->cmdt_cfis, 0, 64); 848 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 849 cmd_tbl->cmdt_cfis[rhd_c] = drive; 850 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 851 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 852 case ERR_DF: 853 case TIMEOUT: 854 /* 855 * without CLO we can't make sure a software reset will 856 * success, as the drive may still have BSY or DRQ set. 857 * in this case, reset the whole channel and retry the 858 * drive reset. The channel reset should clear BSY and DRQ 859 */ 860 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 861 noclo_retry++; 862 ahci_reset_channel(chp, flags); 863 goto again; 864 } 865 aprint_error("%s port %d: setting WDCTL_RST failed " 866 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 867 error = EBUSY; 868 goto end; 869 default: 870 break; 871 } 872 873 /* 874 * SATA specification has toggle period for SRST bit of 5 usec. Some 875 * controllers fail to process the SRST clear operation unless 876 * we wait for at least this period between the set and clear commands. 877 */ 878 ata_delay(chp, 10, "ahcirstw", flags); 879 880 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 881 (drive << AHCI_CMDH_F_PMP_SHIFT)); 882 cmd_h->cmdh_prdbc = 0; 883 memset(cmd_tbl->cmdt_cfis, 0, 64); 884 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 885 cmd_tbl->cmdt_cfis[rhd_c] = drive; 886 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 887 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 888 case ERR_DF: 889 case TIMEOUT: 890 aprint_error("%s port %d: clearing WDCTL_RST failed " 891 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 892 error = EBUSY; 893 goto end; 894 default: 895 break; 896 } 897 898 skip_reset: 899 /* 900 * wait 31s for BSY to clear 901 * This should not be needed, but some controllers clear the 902 * command slot before receiving the D2H FIS ... 903 */ 904 for (i = 0; i < AHCI_RST_WAIT; i++) { 905 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 906 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 907 break; 908 ata_delay(chp, 10, "ahcid2h", flags); 909 } 910 if (i == AHCI_RST_WAIT) { 911 aprint_error("%s: BSY never cleared, TD 0x%x\n", 912 AHCINAME(sc), sig); 913 goto end; 914 } 915 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 916 DEBUG_PROBE); 917 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 918 if (sigp) 919 *sigp = sig; 920 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 921 AHCINAME(sc), chp->ch_channel, sig, 922 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 923 end: 924 ahci_channel_stop(sc, chp, flags); 925 ata_delay(chp, 500, "ahcirst", flags); 926 /* clear port interrupt register */ 927 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 928 ahci_channel_start(sc, chp, flags, 929 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 930 return error; 931 } 932 933 static void 934 ahci_reset_channel(struct ata_channel *chp, int flags) 935 { 936 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 937 struct ahci_channel *achp = (struct ahci_channel *)chp; 938 int i, tfd; 939 940 ata_channel_lock_owned(chp); 941 942 ahci_channel_stop(sc, chp, flags); 943 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 944 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 945 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 946 /* XXX and then ? */ 947 } 948 ata_kill_active(chp, KILL_RESET, flags); 949 ata_delay(chp, 500, "ahcirst", flags); 950 /* clear port interrupt register */ 951 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 952 /* clear SErrors and start operations */ 953 ahci_channel_start(sc, chp, flags, 954 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 955 /* wait 31s for BSY to clear */ 956 for (i = 0; i < AHCI_RST_WAIT; i++) { 957 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 958 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 959 break; 960 ata_delay(chp, 10, "ahcid2h", flags); 961 } 962 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 963 aprint_error("%s: BSY never cleared, TD 0x%x\n", 964 AHCINAME(sc), tfd); 965 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 966 DEBUG_PROBE); 967 /* clear port interrupt register */ 968 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 969 970 return; 971 } 972 973 static int 974 ahci_ata_addref(struct ata_drive_datas *drvp) 975 { 976 return 0; 977 } 978 979 static void 980 ahci_ata_delref(struct ata_drive_datas *drvp) 981 { 982 return; 983 } 984 985 static void 986 ahci_killpending(struct ata_drive_datas *drvp) 987 { 988 return; 989 } 990 991 static void 992 ahci_probe_drive(struct ata_channel *chp) 993 { 994 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 995 struct ahci_channel *achp = (struct ahci_channel *)chp; 996 uint32_t sig; 997 uint8_t c_slot; 998 int error; 999 1000 ata_channel_lock(chp); 1001 1002 /* get a slot for running the command on */ 1003 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1004 aprint_error_dev(sc->sc_atac.atac_dev, 1005 "%s: failed to get xfer port %d\n", 1006 __func__, chp->ch_channel); 1007 ata_channel_unlock(chp); 1008 return; 1009 } 1010 1011 /* bring interface up, accept FISs, power up and spin up device */ 1012 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1013 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1014 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1015 /* reset the PHY and bring online */ 1016 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1017 achp->ahcic_sstatus, AT_WAIT)) { 1018 case SStatus_DET_DEV: 1019 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1020 1021 /* Initial value, used in case the soft reset fails */ 1022 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1023 1024 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1025 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1026 &sig, c_slot); 1027 1028 /* If probe for PMP failed, just fallback to drive 0 */ 1029 if (error) { 1030 aprint_error("%s port %d: drive %d reset " 1031 "failed, disabling PMP\n", 1032 AHCINAME(sc), chp->ch_channel, 1033 PMP_PORT_CTL); 1034 1035 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1036 ahci_reset_channel(chp, AT_WAIT); 1037 } 1038 } else { 1039 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1040 } 1041 sata_interpret_sig(chp, 0, sig); 1042 /* if we have a PMP attached, inform the controller */ 1043 if (chp->ch_ndrives > PMP_PORT_CTL && 1044 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1045 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1046 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1047 AHCI_P_CMD_PMA); 1048 } 1049 /* clear port interrupt register */ 1050 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1051 1052 /* and enable interrupts */ 1053 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1054 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1055 AHCI_P_IX_IFS | 1056 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1057 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1058 /* wait 500ms before actually starting operations */ 1059 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1060 break; 1061 1062 default: 1063 break; 1064 } 1065 1066 ata_queue_free_slot(chp, c_slot); 1067 1068 ata_channel_unlock(chp); 1069 } 1070 1071 static void 1072 ahci_setup_channel(struct ata_channel *chp) 1073 { 1074 return; 1075 } 1076 1077 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1078 .c_start = ahci_cmd_start, 1079 .c_poll = ahci_cmd_poll, 1080 .c_abort = ahci_cmd_abort, 1081 .c_intr = ahci_cmd_complete, 1082 .c_kill_xfer = ahci_cmd_kill_xfer, 1083 }; 1084 1085 static int 1086 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1087 { 1088 struct ata_channel *chp = drvp->chnl_softc; 1089 struct ata_command *ata_c = &xfer->c_ata_c; 1090 int ret; 1091 int s; 1092 1093 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1094 chp->ch_channel, 1095 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1096 DEBUG_XFERS); 1097 if (ata_c->flags & AT_POLL) 1098 xfer->c_flags |= C_POLL; 1099 if (ata_c->flags & AT_WAIT) 1100 xfer->c_flags |= C_WAIT; 1101 xfer->c_drive = drvp->drive; 1102 xfer->c_databuf = ata_c->data; 1103 xfer->c_bcount = ata_c->bcount; 1104 xfer->ops = &ahci_cmd_xfer_ops; 1105 s = splbio(); 1106 ata_exec_xfer(chp, xfer); 1107 #ifdef DIAGNOSTIC 1108 if ((ata_c->flags & AT_POLL) != 0 && 1109 (ata_c->flags & AT_DONE) == 0) 1110 panic("ahci_exec_command: polled command not done"); 1111 #endif 1112 if (ata_c->flags & AT_DONE) { 1113 ret = ATACMD_COMPLETE; 1114 } else { 1115 if (ata_c->flags & AT_WAIT) { 1116 ata_wait_cmd(chp, xfer); 1117 ret = ATACMD_COMPLETE; 1118 } else { 1119 ret = ATACMD_QUEUED; 1120 } 1121 } 1122 splx(s); 1123 return ret; 1124 } 1125 1126 static int 1127 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1128 { 1129 struct ahci_softc *sc = AHCI_CH2SC(chp); 1130 struct ahci_channel *achp = (struct ahci_channel *)chp; 1131 struct ata_command *ata_c = &xfer->c_ata_c; 1132 int slot = xfer->c_slot; 1133 struct ahci_cmd_tbl *cmd_tbl; 1134 struct ahci_cmd_header *cmd_h; 1135 1136 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1137 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1138 ata_c->timeout, slot), 1139 DEBUG_XFERS); 1140 1141 ata_channel_lock_owned(chp); 1142 1143 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1144 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1145 cmd_tbl), DEBUG_XFERS); 1146 1147 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1148 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1149 1150 cmd_h = &achp->ahcic_cmdh[slot]; 1151 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1152 chp->ch_channel, cmd_h), DEBUG_XFERS); 1153 if (ahci_dma_setup(chp, slot, 1154 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1155 ata_c->data : NULL, 1156 ata_c->bcount, 1157 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1158 ata_c->flags |= AT_DF; 1159 return ATASTART_ABORT; 1160 } 1161 cmd_h->cmdh_flags = htole16( 1162 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1163 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1164 cmd_h->cmdh_prdbc = 0; 1165 AHCI_CMDH_SYNC(sc, achp, slot, 1166 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1167 1168 if (ata_c->flags & AT_POLL) { 1169 /* polled command, disable interrupts */ 1170 AHCI_WRITE(sc, AHCI_GHC, 1171 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1172 } 1173 /* start command */ 1174 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1175 1176 if ((ata_c->flags & AT_POLL) == 0) { 1177 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1178 ata_timeout, chp); 1179 return ATASTART_STARTED; 1180 } else 1181 return ATASTART_POLL; 1182 } 1183 1184 static void 1185 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1186 { 1187 struct ahci_softc *sc = AHCI_CH2SC(chp); 1188 struct ahci_channel *achp = (struct ahci_channel *)chp; 1189 1190 ata_channel_lock(chp); 1191 1192 /* 1193 * Polled command. 1194 */ 1195 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1196 if (xfer->c_ata_c.flags & AT_DONE) 1197 break; 1198 ata_channel_unlock(chp); 1199 ahci_intr_port(achp); 1200 ata_channel_lock(chp); 1201 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1202 } 1203 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1204 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1205 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1206 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1207 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1208 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1209 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1210 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1211 DEBUG_XFERS); 1212 1213 ata_channel_unlock(chp); 1214 1215 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1216 xfer->c_ata_c.flags |= AT_TIMEOU; 1217 xfer->ops->c_intr(chp, xfer, 0); 1218 } 1219 /* reenable interrupts */ 1220 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1221 } 1222 1223 static void 1224 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1225 { 1226 ahci_cmd_complete(chp, xfer, 0); 1227 } 1228 1229 static void 1230 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1231 { 1232 struct ata_command *ata_c = &xfer->c_ata_c; 1233 bool deactivate = true; 1234 1235 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1236 DEBUG_FUNCS); 1237 1238 switch (reason) { 1239 case KILL_GONE_INACTIVE: 1240 deactivate = false; 1241 /* FALLTHROUGH */ 1242 case KILL_GONE: 1243 ata_c->flags |= AT_GONE; 1244 break; 1245 case KILL_RESET: 1246 ata_c->flags |= AT_RESET; 1247 break; 1248 case KILL_REQUEUE: 1249 panic("%s: not supposed to be requeued\n", __func__); 1250 break; 1251 default: 1252 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1253 panic("ahci_cmd_kill_xfer"); 1254 } 1255 1256 ahci_cmd_done_end(chp, xfer); 1257 1258 if (deactivate) 1259 ata_deactivate_xfer(chp, xfer); 1260 } 1261 1262 static int 1263 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1264 { 1265 struct ata_command *ata_c = &xfer->c_ata_c; 1266 struct ahci_channel *achp = (struct ahci_channel *)chp; 1267 1268 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1269 chp->ch_channel, 1270 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1271 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1272 DEBUG_FUNCS); 1273 1274 if (ata_waitdrain_xfer_check(chp, xfer)) 1275 return 0; 1276 1277 if (xfer->c_flags & C_TIMEOU) { 1278 ata_c->flags |= AT_TIMEOU; 1279 } 1280 1281 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1282 ata_c->flags |= AT_TIMEOU; 1283 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1284 ata_c->r_error = AHCI_TFD_ERR(tfd); 1285 ata_c->flags |= AT_ERROR; 1286 } 1287 1288 if (ata_c->flags & AT_READREG) 1289 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1290 1291 ahci_cmd_done(chp, xfer); 1292 1293 ata_deactivate_xfer(chp, xfer); 1294 1295 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1296 atastart(chp); 1297 1298 return 0; 1299 } 1300 1301 static void 1302 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1303 { 1304 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1305 struct ahci_channel *achp = (struct ahci_channel *)chp; 1306 struct ata_command *ata_c = &xfer->c_ata_c; 1307 uint16_t *idwordbuf; 1308 int i; 1309 1310 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1311 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1312 1313 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1314 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1315 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1316 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1317 BUS_DMASYNC_POSTWRITE); 1318 bus_dmamap_unload(sc->sc_dmat, map); 1319 } 1320 1321 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1322 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1323 1324 /* ata(4) expects IDENTIFY data to be in host endianess */ 1325 if (ata_c->r_command == WDCC_IDENTIFY || 1326 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1327 idwordbuf = xfer->c_databuf; 1328 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1329 idwordbuf[i] = le16toh(idwordbuf[i]); 1330 } 1331 } 1332 1333 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1334 ata_c->flags |= AT_XFDONE; 1335 1336 ahci_cmd_done_end(chp, xfer); 1337 } 1338 1339 static void 1340 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1341 { 1342 struct ata_command *ata_c = &xfer->c_ata_c; 1343 1344 ata_c->flags |= AT_DONE; 1345 } 1346 1347 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1348 .c_start = ahci_bio_start, 1349 .c_poll = ahci_bio_poll, 1350 .c_abort = ahci_bio_abort, 1351 .c_intr = ahci_bio_complete, 1352 .c_kill_xfer = ahci_bio_kill_xfer, 1353 }; 1354 1355 static int 1356 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1357 { 1358 struct ata_channel *chp = drvp->chnl_softc; 1359 struct ata_bio *ata_bio = &xfer->c_bio; 1360 1361 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1362 chp->ch_channel, 1363 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1364 DEBUG_XFERS); 1365 if (ata_bio->flags & ATA_POLL) 1366 xfer->c_flags |= C_POLL; 1367 xfer->c_drive = drvp->drive; 1368 xfer->c_databuf = ata_bio->databuf; 1369 xfer->c_bcount = ata_bio->bcount; 1370 xfer->ops = &ahci_bio_xfer_ops; 1371 ata_exec_xfer(chp, xfer); 1372 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1373 } 1374 1375 static int 1376 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1377 { 1378 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1379 struct ahci_channel *achp = (struct ahci_channel *)chp; 1380 struct ata_bio *ata_bio = &xfer->c_bio; 1381 struct ahci_cmd_tbl *cmd_tbl; 1382 struct ahci_cmd_header *cmd_h; 1383 1384 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1385 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1386 1387 ata_channel_lock_owned(chp); 1388 1389 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1390 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1391 cmd_tbl), DEBUG_XFERS); 1392 1393 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1394 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1395 1396 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1397 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1398 chp->ch_channel, cmd_h), DEBUG_XFERS); 1399 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1400 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1401 ata_bio->error = ERR_DMA; 1402 ata_bio->r_error = 0; 1403 return ATASTART_ABORT; 1404 } 1405 cmd_h->cmdh_flags = htole16( 1406 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1407 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1408 cmd_h->cmdh_prdbc = 0; 1409 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1410 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1411 1412 if (xfer->c_flags & C_POLL) { 1413 /* polled command, disable interrupts */ 1414 AHCI_WRITE(sc, AHCI_GHC, 1415 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1416 } 1417 if (xfer->c_flags & C_NCQ) 1418 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1419 /* start command */ 1420 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1421 1422 if ((xfer->c_flags & C_POLL) == 0) { 1423 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1424 ata_timeout, chp); 1425 return ATASTART_STARTED; 1426 } else 1427 return ATASTART_POLL; 1428 } 1429 1430 static void 1431 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1432 { 1433 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1434 struct ahci_channel *achp = (struct ahci_channel *)chp; 1435 1436 /* 1437 * Polled command. 1438 */ 1439 for (int i = 0; i < ATA_DELAY * 10; i++) { 1440 if (xfer->c_bio.flags & ATA_ITSDONE) 1441 break; 1442 ahci_intr_port(achp); 1443 delay(100); 1444 } 1445 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1446 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1447 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1448 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1449 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1450 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1451 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1452 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1453 DEBUG_XFERS); 1454 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1455 xfer->c_bio.error = TIMEOUT; 1456 xfer->ops->c_intr(chp, xfer, 0); 1457 } 1458 /* reenable interrupts */ 1459 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1460 } 1461 1462 static void 1463 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1464 { 1465 ahci_bio_complete(chp, xfer, 0); 1466 } 1467 1468 static void 1469 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1470 { 1471 int drive = xfer->c_drive; 1472 struct ata_bio *ata_bio = &xfer->c_bio; 1473 bool deactivate = true; 1474 1475 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1476 DEBUG_FUNCS); 1477 1478 ata_bio->flags |= ATA_ITSDONE; 1479 switch (reason) { 1480 case KILL_GONE_INACTIVE: 1481 deactivate = false; 1482 /* FALLTHROUGH */ 1483 case KILL_GONE: 1484 ata_bio->error = ERR_NODEV; 1485 break; 1486 case KILL_RESET: 1487 ata_bio->error = ERR_RESET; 1488 break; 1489 case KILL_REQUEUE: 1490 ata_bio->error = REQUEUE; 1491 break; 1492 default: 1493 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1494 panic("ahci_bio_kill_xfer"); 1495 } 1496 ata_bio->r_error = WDCE_ABRT; 1497 1498 if (deactivate) 1499 ata_deactivate_xfer(chp, xfer); 1500 1501 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1502 } 1503 1504 static int 1505 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1506 { 1507 struct ata_bio *ata_bio = &xfer->c_bio; 1508 int drive = xfer->c_drive; 1509 struct ahci_channel *achp = (struct ahci_channel *)chp; 1510 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1511 1512 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1513 DEBUG_FUNCS); 1514 1515 if (ata_waitdrain_xfer_check(chp, xfer)) 1516 return 0; 1517 1518 if (xfer->c_flags & C_TIMEOU) { 1519 ata_bio->error = TIMEOUT; 1520 } 1521 1522 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1523 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1524 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1525 BUS_DMASYNC_POSTWRITE); 1526 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1527 1528 ata_bio->flags |= ATA_ITSDONE; 1529 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1530 ata_bio->error = ERR_DF; 1531 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1532 ata_bio->error = ERROR; 1533 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1534 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1535 ata_bio->flags |= ATA_CORR; 1536 1537 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1538 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1539 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1540 ata_bio->bcount), DEBUG_XFERS); 1541 /* 1542 * If it was a write, complete data buffer may have been transfered 1543 * before error detection; in this case don't use cmdh_prdbc 1544 * as it won't reflect what was written to media. Assume nothing 1545 * was transfered and leave bcount as-is. 1546 * For queued commands, PRD Byte Count should not be used, and is 1547 * not required to be valid; in that case underflow is always illegal. 1548 */ 1549 if ((xfer->c_flags & C_NCQ) != 0) { 1550 if (ata_bio->error == NOERROR) 1551 ata_bio->bcount = 0; 1552 } else { 1553 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1554 ata_bio->bcount -= 1555 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1556 } 1557 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1558 1559 ata_deactivate_xfer(chp, xfer); 1560 1561 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1562 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1563 atastart(chp); 1564 return 0; 1565 } 1566 1567 static void 1568 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1569 { 1570 int i; 1571 /* stop channel */ 1572 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1573 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1574 /* wait 1s for channel to stop */ 1575 for (i = 0; i <100; i++) { 1576 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1577 == 0) 1578 break; 1579 ata_delay(chp, 10, "ahcistop", flags); 1580 } 1581 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1582 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1583 /* XXX controller reset ? */ 1584 return; 1585 } 1586 1587 if (sc->sc_channel_stop) 1588 sc->sc_channel_stop(sc, chp); 1589 } 1590 1591 static void 1592 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1593 int flags, int clo) 1594 { 1595 int i; 1596 uint32_t p_cmd; 1597 /* clear error */ 1598 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1599 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1600 1601 if (clo) { 1602 /* issue command list override */ 1603 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1604 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1605 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1606 /* wait 1s for AHCI_CAP_CLO to clear */ 1607 for (i = 0; i <100; i++) { 1608 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1609 AHCI_P_CMD_CLO) == 0) 1610 break; 1611 ata_delay(chp, 10, "ahciclo", flags); 1612 } 1613 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1614 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1615 /* XXX controller reset ? */ 1616 return; 1617 } 1618 } 1619 1620 if (sc->sc_channel_start) 1621 sc->sc_channel_start(sc, chp); 1622 1623 /* and start controller */ 1624 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1625 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1626 if (chp->ch_ndrives > PMP_PORT_CTL && 1627 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1628 p_cmd |= AHCI_P_CMD_PMA; 1629 } 1630 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1631 } 1632 1633 /* Recover channel after command failure */ 1634 static void 1635 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1636 { 1637 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1638 int drive = ATACH_NODRIVE; 1639 bool reset = false; 1640 1641 ata_channel_lock_owned(chp); 1642 1643 /* 1644 * Read FBS to get the drive which caused the error, if PM is in use. 1645 * According to AHCI 1.3 spec, this register is available regardless 1646 * if FIS-based switching (FBSS) feature is supported, or disabled. 1647 * If FIS-based switching is not in use, it merely maintains single 1648 * pair of DRQ/BSY state, but it is enough since in that case we 1649 * never issue commands for more than one device at the time anyway. 1650 * XXX untested 1651 */ 1652 if (chp->ch_ndrives > PMP_PORT_CTL) { 1653 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1654 if (fbs & AHCI_P_FBS_SDE) { 1655 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1656 1657 /* 1658 * Tell HBA to reset PM port X (value in DWE) state, 1659 * and resume processing commands for other ports. 1660 */ 1661 fbs |= AHCI_P_FBS_DEC; 1662 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1663 for (int i = 0; i < 1000; i++) { 1664 fbs = AHCI_READ(sc, 1665 AHCI_P_FBS(chp->ch_channel)); 1666 if ((fbs & AHCI_P_FBS_DEC) == 0) 1667 break; 1668 DELAY(1000); 1669 } 1670 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1671 /* follow non-device specific recovery */ 1672 drive = ATACH_NODRIVE; 1673 reset = true; 1674 } 1675 } else { 1676 /* not device specific, reset channel */ 1677 drive = ATACH_NODRIVE; 1678 reset = true; 1679 } 1680 } else 1681 drive = 0; 1682 1683 /* 1684 * If BSY or DRQ bits are set, must execute COMRESET to return 1685 * device to idle state. If drive is idle, it's enough to just 1686 * reset CMD.ST, it's not necessary to do software reset. 1687 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1688 * to unblock device processing if COMRESET was not done. 1689 */ 1690 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1691 ahci_reset_channel(chp, flags); 1692 goto out; 1693 } 1694 1695 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1696 ahci_channel_stop(sc, chp, flags); 1697 ahci_channel_start(sc, chp, flags, 1698 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1699 1700 ata_recovery_resume(chp, drive, tfd, flags); 1701 1702 out: 1703 /* Drive unblocked, back to normal operation */ 1704 return; 1705 } 1706 1707 static int 1708 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1709 size_t count, int op) 1710 { 1711 int error, seg; 1712 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1713 struct ahci_channel *achp = (struct ahci_channel *)chp; 1714 struct ahci_cmd_tbl *cmd_tbl; 1715 struct ahci_cmd_header *cmd_h; 1716 1717 cmd_h = &achp->ahcic_cmdh[slot]; 1718 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1719 1720 if (data == NULL) { 1721 cmd_h->cmdh_prdtl = 0; 1722 goto end; 1723 } 1724 1725 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1726 data, count, NULL, 1727 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1728 if (error) { 1729 printf("%s port %d: failed to load xfer: %d\n", 1730 AHCINAME(sc), chp->ch_channel, error); 1731 return error; 1732 } 1733 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1734 achp->ahcic_datad[slot]->dm_mapsize, 1735 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1736 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1737 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1738 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1739 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1740 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1741 } 1742 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1743 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1744 end: 1745 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1746 return 0; 1747 } 1748 1749 #if NATAPIBUS > 0 1750 static void 1751 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1752 { 1753 struct ata_channel *chp = ata_sc->sc_chan; 1754 struct atac_softc *atac = chp->ch_atac; 1755 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1756 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1757 /* 1758 * Fill in the scsipi_adapter. 1759 */ 1760 adapt->adapt_dev = atac->atac_dev; 1761 adapt->adapt_nchannels = atac->atac_nchannels; 1762 adapt->adapt_request = ahci_atapi_scsipi_request; 1763 adapt->adapt_minphys = ahci_atapi_minphys; 1764 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1765 1766 /* 1767 * Fill in the scsipi_channel. 1768 */ 1769 memset(chan, 0, sizeof(*chan)); 1770 chan->chan_adapter = adapt; 1771 chan->chan_bustype = &ahci_atapi_bustype; 1772 chan->chan_channel = chp->ch_channel; 1773 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1774 chan->chan_openings = 1; 1775 chan->chan_max_periph = 1; 1776 chan->chan_ntargets = 1; 1777 chan->chan_nluns = 1; 1778 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1779 atapiprint); 1780 } 1781 1782 static void 1783 ahci_atapi_minphys(struct buf *bp) 1784 { 1785 if (bp->b_bcount > MAXPHYS) 1786 bp->b_bcount = MAXPHYS; 1787 minphys(bp); 1788 } 1789 1790 /* 1791 * Kill off all pending xfers for a periph. 1792 * 1793 * Must be called at splbio(). 1794 */ 1795 static void 1796 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1797 { 1798 struct atac_softc *atac = 1799 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1800 struct ata_channel *chp = 1801 atac->atac_channels[periph->periph_channel->chan_channel]; 1802 1803 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1804 } 1805 1806 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1807 .c_start = ahci_atapi_start, 1808 .c_poll = ahci_atapi_poll, 1809 .c_abort = ahci_atapi_abort, 1810 .c_intr = ahci_atapi_complete, 1811 .c_kill_xfer = ahci_atapi_kill_xfer, 1812 }; 1813 1814 static void 1815 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1816 scsipi_adapter_req_t req, void *arg) 1817 { 1818 struct scsipi_adapter *adapt = chan->chan_adapter; 1819 struct scsipi_periph *periph; 1820 struct scsipi_xfer *sc_xfer; 1821 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1822 struct atac_softc *atac = &sc->sc_atac; 1823 struct ata_xfer *xfer; 1824 int channel = chan->chan_channel; 1825 int drive, s; 1826 1827 switch (req) { 1828 case ADAPTER_REQ_RUN_XFER: 1829 sc_xfer = arg; 1830 periph = sc_xfer->xs_periph; 1831 drive = periph->periph_target; 1832 if (!device_is_active(atac->atac_dev)) { 1833 sc_xfer->error = XS_DRIVER_STUFFUP; 1834 scsipi_done(sc_xfer); 1835 return; 1836 } 1837 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1838 if (xfer == NULL) { 1839 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1840 scsipi_done(sc_xfer); 1841 return; 1842 } 1843 1844 if (sc_xfer->xs_control & XS_CTL_POLL) 1845 xfer->c_flags |= C_POLL; 1846 xfer->c_drive = drive; 1847 xfer->c_flags |= C_ATAPI; 1848 xfer->c_databuf = sc_xfer->data; 1849 xfer->c_bcount = sc_xfer->datalen; 1850 xfer->ops = &ahci_atapi_xfer_ops; 1851 xfer->c_scsipi = sc_xfer; 1852 xfer->c_atapi.c_dscpoll = 0; 1853 s = splbio(); 1854 ata_exec_xfer(atac->atac_channels[channel], xfer); 1855 #ifdef DIAGNOSTIC 1856 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1857 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1858 panic("ahci_atapi_scsipi_request: polled command " 1859 "not done"); 1860 #endif 1861 splx(s); 1862 return; 1863 default: 1864 /* Not supported, nothing to do. */ 1865 ; 1866 } 1867 } 1868 1869 static int 1870 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1871 { 1872 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1873 struct ahci_channel *achp = (struct ahci_channel *)chp; 1874 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1875 struct ahci_cmd_tbl *cmd_tbl; 1876 struct ahci_cmd_header *cmd_h; 1877 1878 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1879 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1880 1881 ata_channel_lock_owned(chp); 1882 1883 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1884 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1885 cmd_tbl), DEBUG_XFERS); 1886 1887 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1888 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1889 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1890 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1891 1892 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1893 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1894 chp->ch_channel, cmd_h), DEBUG_XFERS); 1895 if (ahci_dma_setup(chp, xfer->c_slot, 1896 sc_xfer->datalen ? sc_xfer->data : NULL, 1897 sc_xfer->datalen, 1898 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1899 BUS_DMA_READ : BUS_DMA_WRITE)) { 1900 sc_xfer->error = XS_DRIVER_STUFFUP; 1901 return ATASTART_ABORT; 1902 } 1903 cmd_h->cmdh_flags = htole16( 1904 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1905 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1906 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1907 cmd_h->cmdh_prdbc = 0; 1908 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1909 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1910 1911 if (xfer->c_flags & C_POLL) { 1912 /* polled command, disable interrupts */ 1913 AHCI_WRITE(sc, AHCI_GHC, 1914 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1915 } 1916 /* start command */ 1917 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1918 1919 if ((xfer->c_flags & C_POLL) == 0) { 1920 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1921 ata_timeout, chp); 1922 return ATASTART_STARTED; 1923 } else 1924 return ATASTART_POLL; 1925 } 1926 1927 static void 1928 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1929 { 1930 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1931 struct ahci_channel *achp = (struct ahci_channel *)chp; 1932 1933 /* 1934 * Polled command. 1935 */ 1936 for (int i = 0; i < ATA_DELAY / 10; i++) { 1937 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1938 break; 1939 ahci_intr_port(achp); 1940 delay(10000); 1941 } 1942 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1943 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1944 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1945 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1946 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1947 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1948 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1949 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1950 DEBUG_XFERS); 1951 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1952 xfer->c_scsipi->error = XS_TIMEOUT; 1953 xfer->ops->c_intr(chp, xfer, 0); 1954 } 1955 /* reenable interrupts */ 1956 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1957 } 1958 1959 static void 1960 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1961 { 1962 ahci_atapi_complete(chp, xfer, 0); 1963 } 1964 1965 static int 1966 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1967 { 1968 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1969 struct ahci_channel *achp = (struct ahci_channel *)chp; 1970 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1971 1972 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1973 DEBUG_FUNCS); 1974 1975 if (ata_waitdrain_xfer_check(chp, xfer)) 1976 return 0; 1977 1978 if (xfer->c_flags & C_TIMEOU) { 1979 sc_xfer->error = XS_TIMEOUT; 1980 } 1981 1982 if (xfer->c_bcount > 0) { 1983 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1984 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1985 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1986 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1987 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1988 } 1989 1990 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1991 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1992 sc_xfer->resid = sc_xfer->datalen; 1993 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1994 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1995 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1996 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1997 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1998 sc_xfer->resid == sc_xfer->datalen)) { 1999 sc_xfer->error = XS_SHORTSENSE; 2000 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2001 if ((sc_xfer->xs_periph->periph_quirks & 2002 PQUIRK_NOSENSE) == 0) { 2003 /* ask scsipi to send a REQUEST_SENSE */ 2004 sc_xfer->error = XS_BUSY; 2005 sc_xfer->status = SCSI_CHECK; 2006 } 2007 } 2008 2009 ata_deactivate_xfer(chp, xfer); 2010 2011 ata_free_xfer(chp, xfer); 2012 scsipi_done(sc_xfer); 2013 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2014 atastart(chp); 2015 return 0; 2016 } 2017 2018 static void 2019 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2020 { 2021 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2022 bool deactivate = true; 2023 2024 /* remove this command from xfer queue */ 2025 switch (reason) { 2026 case KILL_GONE_INACTIVE: 2027 deactivate = false; 2028 /* FALLTHROUGH */ 2029 case KILL_GONE: 2030 sc_xfer->error = XS_DRIVER_STUFFUP; 2031 break; 2032 case KILL_RESET: 2033 sc_xfer->error = XS_RESET; 2034 break; 2035 case KILL_REQUEUE: 2036 sc_xfer->error = XS_REQUEUE; 2037 break; 2038 default: 2039 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2040 panic("ahci_ata_atapi_kill_xfer"); 2041 } 2042 2043 if (deactivate) 2044 ata_deactivate_xfer(chp, xfer); 2045 2046 ata_free_xfer(chp, xfer); 2047 scsipi_done(sc_xfer); 2048 } 2049 2050 static void 2051 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2052 { 2053 struct scsipi_channel *chan = sc->sc_channel; 2054 struct scsipi_periph *periph; 2055 struct ataparams ids; 2056 struct ataparams *id = &ids; 2057 struct ahci_softc *ahcic = 2058 device_private(chan->chan_adapter->adapt_dev); 2059 struct atac_softc *atac = &ahcic->sc_atac; 2060 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2061 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2062 struct scsipibus_attach_args sa; 2063 char serial_number[21], model[41], firmware_revision[9]; 2064 int s; 2065 2066 /* skip if already attached */ 2067 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2068 return; 2069 2070 /* if no ATAPI device detected at attach time, skip */ 2071 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2072 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2073 "not present\n", target), DEBUG_PROBE); 2074 return; 2075 } 2076 2077 /* Some ATAPI devices need a bit more time after software reset. */ 2078 delay(5000); 2079 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2080 #ifdef ATAPI_DEBUG_PROBE 2081 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2082 AHCINAME(ahcic), target, 2083 id->atap_config & ATAPI_CFG_CMD_MASK, 2084 id->atap_config & ATAPI_CFG_DRQ_MASK); 2085 #endif 2086 periph = scsipi_alloc_periph(M_NOWAIT); 2087 if (periph == NULL) { 2088 aprint_error_dev(sc->sc_dev, 2089 "unable to allocate periph for drive %d\n", 2090 target); 2091 return; 2092 } 2093 periph->periph_dev = NULL; 2094 periph->periph_channel = chan; 2095 periph->periph_switch = &atapi_probe_periphsw; 2096 periph->periph_target = target; 2097 periph->periph_lun = 0; 2098 periph->periph_quirks = PQUIRK_ONLYBIG; 2099 2100 #ifdef SCSIPI_DEBUG 2101 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2102 SCSIPI_DEBUG_TARGET == target) 2103 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2104 #endif 2105 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2106 if (id->atap_config & ATAPI_CFG_REMOV) 2107 periph->periph_flags |= PERIPH_REMOVABLE; 2108 if (periph->periph_type == T_SEQUENTIAL) { 2109 s = splbio(); 2110 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2111 splx(s); 2112 } 2113 2114 sa.sa_periph = periph; 2115 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2116 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2117 T_REMOV : T_FIXED; 2118 strnvisx(model, sizeof(model), id->atap_model, 40, 2119 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2120 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2121 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2122 strnvisx(firmware_revision, sizeof(firmware_revision), 2123 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2124 sa.sa_inqbuf.vendor = model; 2125 sa.sa_inqbuf.product = serial_number; 2126 sa.sa_inqbuf.revision = firmware_revision; 2127 2128 /* 2129 * Determine the operating mode capabilities of the device. 2130 */ 2131 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2132 periph->periph_cap |= PERIPH_CAP_CMD16; 2133 /* XXX This is gross. */ 2134 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2135 2136 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2137 2138 if (drvp->drv_softc) 2139 ata_probe_caps(drvp); 2140 else { 2141 s = splbio(); 2142 drvp->drive_type = ATA_DRIVET_NONE; 2143 splx(s); 2144 } 2145 } else { 2146 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2147 "failed for drive %s:%d:%d\n", 2148 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2149 s = splbio(); 2150 drvp->drive_type = ATA_DRIVET_NONE; 2151 splx(s); 2152 } 2153 } 2154 #endif /* NATAPIBUS */ 2155
Indexes created Fri Sep 26 08:10:20 GMT 2025