ahcisata_core.c revision 1.77
1 /* $NetBSD: ahcisata_core.c,v 1.77 2019/09/29 21:25:08 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.77 2019/09/29 21:25:08 jakllsch Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 280 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 281 ahci_rev = AHCI_READ(sc, AHCI_VS); 282 snprintb(buf, sizeof(buf), "\177\020" 283 /* "f\000\005NP\0" */ 284 "b\005SXS\0" 285 "b\006EMS\0" 286 "b\007CCCS\0" 287 /* "f\010\005NCS\0" */ 288 "b\015PSC\0" 289 "b\016SSC\0" 290 "b\017PMD\0" 291 "b\020FBSS\0" 292 "b\021SPM\0" 293 "b\022SAM\0" 294 "b\023SNZO\0" 295 "f\024\003ISS\0" 296 "=\001Gen1\0" 297 "=\002Gen2\0" 298 "=\003Gen3\0" 299 "b\030SCLO\0" 300 "b\031SAL\0" 301 "b\032SALP\0" 302 "b\033SSS\0" 303 "b\034SMPS\0" 304 "b\035SSNTF\0" 305 "b\036SNCQ\0" 306 "b\037S64A\0" 307 "\0", sc->sc_ahci_cap); 308 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 309 ", %d port%s, %d slot%s, CAP %s\n", 310 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 311 sc->sc_atac.atac_nchannels, 312 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 313 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 314 315 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 316 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 317 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 318 sc->sc_atac.atac_pio_cap = 4; 319 sc->sc_atac.atac_dma_cap = 2; 320 sc->sc_atac.atac_udma_cap = 6; 321 sc->sc_atac.atac_channels = sc->sc_chanarray; 322 sc->sc_atac.atac_probe = ahci_probe_drive; 323 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 324 sc->sc_atac.atac_set_modes = ahci_setup_channel; 325 #if NATAPIBUS > 0 326 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 327 #endif 328 329 dmasize = 330 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 331 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 332 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 333 if (error) { 334 aprint_error("%s: unable to allocate command header memory" 335 ", error=%d\n", AHCINAME(sc), error); 336 return; 337 } 338 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 339 sc->sc_cmd_hdr_nseg, dmasize, 340 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 341 if (error) { 342 aprint_error("%s: unable to map command header memory" 343 ", error=%d\n", AHCINAME(sc), error); 344 return; 345 } 346 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 347 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 348 if (error) { 349 aprint_error("%s: unable to create command header map" 350 ", error=%d\n", AHCINAME(sc), error); 351 return; 352 } 353 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 354 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 355 if (error) { 356 aprint_error("%s: unable to load command header map" 357 ", error=%d\n", AHCINAME(sc), error); 358 return; 359 } 360 sc->sc_cmd_hdr = cmdhp; 361 362 ahci_enable_intrs(sc); 363 364 if (sc->sc_ahci_ports == 0) { 365 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 366 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 367 DEBUG_PROBE); 368 } 369 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 370 if ((sc->sc_ahci_ports & (1U << i)) == 0) 371 continue; 372 if (port >= sc->sc_atac.atac_nchannels) { 373 aprint_error("%s: more ports than announced\n", 374 AHCINAME(sc)); 375 break; 376 } 377 378 /* Optional intr establish per active port */ 379 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 380 aprint_error("%s: intr establish hook failed\n", 381 AHCINAME(sc)); 382 break; 383 } 384 385 achp = &sc->sc_channels[i]; 386 chp = &achp->ata_channel; 387 sc->sc_chanarray[i] = chp; 388 chp->ch_channel = i; 389 chp->ch_atac = &sc->sc_atac; 390 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 391 if (chp->ch_queue == NULL) { 392 aprint_error("%s port %d: can't allocate memory for " 393 "command queue", AHCINAME(sc), i); 394 break; 395 } 396 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 397 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 398 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 399 BUS_DMA_NOWAIT); 400 if (error) { 401 aprint_error("%s: unable to allocate command table " 402 "memory, error=%d\n", AHCINAME(sc), error); 403 break; 404 } 405 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 406 achp->ahcic_cmd_tbl_nseg, dmasize, 407 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 408 if (error) { 409 aprint_error("%s: unable to map command table memory" 410 ", error=%d\n", AHCINAME(sc), error); 411 break; 412 } 413 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 414 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 415 if (error) { 416 aprint_error("%s: unable to create command table map" 417 ", error=%d\n", AHCINAME(sc), error); 418 break; 419 } 420 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 421 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 422 if (error) { 423 aprint_error("%s: unable to load command table map" 424 ", error=%d\n", AHCINAME(sc), error); 425 break; 426 } 427 achp->ahcic_cmdh = (struct ahci_cmd_header *) 428 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 429 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 430 AHCI_CMDH_SIZE * port; 431 achp->ahcic_rfis = (struct ahci_r_fis *) 432 ((char *)cmdhp + 433 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 434 AHCI_RFIS_SIZE * port); 435 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 436 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 437 AHCI_RFIS_SIZE * port; 438 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 439 "rfis %p (0x%" PRIx64 ")\n", i, 440 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 441 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 442 DEBUG_PROBE); 443 444 for (j = 0; j < sc->sc_ncmds; j++) { 445 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 446 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 447 achp->ahcic_bus_cmd_tbl[j] = 448 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 449 AHCI_CMDTBL_SIZE * j; 450 achp->ahcic_cmdh[j].cmdh_cmdtba = 451 htole64(achp->ahcic_bus_cmd_tbl[j]); 452 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 453 achp->ahcic_cmd_tbl[j], 454 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 455 /* The xfer DMA map */ 456 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 457 AHCI_NPRD, 0x400000 /* 4MB */, 0, 458 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 459 &achp->ahcic_datad[j]); 460 if (error) { 461 aprint_error("%s: couldn't alloc xfer DMA map, " 462 "error=%d\n", AHCINAME(sc), error); 463 goto end; 464 } 465 } 466 ahci_setup_port(sc, i); 467 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 468 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 469 aprint_error("%s: couldn't map port %d " 470 "sata_status regs\n", AHCINAME(sc), i); 471 break; 472 } 473 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 474 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 475 aprint_error("%s: couldn't map port %d " 476 "sata_control regs\n", AHCINAME(sc), i); 477 break; 478 } 479 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 480 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 481 aprint_error("%s: couldn't map port %d " 482 "sata_error regs\n", AHCINAME(sc), i); 483 break; 484 } 485 ata_channel_attach(chp); 486 port++; 487 end: 488 continue; 489 } 490 } 491 492 void 493 ahci_childdetached(struct ahci_softc *sc, device_t child) 494 { 495 struct ahci_channel *achp; 496 struct ata_channel *chp; 497 498 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 499 achp = &sc->sc_channels[i]; 500 chp = &achp->ata_channel; 501 502 if ((sc->sc_ahci_ports & (1U << i)) == 0) 503 continue; 504 505 if (child == chp->atabus) 506 chp->atabus = NULL; 507 } 508 } 509 510 int 511 ahci_detach(struct ahci_softc *sc, int flags) 512 { 513 struct atac_softc *atac; 514 struct ahci_channel *achp; 515 struct ata_channel *chp; 516 struct scsipi_adapter *adapt; 517 int i, j, port; 518 int error; 519 520 atac = &sc->sc_atac; 521 adapt = &atac->atac_atapi_adapter._generic; 522 523 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 524 achp = &sc->sc_channels[i]; 525 chp = &achp->ata_channel; 526 527 if ((sc->sc_ahci_ports & (1U << i)) == 0) 528 continue; 529 if (port >= sc->sc_atac.atac_nchannels) { 530 aprint_error("%s: more ports than announced\n", 531 AHCINAME(sc)); 532 break; 533 } 534 535 if (chp->atabus != NULL) { 536 if ((error = config_detach(chp->atabus, flags)) != 0) 537 return error; 538 539 KASSERT(chp->atabus == NULL); 540 } 541 542 if (chp->ch_flags & ATACH_DETACHED) 543 continue; 544 545 for (j = 0; j < sc->sc_ncmds; j++) 546 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 547 548 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 549 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 550 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 551 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 552 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 553 achp->ahcic_cmd_tbl_nseg); 554 555 ata_channel_detach(chp); 556 port++; 557 } 558 559 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 560 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 561 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 562 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 563 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 564 565 if (adapt->adapt_refcnt != 0) 566 return EBUSY; 567 568 return 0; 569 } 570 571 void 572 ahci_resume(struct ahci_softc *sc) 573 { 574 ahci_reset(sc); 575 ahci_setup_ports(sc); 576 ahci_reprobe_drives(sc); 577 ahci_enable_intrs(sc); 578 } 579 580 int 581 ahci_intr(void *v) 582 { 583 struct ahci_softc *sc = v; 584 uint32_t is; 585 int i, r = 0; 586 587 while ((is = AHCI_READ(sc, AHCI_IS))) { 588 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 589 DEBUG_INTR); 590 r = 1; 591 AHCI_WRITE(sc, AHCI_IS, is); 592 for (i = 0; i < AHCI_MAX_PORTS; i++) 593 if (is & (1U << i)) 594 ahci_intr_port(&sc->sc_channels[i]); 595 } 596 597 return r; 598 } 599 600 int 601 ahci_intr_port(void *v) 602 { 603 struct ahci_channel *achp = v; 604 struct ata_channel *chp = &achp->ata_channel; 605 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 606 uint32_t is, tfd, sact; 607 struct ata_xfer *xfer; 608 int slot = -1; 609 bool recover = false; 610 uint32_t aslots; 611 612 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 613 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 614 615 AHCIDEBUG_PRINT(( 616 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 617 AHCINAME(sc), 618 chp->ch_channel, is, 619 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 620 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 621 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 622 DEBUG_INTR); 623 624 if ((chp->ch_flags & ATACH_NCQ) == 0) { 625 /* Non-NCQ operation */ 626 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 627 } else { 628 /* NCQ operation */ 629 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 630 } 631 632 /* Handle errors */ 633 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 634 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 635 /* Fatal errors */ 636 if (is & AHCI_P_IX_TFES) { 637 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 638 639 if ((chp->ch_flags & ATACH_NCQ) == 0) { 640 /* Slot valid only for Non-NCQ operation */ 641 slot = (AHCI_READ(sc, 642 AHCI_P_CMD(chp->ch_channel)) 643 & AHCI_P_CMD_CCS_MASK) 644 >> AHCI_P_CMD_CCS_SHIFT; 645 } 646 647 AHCIDEBUG_PRINT(( 648 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 649 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 650 DEBUG_INTR); 651 } else { 652 /* mark an error, and set BSY */ 653 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 654 WDCS_ERR | WDCS_BSY; 655 } 656 657 if (is & AHCI_P_IX_IFS) { 658 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 659 AHCINAME(sc), chp->ch_channel, 660 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 661 DEBUG_INTR); 662 } 663 664 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 665 recover = true; 666 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 667 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 668 669 /* D2H Register FIS or Set Device Bits */ 670 if ((tfd & WDCS_ERR) != 0) { 671 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 672 recover = true; 673 674 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 675 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 676 677 } 678 } else { 679 tfd = 0; 680 } 681 682 if (__predict_false(recover)) 683 ata_channel_freeze(chp); 684 685 aslots = ata_queue_active(chp); 686 687 if (slot >= 0) { 688 if ((aslots & __BIT(slot)) != 0 && 689 (sact & __BIT(slot)) == 0) { 690 xfer = ata_queue_hwslot_to_xfer(chp, slot); 691 xfer->ops->c_intr(chp, xfer, tfd); 692 } 693 } else { 694 /* 695 * For NCQ, HBA halts processing when error is notified, 696 * and any further D2H FISes are ignored until the error 697 * condition is cleared. Hence if a command is inactive, 698 * it means it actually already finished successfully. 699 * Note: active slots can change as c_intr() callback 700 * can activate another command(s), so must only process 701 * commands active before we start processing. 702 */ 703 704 for (slot=0; slot < sc->sc_ncmds; slot++) { 705 if ((aslots & __BIT(slot)) != 0 && 706 (sact & __BIT(slot)) == 0) { 707 xfer = ata_queue_hwslot_to_xfer(chp, slot); 708 xfer->ops->c_intr(chp, xfer, tfd); 709 } 710 } 711 } 712 713 if (__predict_false(recover)) { 714 ata_channel_lock(chp); 715 ata_channel_thaw_locked(chp); 716 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 717 ata_channel_unlock(chp); 718 } 719 720 return 1; 721 } 722 723 static void 724 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 725 { 726 struct ata_channel *chp = drvp->chnl_softc; 727 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 728 uint8_t c_slot; 729 730 ata_channel_lock_owned(chp); 731 732 /* get a slot for running the command on */ 733 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 734 panic("%s: %s: failed to get xfer for reset, port %d\n", 735 device_xname(sc->sc_atac.atac_dev), 736 __func__, chp->ch_channel); 737 /* NOTREACHED */ 738 } 739 740 AHCI_WRITE(sc, AHCI_GHC, 741 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 742 ahci_channel_stop(sc, chp, flags); 743 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 744 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 745 746 ata_queue_free_slot(chp, c_slot); 747 } 748 749 /* return error code from ata_bio */ 750 static int 751 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 752 { 753 struct ahci_channel *achp = (struct ahci_channel *)chp; 754 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 755 int i; 756 uint32_t is; 757 758 /* 759 * Base timeout is specified in ms. 760 * If we are allowed to sleep, wait a tick each round. 761 * Otherwise delay for 10ms on each round. 762 */ 763 if (flags & AT_WAIT) 764 timeout = MAX(1, mstohz(timeout)); 765 else 766 timeout = timeout / 10; 767 768 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 769 AHCI_CMDH_SYNC(sc, achp, slot, 770 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 771 /* start command */ 772 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 773 for (i = 0; i < timeout; i++) { 774 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 775 0) 776 return 0; 777 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 778 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 779 AHCI_P_IX_IFS | 780 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 781 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 782 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 783 /* 784 * we got the D2H FIS anyway, 785 * assume sig is valid. 786 * channel is restarted later 787 */ 788 return ERROR; 789 } 790 aprint_debug("%s port %d: error 0x%x sending FIS\n", 791 AHCINAME(sc), chp->ch_channel, is); 792 return ERR_DF; 793 } 794 ata_delay(chp, 10, "ahcifis", flags); 795 } 796 797 aprint_debug("%s port %d: timeout sending FIS\n", 798 AHCINAME(sc), chp->ch_channel); 799 return TIMEOUT; 800 } 801 802 static int 803 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 804 uint32_t *sigp, uint8_t c_slot) 805 { 806 struct ahci_channel *achp = (struct ahci_channel *)chp; 807 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 808 struct ahci_cmd_tbl *cmd_tbl; 809 struct ahci_cmd_header *cmd_h; 810 int i, error = 0; 811 uint32_t sig; 812 int noclo_retry = 0; 813 814 ata_channel_lock_owned(chp); 815 816 again: 817 /* clear port interrupt register */ 818 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 819 /* clear SErrors and start operations */ 820 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 821 /* 822 * issue a command list override to clear BSY. 823 * This is needed if there's a PMP with no drive 824 * on port 0 825 */ 826 ahci_channel_start(sc, chp, flags, 1); 827 } else { 828 /* Can't handle command still running without CLO */ 829 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 830 831 ahci_channel_start(sc, chp, flags, 0); 832 } 833 if (drive > 0) { 834 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 835 } 836 837 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 838 goto skip_reset; 839 840 /* polled command, assume interrupts are disabled */ 841 842 cmd_h = &achp->ahcic_cmdh[c_slot]; 843 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 844 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 845 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 846 cmd_h->cmdh_prdtl = 0; 847 cmd_h->cmdh_prdbc = 0; 848 memset(cmd_tbl->cmdt_cfis, 0, 64); 849 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 850 cmd_tbl->cmdt_cfis[rhd_c] = drive; 851 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 852 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 853 case ERR_DF: 854 case TIMEOUT: 855 /* 856 * without CLO we can't make sure a software reset will 857 * success, as the drive may still have BSY or DRQ set. 858 * in this case, reset the whole channel and retry the 859 * drive reset. The channel reset should clear BSY and DRQ 860 */ 861 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 862 noclo_retry++; 863 ahci_reset_channel(chp, flags); 864 goto again; 865 } 866 aprint_error("%s port %d: setting WDCTL_RST failed " 867 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 868 error = EBUSY; 869 goto end; 870 default: 871 break; 872 } 873 874 /* 875 * SATA specification has toggle period for SRST bit of 5 usec. Some 876 * controllers fail to process the SRST clear operation unless 877 * we wait for at least this period between the set and clear commands. 878 */ 879 ata_delay(chp, 10, "ahcirstw", flags); 880 881 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 882 (drive << AHCI_CMDH_F_PMP_SHIFT)); 883 cmd_h->cmdh_prdbc = 0; 884 memset(cmd_tbl->cmdt_cfis, 0, 64); 885 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 886 cmd_tbl->cmdt_cfis[rhd_c] = drive; 887 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 888 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 889 case ERR_DF: 890 case TIMEOUT: 891 aprint_error("%s port %d: clearing WDCTL_RST failed " 892 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 893 error = EBUSY; 894 goto end; 895 default: 896 break; 897 } 898 899 skip_reset: 900 /* 901 * wait 31s for BSY to clear 902 * This should not be needed, but some controllers clear the 903 * command slot before receiving the D2H FIS ... 904 */ 905 for (i = 0; i < AHCI_RST_WAIT; i++) { 906 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 907 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 908 break; 909 ata_delay(chp, 10, "ahcid2h", flags); 910 } 911 if (i == AHCI_RST_WAIT) { 912 aprint_error("%s: BSY never cleared, TD 0x%x\n", 913 AHCINAME(sc), sig); 914 goto end; 915 } 916 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 917 DEBUG_PROBE); 918 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 919 if (sigp) 920 *sigp = sig; 921 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 922 AHCINAME(sc), chp->ch_channel, sig, 923 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 924 end: 925 ahci_channel_stop(sc, chp, flags); 926 ata_delay(chp, 500, "ahcirst", flags); 927 /* clear port interrupt register */ 928 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 929 ahci_channel_start(sc, chp, flags, 930 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 931 return error; 932 } 933 934 static void 935 ahci_reset_channel(struct ata_channel *chp, int flags) 936 { 937 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 938 struct ahci_channel *achp = (struct ahci_channel *)chp; 939 int i, tfd; 940 941 ata_channel_lock_owned(chp); 942 943 ahci_channel_stop(sc, chp, flags); 944 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 945 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 946 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 947 /* XXX and then ? */ 948 } 949 ata_kill_active(chp, KILL_RESET, flags); 950 ata_delay(chp, 500, "ahcirst", flags); 951 /* clear port interrupt register */ 952 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 953 /* clear SErrors and start operations */ 954 ahci_channel_start(sc, chp, flags, 955 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 956 /* wait 31s for BSY to clear */ 957 for (i = 0; i < AHCI_RST_WAIT; i++) { 958 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 959 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 960 break; 961 ata_delay(chp, 10, "ahcid2h", flags); 962 } 963 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 964 aprint_error("%s: BSY never cleared, TD 0x%x\n", 965 AHCINAME(sc), tfd); 966 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 967 DEBUG_PROBE); 968 /* clear port interrupt register */ 969 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 970 971 return; 972 } 973 974 static int 975 ahci_ata_addref(struct ata_drive_datas *drvp) 976 { 977 return 0; 978 } 979 980 static void 981 ahci_ata_delref(struct ata_drive_datas *drvp) 982 { 983 return; 984 } 985 986 static void 987 ahci_killpending(struct ata_drive_datas *drvp) 988 { 989 return; 990 } 991 992 static void 993 ahci_probe_drive(struct ata_channel *chp) 994 { 995 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 996 struct ahci_channel *achp = (struct ahci_channel *)chp; 997 uint32_t sig; 998 uint8_t c_slot; 999 int error; 1000 1001 ata_channel_lock(chp); 1002 1003 /* get a slot for running the command on */ 1004 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1005 aprint_error_dev(sc->sc_atac.atac_dev, 1006 "%s: failed to get xfer port %d\n", 1007 __func__, chp->ch_channel); 1008 ata_channel_unlock(chp); 1009 return; 1010 } 1011 1012 /* bring interface up, accept FISs, power up and spin up device */ 1013 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1014 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1015 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1016 /* reset the PHY and bring online */ 1017 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1018 achp->ahcic_sstatus, AT_WAIT)) { 1019 case SStatus_DET_DEV: 1020 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1021 1022 /* Initial value, used in case the soft reset fails */ 1023 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1024 1025 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1026 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1027 &sig, c_slot); 1028 1029 /* If probe for PMP failed, just fallback to drive 0 */ 1030 if (error) { 1031 aprint_error("%s port %d: drive %d reset " 1032 "failed, disabling PMP\n", 1033 AHCINAME(sc), chp->ch_channel, 1034 PMP_PORT_CTL); 1035 1036 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1037 ahci_reset_channel(chp, AT_WAIT); 1038 } 1039 } else { 1040 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1041 } 1042 sata_interpret_sig(chp, 0, sig); 1043 /* if we have a PMP attached, inform the controller */ 1044 if (chp->ch_ndrives > PMP_PORT_CTL && 1045 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1046 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1047 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1048 AHCI_P_CMD_PMA); 1049 } 1050 /* clear port interrupt register */ 1051 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1052 1053 /* and enable interrupts */ 1054 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1055 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1056 AHCI_P_IX_IFS | 1057 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1058 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1059 /* wait 500ms before actually starting operations */ 1060 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1061 break; 1062 1063 default: 1064 break; 1065 } 1066 1067 ata_queue_free_slot(chp, c_slot); 1068 1069 ata_channel_unlock(chp); 1070 } 1071 1072 static void 1073 ahci_setup_channel(struct ata_channel *chp) 1074 { 1075 return; 1076 } 1077 1078 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1079 .c_start = ahci_cmd_start, 1080 .c_poll = ahci_cmd_poll, 1081 .c_abort = ahci_cmd_abort, 1082 .c_intr = ahci_cmd_complete, 1083 .c_kill_xfer = ahci_cmd_kill_xfer, 1084 }; 1085 1086 static int 1087 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1088 { 1089 struct ata_channel *chp = drvp->chnl_softc; 1090 struct ata_command *ata_c = &xfer->c_ata_c; 1091 int ret; 1092 int s; 1093 1094 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1095 chp->ch_channel, 1096 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1097 DEBUG_XFERS); 1098 if (ata_c->flags & AT_POLL) 1099 xfer->c_flags |= C_POLL; 1100 if (ata_c->flags & AT_WAIT) 1101 xfer->c_flags |= C_WAIT; 1102 xfer->c_drive = drvp->drive; 1103 xfer->c_databuf = ata_c->data; 1104 xfer->c_bcount = ata_c->bcount; 1105 xfer->ops = &ahci_cmd_xfer_ops; 1106 s = splbio(); 1107 ata_exec_xfer(chp, xfer); 1108 #ifdef DIAGNOSTIC 1109 if ((ata_c->flags & AT_POLL) != 0 && 1110 (ata_c->flags & AT_DONE) == 0) 1111 panic("ahci_exec_command: polled command not done"); 1112 #endif 1113 if (ata_c->flags & AT_DONE) { 1114 ret = ATACMD_COMPLETE; 1115 } else { 1116 if (ata_c->flags & AT_WAIT) { 1117 ata_wait_cmd(chp, xfer); 1118 ret = ATACMD_COMPLETE; 1119 } else { 1120 ret = ATACMD_QUEUED; 1121 } 1122 } 1123 splx(s); 1124 return ret; 1125 } 1126 1127 static int 1128 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1129 { 1130 struct ahci_softc *sc = AHCI_CH2SC(chp); 1131 struct ahci_channel *achp = (struct ahci_channel *)chp; 1132 struct ata_command *ata_c = &xfer->c_ata_c; 1133 int slot = xfer->c_slot; 1134 struct ahci_cmd_tbl *cmd_tbl; 1135 struct ahci_cmd_header *cmd_h; 1136 1137 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1138 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1139 ata_c->timeout, slot), 1140 DEBUG_XFERS); 1141 1142 ata_channel_lock_owned(chp); 1143 1144 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1145 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1146 cmd_tbl), DEBUG_XFERS); 1147 1148 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1149 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1150 1151 cmd_h = &achp->ahcic_cmdh[slot]; 1152 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1153 chp->ch_channel, cmd_h), DEBUG_XFERS); 1154 if (ahci_dma_setup(chp, slot, 1155 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1156 ata_c->data : NULL, 1157 ata_c->bcount, 1158 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1159 ata_c->flags |= AT_DF; 1160 return ATASTART_ABORT; 1161 } 1162 cmd_h->cmdh_flags = htole16( 1163 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1164 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1165 cmd_h->cmdh_prdbc = 0; 1166 AHCI_CMDH_SYNC(sc, achp, slot, 1167 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1168 1169 if (ata_c->flags & AT_POLL) { 1170 /* polled command, disable interrupts */ 1171 AHCI_WRITE(sc, AHCI_GHC, 1172 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1173 } 1174 /* start command */ 1175 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1176 1177 if ((ata_c->flags & AT_POLL) == 0) { 1178 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1179 ata_timeout, chp); 1180 return ATASTART_STARTED; 1181 } else 1182 return ATASTART_POLL; 1183 } 1184 1185 static void 1186 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1187 { 1188 struct ahci_softc *sc = AHCI_CH2SC(chp); 1189 struct ahci_channel *achp = (struct ahci_channel *)chp; 1190 1191 ata_channel_lock(chp); 1192 1193 /* 1194 * Polled command. 1195 */ 1196 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1197 if (xfer->c_ata_c.flags & AT_DONE) 1198 break; 1199 ata_channel_unlock(chp); 1200 ahci_intr_port(achp); 1201 ata_channel_lock(chp); 1202 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1203 } 1204 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1205 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1206 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1207 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1208 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1209 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1210 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1211 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1212 DEBUG_XFERS); 1213 1214 ata_channel_unlock(chp); 1215 1216 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1217 xfer->c_ata_c.flags |= AT_TIMEOU; 1218 xfer->ops->c_intr(chp, xfer, 0); 1219 } 1220 /* reenable interrupts */ 1221 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1222 } 1223 1224 static void 1225 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1226 { 1227 ahci_cmd_complete(chp, xfer, 0); 1228 } 1229 1230 static void 1231 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1232 { 1233 struct ata_command *ata_c = &xfer->c_ata_c; 1234 bool deactivate = true; 1235 1236 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1237 DEBUG_FUNCS); 1238 1239 switch (reason) { 1240 case KILL_GONE_INACTIVE: 1241 deactivate = false; 1242 /* FALLTHROUGH */ 1243 case KILL_GONE: 1244 ata_c->flags |= AT_GONE; 1245 break; 1246 case KILL_RESET: 1247 ata_c->flags |= AT_RESET; 1248 break; 1249 case KILL_REQUEUE: 1250 panic("%s: not supposed to be requeued\n", __func__); 1251 break; 1252 default: 1253 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1254 panic("ahci_cmd_kill_xfer"); 1255 } 1256 1257 ahci_cmd_done_end(chp, xfer); 1258 1259 if (deactivate) 1260 ata_deactivate_xfer(chp, xfer); 1261 } 1262 1263 static int 1264 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1265 { 1266 struct ata_command *ata_c = &xfer->c_ata_c; 1267 struct ahci_channel *achp = (struct ahci_channel *)chp; 1268 1269 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1270 chp->ch_channel, 1271 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1272 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1273 DEBUG_FUNCS); 1274 1275 if (ata_waitdrain_xfer_check(chp, xfer)) 1276 return 0; 1277 1278 if (xfer->c_flags & C_TIMEOU) { 1279 ata_c->flags |= AT_TIMEOU; 1280 } 1281 1282 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1283 ata_c->flags |= AT_TIMEOU; 1284 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1285 ata_c->r_error = AHCI_TFD_ERR(tfd); 1286 ata_c->flags |= AT_ERROR; 1287 } 1288 1289 if (ata_c->flags & AT_READREG) 1290 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1291 1292 ahci_cmd_done(chp, xfer); 1293 1294 ata_deactivate_xfer(chp, xfer); 1295 1296 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1297 atastart(chp); 1298 1299 return 0; 1300 } 1301 1302 static void 1303 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1304 { 1305 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1306 struct ahci_channel *achp = (struct ahci_channel *)chp; 1307 struct ata_command *ata_c = &xfer->c_ata_c; 1308 uint16_t *idwordbuf; 1309 int i; 1310 1311 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1312 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1313 1314 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1315 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1316 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1317 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1318 BUS_DMASYNC_POSTWRITE); 1319 bus_dmamap_unload(sc->sc_dmat, map); 1320 } 1321 1322 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1323 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1324 1325 /* ata(4) expects IDENTIFY data to be in host endianess */ 1326 if (ata_c->r_command == WDCC_IDENTIFY || 1327 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1328 idwordbuf = xfer->c_databuf; 1329 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1330 idwordbuf[i] = le16toh(idwordbuf[i]); 1331 } 1332 } 1333 1334 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1335 ata_c->flags |= AT_XFDONE; 1336 1337 ahci_cmd_done_end(chp, xfer); 1338 } 1339 1340 static void 1341 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1342 { 1343 struct ata_command *ata_c = &xfer->c_ata_c; 1344 1345 ata_c->flags |= AT_DONE; 1346 } 1347 1348 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1349 .c_start = ahci_bio_start, 1350 .c_poll = ahci_bio_poll, 1351 .c_abort = ahci_bio_abort, 1352 .c_intr = ahci_bio_complete, 1353 .c_kill_xfer = ahci_bio_kill_xfer, 1354 }; 1355 1356 static int 1357 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1358 { 1359 struct ata_channel *chp = drvp->chnl_softc; 1360 struct ata_bio *ata_bio = &xfer->c_bio; 1361 1362 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1363 chp->ch_channel, 1364 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1365 DEBUG_XFERS); 1366 if (ata_bio->flags & ATA_POLL) 1367 xfer->c_flags |= C_POLL; 1368 xfer->c_drive = drvp->drive; 1369 xfer->c_databuf = ata_bio->databuf; 1370 xfer->c_bcount = ata_bio->bcount; 1371 xfer->ops = &ahci_bio_xfer_ops; 1372 ata_exec_xfer(chp, xfer); 1373 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1374 } 1375 1376 static int 1377 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1378 { 1379 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1380 struct ahci_channel *achp = (struct ahci_channel *)chp; 1381 struct ata_bio *ata_bio = &xfer->c_bio; 1382 struct ahci_cmd_tbl *cmd_tbl; 1383 struct ahci_cmd_header *cmd_h; 1384 1385 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1386 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1387 1388 ata_channel_lock_owned(chp); 1389 1390 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1391 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1392 cmd_tbl), DEBUG_XFERS); 1393 1394 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1395 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1396 1397 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1398 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1399 chp->ch_channel, cmd_h), DEBUG_XFERS); 1400 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1401 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1402 ata_bio->error = ERR_DMA; 1403 ata_bio->r_error = 0; 1404 return ATASTART_ABORT; 1405 } 1406 cmd_h->cmdh_flags = htole16( 1407 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1408 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1409 cmd_h->cmdh_prdbc = 0; 1410 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1411 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1412 1413 if (xfer->c_flags & C_POLL) { 1414 /* polled command, disable interrupts */ 1415 AHCI_WRITE(sc, AHCI_GHC, 1416 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1417 } 1418 if (xfer->c_flags & C_NCQ) 1419 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1420 /* start command */ 1421 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1422 1423 if ((xfer->c_flags & C_POLL) == 0) { 1424 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1425 ata_timeout, chp); 1426 return ATASTART_STARTED; 1427 } else 1428 return ATASTART_POLL; 1429 } 1430 1431 static void 1432 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1433 { 1434 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1435 struct ahci_channel *achp = (struct ahci_channel *)chp; 1436 1437 /* 1438 * Polled command. 1439 */ 1440 for (int i = 0; i < ATA_DELAY * 10; i++) { 1441 if (xfer->c_bio.flags & ATA_ITSDONE) 1442 break; 1443 ahci_intr_port(achp); 1444 delay(100); 1445 } 1446 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1447 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1448 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1449 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1450 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1451 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1452 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1453 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1454 DEBUG_XFERS); 1455 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1456 xfer->c_bio.error = TIMEOUT; 1457 xfer->ops->c_intr(chp, xfer, 0); 1458 } 1459 /* reenable interrupts */ 1460 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1461 } 1462 1463 static void 1464 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1465 { 1466 ahci_bio_complete(chp, xfer, 0); 1467 } 1468 1469 static void 1470 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1471 { 1472 int drive = xfer->c_drive; 1473 struct ata_bio *ata_bio = &xfer->c_bio; 1474 bool deactivate = true; 1475 1476 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1477 DEBUG_FUNCS); 1478 1479 ata_bio->flags |= ATA_ITSDONE; 1480 switch (reason) { 1481 case KILL_GONE_INACTIVE: 1482 deactivate = false; 1483 /* FALLTHROUGH */ 1484 case KILL_GONE: 1485 ata_bio->error = ERR_NODEV; 1486 break; 1487 case KILL_RESET: 1488 ata_bio->error = ERR_RESET; 1489 break; 1490 case KILL_REQUEUE: 1491 ata_bio->error = REQUEUE; 1492 break; 1493 default: 1494 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1495 panic("ahci_bio_kill_xfer"); 1496 } 1497 ata_bio->r_error = WDCE_ABRT; 1498 1499 if (deactivate) 1500 ata_deactivate_xfer(chp, xfer); 1501 1502 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1503 } 1504 1505 static int 1506 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1507 { 1508 struct ata_bio *ata_bio = &xfer->c_bio; 1509 int drive = xfer->c_drive; 1510 struct ahci_channel *achp = (struct ahci_channel *)chp; 1511 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1512 1513 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1514 DEBUG_FUNCS); 1515 1516 if (ata_waitdrain_xfer_check(chp, xfer)) 1517 return 0; 1518 1519 if (xfer->c_flags & C_TIMEOU) { 1520 ata_bio->error = TIMEOUT; 1521 } 1522 1523 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1524 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1525 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1526 BUS_DMASYNC_POSTWRITE); 1527 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1528 1529 ata_bio->flags |= ATA_ITSDONE; 1530 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1531 ata_bio->error = ERR_DF; 1532 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1533 ata_bio->error = ERROR; 1534 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1535 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1536 ata_bio->flags |= ATA_CORR; 1537 1538 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1539 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1540 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1541 ata_bio->bcount), DEBUG_XFERS); 1542 /* 1543 * If it was a write, complete data buffer may have been transfered 1544 * before error detection; in this case don't use cmdh_prdbc 1545 * as it won't reflect what was written to media. Assume nothing 1546 * was transfered and leave bcount as-is. 1547 * For queued commands, PRD Byte Count should not be used, and is 1548 * not required to be valid; in that case underflow is always illegal. 1549 */ 1550 if ((xfer->c_flags & C_NCQ) != 0) { 1551 if (ata_bio->error == NOERROR) 1552 ata_bio->bcount = 0; 1553 } else { 1554 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1555 ata_bio->bcount -= 1556 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1557 } 1558 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1559 1560 ata_deactivate_xfer(chp, xfer); 1561 1562 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1563 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1564 atastart(chp); 1565 return 0; 1566 } 1567 1568 static void 1569 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1570 { 1571 int i; 1572 /* stop channel */ 1573 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1574 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1575 /* wait 1s for channel to stop */ 1576 for (i = 0; i <100; i++) { 1577 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1578 == 0) 1579 break; 1580 ata_delay(chp, 10, "ahcistop", flags); 1581 } 1582 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1583 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1584 /* XXX controller reset ? */ 1585 return; 1586 } 1587 1588 if (sc->sc_channel_stop) 1589 sc->sc_channel_stop(sc, chp); 1590 } 1591 1592 static void 1593 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1594 int flags, int clo) 1595 { 1596 int i; 1597 uint32_t p_cmd; 1598 /* clear error */ 1599 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1600 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1601 1602 if (clo) { 1603 /* issue command list override */ 1604 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1605 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1606 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1607 /* wait 1s for AHCI_CAP_CLO to clear */ 1608 for (i = 0; i <100; i++) { 1609 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1610 AHCI_P_CMD_CLO) == 0) 1611 break; 1612 ata_delay(chp, 10, "ahciclo", flags); 1613 } 1614 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1615 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1616 /* XXX controller reset ? */ 1617 return; 1618 } 1619 } 1620 1621 if (sc->sc_channel_start) 1622 sc->sc_channel_start(sc, chp); 1623 1624 /* and start controller */ 1625 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1626 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1627 if (chp->ch_ndrives > PMP_PORT_CTL && 1628 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1629 p_cmd |= AHCI_P_CMD_PMA; 1630 } 1631 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1632 } 1633 1634 /* Recover channel after command failure */ 1635 static void 1636 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1637 { 1638 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1639 int drive = ATACH_NODRIVE; 1640 bool reset = false; 1641 1642 ata_channel_lock_owned(chp); 1643 1644 /* 1645 * Read FBS to get the drive which caused the error, if PM is in use. 1646 * According to AHCI 1.3 spec, this register is available regardless 1647 * if FIS-based switching (FBSS) feature is supported, or disabled. 1648 * If FIS-based switching is not in use, it merely maintains single 1649 * pair of DRQ/BSY state, but it is enough since in that case we 1650 * never issue commands for more than one device at the time anyway. 1651 * XXX untested 1652 */ 1653 if (chp->ch_ndrives > PMP_PORT_CTL) { 1654 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1655 if (fbs & AHCI_P_FBS_SDE) { 1656 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1657 1658 /* 1659 * Tell HBA to reset PM port X (value in DWE) state, 1660 * and resume processing commands for other ports. 1661 */ 1662 fbs |= AHCI_P_FBS_DEC; 1663 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1664 for (int i = 0; i < 1000; i++) { 1665 fbs = AHCI_READ(sc, 1666 AHCI_P_FBS(chp->ch_channel)); 1667 if ((fbs & AHCI_P_FBS_DEC) == 0) 1668 break; 1669 DELAY(1000); 1670 } 1671 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1672 /* follow non-device specific recovery */ 1673 drive = ATACH_NODRIVE; 1674 reset = true; 1675 } 1676 } else { 1677 /* not device specific, reset channel */ 1678 drive = ATACH_NODRIVE; 1679 reset = true; 1680 } 1681 } else 1682 drive = 0; 1683 1684 /* 1685 * If BSY or DRQ bits are set, must execute COMRESET to return 1686 * device to idle state. If drive is idle, it's enough to just 1687 * reset CMD.ST, it's not necessary to do software reset. 1688 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1689 * to unblock device processing if COMRESET was not done. 1690 */ 1691 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1692 ahci_reset_channel(chp, flags); 1693 goto out; 1694 } 1695 1696 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1697 ahci_channel_stop(sc, chp, flags); 1698 ahci_channel_start(sc, chp, flags, 1699 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1700 1701 ata_recovery_resume(chp, drive, tfd, flags); 1702 1703 out: 1704 /* Drive unblocked, back to normal operation */ 1705 return; 1706 } 1707 1708 static int 1709 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1710 size_t count, int op) 1711 { 1712 int error, seg; 1713 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1714 struct ahci_channel *achp = (struct ahci_channel *)chp; 1715 struct ahci_cmd_tbl *cmd_tbl; 1716 struct ahci_cmd_header *cmd_h; 1717 1718 cmd_h = &achp->ahcic_cmdh[slot]; 1719 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1720 1721 if (data == NULL) { 1722 cmd_h->cmdh_prdtl = 0; 1723 goto end; 1724 } 1725 1726 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1727 data, count, NULL, 1728 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1729 if (error) { 1730 printf("%s port %d: failed to load xfer: %d\n", 1731 AHCINAME(sc), chp->ch_channel, error); 1732 return error; 1733 } 1734 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1735 achp->ahcic_datad[slot]->dm_mapsize, 1736 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1737 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1738 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1739 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1740 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1741 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1742 } 1743 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1744 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1745 end: 1746 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1747 return 0; 1748 } 1749 1750 #if NATAPIBUS > 0 1751 static void 1752 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1753 { 1754 struct ata_channel *chp = ata_sc->sc_chan; 1755 struct atac_softc *atac = chp->ch_atac; 1756 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1757 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1758 /* 1759 * Fill in the scsipi_adapter. 1760 */ 1761 adapt->adapt_dev = atac->atac_dev; 1762 adapt->adapt_nchannels = atac->atac_nchannels; 1763 adapt->adapt_request = ahci_atapi_scsipi_request; 1764 adapt->adapt_minphys = ahci_atapi_minphys; 1765 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1766 1767 /* 1768 * Fill in the scsipi_channel. 1769 */ 1770 memset(chan, 0, sizeof(*chan)); 1771 chan->chan_adapter = adapt; 1772 chan->chan_bustype = &ahci_atapi_bustype; 1773 chan->chan_channel = chp->ch_channel; 1774 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1775 chan->chan_openings = 1; 1776 chan->chan_max_periph = 1; 1777 chan->chan_ntargets = 1; 1778 chan->chan_nluns = 1; 1779 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1780 atapiprint); 1781 } 1782 1783 static void 1784 ahci_atapi_minphys(struct buf *bp) 1785 { 1786 if (bp->b_bcount > MAXPHYS) 1787 bp->b_bcount = MAXPHYS; 1788 minphys(bp); 1789 } 1790 1791 /* 1792 * Kill off all pending xfers for a periph. 1793 * 1794 * Must be called at splbio(). 1795 */ 1796 static void 1797 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1798 { 1799 struct atac_softc *atac = 1800 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1801 struct ata_channel *chp = 1802 atac->atac_channels[periph->periph_channel->chan_channel]; 1803 1804 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1805 } 1806 1807 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1808 .c_start = ahci_atapi_start, 1809 .c_poll = ahci_atapi_poll, 1810 .c_abort = ahci_atapi_abort, 1811 .c_intr = ahci_atapi_complete, 1812 .c_kill_xfer = ahci_atapi_kill_xfer, 1813 }; 1814 1815 static void 1816 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1817 scsipi_adapter_req_t req, void *arg) 1818 { 1819 struct scsipi_adapter *adapt = chan->chan_adapter; 1820 struct scsipi_periph *periph; 1821 struct scsipi_xfer *sc_xfer; 1822 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1823 struct atac_softc *atac = &sc->sc_atac; 1824 struct ata_xfer *xfer; 1825 int channel = chan->chan_channel; 1826 int drive, s; 1827 1828 switch (req) { 1829 case ADAPTER_REQ_RUN_XFER: 1830 sc_xfer = arg; 1831 periph = sc_xfer->xs_periph; 1832 drive = periph->periph_target; 1833 if (!device_is_active(atac->atac_dev)) { 1834 sc_xfer->error = XS_DRIVER_STUFFUP; 1835 scsipi_done(sc_xfer); 1836 return; 1837 } 1838 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1839 if (xfer == NULL) { 1840 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1841 scsipi_done(sc_xfer); 1842 return; 1843 } 1844 1845 if (sc_xfer->xs_control & XS_CTL_POLL) 1846 xfer->c_flags |= C_POLL; 1847 xfer->c_drive = drive; 1848 xfer->c_flags |= C_ATAPI; 1849 xfer->c_databuf = sc_xfer->data; 1850 xfer->c_bcount = sc_xfer->datalen; 1851 xfer->ops = &ahci_atapi_xfer_ops; 1852 xfer->c_scsipi = sc_xfer; 1853 xfer->c_atapi.c_dscpoll = 0; 1854 s = splbio(); 1855 ata_exec_xfer(atac->atac_channels[channel], xfer); 1856 #ifdef DIAGNOSTIC 1857 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1858 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1859 panic("ahci_atapi_scsipi_request: polled command " 1860 "not done"); 1861 #endif 1862 splx(s); 1863 return; 1864 default: 1865 /* Not supported, nothing to do. */ 1866 ; 1867 } 1868 } 1869 1870 static int 1871 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1872 { 1873 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1874 struct ahci_channel *achp = (struct ahci_channel *)chp; 1875 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1876 struct ahci_cmd_tbl *cmd_tbl; 1877 struct ahci_cmd_header *cmd_h; 1878 1879 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1880 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1881 1882 ata_channel_lock_owned(chp); 1883 1884 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1885 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1886 cmd_tbl), DEBUG_XFERS); 1887 1888 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1889 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1890 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1891 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1892 1893 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1894 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1895 chp->ch_channel, cmd_h), DEBUG_XFERS); 1896 if (ahci_dma_setup(chp, xfer->c_slot, 1897 sc_xfer->datalen ? sc_xfer->data : NULL, 1898 sc_xfer->datalen, 1899 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1900 BUS_DMA_READ : BUS_DMA_WRITE)) { 1901 sc_xfer->error = XS_DRIVER_STUFFUP; 1902 return ATASTART_ABORT; 1903 } 1904 cmd_h->cmdh_flags = htole16( 1905 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1906 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1907 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1908 cmd_h->cmdh_prdbc = 0; 1909 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1910 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1911 1912 if (xfer->c_flags & C_POLL) { 1913 /* polled command, disable interrupts */ 1914 AHCI_WRITE(sc, AHCI_GHC, 1915 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1916 } 1917 /* start command */ 1918 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1919 1920 if ((xfer->c_flags & C_POLL) == 0) { 1921 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1922 ata_timeout, chp); 1923 return ATASTART_STARTED; 1924 } else 1925 return ATASTART_POLL; 1926 } 1927 1928 static void 1929 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1930 { 1931 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1932 struct ahci_channel *achp = (struct ahci_channel *)chp; 1933 1934 /* 1935 * Polled command. 1936 */ 1937 for (int i = 0; i < ATA_DELAY / 10; i++) { 1938 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1939 break; 1940 ahci_intr_port(achp); 1941 delay(10000); 1942 } 1943 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1944 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1945 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1946 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1947 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1948 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1949 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1950 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1951 DEBUG_XFERS); 1952 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1953 xfer->c_scsipi->error = XS_TIMEOUT; 1954 xfer->ops->c_intr(chp, xfer, 0); 1955 } 1956 /* reenable interrupts */ 1957 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1958 } 1959 1960 static void 1961 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1962 { 1963 ahci_atapi_complete(chp, xfer, 0); 1964 } 1965 1966 static int 1967 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1968 { 1969 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1970 struct ahci_channel *achp = (struct ahci_channel *)chp; 1971 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1972 1973 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1974 DEBUG_FUNCS); 1975 1976 if (ata_waitdrain_xfer_check(chp, xfer)) 1977 return 0; 1978 1979 if (xfer->c_flags & C_TIMEOU) { 1980 sc_xfer->error = XS_TIMEOUT; 1981 } 1982 1983 if (xfer->c_bcount > 0) { 1984 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1985 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1986 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1987 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1988 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1989 } 1990 1991 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1992 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1993 sc_xfer->resid = sc_xfer->datalen; 1994 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1995 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1996 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1997 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 1998 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1999 sc_xfer->resid == sc_xfer->datalen)) { 2000 sc_xfer->error = XS_SHORTSENSE; 2001 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2002 if ((sc_xfer->xs_periph->periph_quirks & 2003 PQUIRK_NOSENSE) == 0) { 2004 /* ask scsipi to send a REQUEST_SENSE */ 2005 sc_xfer->error = XS_BUSY; 2006 sc_xfer->status = SCSI_CHECK; 2007 } 2008 } 2009 2010 ata_deactivate_xfer(chp, xfer); 2011 2012 ata_free_xfer(chp, xfer); 2013 scsipi_done(sc_xfer); 2014 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2015 atastart(chp); 2016 return 0; 2017 } 2018 2019 static void 2020 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2021 { 2022 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2023 bool deactivate = true; 2024 2025 /* remove this command from xfer queue */ 2026 switch (reason) { 2027 case KILL_GONE_INACTIVE: 2028 deactivate = false; 2029 /* FALLTHROUGH */ 2030 case KILL_GONE: 2031 sc_xfer->error = XS_DRIVER_STUFFUP; 2032 break; 2033 case KILL_RESET: 2034 sc_xfer->error = XS_RESET; 2035 break; 2036 case KILL_REQUEUE: 2037 sc_xfer->error = XS_REQUEUE; 2038 break; 2039 default: 2040 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2041 panic("ahci_ata_atapi_kill_xfer"); 2042 } 2043 2044 if (deactivate) 2045 ata_deactivate_xfer(chp, xfer); 2046 2047 ata_free_xfer(chp, xfer); 2048 scsipi_done(sc_xfer); 2049 } 2050 2051 static void 2052 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2053 { 2054 struct scsipi_channel *chan = sc->sc_channel; 2055 struct scsipi_periph *periph; 2056 struct ataparams ids; 2057 struct ataparams *id = &ids; 2058 struct ahci_softc *ahcic = 2059 device_private(chan->chan_adapter->adapt_dev); 2060 struct atac_softc *atac = &ahcic->sc_atac; 2061 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2062 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2063 struct scsipibus_attach_args sa; 2064 char serial_number[21], model[41], firmware_revision[9]; 2065 int s; 2066 2067 /* skip if already attached */ 2068 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2069 return; 2070 2071 /* if no ATAPI device detected at attach time, skip */ 2072 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2073 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2074 "not present\n", target), DEBUG_PROBE); 2075 return; 2076 } 2077 2078 /* Some ATAPI devices need a bit more time after software reset. */ 2079 delay(5000); 2080 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2081 #ifdef ATAPI_DEBUG_PROBE 2082 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2083 AHCINAME(ahcic), target, 2084 id->atap_config & ATAPI_CFG_CMD_MASK, 2085 id->atap_config & ATAPI_CFG_DRQ_MASK); 2086 #endif 2087 periph = scsipi_alloc_periph(M_NOWAIT); 2088 if (periph == NULL) { 2089 aprint_error_dev(sc->sc_dev, 2090 "unable to allocate periph for drive %d\n", 2091 target); 2092 return; 2093 } 2094 periph->periph_dev = NULL; 2095 periph->periph_channel = chan; 2096 periph->periph_switch = &atapi_probe_periphsw; 2097 periph->periph_target = target; 2098 periph->periph_lun = 0; 2099 periph->periph_quirks = PQUIRK_ONLYBIG; 2100 2101 #ifdef SCSIPI_DEBUG 2102 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2103 SCSIPI_DEBUG_TARGET == target) 2104 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2105 #endif 2106 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2107 if (id->atap_config & ATAPI_CFG_REMOV) 2108 periph->periph_flags |= PERIPH_REMOVABLE; 2109 if (periph->periph_type == T_SEQUENTIAL) { 2110 s = splbio(); 2111 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2112 splx(s); 2113 } 2114 2115 sa.sa_periph = periph; 2116 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2117 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2118 T_REMOV : T_FIXED; 2119 strnvisx(model, sizeof(model), id->atap_model, 40, 2120 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2121 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2122 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2123 strnvisx(firmware_revision, sizeof(firmware_revision), 2124 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2125 sa.sa_inqbuf.vendor = model; 2126 sa.sa_inqbuf.product = serial_number; 2127 sa.sa_inqbuf.revision = firmware_revision; 2128 2129 /* 2130 * Determine the operating mode capabilities of the device. 2131 */ 2132 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2133 periph->periph_cap |= PERIPH_CAP_CMD16; 2134 /* XXX This is gross. */ 2135 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2136 2137 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2138 2139 if (drvp->drv_softc) 2140 ata_probe_caps(drvp); 2141 else { 2142 s = splbio(); 2143 drvp->drive_type = ATA_DRIVET_NONE; 2144 splx(s); 2145 } 2146 } else { 2147 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2148 "failed for drive %s:%d:%d\n", 2149 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2150 s = splbio(); 2151 drvp->drive_type = ATA_DRIVET_NONE; 2152 splx(s); 2153 } 2154 } 2155 #endif /* NATAPIBUS */ 2156
Indexes created Fri Sep 26 08:10:20 GMT 2025