ahcisata_core.c revision 1.80.2.1
1 /* $NetBSD: ahcisata_core.c,v 1.80.2.1 2020/01/25 22:38:46 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.80.2.1 2020/01/25 22:38:46 ad Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static int ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 SCSIPI_BUSTYPE_ATAPI, 103 atapi_scsipi_cmd, 104 atapi_interpret_sense, 105 atapi_print_addr, 106 ahci_atapi_kill_pending, 107 NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 SCSIPI_BUSTYPE_ATA, 117 ahci_ata_bio, 118 ahci_reset_drive, 119 ahci_reset_channel, 120 ahci_exec_command, 121 ata_get_params, 122 ahci_ata_addref, 123 ahci_ata_delref, 124 ahci_killpending, 125 ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADNCQ) { 280 aprint_verbose_dev(sc->sc_atac.atac_dev, 281 "ignoring broken NCQ support\n"); 282 sc->sc_ahci_cap &= ~AHCI_CAP_NCQ; 283 } 284 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 285 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 286 ahci_rev = AHCI_READ(sc, AHCI_VS); 287 snprintb(buf, sizeof(buf), "\177\020" 288 /* "f\000\005NP\0" */ 289 "b\005SXS\0" 290 "b\006EMS\0" 291 "b\007CCCS\0" 292 /* "f\010\005NCS\0" */ 293 "b\015PSC\0" 294 "b\016SSC\0" 295 "b\017PMD\0" 296 "b\020FBSS\0" 297 "b\021SPM\0" 298 "b\022SAM\0" 299 "b\023SNZO\0" 300 "f\024\003ISS\0" 301 "=\001Gen1\0" 302 "=\002Gen2\0" 303 "=\003Gen3\0" 304 "b\030SCLO\0" 305 "b\031SAL\0" 306 "b\032SALP\0" 307 "b\033SSS\0" 308 "b\034SMPS\0" 309 "b\035SSNTF\0" 310 "b\036SNCQ\0" 311 "b\037S64A\0" 312 "\0", sc->sc_ahci_cap); 313 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 314 ", %d port%s, %d slot%s, CAP %s\n", 315 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 316 sc->sc_atac.atac_nchannels, 317 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 318 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 319 320 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 321 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 322 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 323 sc->sc_atac.atac_pio_cap = 4; 324 sc->sc_atac.atac_dma_cap = 2; 325 sc->sc_atac.atac_udma_cap = 6; 326 sc->sc_atac.atac_channels = sc->sc_chanarray; 327 sc->sc_atac.atac_probe = ahci_probe_drive; 328 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 329 sc->sc_atac.atac_set_modes = ahci_setup_channel; 330 #if NATAPIBUS > 0 331 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 332 #endif 333 334 dmasize = 335 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 338 if (error) { 339 aprint_error("%s: unable to allocate command header memory" 340 ", error=%d\n", AHCINAME(sc), error); 341 return; 342 } 343 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 344 sc->sc_cmd_hdr_nseg, dmasize, 345 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 346 if (error) { 347 aprint_error("%s: unable to map command header memory" 348 ", error=%d\n", AHCINAME(sc), error); 349 return; 350 } 351 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 352 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 353 if (error) { 354 aprint_error("%s: unable to create command header map" 355 ", error=%d\n", AHCINAME(sc), error); 356 return; 357 } 358 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 359 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 360 if (error) { 361 aprint_error("%s: unable to load command header map" 362 ", error=%d\n", AHCINAME(sc), error); 363 return; 364 } 365 sc->sc_cmd_hdr = cmdhp; 366 367 ahci_enable_intrs(sc); 368 369 if (sc->sc_ahci_ports == 0) { 370 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 371 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 372 DEBUG_PROBE); 373 } 374 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 375 if ((sc->sc_ahci_ports & (1U << i)) == 0) 376 continue; 377 if (port >= sc->sc_atac.atac_nchannels) { 378 aprint_error("%s: more ports than announced\n", 379 AHCINAME(sc)); 380 break; 381 } 382 383 /* Optional intr establish per active port */ 384 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 385 aprint_error("%s: intr establish hook failed\n", 386 AHCINAME(sc)); 387 break; 388 } 389 390 achp = &sc->sc_channels[i]; 391 chp = &achp->ata_channel; 392 sc->sc_chanarray[i] = chp; 393 chp->ch_channel = i; 394 chp->ch_atac = &sc->sc_atac; 395 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 396 if (chp->ch_queue == NULL) { 397 aprint_error("%s port %d: can't allocate memory for " 398 "command queue", AHCINAME(sc), i); 399 break; 400 } 401 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 402 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 403 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 404 BUS_DMA_NOWAIT); 405 if (error) { 406 aprint_error("%s: unable to allocate command table " 407 "memory, error=%d\n", AHCINAME(sc), error); 408 break; 409 } 410 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 411 achp->ahcic_cmd_tbl_nseg, dmasize, 412 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 413 if (error) { 414 aprint_error("%s: unable to map command table memory" 415 ", error=%d\n", AHCINAME(sc), error); 416 break; 417 } 418 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 419 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 420 if (error) { 421 aprint_error("%s: unable to create command table map" 422 ", error=%d\n", AHCINAME(sc), error); 423 break; 424 } 425 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 426 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 427 if (error) { 428 aprint_error("%s: unable to load command table map" 429 ", error=%d\n", AHCINAME(sc), error); 430 break; 431 } 432 achp->ahcic_cmdh = (struct ahci_cmd_header *) 433 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 434 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 435 AHCI_CMDH_SIZE * port; 436 achp->ahcic_rfis = (struct ahci_r_fis *) 437 ((char *)cmdhp + 438 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 439 AHCI_RFIS_SIZE * port); 440 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 441 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 442 AHCI_RFIS_SIZE * port; 443 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 444 "rfis %p (0x%" PRIx64 ")\n", i, 445 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 446 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 447 DEBUG_PROBE); 448 449 for (j = 0; j < sc->sc_ncmds; j++) { 450 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 451 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 452 achp->ahcic_bus_cmd_tbl[j] = 453 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 454 AHCI_CMDTBL_SIZE * j; 455 achp->ahcic_cmdh[j].cmdh_cmdtba = 456 htole64(achp->ahcic_bus_cmd_tbl[j]); 457 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 458 achp->ahcic_cmd_tbl[j], 459 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 460 /* The xfer DMA map */ 461 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 462 AHCI_NPRD, 0x400000 /* 4MB */, 0, 463 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 464 &achp->ahcic_datad[j]); 465 if (error) { 466 aprint_error("%s: couldn't alloc xfer DMA map, " 467 "error=%d\n", AHCINAME(sc), error); 468 goto end; 469 } 470 } 471 ahci_setup_port(sc, i); 472 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 473 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 474 aprint_error("%s: couldn't map port %d " 475 "sata_status regs\n", AHCINAME(sc), i); 476 break; 477 } 478 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 479 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 480 aprint_error("%s: couldn't map port %d " 481 "sata_control regs\n", AHCINAME(sc), i); 482 break; 483 } 484 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 485 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 486 aprint_error("%s: couldn't map port %d " 487 "sata_error regs\n", AHCINAME(sc), i); 488 break; 489 } 490 ata_channel_attach(chp); 491 port++; 492 end: 493 continue; 494 } 495 } 496 497 void 498 ahci_childdetached(struct ahci_softc *sc, device_t child) 499 { 500 struct ahci_channel *achp; 501 struct ata_channel *chp; 502 503 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 504 achp = &sc->sc_channels[i]; 505 chp = &achp->ata_channel; 506 507 if ((sc->sc_ahci_ports & (1U << i)) == 0) 508 continue; 509 510 if (child == chp->atabus) 511 chp->atabus = NULL; 512 } 513 } 514 515 int 516 ahci_detach(struct ahci_softc *sc, int flags) 517 { 518 struct atac_softc *atac; 519 struct ahci_channel *achp; 520 struct ata_channel *chp; 521 struct scsipi_adapter *adapt; 522 int i, j, port; 523 int error; 524 525 atac = &sc->sc_atac; 526 adapt = &atac->atac_atapi_adapter._generic; 527 528 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 529 achp = &sc->sc_channels[i]; 530 chp = &achp->ata_channel; 531 532 if ((sc->sc_ahci_ports & (1U << i)) == 0) 533 continue; 534 if (port >= sc->sc_atac.atac_nchannels) { 535 aprint_error("%s: more ports than announced\n", 536 AHCINAME(sc)); 537 break; 538 } 539 540 if (chp->atabus != NULL) { 541 if ((error = config_detach(chp->atabus, flags)) != 0) 542 return error; 543 544 KASSERT(chp->atabus == NULL); 545 } 546 547 if (chp->ch_flags & ATACH_DETACHED) 548 continue; 549 550 for (j = 0; j < sc->sc_ncmds; j++) 551 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 552 553 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 554 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 555 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 556 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 557 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 558 achp->ahcic_cmd_tbl_nseg); 559 560 ata_channel_detach(chp); 561 port++; 562 } 563 564 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 565 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 566 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 567 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 568 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 569 570 if (adapt->adapt_refcnt != 0) 571 return EBUSY; 572 573 return 0; 574 } 575 576 void 577 ahci_resume(struct ahci_softc *sc) 578 { 579 ahci_reset(sc); 580 ahci_setup_ports(sc); 581 ahci_reprobe_drives(sc); 582 ahci_enable_intrs(sc); 583 } 584 585 int 586 ahci_intr(void *v) 587 { 588 struct ahci_softc *sc = v; 589 uint32_t is; 590 int i, r = 0; 591 592 while ((is = AHCI_READ(sc, AHCI_IS))) { 593 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 594 DEBUG_INTR); 595 r = 1; 596 AHCI_WRITE(sc, AHCI_IS, is); 597 for (i = 0; i < AHCI_MAX_PORTS; i++) 598 if (is & (1U << i)) 599 ahci_intr_port(&sc->sc_channels[i]); 600 } 601 602 return r; 603 } 604 605 int 606 ahci_intr_port(void *v) 607 { 608 struct ahci_channel *achp = v; 609 struct ata_channel *chp = &achp->ata_channel; 610 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 611 uint32_t is, tfd, sact; 612 struct ata_xfer *xfer; 613 int slot = -1; 614 bool recover = false; 615 uint32_t aslots; 616 617 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 618 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 619 620 AHCIDEBUG_PRINT(( 621 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 622 AHCINAME(sc), 623 chp->ch_channel, is, 624 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 625 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 626 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 627 DEBUG_INTR); 628 629 if ((chp->ch_flags & ATACH_NCQ) == 0) { 630 /* Non-NCQ operation */ 631 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 632 } else { 633 /* NCQ operation */ 634 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 635 } 636 637 /* Handle errors */ 638 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 639 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 640 /* Fatal errors */ 641 if (is & AHCI_P_IX_TFES) { 642 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 643 644 if ((chp->ch_flags & ATACH_NCQ) == 0) { 645 /* Slot valid only for Non-NCQ operation */ 646 slot = (AHCI_READ(sc, 647 AHCI_P_CMD(chp->ch_channel)) 648 & AHCI_P_CMD_CCS_MASK) 649 >> AHCI_P_CMD_CCS_SHIFT; 650 } 651 652 AHCIDEBUG_PRINT(( 653 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 654 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 655 DEBUG_INTR); 656 } else { 657 /* mark an error, and set BSY */ 658 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 659 WDCS_ERR | WDCS_BSY; 660 } 661 662 if (is & AHCI_P_IX_IFS) { 663 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 664 AHCINAME(sc), chp->ch_channel, 665 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 666 DEBUG_INTR); 667 } 668 669 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 670 recover = true; 671 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 672 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 673 674 /* D2H Register FIS or Set Device Bits */ 675 if ((tfd & WDCS_ERR) != 0) { 676 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 677 recover = true; 678 679 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 680 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 681 682 } 683 } else { 684 tfd = 0; 685 } 686 687 if (__predict_false(recover)) 688 ata_channel_freeze(chp); 689 690 aslots = ata_queue_active(chp); 691 692 if (slot >= 0) { 693 if ((aslots & __BIT(slot)) != 0 && 694 (sact & __BIT(slot)) == 0) { 695 xfer = ata_queue_hwslot_to_xfer(chp, slot); 696 xfer->ops->c_intr(chp, xfer, tfd); 697 } 698 } else { 699 /* 700 * For NCQ, HBA halts processing when error is notified, 701 * and any further D2H FISes are ignored until the error 702 * condition is cleared. Hence if a command is inactive, 703 * it means it actually already finished successfully. 704 * Note: active slots can change as c_intr() callback 705 * can activate another command(s), so must only process 706 * commands active before we start processing. 707 */ 708 709 for (slot=0; slot < sc->sc_ncmds; slot++) { 710 if ((aslots & __BIT(slot)) != 0 && 711 (sact & __BIT(slot)) == 0) { 712 xfer = ata_queue_hwslot_to_xfer(chp, slot); 713 xfer->ops->c_intr(chp, xfer, tfd); 714 } 715 } 716 } 717 718 if (__predict_false(recover)) { 719 ata_channel_lock(chp); 720 ata_channel_thaw_locked(chp); 721 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 722 ata_channel_unlock(chp); 723 } 724 725 return 1; 726 } 727 728 static void 729 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 730 { 731 struct ata_channel *chp = drvp->chnl_softc; 732 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 733 uint8_t c_slot; 734 735 ata_channel_lock_owned(chp); 736 737 /* get a slot for running the command on */ 738 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 739 panic("%s: %s: failed to get xfer for reset, port %d\n", 740 device_xname(sc->sc_atac.atac_dev), 741 __func__, chp->ch_channel); 742 /* NOTREACHED */ 743 } 744 745 AHCI_WRITE(sc, AHCI_GHC, 746 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 747 ahci_channel_stop(sc, chp, flags); 748 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 749 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 750 751 ata_queue_free_slot(chp, c_slot); 752 } 753 754 /* return error code from ata_bio */ 755 static int 756 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 757 { 758 struct ahci_channel *achp = (struct ahci_channel *)chp; 759 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 760 int i; 761 uint32_t is; 762 763 /* 764 * Base timeout is specified in ms. 765 * If we are allowed to sleep, wait a tick each round. 766 * Otherwise delay for 10ms on each round. 767 */ 768 if (flags & AT_WAIT) 769 timeout = MAX(1, mstohz(timeout)); 770 else 771 timeout = timeout / 10; 772 773 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 774 AHCI_CMDH_SYNC(sc, achp, slot, 775 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 776 /* start command */ 777 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 778 for (i = 0; i < timeout; i++) { 779 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 780 0) 781 return 0; 782 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 783 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 784 AHCI_P_IX_IFS | 785 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 786 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 787 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 788 /* 789 * we got the D2H FIS anyway, 790 * assume sig is valid. 791 * channel is restarted later 792 */ 793 return ERROR; 794 } 795 aprint_debug("%s port %d: error 0x%x sending FIS\n", 796 AHCINAME(sc), chp->ch_channel, is); 797 return ERR_DF; 798 } 799 ata_delay(chp, 10, "ahcifis", flags); 800 } 801 802 aprint_debug("%s port %d: timeout sending FIS\n", 803 AHCINAME(sc), chp->ch_channel); 804 return TIMEOUT; 805 } 806 807 static int 808 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 809 uint32_t *sigp, uint8_t c_slot) 810 { 811 struct ahci_channel *achp = (struct ahci_channel *)chp; 812 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 813 struct ahci_cmd_tbl *cmd_tbl; 814 struct ahci_cmd_header *cmd_h; 815 int i, error = 0; 816 uint32_t sig, cmd; 817 int noclo_retry = 0; 818 819 ata_channel_lock_owned(chp); 820 821 again: 822 /* clear port interrupt register */ 823 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 824 /* clear SErrors and start operations */ 825 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 826 /* 827 * issue a command list override to clear BSY. 828 * This is needed if there's a PMP with no drive 829 * on port 0 830 */ 831 ahci_channel_start(sc, chp, flags, 1); 832 } else { 833 /* Can't handle command still running without CLO */ 834 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 835 if ((cmd & AHCI_P_CMD_CR) != 0) { 836 ahci_channel_stop(sc, chp, flags); 837 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 838 if ((cmd & AHCI_P_CMD_CR) != 0) { 839 aprint_error("%s port %d: DMA engine busy " 840 "for drive %d\n", AHCINAME(sc), 841 chp->ch_channel, drive); 842 error = EBUSY; 843 goto end; 844 } 845 } 846 847 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 848 849 ahci_channel_start(sc, chp, flags, 0); 850 } 851 if (drive > 0) { 852 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 853 } 854 855 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 856 goto skip_reset; 857 858 /* polled command, assume interrupts are disabled */ 859 860 cmd_h = &achp->ahcic_cmdh[c_slot]; 861 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 862 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 863 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 864 cmd_h->cmdh_prdtl = 0; 865 cmd_h->cmdh_prdbc = 0; 866 memset(cmd_tbl->cmdt_cfis, 0, 64); 867 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 868 cmd_tbl->cmdt_cfis[rhd_c] = drive; 869 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 870 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 871 case ERR_DF: 872 case TIMEOUT: 873 /* 874 * without CLO we can't make sure a software reset will 875 * success, as the drive may still have BSY or DRQ set. 876 * in this case, reset the whole channel and retry the 877 * drive reset. The channel reset should clear BSY and DRQ 878 */ 879 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 880 noclo_retry++; 881 ahci_reset_channel(chp, flags); 882 goto again; 883 } 884 aprint_error("%s port %d: setting WDCTL_RST failed " 885 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 886 error = EBUSY; 887 goto end; 888 default: 889 break; 890 } 891 892 /* 893 * SATA specification has toggle period for SRST bit of 5 usec. Some 894 * controllers fail to process the SRST clear operation unless 895 * we wait for at least this period between the set and clear commands. 896 */ 897 ata_delay(chp, 10, "ahcirstw", flags); 898 899 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 900 (drive << AHCI_CMDH_F_PMP_SHIFT)); 901 cmd_h->cmdh_prdbc = 0; 902 memset(cmd_tbl->cmdt_cfis, 0, 64); 903 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 904 cmd_tbl->cmdt_cfis[rhd_c] = drive; 905 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 906 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 907 case ERR_DF: 908 case TIMEOUT: 909 aprint_error("%s port %d: clearing WDCTL_RST failed " 910 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 911 error = EBUSY; 912 goto end; 913 default: 914 break; 915 } 916 917 skip_reset: 918 /* 919 * wait 31s for BSY to clear 920 * This should not be needed, but some controllers clear the 921 * command slot before receiving the D2H FIS ... 922 */ 923 for (i = 0; i < AHCI_RST_WAIT; i++) { 924 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 925 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 926 break; 927 ata_delay(chp, 10, "ahcid2h", flags); 928 } 929 if (i == AHCI_RST_WAIT) { 930 aprint_error("%s: BSY never cleared, TD 0x%x\n", 931 AHCINAME(sc), sig); 932 goto end; 933 } 934 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 935 DEBUG_PROBE); 936 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 937 if (sigp) 938 *sigp = sig; 939 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 940 AHCINAME(sc), chp->ch_channel, sig, 941 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 942 end: 943 ahci_channel_stop(sc, chp, flags); 944 ata_delay(chp, 500, "ahcirst", flags); 945 /* clear port interrupt register */ 946 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 947 ahci_channel_start(sc, chp, flags, 948 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 949 return error; 950 } 951 952 static void 953 ahci_reset_channel(struct ata_channel *chp, int flags) 954 { 955 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 956 struct ahci_channel *achp = (struct ahci_channel *)chp; 957 int i, tfd; 958 959 ata_channel_lock_owned(chp); 960 961 ahci_channel_stop(sc, chp, flags); 962 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 963 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 964 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 965 /* XXX and then ? */ 966 } 967 ata_kill_active(chp, KILL_RESET, flags); 968 ata_delay(chp, 500, "ahcirst", flags); 969 /* clear port interrupt register */ 970 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 971 /* clear SErrors and start operations */ 972 ahci_channel_start(sc, chp, flags, 973 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 974 /* wait 31s for BSY to clear */ 975 for (i = 0; i < AHCI_RST_WAIT; i++) { 976 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 977 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 978 break; 979 ata_delay(chp, 10, "ahcid2h", flags); 980 } 981 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 982 aprint_error("%s: BSY never cleared, TD 0x%x\n", 983 AHCINAME(sc), tfd); 984 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 985 DEBUG_PROBE); 986 /* clear port interrupt register */ 987 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 988 989 return; 990 } 991 992 static int 993 ahci_ata_addref(struct ata_drive_datas *drvp) 994 { 995 return 0; 996 } 997 998 static void 999 ahci_ata_delref(struct ata_drive_datas *drvp) 1000 { 1001 return; 1002 } 1003 1004 static void 1005 ahci_killpending(struct ata_drive_datas *drvp) 1006 { 1007 return; 1008 } 1009 1010 static void 1011 ahci_probe_drive(struct ata_channel *chp) 1012 { 1013 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1014 struct ahci_channel *achp = (struct ahci_channel *)chp; 1015 uint32_t sig; 1016 uint8_t c_slot; 1017 int error; 1018 1019 ata_channel_lock(chp); 1020 1021 /* get a slot for running the command on */ 1022 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1023 aprint_error_dev(sc->sc_atac.atac_dev, 1024 "%s: failed to get xfer port %d\n", 1025 __func__, chp->ch_channel); 1026 ata_channel_unlock(chp); 1027 return; 1028 } 1029 1030 /* bring interface up, accept FISs, power up and spin up device */ 1031 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1032 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1033 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1034 /* reset the PHY and bring online */ 1035 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1036 achp->ahcic_sstatus, AT_WAIT)) { 1037 case SStatus_DET_DEV: 1038 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1039 1040 /* Initial value, used in case the soft reset fails */ 1041 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1042 1043 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1044 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1045 &sig, c_slot); 1046 1047 /* If probe for PMP failed, just fallback to drive 0 */ 1048 if (error) { 1049 aprint_error("%s port %d: drive %d reset " 1050 "failed, disabling PMP\n", 1051 AHCINAME(sc), chp->ch_channel, 1052 PMP_PORT_CTL); 1053 1054 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1055 ahci_reset_channel(chp, AT_WAIT); 1056 } 1057 } else { 1058 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1059 } 1060 sata_interpret_sig(chp, 0, sig); 1061 /* if we have a PMP attached, inform the controller */ 1062 if (chp->ch_ndrives > PMP_PORT_CTL && 1063 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1064 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1065 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1066 AHCI_P_CMD_PMA); 1067 } 1068 /* clear port interrupt register */ 1069 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1070 1071 /* and enable interrupts */ 1072 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1073 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1074 AHCI_P_IX_IFS | 1075 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1076 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1077 /* wait 500ms before actually starting operations */ 1078 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1079 break; 1080 1081 default: 1082 break; 1083 } 1084 1085 ata_queue_free_slot(chp, c_slot); 1086 1087 ata_channel_unlock(chp); 1088 } 1089 1090 static void 1091 ahci_setup_channel(struct ata_channel *chp) 1092 { 1093 return; 1094 } 1095 1096 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1097 .c_start = ahci_cmd_start, 1098 .c_poll = ahci_cmd_poll, 1099 .c_abort = ahci_cmd_abort, 1100 .c_intr = ahci_cmd_complete, 1101 .c_kill_xfer = ahci_cmd_kill_xfer, 1102 }; 1103 1104 static int 1105 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1106 { 1107 struct ata_channel *chp = drvp->chnl_softc; 1108 struct ata_command *ata_c = &xfer->c_ata_c; 1109 int ret; 1110 int s; 1111 1112 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1113 chp->ch_channel, 1114 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1115 DEBUG_XFERS); 1116 if (ata_c->flags & AT_POLL) 1117 xfer->c_flags |= C_POLL; 1118 if (ata_c->flags & AT_WAIT) 1119 xfer->c_flags |= C_WAIT; 1120 xfer->c_drive = drvp->drive; 1121 xfer->c_databuf = ata_c->data; 1122 xfer->c_bcount = ata_c->bcount; 1123 xfer->ops = &ahci_cmd_xfer_ops; 1124 s = splbio(); 1125 ata_exec_xfer(chp, xfer); 1126 #ifdef DIAGNOSTIC 1127 if ((ata_c->flags & AT_POLL) != 0 && 1128 (ata_c->flags & AT_DONE) == 0) 1129 panic("ahci_exec_command: polled command not done"); 1130 #endif 1131 if (ata_c->flags & AT_DONE) { 1132 ret = ATACMD_COMPLETE; 1133 } else { 1134 if (ata_c->flags & AT_WAIT) { 1135 ata_wait_cmd(chp, xfer); 1136 ret = ATACMD_COMPLETE; 1137 } else { 1138 ret = ATACMD_QUEUED; 1139 } 1140 } 1141 splx(s); 1142 return ret; 1143 } 1144 1145 static int 1146 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1147 { 1148 struct ahci_softc *sc = AHCI_CH2SC(chp); 1149 struct ahci_channel *achp = (struct ahci_channel *)chp; 1150 struct ata_command *ata_c = &xfer->c_ata_c; 1151 int slot = xfer->c_slot; 1152 struct ahci_cmd_tbl *cmd_tbl; 1153 struct ahci_cmd_header *cmd_h; 1154 1155 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1156 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1157 ata_c->timeout, slot), 1158 DEBUG_XFERS); 1159 1160 ata_channel_lock_owned(chp); 1161 1162 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1163 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1164 cmd_tbl), DEBUG_XFERS); 1165 1166 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1167 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1168 1169 cmd_h = &achp->ahcic_cmdh[slot]; 1170 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1171 chp->ch_channel, cmd_h), DEBUG_XFERS); 1172 if (ahci_dma_setup(chp, slot, 1173 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1174 ata_c->data : NULL, 1175 ata_c->bcount, 1176 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1177 ata_c->flags |= AT_DF; 1178 return ATASTART_ABORT; 1179 } 1180 cmd_h->cmdh_flags = htole16( 1181 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1182 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1183 cmd_h->cmdh_prdbc = 0; 1184 AHCI_CMDH_SYNC(sc, achp, slot, 1185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1186 1187 if (ata_c->flags & AT_POLL) { 1188 /* polled command, disable interrupts */ 1189 AHCI_WRITE(sc, AHCI_GHC, 1190 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1191 } 1192 /* start command */ 1193 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1194 1195 if ((ata_c->flags & AT_POLL) == 0) { 1196 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1197 ata_timeout, chp); 1198 return ATASTART_STARTED; 1199 } else 1200 return ATASTART_POLL; 1201 } 1202 1203 static void 1204 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1205 { 1206 struct ahci_softc *sc = AHCI_CH2SC(chp); 1207 struct ahci_channel *achp = (struct ahci_channel *)chp; 1208 1209 ata_channel_lock(chp); 1210 1211 /* 1212 * Polled command. 1213 */ 1214 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1215 if (xfer->c_ata_c.flags & AT_DONE) 1216 break; 1217 ata_channel_unlock(chp); 1218 ahci_intr_port(achp); 1219 ata_channel_lock(chp); 1220 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1221 } 1222 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1223 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1224 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1225 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1226 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1227 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1228 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1229 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1230 DEBUG_XFERS); 1231 1232 ata_channel_unlock(chp); 1233 1234 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1235 xfer->c_ata_c.flags |= AT_TIMEOU; 1236 xfer->ops->c_intr(chp, xfer, 0); 1237 } 1238 /* reenable interrupts */ 1239 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1240 } 1241 1242 static void 1243 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1244 { 1245 ahci_cmd_complete(chp, xfer, 0); 1246 } 1247 1248 static void 1249 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1250 { 1251 struct ata_command *ata_c = &xfer->c_ata_c; 1252 bool deactivate = true; 1253 1254 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1255 DEBUG_FUNCS); 1256 1257 switch (reason) { 1258 case KILL_GONE_INACTIVE: 1259 deactivate = false; 1260 /* FALLTHROUGH */ 1261 case KILL_GONE: 1262 ata_c->flags |= AT_GONE; 1263 break; 1264 case KILL_RESET: 1265 ata_c->flags |= AT_RESET; 1266 break; 1267 case KILL_REQUEUE: 1268 panic("%s: not supposed to be requeued\n", __func__); 1269 break; 1270 default: 1271 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1272 panic("ahci_cmd_kill_xfer"); 1273 } 1274 1275 ahci_cmd_done_end(chp, xfer); 1276 1277 if (deactivate) 1278 ata_deactivate_xfer(chp, xfer); 1279 } 1280 1281 static int 1282 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1283 { 1284 struct ata_command *ata_c = &xfer->c_ata_c; 1285 struct ahci_channel *achp = (struct ahci_channel *)chp; 1286 struct ahci_softc *sc = AHCI_CH2SC(chp); 1287 1288 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1289 chp->ch_channel, 1290 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1291 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1292 DEBUG_FUNCS); 1293 1294 if (ata_waitdrain_xfer_check(chp, xfer)) 1295 return 0; 1296 1297 if (xfer->c_flags & C_TIMEOU) { 1298 ata_c->flags |= AT_TIMEOU; 1299 } 1300 1301 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1302 ata_c->flags |= AT_TIMEOU; 1303 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1304 ata_c->r_error = AHCI_TFD_ERR(tfd); 1305 ata_c->flags |= AT_ERROR; 1306 } 1307 1308 if (ata_c->flags & AT_READREG) { 1309 AHCI_RFIS_SYNC(sc, achp, BUS_DMASYNC_POSTREAD); 1310 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1311 } 1312 1313 ahci_cmd_done(chp, xfer); 1314 1315 ata_deactivate_xfer(chp, xfer); 1316 1317 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1318 atastart(chp); 1319 1320 return 0; 1321 } 1322 1323 static void 1324 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1325 { 1326 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1327 struct ahci_channel *achp = (struct ahci_channel *)chp; 1328 struct ata_command *ata_c = &xfer->c_ata_c; 1329 uint16_t *idwordbuf; 1330 int i; 1331 1332 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1333 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1334 1335 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1336 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1337 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1338 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1339 BUS_DMASYNC_POSTWRITE); 1340 bus_dmamap_unload(sc->sc_dmat, map); 1341 } 1342 1343 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1344 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1345 1346 /* ata(4) expects IDENTIFY data to be in host endianess */ 1347 if (ata_c->r_command == WDCC_IDENTIFY || 1348 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1349 idwordbuf = xfer->c_databuf; 1350 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1351 idwordbuf[i] = le16toh(idwordbuf[i]); 1352 } 1353 } 1354 1355 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1356 ata_c->flags |= AT_XFDONE; 1357 1358 ahci_cmd_done_end(chp, xfer); 1359 } 1360 1361 static void 1362 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1363 { 1364 struct ata_command *ata_c = &xfer->c_ata_c; 1365 1366 ata_c->flags |= AT_DONE; 1367 } 1368 1369 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1370 .c_start = ahci_bio_start, 1371 .c_poll = ahci_bio_poll, 1372 .c_abort = ahci_bio_abort, 1373 .c_intr = ahci_bio_complete, 1374 .c_kill_xfer = ahci_bio_kill_xfer, 1375 }; 1376 1377 static int 1378 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1379 { 1380 struct ata_channel *chp = drvp->chnl_softc; 1381 struct ata_bio *ata_bio = &xfer->c_bio; 1382 1383 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1384 chp->ch_channel, 1385 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1386 DEBUG_XFERS); 1387 if (ata_bio->flags & ATA_POLL) 1388 xfer->c_flags |= C_POLL; 1389 xfer->c_drive = drvp->drive; 1390 xfer->c_databuf = ata_bio->databuf; 1391 xfer->c_bcount = ata_bio->bcount; 1392 xfer->ops = &ahci_bio_xfer_ops; 1393 ata_exec_xfer(chp, xfer); 1394 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1395 } 1396 1397 static int 1398 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1399 { 1400 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1401 struct ahci_channel *achp = (struct ahci_channel *)chp; 1402 struct ata_bio *ata_bio = &xfer->c_bio; 1403 struct ahci_cmd_tbl *cmd_tbl; 1404 struct ahci_cmd_header *cmd_h; 1405 1406 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1407 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1408 1409 ata_channel_lock_owned(chp); 1410 1411 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1412 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1413 cmd_tbl), DEBUG_XFERS); 1414 1415 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1416 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1417 1418 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1419 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1420 chp->ch_channel, cmd_h), DEBUG_XFERS); 1421 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1422 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1423 ata_bio->error = ERR_DMA; 1424 ata_bio->r_error = 0; 1425 return ATASTART_ABORT; 1426 } 1427 cmd_h->cmdh_flags = htole16( 1428 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1429 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1430 cmd_h->cmdh_prdbc = 0; 1431 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1432 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1433 1434 if (xfer->c_flags & C_POLL) { 1435 /* polled command, disable interrupts */ 1436 AHCI_WRITE(sc, AHCI_GHC, 1437 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1438 } 1439 if (xfer->c_flags & C_NCQ) 1440 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1441 /* start command */ 1442 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1443 1444 if ((xfer->c_flags & C_POLL) == 0) { 1445 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1446 ata_timeout, chp); 1447 return ATASTART_STARTED; 1448 } else 1449 return ATASTART_POLL; 1450 } 1451 1452 static void 1453 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1454 { 1455 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1456 struct ahci_channel *achp = (struct ahci_channel *)chp; 1457 1458 /* 1459 * Polled command. 1460 */ 1461 for (int i = 0; i < ATA_DELAY * 10; i++) { 1462 if (xfer->c_bio.flags & ATA_ITSDONE) 1463 break; 1464 ahci_intr_port(achp); 1465 delay(100); 1466 } 1467 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1468 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1469 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1470 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1471 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1472 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1473 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1474 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1475 DEBUG_XFERS); 1476 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1477 xfer->c_bio.error = TIMEOUT; 1478 xfer->ops->c_intr(chp, xfer, 0); 1479 } 1480 /* reenable interrupts */ 1481 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1482 } 1483 1484 static void 1485 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1486 { 1487 ahci_bio_complete(chp, xfer, 0); 1488 } 1489 1490 static void 1491 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1492 { 1493 int drive = xfer->c_drive; 1494 struct ata_bio *ata_bio = &xfer->c_bio; 1495 bool deactivate = true; 1496 1497 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1498 DEBUG_FUNCS); 1499 1500 ata_bio->flags |= ATA_ITSDONE; 1501 switch (reason) { 1502 case KILL_GONE_INACTIVE: 1503 deactivate = false; 1504 /* FALLTHROUGH */ 1505 case KILL_GONE: 1506 ata_bio->error = ERR_NODEV; 1507 break; 1508 case KILL_RESET: 1509 ata_bio->error = ERR_RESET; 1510 break; 1511 case KILL_REQUEUE: 1512 ata_bio->error = REQUEUE; 1513 break; 1514 default: 1515 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1516 panic("ahci_bio_kill_xfer"); 1517 } 1518 ata_bio->r_error = WDCE_ABRT; 1519 1520 if (deactivate) 1521 ata_deactivate_xfer(chp, xfer); 1522 1523 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1524 } 1525 1526 static int 1527 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1528 { 1529 struct ata_bio *ata_bio = &xfer->c_bio; 1530 int drive = xfer->c_drive; 1531 struct ahci_channel *achp = (struct ahci_channel *)chp; 1532 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1533 1534 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1535 DEBUG_FUNCS); 1536 1537 if (ata_waitdrain_xfer_check(chp, xfer)) 1538 return 0; 1539 1540 if (xfer->c_flags & C_TIMEOU) { 1541 ata_bio->error = TIMEOUT; 1542 } 1543 1544 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1545 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1546 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1547 BUS_DMASYNC_POSTWRITE); 1548 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1549 1550 ata_bio->flags |= ATA_ITSDONE; 1551 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1552 ata_bio->error = ERR_DF; 1553 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1554 ata_bio->error = ERROR; 1555 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1556 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1557 ata_bio->flags |= ATA_CORR; 1558 1559 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1560 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1561 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1562 ata_bio->bcount), DEBUG_XFERS); 1563 /* 1564 * If it was a write, complete data buffer may have been transferred 1565 * before error detection; in this case don't use cmdh_prdbc 1566 * as it won't reflect what was written to media. Assume nothing 1567 * was transferred and leave bcount as-is. 1568 * For queued commands, PRD Byte Count should not be used, and is 1569 * not required to be valid; in that case underflow is always illegal. 1570 */ 1571 if ((xfer->c_flags & C_NCQ) != 0) { 1572 if (ata_bio->error == NOERROR) 1573 ata_bio->bcount = 0; 1574 } else { 1575 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1576 ata_bio->bcount -= 1577 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1578 } 1579 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1580 1581 ata_deactivate_xfer(chp, xfer); 1582 1583 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1584 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1585 atastart(chp); 1586 return 0; 1587 } 1588 1589 static void 1590 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1591 { 1592 int i; 1593 /* stop channel */ 1594 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1595 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1596 /* wait 1s for channel to stop */ 1597 for (i = 0; i <100; i++) { 1598 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1599 == 0) 1600 break; 1601 ata_delay(chp, 10, "ahcistop", flags); 1602 } 1603 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1604 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1605 /* XXX controller reset ? */ 1606 return; 1607 } 1608 1609 if (sc->sc_channel_stop) 1610 sc->sc_channel_stop(sc, chp); 1611 } 1612 1613 static void 1614 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1615 int flags, int clo) 1616 { 1617 int i; 1618 uint32_t p_cmd; 1619 /* clear error */ 1620 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1621 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1622 1623 if (clo) { 1624 /* issue command list override */ 1625 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1626 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1627 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1628 /* wait 1s for AHCI_CAP_CLO to clear */ 1629 for (i = 0; i <100; i++) { 1630 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1631 AHCI_P_CMD_CLO) == 0) 1632 break; 1633 ata_delay(chp, 10, "ahciclo", flags); 1634 } 1635 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1636 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1637 /* XXX controller reset ? */ 1638 return; 1639 } 1640 } 1641 1642 if (sc->sc_channel_start) 1643 sc->sc_channel_start(sc, chp); 1644 1645 /* and start controller */ 1646 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1647 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1648 if (chp->ch_ndrives > PMP_PORT_CTL && 1649 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1650 p_cmd |= AHCI_P_CMD_PMA; 1651 } 1652 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1653 } 1654 1655 /* Recover channel after command failure */ 1656 static void 1657 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1658 { 1659 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1660 int drive = ATACH_NODRIVE; 1661 bool reset = false; 1662 1663 ata_channel_lock_owned(chp); 1664 1665 /* 1666 * Read FBS to get the drive which caused the error, if PM is in use. 1667 * According to AHCI 1.3 spec, this register is available regardless 1668 * if FIS-based switching (FBSS) feature is supported, or disabled. 1669 * If FIS-based switching is not in use, it merely maintains single 1670 * pair of DRQ/BSY state, but it is enough since in that case we 1671 * never issue commands for more than one device at the time anyway. 1672 * XXX untested 1673 */ 1674 if (chp->ch_ndrives > PMP_PORT_CTL) { 1675 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1676 if (fbs & AHCI_P_FBS_SDE) { 1677 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1678 1679 /* 1680 * Tell HBA to reset PM port X (value in DWE) state, 1681 * and resume processing commands for other ports. 1682 */ 1683 fbs |= AHCI_P_FBS_DEC; 1684 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1685 for (int i = 0; i < 1000; i++) { 1686 fbs = AHCI_READ(sc, 1687 AHCI_P_FBS(chp->ch_channel)); 1688 if ((fbs & AHCI_P_FBS_DEC) == 0) 1689 break; 1690 DELAY(1000); 1691 } 1692 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1693 /* follow non-device specific recovery */ 1694 drive = ATACH_NODRIVE; 1695 reset = true; 1696 } 1697 } else { 1698 /* not device specific, reset channel */ 1699 drive = ATACH_NODRIVE; 1700 reset = true; 1701 } 1702 } else 1703 drive = 0; 1704 1705 /* 1706 * If BSY or DRQ bits are set, must execute COMRESET to return 1707 * device to idle state. If drive is idle, it's enough to just 1708 * reset CMD.ST, it's not necessary to do software reset. 1709 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1710 * to unblock device processing if COMRESET was not done. 1711 */ 1712 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1713 ahci_reset_channel(chp, flags); 1714 goto out; 1715 } 1716 1717 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1718 ahci_channel_stop(sc, chp, flags); 1719 ahci_channel_start(sc, chp, flags, 1720 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1721 1722 ata_recovery_resume(chp, drive, tfd, flags); 1723 1724 out: 1725 /* Drive unblocked, back to normal operation */ 1726 return; 1727 } 1728 1729 static int 1730 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1731 size_t count, int op) 1732 { 1733 int error, seg; 1734 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1735 struct ahci_channel *achp = (struct ahci_channel *)chp; 1736 struct ahci_cmd_tbl *cmd_tbl; 1737 struct ahci_cmd_header *cmd_h; 1738 1739 cmd_h = &achp->ahcic_cmdh[slot]; 1740 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1741 1742 if (data == NULL) { 1743 cmd_h->cmdh_prdtl = 0; 1744 goto end; 1745 } 1746 1747 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1748 data, count, NULL, 1749 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1750 if (error) { 1751 printf("%s port %d: failed to load xfer: %d\n", 1752 AHCINAME(sc), chp->ch_channel, error); 1753 return error; 1754 } 1755 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1756 achp->ahcic_datad[slot]->dm_mapsize, 1757 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1758 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1759 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1760 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1761 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1762 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1763 } 1764 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1765 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1766 end: 1767 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1768 return 0; 1769 } 1770 1771 #if NATAPIBUS > 0 1772 static void 1773 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1774 { 1775 struct ata_channel *chp = ata_sc->sc_chan; 1776 struct atac_softc *atac = chp->ch_atac; 1777 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1778 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1779 /* 1780 * Fill in the scsipi_adapter. 1781 */ 1782 adapt->adapt_dev = atac->atac_dev; 1783 adapt->adapt_nchannels = atac->atac_nchannels; 1784 adapt->adapt_request = ahci_atapi_scsipi_request; 1785 adapt->adapt_minphys = ahci_atapi_minphys; 1786 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1787 1788 /* 1789 * Fill in the scsipi_channel. 1790 */ 1791 memset(chan, 0, sizeof(*chan)); 1792 chan->chan_adapter = adapt; 1793 chan->chan_bustype = &ahci_atapi_bustype; 1794 chan->chan_channel = chp->ch_channel; 1795 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1796 chan->chan_openings = 1; 1797 chan->chan_max_periph = 1; 1798 chan->chan_ntargets = 1; 1799 chan->chan_nluns = 1; 1800 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1801 atapiprint); 1802 } 1803 1804 static void 1805 ahci_atapi_minphys(struct buf *bp) 1806 { 1807 if (bp->b_bcount > MAXPHYS) 1808 bp->b_bcount = MAXPHYS; 1809 minphys(bp); 1810 } 1811 1812 /* 1813 * Kill off all pending xfers for a periph. 1814 * 1815 * Must be called at splbio(). 1816 */ 1817 static void 1818 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1819 { 1820 struct atac_softc *atac = 1821 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1822 struct ata_channel *chp = 1823 atac->atac_channels[periph->periph_channel->chan_channel]; 1824 1825 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1826 } 1827 1828 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1829 .c_start = ahci_atapi_start, 1830 .c_poll = ahci_atapi_poll, 1831 .c_abort = ahci_atapi_abort, 1832 .c_intr = ahci_atapi_complete, 1833 .c_kill_xfer = ahci_atapi_kill_xfer, 1834 }; 1835 1836 static void 1837 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1838 scsipi_adapter_req_t req, void *arg) 1839 { 1840 struct scsipi_adapter *adapt = chan->chan_adapter; 1841 struct scsipi_periph *periph; 1842 struct scsipi_xfer *sc_xfer; 1843 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1844 struct atac_softc *atac = &sc->sc_atac; 1845 struct ata_xfer *xfer; 1846 int channel = chan->chan_channel; 1847 int drive, s; 1848 1849 switch (req) { 1850 case ADAPTER_REQ_RUN_XFER: 1851 sc_xfer = arg; 1852 periph = sc_xfer->xs_periph; 1853 drive = periph->periph_target; 1854 if (!device_is_active(atac->atac_dev)) { 1855 sc_xfer->error = XS_DRIVER_STUFFUP; 1856 scsipi_done(sc_xfer); 1857 return; 1858 } 1859 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1860 if (xfer == NULL) { 1861 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1862 scsipi_done(sc_xfer); 1863 return; 1864 } 1865 1866 if (sc_xfer->xs_control & XS_CTL_POLL) 1867 xfer->c_flags |= C_POLL; 1868 xfer->c_drive = drive; 1869 xfer->c_flags |= C_ATAPI; 1870 xfer->c_databuf = sc_xfer->data; 1871 xfer->c_bcount = sc_xfer->datalen; 1872 xfer->ops = &ahci_atapi_xfer_ops; 1873 xfer->c_scsipi = sc_xfer; 1874 xfer->c_atapi.c_dscpoll = 0; 1875 s = splbio(); 1876 ata_exec_xfer(atac->atac_channels[channel], xfer); 1877 #ifdef DIAGNOSTIC 1878 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1879 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1880 panic("ahci_atapi_scsipi_request: polled command " 1881 "not done"); 1882 #endif 1883 splx(s); 1884 return; 1885 default: 1886 /* Not supported, nothing to do. */ 1887 ; 1888 } 1889 } 1890 1891 static int 1892 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1893 { 1894 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1895 struct ahci_channel *achp = (struct ahci_channel *)chp; 1896 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1897 struct ahci_cmd_tbl *cmd_tbl; 1898 struct ahci_cmd_header *cmd_h; 1899 1900 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1901 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1902 1903 ata_channel_lock_owned(chp); 1904 1905 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1906 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1907 cmd_tbl), DEBUG_XFERS); 1908 1909 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1910 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1911 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1912 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1913 1914 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1915 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1916 chp->ch_channel, cmd_h), DEBUG_XFERS); 1917 if (ahci_dma_setup(chp, xfer->c_slot, 1918 sc_xfer->datalen ? sc_xfer->data : NULL, 1919 sc_xfer->datalen, 1920 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1921 BUS_DMA_READ : BUS_DMA_WRITE)) { 1922 sc_xfer->error = XS_DRIVER_STUFFUP; 1923 return ATASTART_ABORT; 1924 } 1925 cmd_h->cmdh_flags = htole16( 1926 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1927 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1928 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1929 cmd_h->cmdh_prdbc = 0; 1930 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1931 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1932 1933 if (xfer->c_flags & C_POLL) { 1934 /* polled command, disable interrupts */ 1935 AHCI_WRITE(sc, AHCI_GHC, 1936 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1937 } 1938 /* start command */ 1939 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1940 1941 if ((xfer->c_flags & C_POLL) == 0) { 1942 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1943 ata_timeout, chp); 1944 return ATASTART_STARTED; 1945 } else 1946 return ATASTART_POLL; 1947 } 1948 1949 static void 1950 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1951 { 1952 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1953 struct ahci_channel *achp = (struct ahci_channel *)chp; 1954 1955 /* 1956 * Polled command. 1957 */ 1958 for (int i = 0; i < ATA_DELAY / 10; i++) { 1959 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1960 break; 1961 ahci_intr_port(achp); 1962 delay(10000); 1963 } 1964 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1965 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1966 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1967 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1968 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1969 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1970 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1971 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1972 DEBUG_XFERS); 1973 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1974 xfer->c_scsipi->error = XS_TIMEOUT; 1975 xfer->ops->c_intr(chp, xfer, 0); 1976 } 1977 /* reenable interrupts */ 1978 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1979 } 1980 1981 static void 1982 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1983 { 1984 ahci_atapi_complete(chp, xfer, 0); 1985 } 1986 1987 static int 1988 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1989 { 1990 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1991 struct ahci_channel *achp = (struct ahci_channel *)chp; 1992 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1993 1994 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1995 DEBUG_FUNCS); 1996 1997 if (ata_waitdrain_xfer_check(chp, xfer)) 1998 return 0; 1999 2000 if (xfer->c_flags & C_TIMEOU) { 2001 sc_xfer->error = XS_TIMEOUT; 2002 } 2003 2004 if (xfer->c_bcount > 0) { 2005 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2006 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2007 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2008 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2009 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2010 } 2011 2012 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2013 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2014 sc_xfer->resid = sc_xfer->datalen; 2015 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2016 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2017 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2018 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2019 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2020 sc_xfer->resid == sc_xfer->datalen)) { 2021 sc_xfer->error = XS_SHORTSENSE; 2022 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2023 if ((sc_xfer->xs_periph->periph_quirks & 2024 PQUIRK_NOSENSE) == 0) { 2025 /* ask scsipi to send a REQUEST_SENSE */ 2026 sc_xfer->error = XS_BUSY; 2027 sc_xfer->status = SCSI_CHECK; 2028 } 2029 } 2030 2031 ata_deactivate_xfer(chp, xfer); 2032 2033 ata_free_xfer(chp, xfer); 2034 scsipi_done(sc_xfer); 2035 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2036 atastart(chp); 2037 return 0; 2038 } 2039 2040 static void 2041 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2042 { 2043 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2044 bool deactivate = true; 2045 2046 /* remove this command from xfer queue */ 2047 switch (reason) { 2048 case KILL_GONE_INACTIVE: 2049 deactivate = false; 2050 /* FALLTHROUGH */ 2051 case KILL_GONE: 2052 sc_xfer->error = XS_DRIVER_STUFFUP; 2053 break; 2054 case KILL_RESET: 2055 sc_xfer->error = XS_RESET; 2056 break; 2057 case KILL_REQUEUE: 2058 sc_xfer->error = XS_REQUEUE; 2059 break; 2060 default: 2061 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2062 panic("ahci_ata_atapi_kill_xfer"); 2063 } 2064 2065 if (deactivate) 2066 ata_deactivate_xfer(chp, xfer); 2067 2068 ata_free_xfer(chp, xfer); 2069 scsipi_done(sc_xfer); 2070 } 2071 2072 static void 2073 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2074 { 2075 struct scsipi_channel *chan = sc->sc_channel; 2076 struct scsipi_periph *periph; 2077 struct ataparams ids; 2078 struct ataparams *id = &ids; 2079 struct ahci_softc *ahcic = 2080 device_private(chan->chan_adapter->adapt_dev); 2081 struct atac_softc *atac = &ahcic->sc_atac; 2082 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2083 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2084 struct scsipibus_attach_args sa; 2085 char serial_number[21], model[41], firmware_revision[9]; 2086 int s; 2087 2088 /* skip if already attached */ 2089 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2090 return; 2091 2092 /* if no ATAPI device detected at attach time, skip */ 2093 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2094 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2095 "not present\n", target), DEBUG_PROBE); 2096 return; 2097 } 2098 2099 /* Some ATAPI devices need a bit more time after software reset. */ 2100 delay(5000); 2101 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2102 #ifdef ATAPI_DEBUG_PROBE 2103 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2104 AHCINAME(ahcic), target, 2105 id->atap_config & ATAPI_CFG_CMD_MASK, 2106 id->atap_config & ATAPI_CFG_DRQ_MASK); 2107 #endif 2108 periph = scsipi_alloc_periph(M_NOWAIT); 2109 if (periph == NULL) { 2110 aprint_error_dev(sc->sc_dev, 2111 "unable to allocate periph for drive %d\n", 2112 target); 2113 return; 2114 } 2115 periph->periph_dev = NULL; 2116 periph->periph_channel = chan; 2117 periph->periph_switch = &atapi_probe_periphsw; 2118 periph->periph_target = target; 2119 periph->periph_lun = 0; 2120 periph->periph_quirks = PQUIRK_ONLYBIG; 2121 2122 #ifdef SCSIPI_DEBUG 2123 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2124 SCSIPI_DEBUG_TARGET == target) 2125 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2126 #endif 2127 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2128 if (id->atap_config & ATAPI_CFG_REMOV) 2129 periph->periph_flags |= PERIPH_REMOVABLE; 2130 if (periph->periph_type == T_SEQUENTIAL) { 2131 s = splbio(); 2132 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2133 splx(s); 2134 } 2135 2136 sa.sa_periph = periph; 2137 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2138 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2139 T_REMOV : T_FIXED; 2140 strnvisx(model, sizeof(model), id->atap_model, 40, 2141 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2142 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2143 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2144 strnvisx(firmware_revision, sizeof(firmware_revision), 2145 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2146 sa.sa_inqbuf.vendor = model; 2147 sa.sa_inqbuf.product = serial_number; 2148 sa.sa_inqbuf.revision = firmware_revision; 2149 2150 /* 2151 * Determine the operating mode capabilities of the device. 2152 */ 2153 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2154 periph->periph_cap |= PERIPH_CAP_CMD16; 2155 /* XXX This is gross. */ 2156 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2157 2158 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2159 2160 if (drvp->drv_softc) 2161 ata_probe_caps(drvp); 2162 else { 2163 s = splbio(); 2164 drvp->drive_type = ATA_DRIVET_NONE; 2165 splx(s); 2166 } 2167 } else { 2168 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2169 "failed for drive %s:%d:%d\n", 2170 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2171 s = splbio(); 2172 drvp->drive_type = ATA_DRIVET_NONE; 2173 splx(s); 2174 } 2175 } 2176 #endif /* NATAPIBUS */ 2177
Indexes created Fri Oct 17 00:09:41 GMT 2025