ahcisata_core.c revision 1.87
1 /* $NetBSD: ahcisata_core.c,v 1.87 2020/12/25 08:57:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.87 2020/12/25 08:57:38 skrll Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static void ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static void ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 103 .bustype_cmd = atapi_scsipi_cmd, 104 .bustype_interpret_sense = atapi_interpret_sense, 105 .bustype_printaddr = atapi_print_addr, 106 .bustype_kill_pending = ahci_atapi_kill_pending, 107 .bustype_async_event_xfer_mode = NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 .bustype_type = SCSIPI_BUSTYPE_ATA, 117 .ata_bio = ahci_ata_bio, 118 .ata_reset_drive = ahci_reset_drive, 119 .ata_reset_channel = ahci_reset_channel, 120 .ata_exec_command = ahci_exec_command, 121 .ata_get_params = ata_get_params, 122 .ata_addref = ahci_ata_addref, 123 .ata_delref = ahci_ata_delref, 124 .ata_killpending = ahci_killpending, 125 .ata_recovery = ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADNCQ) { 280 aprint_verbose_dev(sc->sc_atac.atac_dev, 281 "ignoring broken NCQ support\n"); 282 sc->sc_ahci_cap &= ~AHCI_CAP_NCQ; 283 } 284 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 285 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 286 ahci_rev = AHCI_READ(sc, AHCI_VS); 287 snprintb(buf, sizeof(buf), "\177\020" 288 /* "f\000\005NP\0" */ 289 "b\005SXS\0" 290 "b\006EMS\0" 291 "b\007CCCS\0" 292 /* "f\010\005NCS\0" */ 293 "b\015PSC\0" 294 "b\016SSC\0" 295 "b\017PMD\0" 296 "b\020FBSS\0" 297 "b\021SPM\0" 298 "b\022SAM\0" 299 "b\023SNZO\0" 300 "f\024\003ISS\0" 301 "=\001Gen1\0" 302 "=\002Gen2\0" 303 "=\003Gen3\0" 304 "b\030SCLO\0" 305 "b\031SAL\0" 306 "b\032SALP\0" 307 "b\033SSS\0" 308 "b\034SMPS\0" 309 "b\035SSNTF\0" 310 "b\036SNCQ\0" 311 "b\037S64A\0" 312 "\0", sc->sc_ahci_cap); 313 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 314 ", %d port%s, %d slot%s, CAP %s\n", 315 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 316 sc->sc_atac.atac_nchannels, 317 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 318 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 319 320 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 321 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 322 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 323 sc->sc_atac.atac_pio_cap = 4; 324 sc->sc_atac.atac_dma_cap = 2; 325 sc->sc_atac.atac_udma_cap = 6; 326 sc->sc_atac.atac_channels = sc->sc_chanarray; 327 sc->sc_atac.atac_probe = ahci_probe_drive; 328 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 329 sc->sc_atac.atac_set_modes = ahci_setup_channel; 330 #if NATAPIBUS > 0 331 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 332 #endif 333 334 dmasize = 335 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 338 if (error) { 339 aprint_error("%s: unable to allocate command header memory" 340 ", error=%d\n", AHCINAME(sc), error); 341 return; 342 } 343 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 344 sc->sc_cmd_hdr_nseg, dmasize, 345 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 346 if (error) { 347 aprint_error("%s: unable to map command header memory" 348 ", error=%d\n", AHCINAME(sc), error); 349 return; 350 } 351 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 352 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 353 if (error) { 354 aprint_error("%s: unable to create command header map" 355 ", error=%d\n", AHCINAME(sc), error); 356 return; 357 } 358 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 359 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 360 if (error) { 361 aprint_error("%s: unable to load command header map" 362 ", error=%d\n", AHCINAME(sc), error); 363 return; 364 } 365 sc->sc_cmd_hdr = cmdhp; 366 367 ahci_enable_intrs(sc); 368 369 if (sc->sc_ahci_ports == 0) { 370 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 371 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 372 DEBUG_PROBE); 373 } 374 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 375 if ((sc->sc_ahci_ports & (1U << i)) == 0) 376 continue; 377 if (port >= sc->sc_atac.atac_nchannels) { 378 aprint_error("%s: more ports than announced\n", 379 AHCINAME(sc)); 380 break; 381 } 382 383 /* Optional intr establish per active port */ 384 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 385 aprint_error("%s: intr establish hook failed\n", 386 AHCINAME(sc)); 387 break; 388 } 389 390 achp = &sc->sc_channels[i]; 391 chp = &achp->ata_channel; 392 sc->sc_chanarray[i] = chp; 393 chp->ch_channel = i; 394 chp->ch_atac = &sc->sc_atac; 395 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 396 if (chp->ch_queue == NULL) { 397 aprint_error("%s port %d: can't allocate memory for " 398 "command queue", AHCINAME(sc), i); 399 break; 400 } 401 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 402 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 403 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 404 BUS_DMA_NOWAIT); 405 if (error) { 406 aprint_error("%s: unable to allocate command table " 407 "memory, error=%d\n", AHCINAME(sc), error); 408 break; 409 } 410 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 411 achp->ahcic_cmd_tbl_nseg, dmasize, 412 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 413 if (error) { 414 aprint_error("%s: unable to map command table memory" 415 ", error=%d\n", AHCINAME(sc), error); 416 break; 417 } 418 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 419 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 420 if (error) { 421 aprint_error("%s: unable to create command table map" 422 ", error=%d\n", AHCINAME(sc), error); 423 break; 424 } 425 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 426 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 427 if (error) { 428 aprint_error("%s: unable to load command table map" 429 ", error=%d\n", AHCINAME(sc), error); 430 break; 431 } 432 achp->ahcic_cmdh = (struct ahci_cmd_header *) 433 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 434 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 435 AHCI_CMDH_SIZE * port; 436 achp->ahcic_rfis = (struct ahci_r_fis *) 437 ((char *)cmdhp + 438 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 439 AHCI_RFIS_SIZE * port); 440 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 441 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 442 AHCI_RFIS_SIZE * port; 443 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 444 "rfis %p (0x%" PRIx64 ")\n", i, 445 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 446 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 447 DEBUG_PROBE); 448 449 for (j = 0; j < sc->sc_ncmds; j++) { 450 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 451 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 452 achp->ahcic_bus_cmd_tbl[j] = 453 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 454 AHCI_CMDTBL_SIZE * j; 455 achp->ahcic_cmdh[j].cmdh_cmdtba = 456 htole64(achp->ahcic_bus_cmd_tbl[j]); 457 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 458 achp->ahcic_cmd_tbl[j], 459 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 460 /* The xfer DMA map */ 461 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 462 AHCI_NPRD, 0x400000 /* 4MB */, 0, 463 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 464 &achp->ahcic_datad[j]); 465 if (error) { 466 aprint_error("%s: couldn't alloc xfer DMA map, " 467 "error=%d\n", AHCINAME(sc), error); 468 goto end; 469 } 470 } 471 ahci_setup_port(sc, i); 472 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 473 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 474 aprint_error("%s: couldn't map port %d " 475 "sata_status regs\n", AHCINAME(sc), i); 476 break; 477 } 478 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 479 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 480 aprint_error("%s: couldn't map port %d " 481 "sata_control regs\n", AHCINAME(sc), i); 482 break; 483 } 484 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 485 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 486 aprint_error("%s: couldn't map port %d " 487 "sata_error regs\n", AHCINAME(sc), i); 488 break; 489 } 490 ata_channel_attach(chp); 491 port++; 492 end: 493 continue; 494 } 495 } 496 497 void 498 ahci_childdetached(struct ahci_softc *sc, device_t child) 499 { 500 struct ahci_channel *achp; 501 struct ata_channel *chp; 502 503 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 504 achp = &sc->sc_channels[i]; 505 chp = &achp->ata_channel; 506 507 if ((sc->sc_ahci_ports & (1U << i)) == 0) 508 continue; 509 510 if (child == chp->atabus) 511 chp->atabus = NULL; 512 } 513 } 514 515 int 516 ahci_detach(struct ahci_softc *sc, int flags) 517 { 518 struct atac_softc *atac; 519 struct ahci_channel *achp; 520 struct ata_channel *chp; 521 struct scsipi_adapter *adapt; 522 int i, j, port; 523 int error; 524 525 atac = &sc->sc_atac; 526 adapt = &atac->atac_atapi_adapter._generic; 527 528 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 529 achp = &sc->sc_channels[i]; 530 chp = &achp->ata_channel; 531 532 if ((sc->sc_ahci_ports & (1U << i)) == 0) 533 continue; 534 if (port >= sc->sc_atac.atac_nchannels) { 535 aprint_error("%s: more ports than announced\n", 536 AHCINAME(sc)); 537 break; 538 } 539 540 if (chp->atabus != NULL) { 541 if ((error = config_detach(chp->atabus, flags)) != 0) 542 return error; 543 544 KASSERT(chp->atabus == NULL); 545 } 546 547 if (chp->ch_flags & ATACH_DETACHED) 548 continue; 549 550 for (j = 0; j < sc->sc_ncmds; j++) 551 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 552 553 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 554 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 555 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 556 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 557 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 558 achp->ahcic_cmd_tbl_nseg); 559 560 ata_channel_detach(chp); 561 port++; 562 } 563 564 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 565 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 566 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 567 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 568 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 569 570 if (adapt->adapt_refcnt != 0) 571 return EBUSY; 572 573 return 0; 574 } 575 576 void 577 ahci_resume(struct ahci_softc *sc) 578 { 579 ahci_reset(sc); 580 ahci_setup_ports(sc); 581 ahci_reprobe_drives(sc); 582 ahci_enable_intrs(sc); 583 } 584 585 int 586 ahci_intr(void *v) 587 { 588 struct ahci_softc *sc = v; 589 uint32_t is; 590 int i, r = 0; 591 592 while ((is = AHCI_READ(sc, AHCI_IS))) { 593 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 594 DEBUG_INTR); 595 r = 1; 596 AHCI_WRITE(sc, AHCI_IS, is); 597 for (i = 0; i < AHCI_MAX_PORTS; i++) 598 if (is & (1U << i)) 599 ahci_intr_port(&sc->sc_channels[i]); 600 } 601 602 return r; 603 } 604 605 int 606 ahci_intr_port(void *v) 607 { 608 struct ahci_channel *achp = v; 609 struct ata_channel *chp = &achp->ata_channel; 610 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 611 uint32_t is, tfd, sact; 612 struct ata_xfer *xfer; 613 int slot = -1; 614 bool recover = false; 615 uint32_t aslots; 616 617 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 618 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 619 620 AHCIDEBUG_PRINT(( 621 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 622 AHCINAME(sc), 623 chp->ch_channel, is, 624 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 625 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 626 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 627 DEBUG_INTR); 628 629 if ((chp->ch_flags & ATACH_NCQ) == 0) { 630 /* Non-NCQ operation */ 631 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 632 } else { 633 /* NCQ operation */ 634 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 635 } 636 637 /* Handle errors */ 638 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 639 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 640 /* Fatal errors */ 641 if (is & AHCI_P_IX_TFES) { 642 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 643 644 if ((chp->ch_flags & ATACH_NCQ) == 0) { 645 /* Slot valid only for Non-NCQ operation */ 646 slot = (AHCI_READ(sc, 647 AHCI_P_CMD(chp->ch_channel)) 648 & AHCI_P_CMD_CCS_MASK) 649 >> AHCI_P_CMD_CCS_SHIFT; 650 } 651 652 AHCIDEBUG_PRINT(( 653 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 654 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 655 DEBUG_INTR); 656 } else { 657 /* mark an error, and set BSY */ 658 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 659 WDCS_ERR | WDCS_BSY; 660 } 661 662 if (is & AHCI_P_IX_IFS) { 663 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 664 AHCINAME(sc), chp->ch_channel, 665 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 666 DEBUG_INTR); 667 } 668 669 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 670 recover = true; 671 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 672 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 673 674 /* D2H Register FIS or Set Device Bits */ 675 if ((tfd & WDCS_ERR) != 0) { 676 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 677 recover = true; 678 679 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 680 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 681 682 } 683 } else { 684 tfd = 0; 685 } 686 687 if (__predict_false(recover)) 688 ata_channel_freeze(chp); 689 690 aslots = ata_queue_active(chp); 691 692 if (slot >= 0) { 693 if ((aslots & __BIT(slot)) != 0 && 694 (sact & __BIT(slot)) == 0) { 695 xfer = ata_queue_hwslot_to_xfer(chp, slot); 696 xfer->ops->c_intr(chp, xfer, tfd); 697 } 698 } else { 699 /* 700 * For NCQ, HBA halts processing when error is notified, 701 * and any further D2H FISes are ignored until the error 702 * condition is cleared. Hence if a command is inactive, 703 * it means it actually already finished successfully. 704 * Note: active slots can change as c_intr() callback 705 * can activate another command(s), so must only process 706 * commands active before we start processing. 707 */ 708 709 for (slot=0; slot < sc->sc_ncmds; slot++) { 710 if ((aslots & __BIT(slot)) != 0 && 711 (sact & __BIT(slot)) == 0) { 712 xfer = ata_queue_hwslot_to_xfer(chp, slot); 713 xfer->ops->c_intr(chp, xfer, tfd); 714 } 715 } 716 } 717 718 if (__predict_false(recover)) { 719 ata_channel_lock(chp); 720 ata_channel_thaw_locked(chp); 721 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 722 ata_channel_unlock(chp); 723 } 724 725 return 1; 726 } 727 728 static void 729 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 730 { 731 struct ata_channel *chp = drvp->chnl_softc; 732 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 733 uint8_t c_slot; 734 735 ata_channel_lock_owned(chp); 736 737 /* get a slot for running the command on */ 738 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 739 panic("%s: %s: failed to get xfer for reset, port %d\n", 740 device_xname(sc->sc_atac.atac_dev), 741 __func__, chp->ch_channel); 742 /* NOTREACHED */ 743 } 744 745 AHCI_WRITE(sc, AHCI_GHC, 746 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 747 ahci_channel_stop(sc, chp, flags); 748 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 749 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 750 751 ata_queue_free_slot(chp, c_slot); 752 } 753 754 /* return error code from ata_bio */ 755 static int 756 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 757 { 758 struct ahci_channel *achp = (struct ahci_channel *)chp; 759 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 760 int i; 761 uint32_t is; 762 763 /* 764 * Base timeout is specified in ms. Delay for 10ms 765 * on each round. 766 */ 767 timeout = timeout / 10; 768 769 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 770 AHCI_CMDH_SYNC(sc, achp, slot, 771 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 772 /* start command */ 773 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 774 for (i = 0; i < timeout; i++) { 775 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 776 0) 777 return 0; 778 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 779 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 780 AHCI_P_IX_IFS | 781 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 782 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 783 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 784 /* 785 * we got the D2H FIS anyway, 786 * assume sig is valid. 787 * channel is restarted later 788 */ 789 return ERROR; 790 } 791 aprint_debug("%s port %d: error 0x%x sending FIS\n", 792 AHCINAME(sc), chp->ch_channel, is); 793 return ERR_DF; 794 } 795 ata_delay(chp, 10, "ahcifis", flags); 796 } 797 798 aprint_debug("%s port %d: timeout sending FIS\n", 799 AHCINAME(sc), chp->ch_channel); 800 return TIMEOUT; 801 } 802 803 static int 804 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 805 uint32_t *sigp, uint8_t c_slot) 806 { 807 struct ahci_channel *achp = (struct ahci_channel *)chp; 808 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 809 struct ahci_cmd_tbl *cmd_tbl; 810 struct ahci_cmd_header *cmd_h; 811 int i, error = 0; 812 uint32_t sig, cmd; 813 int noclo_retry = 0, retry; 814 815 ata_channel_lock_owned(chp); 816 817 again: 818 /* clear port interrupt register */ 819 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 820 /* clear SErrors and start operations */ 821 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 822 /* 823 * issue a command list override to clear BSY. 824 * This is needed if there's a PMP with no drive 825 * on port 0 826 */ 827 ahci_channel_start(sc, chp, flags, 1); 828 } else { 829 /* Can't handle command still running without CLO */ 830 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 831 if ((cmd & AHCI_P_CMD_CR) != 0) { 832 ahci_channel_stop(sc, chp, flags); 833 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 834 if ((cmd & AHCI_P_CMD_CR) != 0) { 835 aprint_error("%s port %d: DMA engine busy " 836 "for drive %d\n", AHCINAME(sc), 837 chp->ch_channel, drive); 838 error = EBUSY; 839 goto end; 840 } 841 } 842 843 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 844 845 ahci_channel_start(sc, chp, flags, 0); 846 } 847 if (drive > 0) { 848 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 849 } 850 851 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 852 goto skip_reset; 853 854 /* polled command, assume interrupts are disabled */ 855 856 cmd_h = &achp->ahcic_cmdh[c_slot]; 857 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 858 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 859 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 860 cmd_h->cmdh_prdtl = 0; 861 cmd_h->cmdh_prdbc = 0; 862 memset(cmd_tbl->cmdt_cfis, 0, 64); 863 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 864 cmd_tbl->cmdt_cfis[rhd_c] = drive; 865 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 866 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 867 case ERR_DF: 868 case TIMEOUT: 869 /* 870 * without CLO we can't make sure a software reset will 871 * success, as the drive may still have BSY or DRQ set. 872 * in this case, reset the whole channel and retry the 873 * drive reset. The channel reset should clear BSY and DRQ 874 */ 875 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 876 noclo_retry++; 877 ahci_reset_channel(chp, flags); 878 goto again; 879 } 880 aprint_error("%s port %d: setting WDCTL_RST failed " 881 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 882 error = EBUSY; 883 goto end; 884 default: 885 break; 886 } 887 888 /* 889 * SATA specification has toggle period for SRST bit of 5 usec. Some 890 * controllers fail to process the SRST clear operation unless 891 * we wait for at least this period between the set and clear commands. 892 */ 893 ata_delay(chp, 10, "ahcirstw", flags); 894 895 /* 896 * Try to clear WDCTL_RST a few times before giving up. 897 */ 898 for (error = EBUSY, retry = 0; error != 0 && retry < 5; retry++) { 899 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 900 (drive << AHCI_CMDH_F_PMP_SHIFT)); 901 cmd_h->cmdh_prdbc = 0; 902 memset(cmd_tbl->cmdt_cfis, 0, 64); 903 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 904 cmd_tbl->cmdt_cfis[rhd_c] = drive; 905 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 906 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 907 case ERR_DF: 908 case TIMEOUT: 909 error = EBUSY; 910 break; 911 default: 912 error = 0; 913 break; 914 } 915 if (error == 0) { 916 break; 917 } 918 } 919 if (error == EBUSY) { 920 aprint_error("%s port %d: clearing WDCTL_RST failed " 921 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 922 goto end; 923 } 924 925 skip_reset: 926 /* 927 * wait 31s for BSY to clear 928 * This should not be needed, but some controllers clear the 929 * command slot before receiving the D2H FIS ... 930 */ 931 for (i = 0; i < AHCI_RST_WAIT; i++) { 932 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 933 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 934 break; 935 ata_delay(chp, 10, "ahcid2h", flags); 936 } 937 if (i == AHCI_RST_WAIT) { 938 aprint_error("%s: BSY never cleared, TD 0x%x\n", 939 AHCINAME(sc), sig); 940 goto end; 941 } 942 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 943 DEBUG_PROBE); 944 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 945 if (sigp) 946 *sigp = sig; 947 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 948 AHCINAME(sc), chp->ch_channel, sig, 949 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 950 end: 951 ahci_channel_stop(sc, chp, flags); 952 ata_delay(chp, 500, "ahcirst", flags); 953 /* clear port interrupt register */ 954 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 955 ahci_channel_start(sc, chp, flags, 956 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 957 return error; 958 } 959 960 static void 961 ahci_reset_channel(struct ata_channel *chp, int flags) 962 { 963 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 964 struct ahci_channel *achp = (struct ahci_channel *)chp; 965 int i, tfd; 966 967 ata_channel_lock_owned(chp); 968 969 ahci_channel_stop(sc, chp, flags); 970 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 971 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 972 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 973 /* XXX and then ? */ 974 } 975 ata_kill_active(chp, KILL_RESET, flags); 976 ata_delay(chp, 500, "ahcirst", flags); 977 /* clear port interrupt register */ 978 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 979 /* clear SErrors and start operations */ 980 ahci_channel_start(sc, chp, flags, 981 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 982 /* wait 31s for BSY to clear */ 983 for (i = 0; i < AHCI_RST_WAIT; i++) { 984 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 985 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 986 break; 987 ata_delay(chp, 10, "ahcid2h", flags); 988 } 989 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 990 aprint_error("%s: BSY never cleared, TD 0x%x\n", 991 AHCINAME(sc), tfd); 992 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 993 DEBUG_PROBE); 994 /* clear port interrupt register */ 995 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 996 997 return; 998 } 999 1000 static int 1001 ahci_ata_addref(struct ata_drive_datas *drvp) 1002 { 1003 return 0; 1004 } 1005 1006 static void 1007 ahci_ata_delref(struct ata_drive_datas *drvp) 1008 { 1009 return; 1010 } 1011 1012 static void 1013 ahci_killpending(struct ata_drive_datas *drvp) 1014 { 1015 return; 1016 } 1017 1018 static void 1019 ahci_probe_drive(struct ata_channel *chp) 1020 { 1021 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1022 struct ahci_channel *achp = (struct ahci_channel *)chp; 1023 uint32_t sig; 1024 uint8_t c_slot; 1025 int error; 1026 1027 ata_channel_lock(chp); 1028 1029 /* get a slot for running the command on */ 1030 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1031 aprint_error_dev(sc->sc_atac.atac_dev, 1032 "%s: failed to get xfer port %d\n", 1033 __func__, chp->ch_channel); 1034 ata_channel_unlock(chp); 1035 return; 1036 } 1037 1038 /* bring interface up, accept FISs, power up and spin up device */ 1039 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1040 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1041 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1042 /* reset the PHY and bring online */ 1043 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1044 achp->ahcic_sstatus, AT_WAIT)) { 1045 case SStatus_DET_DEV: 1046 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1047 1048 /* Initial value, used in case the soft reset fails */ 1049 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1050 1051 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1052 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1053 &sig, c_slot); 1054 1055 /* If probe for PMP failed, just fallback to drive 0 */ 1056 if (error) { 1057 aprint_error("%s port %d: drive %d reset " 1058 "failed, disabling PMP\n", 1059 AHCINAME(sc), chp->ch_channel, 1060 PMP_PORT_CTL); 1061 1062 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1063 ahci_reset_channel(chp, AT_WAIT); 1064 } 1065 } else { 1066 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1067 } 1068 sata_interpret_sig(chp, 0, sig); 1069 /* if we have a PMP attached, inform the controller */ 1070 if (chp->ch_ndrives > PMP_PORT_CTL && 1071 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1072 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1073 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1074 AHCI_P_CMD_PMA); 1075 } 1076 /* clear port interrupt register */ 1077 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1078 1079 /* and enable interrupts */ 1080 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1081 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1082 AHCI_P_IX_IFS | 1083 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1084 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1085 /* wait 500ms before actually starting operations */ 1086 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1087 break; 1088 1089 default: 1090 break; 1091 } 1092 1093 ata_queue_free_slot(chp, c_slot); 1094 1095 ata_channel_unlock(chp); 1096 } 1097 1098 static void 1099 ahci_setup_channel(struct ata_channel *chp) 1100 { 1101 return; 1102 } 1103 1104 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1105 .c_start = ahci_cmd_start, 1106 .c_poll = ahci_cmd_poll, 1107 .c_abort = ahci_cmd_abort, 1108 .c_intr = ahci_cmd_complete, 1109 .c_kill_xfer = ahci_cmd_kill_xfer, 1110 }; 1111 1112 static void 1113 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1114 { 1115 struct ata_channel *chp = drvp->chnl_softc; 1116 struct ata_command *ata_c = &xfer->c_ata_c; 1117 1118 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1119 chp->ch_channel, 1120 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1121 DEBUG_XFERS); 1122 if (ata_c->flags & AT_POLL) 1123 xfer->c_flags |= C_POLL; 1124 if (ata_c->flags & AT_WAIT) 1125 xfer->c_flags |= C_WAIT; 1126 xfer->c_drive = drvp->drive; 1127 xfer->c_databuf = ata_c->data; 1128 xfer->c_bcount = ata_c->bcount; 1129 xfer->ops = &ahci_cmd_xfer_ops; 1130 1131 ata_exec_xfer(chp, xfer); 1132 } 1133 1134 static int 1135 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1136 { 1137 struct ahci_softc *sc = AHCI_CH2SC(chp); 1138 struct ahci_channel *achp = (struct ahci_channel *)chp; 1139 struct ata_command *ata_c = &xfer->c_ata_c; 1140 int slot = xfer->c_slot; 1141 struct ahci_cmd_tbl *cmd_tbl; 1142 struct ahci_cmd_header *cmd_h; 1143 1144 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1145 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1146 ata_c->timeout, slot), 1147 DEBUG_XFERS); 1148 1149 ata_channel_lock_owned(chp); 1150 1151 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1152 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1153 cmd_tbl), DEBUG_XFERS); 1154 1155 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1156 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1157 1158 cmd_h = &achp->ahcic_cmdh[slot]; 1159 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1160 chp->ch_channel, cmd_h), DEBUG_XFERS); 1161 if (ahci_dma_setup(chp, slot, 1162 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1163 ata_c->data : NULL, 1164 ata_c->bcount, 1165 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1166 ata_c->flags |= AT_DF; 1167 return ATASTART_ABORT; 1168 } 1169 cmd_h->cmdh_flags = htole16( 1170 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1171 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1172 cmd_h->cmdh_prdbc = 0; 1173 AHCI_CMDH_SYNC(sc, achp, slot, 1174 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1175 1176 if (ata_c->flags & AT_POLL) { 1177 /* polled command, disable interrupts */ 1178 AHCI_WRITE(sc, AHCI_GHC, 1179 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1180 } 1181 /* start command */ 1182 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1183 1184 if ((ata_c->flags & AT_POLL) == 0) { 1185 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1186 ata_timeout, chp); 1187 return ATASTART_STARTED; 1188 } else 1189 return ATASTART_POLL; 1190 } 1191 1192 static void 1193 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1194 { 1195 struct ahci_softc *sc = AHCI_CH2SC(chp); 1196 struct ahci_channel *achp = (struct ahci_channel *)chp; 1197 1198 ata_channel_lock(chp); 1199 1200 /* 1201 * Polled command. 1202 */ 1203 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1204 if (xfer->c_ata_c.flags & AT_DONE) 1205 break; 1206 ata_channel_unlock(chp); 1207 ahci_intr_port(achp); 1208 ata_channel_lock(chp); 1209 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1210 } 1211 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1212 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1213 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1214 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1215 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1216 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1217 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1218 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1219 DEBUG_XFERS); 1220 1221 ata_channel_unlock(chp); 1222 1223 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1224 xfer->c_ata_c.flags |= AT_TIMEOU; 1225 xfer->ops->c_intr(chp, xfer, 0); 1226 } 1227 /* reenable interrupts */ 1228 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1229 } 1230 1231 static void 1232 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1233 { 1234 ahci_cmd_complete(chp, xfer, 0); 1235 } 1236 1237 static void 1238 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1239 { 1240 struct ata_command *ata_c = &xfer->c_ata_c; 1241 bool deactivate = true; 1242 1243 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1244 DEBUG_FUNCS); 1245 1246 switch (reason) { 1247 case KILL_GONE_INACTIVE: 1248 deactivate = false; 1249 /* FALLTHROUGH */ 1250 case KILL_GONE: 1251 ata_c->flags |= AT_GONE; 1252 break; 1253 case KILL_RESET: 1254 ata_c->flags |= AT_RESET; 1255 break; 1256 case KILL_REQUEUE: 1257 panic("%s: not supposed to be requeued\n", __func__); 1258 break; 1259 default: 1260 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1261 panic("ahci_cmd_kill_xfer"); 1262 } 1263 1264 ahci_cmd_done_end(chp, xfer); 1265 1266 if (deactivate) 1267 ata_deactivate_xfer(chp, xfer); 1268 } 1269 1270 static int 1271 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1272 { 1273 struct ata_command *ata_c = &xfer->c_ata_c; 1274 struct ahci_channel *achp = (struct ahci_channel *)chp; 1275 struct ahci_softc *sc = AHCI_CH2SC(chp); 1276 1277 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1278 chp->ch_channel, 1279 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1280 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1281 DEBUG_FUNCS); 1282 1283 if (ata_waitdrain_xfer_check(chp, xfer)) 1284 return 0; 1285 1286 if (xfer->c_flags & C_TIMEOU) { 1287 ata_c->flags |= AT_TIMEOU; 1288 } 1289 1290 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1291 ata_c->flags |= AT_TIMEOU; 1292 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1293 ata_c->r_error = AHCI_TFD_ERR(tfd); 1294 ata_c->flags |= AT_ERROR; 1295 } 1296 1297 if (ata_c->flags & AT_READREG) { 1298 AHCI_RFIS_SYNC(sc, achp, BUS_DMASYNC_POSTREAD); 1299 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1300 } 1301 1302 ahci_cmd_done(chp, xfer); 1303 1304 ata_deactivate_xfer(chp, xfer); 1305 1306 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1307 atastart(chp); 1308 1309 return 0; 1310 } 1311 1312 static void 1313 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1314 { 1315 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1316 struct ahci_channel *achp = (struct ahci_channel *)chp; 1317 struct ata_command *ata_c = &xfer->c_ata_c; 1318 uint16_t *idwordbuf; 1319 int i; 1320 1321 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1322 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1323 1324 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1325 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1326 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1327 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1328 BUS_DMASYNC_POSTWRITE); 1329 bus_dmamap_unload(sc->sc_dmat, map); 1330 } 1331 1332 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1333 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1334 1335 /* ata(4) expects IDENTIFY data to be in host endianess */ 1336 if (ata_c->r_command == WDCC_IDENTIFY || 1337 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1338 idwordbuf = xfer->c_databuf; 1339 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1340 idwordbuf[i] = le16toh(idwordbuf[i]); 1341 } 1342 } 1343 1344 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1345 ata_c->flags |= AT_XFDONE; 1346 1347 ahci_cmd_done_end(chp, xfer); 1348 } 1349 1350 static void 1351 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1352 { 1353 struct ata_command *ata_c = &xfer->c_ata_c; 1354 1355 ata_c->flags |= AT_DONE; 1356 } 1357 1358 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1359 .c_start = ahci_bio_start, 1360 .c_poll = ahci_bio_poll, 1361 .c_abort = ahci_bio_abort, 1362 .c_intr = ahci_bio_complete, 1363 .c_kill_xfer = ahci_bio_kill_xfer, 1364 }; 1365 1366 static void 1367 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1368 { 1369 struct ata_channel *chp = drvp->chnl_softc; 1370 struct ata_bio *ata_bio = &xfer->c_bio; 1371 1372 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1373 chp->ch_channel, 1374 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1375 DEBUG_XFERS); 1376 if (ata_bio->flags & ATA_POLL) 1377 xfer->c_flags |= C_POLL; 1378 xfer->c_drive = drvp->drive; 1379 xfer->c_databuf = ata_bio->databuf; 1380 xfer->c_bcount = ata_bio->bcount; 1381 xfer->ops = &ahci_bio_xfer_ops; 1382 ata_exec_xfer(chp, xfer); 1383 } 1384 1385 static int 1386 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1387 { 1388 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1389 struct ahci_channel *achp = (struct ahci_channel *)chp; 1390 struct ata_bio *ata_bio = &xfer->c_bio; 1391 struct ahci_cmd_tbl *cmd_tbl; 1392 struct ahci_cmd_header *cmd_h; 1393 1394 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1395 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1396 1397 ata_channel_lock_owned(chp); 1398 1399 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1400 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1401 cmd_tbl), DEBUG_XFERS); 1402 1403 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1404 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1405 1406 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1407 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1408 chp->ch_channel, cmd_h), DEBUG_XFERS); 1409 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1410 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1411 ata_bio->error = ERR_DMA; 1412 ata_bio->r_error = 0; 1413 return ATASTART_ABORT; 1414 } 1415 cmd_h->cmdh_flags = htole16( 1416 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1417 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1418 cmd_h->cmdh_prdbc = 0; 1419 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1421 1422 if (xfer->c_flags & C_POLL) { 1423 /* polled command, disable interrupts */ 1424 AHCI_WRITE(sc, AHCI_GHC, 1425 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1426 } 1427 if (xfer->c_flags & C_NCQ) 1428 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1429 /* start command */ 1430 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1431 1432 if ((xfer->c_flags & C_POLL) == 0) { 1433 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1434 ata_timeout, chp); 1435 return ATASTART_STARTED; 1436 } else 1437 return ATASTART_POLL; 1438 } 1439 1440 static void 1441 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1442 { 1443 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1444 struct ahci_channel *achp = (struct ahci_channel *)chp; 1445 1446 /* 1447 * Polled command. 1448 */ 1449 for (int i = 0; i < ATA_DELAY * 10; i++) { 1450 if (xfer->c_bio.flags & ATA_ITSDONE) 1451 break; 1452 ahci_intr_port(achp); 1453 delay(100); 1454 } 1455 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1456 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1457 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1458 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1459 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1460 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1461 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1462 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1463 DEBUG_XFERS); 1464 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1465 xfer->c_bio.error = TIMEOUT; 1466 xfer->ops->c_intr(chp, xfer, 0); 1467 } 1468 /* reenable interrupts */ 1469 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1470 } 1471 1472 static void 1473 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1474 { 1475 ahci_bio_complete(chp, xfer, 0); 1476 } 1477 1478 static void 1479 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1480 { 1481 int drive = xfer->c_drive; 1482 struct ata_bio *ata_bio = &xfer->c_bio; 1483 bool deactivate = true; 1484 1485 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1486 DEBUG_FUNCS); 1487 1488 ata_bio->flags |= ATA_ITSDONE; 1489 switch (reason) { 1490 case KILL_GONE_INACTIVE: 1491 deactivate = false; 1492 /* FALLTHROUGH */ 1493 case KILL_GONE: 1494 ata_bio->error = ERR_NODEV; 1495 break; 1496 case KILL_RESET: 1497 ata_bio->error = ERR_RESET; 1498 break; 1499 case KILL_REQUEUE: 1500 ata_bio->error = REQUEUE; 1501 break; 1502 default: 1503 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1504 panic("ahci_bio_kill_xfer"); 1505 } 1506 ata_bio->r_error = WDCE_ABRT; 1507 1508 if (deactivate) 1509 ata_deactivate_xfer(chp, xfer); 1510 1511 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1512 } 1513 1514 static int 1515 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1516 { 1517 struct ata_bio *ata_bio = &xfer->c_bio; 1518 int drive = xfer->c_drive; 1519 struct ahci_channel *achp = (struct ahci_channel *)chp; 1520 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1521 1522 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1523 DEBUG_FUNCS); 1524 1525 if (ata_waitdrain_xfer_check(chp, xfer)) 1526 return 0; 1527 1528 if (xfer->c_flags & C_TIMEOU) { 1529 ata_bio->error = TIMEOUT; 1530 } 1531 1532 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1533 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1534 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1535 BUS_DMASYNC_POSTWRITE); 1536 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1537 1538 ata_bio->flags |= ATA_ITSDONE; 1539 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1540 ata_bio->error = ERR_DF; 1541 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1542 ata_bio->error = ERROR; 1543 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1544 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1545 ata_bio->flags |= ATA_CORR; 1546 1547 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1548 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1549 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1550 ata_bio->bcount), DEBUG_XFERS); 1551 /* 1552 * If it was a write, complete data buffer may have been transferred 1553 * before error detection; in this case don't use cmdh_prdbc 1554 * as it won't reflect what was written to media. Assume nothing 1555 * was transferred and leave bcount as-is. 1556 * For queued commands, PRD Byte Count should not be used, and is 1557 * not required to be valid; in that case underflow is always illegal. 1558 */ 1559 if ((xfer->c_flags & C_NCQ) != 0) { 1560 if (ata_bio->error == NOERROR) 1561 ata_bio->bcount = 0; 1562 } else { 1563 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1564 ata_bio->bcount -= 1565 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1566 } 1567 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1568 1569 ata_deactivate_xfer(chp, xfer); 1570 1571 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1572 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1573 atastart(chp); 1574 return 0; 1575 } 1576 1577 static void 1578 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1579 { 1580 int i; 1581 /* stop channel */ 1582 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1583 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1584 /* wait 1s for channel to stop */ 1585 for (i = 0; i <100; i++) { 1586 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1587 == 0) 1588 break; 1589 ata_delay(chp, 10, "ahcistop", flags); 1590 } 1591 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1592 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1593 /* XXX controller reset ? */ 1594 return; 1595 } 1596 1597 if (sc->sc_channel_stop) 1598 sc->sc_channel_stop(sc, chp); 1599 } 1600 1601 static void 1602 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1603 int flags, int clo) 1604 { 1605 int i; 1606 uint32_t p_cmd; 1607 /* clear error */ 1608 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1609 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1610 1611 if (clo) { 1612 /* issue command list override */ 1613 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1614 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1615 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1616 /* wait 1s for AHCI_CAP_CLO to clear */ 1617 for (i = 0; i <100; i++) { 1618 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1619 AHCI_P_CMD_CLO) == 0) 1620 break; 1621 ata_delay(chp, 10, "ahciclo", flags); 1622 } 1623 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1624 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1625 /* XXX controller reset ? */ 1626 return; 1627 } 1628 } 1629 1630 if (sc->sc_channel_start) 1631 sc->sc_channel_start(sc, chp); 1632 1633 /* and start controller */ 1634 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1635 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1636 if (chp->ch_ndrives > PMP_PORT_CTL && 1637 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1638 p_cmd |= AHCI_P_CMD_PMA; 1639 } 1640 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1641 } 1642 1643 /* Recover channel after command failure */ 1644 static void 1645 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1646 { 1647 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1648 int drive = ATACH_NODRIVE; 1649 bool reset = false; 1650 1651 ata_channel_lock_owned(chp); 1652 1653 /* 1654 * Read FBS to get the drive which caused the error, if PM is in use. 1655 * According to AHCI 1.3 spec, this register is available regardless 1656 * if FIS-based switching (FBSS) feature is supported, or disabled. 1657 * If FIS-based switching is not in use, it merely maintains single 1658 * pair of DRQ/BSY state, but it is enough since in that case we 1659 * never issue commands for more than one device at the time anyway. 1660 * XXX untested 1661 */ 1662 if (chp->ch_ndrives > PMP_PORT_CTL) { 1663 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1664 if (fbs & AHCI_P_FBS_SDE) { 1665 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1666 1667 /* 1668 * Tell HBA to reset PM port X (value in DWE) state, 1669 * and resume processing commands for other ports. 1670 */ 1671 fbs |= AHCI_P_FBS_DEC; 1672 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1673 for (int i = 0; i < 1000; i++) { 1674 fbs = AHCI_READ(sc, 1675 AHCI_P_FBS(chp->ch_channel)); 1676 if ((fbs & AHCI_P_FBS_DEC) == 0) 1677 break; 1678 DELAY(1000); 1679 } 1680 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1681 /* follow non-device specific recovery */ 1682 drive = ATACH_NODRIVE; 1683 reset = true; 1684 } 1685 } else { 1686 /* not device specific, reset channel */ 1687 drive = ATACH_NODRIVE; 1688 reset = true; 1689 } 1690 } else 1691 drive = 0; 1692 1693 /* 1694 * If BSY or DRQ bits are set, must execute COMRESET to return 1695 * device to idle state. If drive is idle, it's enough to just 1696 * reset CMD.ST, it's not necessary to do software reset. 1697 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1698 * to unblock device processing if COMRESET was not done. 1699 */ 1700 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1701 ahci_reset_channel(chp, flags); 1702 goto out; 1703 } 1704 1705 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1706 ahci_channel_stop(sc, chp, flags); 1707 ahci_channel_start(sc, chp, flags, 1708 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1709 1710 ata_recovery_resume(chp, drive, tfd, flags); 1711 1712 out: 1713 /* Drive unblocked, back to normal operation */ 1714 return; 1715 } 1716 1717 static int 1718 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1719 size_t count, int op) 1720 { 1721 int error, seg; 1722 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1723 struct ahci_channel *achp = (struct ahci_channel *)chp; 1724 struct ahci_cmd_tbl *cmd_tbl; 1725 struct ahci_cmd_header *cmd_h; 1726 1727 cmd_h = &achp->ahcic_cmdh[slot]; 1728 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1729 1730 if (data == NULL) { 1731 cmd_h->cmdh_prdtl = 0; 1732 goto end; 1733 } 1734 1735 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1736 data, count, NULL, 1737 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1738 if (error) { 1739 printf("%s port %d: failed to load xfer: %d\n", 1740 AHCINAME(sc), chp->ch_channel, error); 1741 return error; 1742 } 1743 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1744 achp->ahcic_datad[slot]->dm_mapsize, 1745 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1746 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1747 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1748 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1749 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1750 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1751 } 1752 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1753 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1754 end: 1755 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1756 return 0; 1757 } 1758 1759 #if NATAPIBUS > 0 1760 static void 1761 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1762 { 1763 struct ata_channel *chp = ata_sc->sc_chan; 1764 struct atac_softc *atac = chp->ch_atac; 1765 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1766 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1767 /* 1768 * Fill in the scsipi_adapter. 1769 */ 1770 adapt->adapt_dev = atac->atac_dev; 1771 adapt->adapt_nchannels = atac->atac_nchannels; 1772 adapt->adapt_request = ahci_atapi_scsipi_request; 1773 adapt->adapt_minphys = ahci_atapi_minphys; 1774 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1775 1776 /* 1777 * Fill in the scsipi_channel. 1778 */ 1779 memset(chan, 0, sizeof(*chan)); 1780 chan->chan_adapter = adapt; 1781 chan->chan_bustype = &ahci_atapi_bustype; 1782 chan->chan_channel = chp->ch_channel; 1783 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1784 chan->chan_openings = 1; 1785 chan->chan_max_periph = 1; 1786 chan->chan_ntargets = 1; 1787 chan->chan_nluns = 1; 1788 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1789 atapiprint); 1790 } 1791 1792 static void 1793 ahci_atapi_minphys(struct buf *bp) 1794 { 1795 if (bp->b_bcount > MAXPHYS) 1796 bp->b_bcount = MAXPHYS; 1797 minphys(bp); 1798 } 1799 1800 /* 1801 * Kill off all pending xfers for a periph. 1802 * 1803 * Must be called at splbio(). 1804 */ 1805 static void 1806 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1807 { 1808 struct atac_softc *atac = 1809 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1810 struct ata_channel *chp = 1811 atac->atac_channels[periph->periph_channel->chan_channel]; 1812 1813 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1814 } 1815 1816 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1817 .c_start = ahci_atapi_start, 1818 .c_poll = ahci_atapi_poll, 1819 .c_abort = ahci_atapi_abort, 1820 .c_intr = ahci_atapi_complete, 1821 .c_kill_xfer = ahci_atapi_kill_xfer, 1822 }; 1823 1824 static void 1825 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1826 scsipi_adapter_req_t req, void *arg) 1827 { 1828 struct scsipi_adapter *adapt = chan->chan_adapter; 1829 struct scsipi_periph *periph; 1830 struct scsipi_xfer *sc_xfer; 1831 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1832 struct atac_softc *atac = &sc->sc_atac; 1833 struct ata_xfer *xfer; 1834 int channel = chan->chan_channel; 1835 int drive, s; 1836 1837 switch (req) { 1838 case ADAPTER_REQ_RUN_XFER: 1839 sc_xfer = arg; 1840 periph = sc_xfer->xs_periph; 1841 drive = periph->periph_target; 1842 if (!device_is_active(atac->atac_dev)) { 1843 sc_xfer->error = XS_DRIVER_STUFFUP; 1844 scsipi_done(sc_xfer); 1845 return; 1846 } 1847 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1848 if (xfer == NULL) { 1849 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1850 scsipi_done(sc_xfer); 1851 return; 1852 } 1853 1854 if (sc_xfer->xs_control & XS_CTL_POLL) 1855 xfer->c_flags |= C_POLL; 1856 xfer->c_drive = drive; 1857 xfer->c_flags |= C_ATAPI; 1858 xfer->c_databuf = sc_xfer->data; 1859 xfer->c_bcount = sc_xfer->datalen; 1860 xfer->ops = &ahci_atapi_xfer_ops; 1861 xfer->c_scsipi = sc_xfer; 1862 xfer->c_atapi.c_dscpoll = 0; 1863 s = splbio(); 1864 ata_exec_xfer(atac->atac_channels[channel], xfer); 1865 #ifdef DIAGNOSTIC 1866 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1867 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1868 panic("ahci_atapi_scsipi_request: polled command " 1869 "not done"); 1870 #endif 1871 splx(s); 1872 return; 1873 default: 1874 /* Not supported, nothing to do. */ 1875 ; 1876 } 1877 } 1878 1879 static int 1880 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1881 { 1882 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1883 struct ahci_channel *achp = (struct ahci_channel *)chp; 1884 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1885 struct ahci_cmd_tbl *cmd_tbl; 1886 struct ahci_cmd_header *cmd_h; 1887 1888 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1889 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1890 1891 ata_channel_lock_owned(chp); 1892 1893 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1894 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1895 cmd_tbl), DEBUG_XFERS); 1896 1897 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1898 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1899 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1900 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1901 1902 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1903 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1904 chp->ch_channel, cmd_h), DEBUG_XFERS); 1905 if (ahci_dma_setup(chp, xfer->c_slot, 1906 sc_xfer->datalen ? sc_xfer->data : NULL, 1907 sc_xfer->datalen, 1908 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1909 BUS_DMA_READ : BUS_DMA_WRITE)) { 1910 sc_xfer->error = XS_DRIVER_STUFFUP; 1911 return ATASTART_ABORT; 1912 } 1913 cmd_h->cmdh_flags = htole16( 1914 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1915 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1916 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1917 cmd_h->cmdh_prdbc = 0; 1918 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1919 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1920 1921 if (xfer->c_flags & C_POLL) { 1922 /* polled command, disable interrupts */ 1923 AHCI_WRITE(sc, AHCI_GHC, 1924 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1925 } 1926 /* start command */ 1927 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1928 1929 if ((xfer->c_flags & C_POLL) == 0) { 1930 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1931 ata_timeout, chp); 1932 return ATASTART_STARTED; 1933 } else 1934 return ATASTART_POLL; 1935 } 1936 1937 static void 1938 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1939 { 1940 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1941 struct ahci_channel *achp = (struct ahci_channel *)chp; 1942 1943 /* 1944 * Polled command. 1945 */ 1946 for (int i = 0; i < ATA_DELAY / 10; i++) { 1947 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1948 break; 1949 ahci_intr_port(achp); 1950 delay(10000); 1951 } 1952 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1953 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1954 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1955 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1956 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1957 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1958 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1959 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1960 DEBUG_XFERS); 1961 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1962 xfer->c_scsipi->error = XS_TIMEOUT; 1963 xfer->ops->c_intr(chp, xfer, 0); 1964 } 1965 /* reenable interrupts */ 1966 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1967 } 1968 1969 static void 1970 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1971 { 1972 ahci_atapi_complete(chp, xfer, 0); 1973 } 1974 1975 static int 1976 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1977 { 1978 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1979 struct ahci_channel *achp = (struct ahci_channel *)chp; 1980 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1981 1982 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1983 DEBUG_FUNCS); 1984 1985 if (ata_waitdrain_xfer_check(chp, xfer)) 1986 return 0; 1987 1988 if (xfer->c_flags & C_TIMEOU) { 1989 sc_xfer->error = XS_TIMEOUT; 1990 } 1991 1992 if (xfer->c_bcount > 0) { 1993 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1994 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1995 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1996 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1997 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1998 } 1999 2000 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2001 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2002 sc_xfer->resid = sc_xfer->datalen; 2003 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2004 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2005 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2006 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2007 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2008 sc_xfer->resid == sc_xfer->datalen)) { 2009 sc_xfer->error = XS_SHORTSENSE; 2010 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2011 if ((sc_xfer->xs_periph->periph_quirks & 2012 PQUIRK_NOSENSE) == 0) { 2013 /* ask scsipi to send a REQUEST_SENSE */ 2014 sc_xfer->error = XS_BUSY; 2015 sc_xfer->status = SCSI_CHECK; 2016 } 2017 } 2018 2019 ata_deactivate_xfer(chp, xfer); 2020 2021 ata_free_xfer(chp, xfer); 2022 scsipi_done(sc_xfer); 2023 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2024 atastart(chp); 2025 return 0; 2026 } 2027 2028 static void 2029 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2030 { 2031 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2032 bool deactivate = true; 2033 2034 /* remove this command from xfer queue */ 2035 switch (reason) { 2036 case KILL_GONE_INACTIVE: 2037 deactivate = false; 2038 /* FALLTHROUGH */ 2039 case KILL_GONE: 2040 sc_xfer->error = XS_DRIVER_STUFFUP; 2041 break; 2042 case KILL_RESET: 2043 sc_xfer->error = XS_RESET; 2044 break; 2045 case KILL_REQUEUE: 2046 sc_xfer->error = XS_REQUEUE; 2047 break; 2048 default: 2049 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2050 panic("ahci_ata_atapi_kill_xfer"); 2051 } 2052 2053 if (deactivate) 2054 ata_deactivate_xfer(chp, xfer); 2055 2056 ata_free_xfer(chp, xfer); 2057 scsipi_done(sc_xfer); 2058 } 2059 2060 static void 2061 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2062 { 2063 struct scsipi_channel *chan = sc->sc_channel; 2064 struct scsipi_periph *periph; 2065 struct ataparams ids; 2066 struct ataparams *id = &ids; 2067 struct ahci_softc *ahcic = 2068 device_private(chan->chan_adapter->adapt_dev); 2069 struct atac_softc *atac = &ahcic->sc_atac; 2070 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2071 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2072 struct scsipibus_attach_args sa; 2073 char serial_number[21], model[41], firmware_revision[9]; 2074 int s; 2075 2076 /* skip if already attached */ 2077 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2078 return; 2079 2080 /* if no ATAPI device detected at attach time, skip */ 2081 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2082 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2083 "not present\n", target), DEBUG_PROBE); 2084 return; 2085 } 2086 2087 /* Some ATAPI devices need a bit more time after software reset. */ 2088 delay(5000); 2089 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2090 #ifdef ATAPI_DEBUG_PROBE 2091 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2092 AHCINAME(ahcic), target, 2093 id->atap_config & ATAPI_CFG_CMD_MASK, 2094 id->atap_config & ATAPI_CFG_DRQ_MASK); 2095 #endif 2096 periph = scsipi_alloc_periph(M_NOWAIT); 2097 if (periph == NULL) { 2098 aprint_error_dev(sc->sc_dev, 2099 "unable to allocate periph for drive %d\n", 2100 target); 2101 return; 2102 } 2103 periph->periph_dev = NULL; 2104 periph->periph_channel = chan; 2105 periph->periph_switch = &atapi_probe_periphsw; 2106 periph->periph_target = target; 2107 periph->periph_lun = 0; 2108 periph->periph_quirks = PQUIRK_ONLYBIG; 2109 2110 #ifdef SCSIPI_DEBUG 2111 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2112 SCSIPI_DEBUG_TARGET == target) 2113 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2114 #endif 2115 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2116 if (id->atap_config & ATAPI_CFG_REMOV) 2117 periph->periph_flags |= PERIPH_REMOVABLE; 2118 if (periph->periph_type == T_SEQUENTIAL) { 2119 s = splbio(); 2120 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2121 splx(s); 2122 } 2123 2124 sa.sa_periph = periph; 2125 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2126 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2127 T_REMOV : T_FIXED; 2128 strnvisx(model, sizeof(model), id->atap_model, 40, 2129 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2130 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2131 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2132 strnvisx(firmware_revision, sizeof(firmware_revision), 2133 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2134 sa.sa_inqbuf.vendor = model; 2135 sa.sa_inqbuf.product = serial_number; 2136 sa.sa_inqbuf.revision = firmware_revision; 2137 2138 /* 2139 * Determine the operating mode capabilities of the device. 2140 */ 2141 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2142 periph->periph_cap |= PERIPH_CAP_CMD16; 2143 /* XXX This is gross. */ 2144 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2145 2146 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2147 2148 if (drvp->drv_softc) 2149 ata_probe_caps(drvp); 2150 else { 2151 s = splbio(); 2152 drvp->drive_type = ATA_DRIVET_NONE; 2153 splx(s); 2154 } 2155 } else { 2156 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2157 "failed for drive %s:%d:%d\n", 2158 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2159 s = splbio(); 2160 drvp->drive_type = ATA_DRIVET_NONE; 2161 splx(s); 2162 } 2163 } 2164 #endif /* NATAPIBUS */ 2165
Indexes created Fri Sep 26 20:09:58 GMT 2025