ahcisata_core.c revision 1.88
1 /* $NetBSD: ahcisata_core.c,v 1.88 2020/12/26 10:56:25 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.88 2020/12/26 10:56:25 jmcneill Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static void ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static void ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 103 .bustype_cmd = atapi_scsipi_cmd, 104 .bustype_interpret_sense = atapi_interpret_sense, 105 .bustype_printaddr = atapi_print_addr, 106 .bustype_kill_pending = ahci_atapi_kill_pending, 107 .bustype_async_event_xfer_mode = NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 .bustype_type = SCSIPI_BUSTYPE_ATA, 117 .ata_bio = ahci_ata_bio, 118 .ata_reset_drive = ahci_reset_drive, 119 .ata_reset_channel = ahci_reset_channel, 120 .ata_exec_command = ahci_exec_command, 121 .ata_get_params = ata_get_params, 122 .ata_addref = ahci_ata_addref, 123 .ata_delref = ahci_ata_delref, 124 .ata_killpending = ahci_killpending, 125 .ata_recovery = ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADNCQ) { 280 aprint_verbose_dev(sc->sc_atac.atac_dev, 281 "ignoring broken NCQ support\n"); 282 sc->sc_ahci_cap &= ~AHCI_CAP_NCQ; 283 } 284 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 285 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 286 ahci_rev = AHCI_READ(sc, AHCI_VS); 287 snprintb(buf, sizeof(buf), "\177\020" 288 /* "f\000\005NP\0" */ 289 "b\005SXS\0" 290 "b\006EMS\0" 291 "b\007CCCS\0" 292 /* "f\010\005NCS\0" */ 293 "b\015PSC\0" 294 "b\016SSC\0" 295 "b\017PMD\0" 296 "b\020FBSS\0" 297 "b\021SPM\0" 298 "b\022SAM\0" 299 "b\023SNZO\0" 300 "f\024\003ISS\0" 301 "=\001Gen1\0" 302 "=\002Gen2\0" 303 "=\003Gen3\0" 304 "b\030SCLO\0" 305 "b\031SAL\0" 306 "b\032SALP\0" 307 "b\033SSS\0" 308 "b\034SMPS\0" 309 "b\035SSNTF\0" 310 "b\036SNCQ\0" 311 "b\037S64A\0" 312 "\0", sc->sc_ahci_cap); 313 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 314 ", %d port%s, %d slot%s, CAP %s\n", 315 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 316 sc->sc_atac.atac_nchannels, 317 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 318 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 319 320 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 321 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 322 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 323 sc->sc_atac.atac_pio_cap = 4; 324 sc->sc_atac.atac_dma_cap = 2; 325 sc->sc_atac.atac_udma_cap = 6; 326 sc->sc_atac.atac_channels = sc->sc_chanarray; 327 sc->sc_atac.atac_probe = ahci_probe_drive; 328 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 329 sc->sc_atac.atac_set_modes = ahci_setup_channel; 330 #if NATAPIBUS > 0 331 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 332 #endif 333 334 dmasize = 335 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 338 if (error) { 339 aprint_error("%s: unable to allocate command header memory" 340 ", error=%d\n", AHCINAME(sc), error); 341 return; 342 } 343 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 344 sc->sc_cmd_hdr_nseg, dmasize, 345 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 346 if (error) { 347 aprint_error("%s: unable to map command header memory" 348 ", error=%d\n", AHCINAME(sc), error); 349 return; 350 } 351 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 352 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 353 if (error) { 354 aprint_error("%s: unable to create command header map" 355 ", error=%d\n", AHCINAME(sc), error); 356 return; 357 } 358 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 359 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 360 if (error) { 361 aprint_error("%s: unable to load command header map" 362 ", error=%d\n", AHCINAME(sc), error); 363 return; 364 } 365 sc->sc_cmd_hdr = cmdhp; 366 memset(cmdhp, 0, dmasize); 367 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_hdrd, 0, dmasize, 368 BUS_DMASYNC_PREWRITE); 369 370 ahci_enable_intrs(sc); 371 372 if (sc->sc_ahci_ports == 0) { 373 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 374 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 375 DEBUG_PROBE); 376 } 377 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 378 if ((sc->sc_ahci_ports & (1U << i)) == 0) 379 continue; 380 if (port >= sc->sc_atac.atac_nchannels) { 381 aprint_error("%s: more ports than announced\n", 382 AHCINAME(sc)); 383 break; 384 } 385 386 /* Optional intr establish per active port */ 387 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 388 aprint_error("%s: intr establish hook failed\n", 389 AHCINAME(sc)); 390 break; 391 } 392 393 achp = &sc->sc_channels[i]; 394 chp = &achp->ata_channel; 395 sc->sc_chanarray[i] = chp; 396 chp->ch_channel = i; 397 chp->ch_atac = &sc->sc_atac; 398 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 399 if (chp->ch_queue == NULL) { 400 aprint_error("%s port %d: can't allocate memory for " 401 "command queue", AHCINAME(sc), i); 402 break; 403 } 404 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 405 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 406 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 407 BUS_DMA_NOWAIT); 408 if (error) { 409 aprint_error("%s: unable to allocate command table " 410 "memory, error=%d\n", AHCINAME(sc), error); 411 break; 412 } 413 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 414 achp->ahcic_cmd_tbl_nseg, dmasize, 415 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 416 if (error) { 417 aprint_error("%s: unable to map command table memory" 418 ", error=%d\n", AHCINAME(sc), error); 419 break; 420 } 421 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 422 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 423 if (error) { 424 aprint_error("%s: unable to create command table map" 425 ", error=%d\n", AHCINAME(sc), error); 426 break; 427 } 428 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 429 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 430 if (error) { 431 aprint_error("%s: unable to load command table map" 432 ", error=%d\n", AHCINAME(sc), error); 433 break; 434 } 435 memset(cmdtblp, 0, dmasize); 436 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_cmd_tbld, 0, 437 dmasize, BUS_DMASYNC_PREWRITE); 438 achp->ahcic_cmdh = (struct ahci_cmd_header *) 439 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 440 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 441 AHCI_CMDH_SIZE * port; 442 achp->ahcic_rfis = (struct ahci_r_fis *) 443 ((char *)cmdhp + 444 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 445 AHCI_RFIS_SIZE * port); 446 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 447 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 448 AHCI_RFIS_SIZE * port; 449 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 450 "rfis %p (0x%" PRIx64 ")\n", i, 451 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 452 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 453 DEBUG_PROBE); 454 455 for (j = 0; j < sc->sc_ncmds; j++) { 456 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 457 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 458 achp->ahcic_bus_cmd_tbl[j] = 459 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 460 AHCI_CMDTBL_SIZE * j; 461 achp->ahcic_cmdh[j].cmdh_cmdtba = 462 htole64(achp->ahcic_bus_cmd_tbl[j]); 463 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 464 achp->ahcic_cmd_tbl[j], 465 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 466 /* The xfer DMA map */ 467 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 468 AHCI_NPRD, 0x400000 /* 4MB */, 0, 469 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 470 &achp->ahcic_datad[j]); 471 if (error) { 472 aprint_error("%s: couldn't alloc xfer DMA map, " 473 "error=%d\n", AHCINAME(sc), error); 474 goto end; 475 } 476 } 477 ahci_setup_port(sc, i); 478 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 479 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 480 aprint_error("%s: couldn't map port %d " 481 "sata_status regs\n", AHCINAME(sc), i); 482 break; 483 } 484 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 485 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 486 aprint_error("%s: couldn't map port %d " 487 "sata_control regs\n", AHCINAME(sc), i); 488 break; 489 } 490 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 491 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 492 aprint_error("%s: couldn't map port %d " 493 "sata_error regs\n", AHCINAME(sc), i); 494 break; 495 } 496 ata_channel_attach(chp); 497 port++; 498 end: 499 continue; 500 } 501 } 502 503 void 504 ahci_childdetached(struct ahci_softc *sc, device_t child) 505 { 506 struct ahci_channel *achp; 507 struct ata_channel *chp; 508 509 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 510 achp = &sc->sc_channels[i]; 511 chp = &achp->ata_channel; 512 513 if ((sc->sc_ahci_ports & (1U << i)) == 0) 514 continue; 515 516 if (child == chp->atabus) 517 chp->atabus = NULL; 518 } 519 } 520 521 int 522 ahci_detach(struct ahci_softc *sc, int flags) 523 { 524 struct atac_softc *atac; 525 struct ahci_channel *achp; 526 struct ata_channel *chp; 527 struct scsipi_adapter *adapt; 528 int i, j, port; 529 int error; 530 531 atac = &sc->sc_atac; 532 adapt = &atac->atac_atapi_adapter._generic; 533 534 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 535 achp = &sc->sc_channels[i]; 536 chp = &achp->ata_channel; 537 538 if ((sc->sc_ahci_ports & (1U << i)) == 0) 539 continue; 540 if (port >= sc->sc_atac.atac_nchannels) { 541 aprint_error("%s: more ports than announced\n", 542 AHCINAME(sc)); 543 break; 544 } 545 546 if (chp->atabus != NULL) { 547 if ((error = config_detach(chp->atabus, flags)) != 0) 548 return error; 549 550 KASSERT(chp->atabus == NULL); 551 } 552 553 if (chp->ch_flags & ATACH_DETACHED) 554 continue; 555 556 for (j = 0; j < sc->sc_ncmds; j++) 557 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 558 559 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 560 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 561 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 562 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 563 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 564 achp->ahcic_cmd_tbl_nseg); 565 566 ata_channel_detach(chp); 567 port++; 568 } 569 570 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 571 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 572 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 573 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 574 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 575 576 if (adapt->adapt_refcnt != 0) 577 return EBUSY; 578 579 return 0; 580 } 581 582 void 583 ahci_resume(struct ahci_softc *sc) 584 { 585 ahci_reset(sc); 586 ahci_setup_ports(sc); 587 ahci_reprobe_drives(sc); 588 ahci_enable_intrs(sc); 589 } 590 591 int 592 ahci_intr(void *v) 593 { 594 struct ahci_softc *sc = v; 595 uint32_t is; 596 int i, r = 0; 597 598 while ((is = AHCI_READ(sc, AHCI_IS))) { 599 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 600 DEBUG_INTR); 601 r = 1; 602 AHCI_WRITE(sc, AHCI_IS, is); 603 for (i = 0; i < AHCI_MAX_PORTS; i++) 604 if (is & (1U << i)) 605 ahci_intr_port(&sc->sc_channels[i]); 606 } 607 608 return r; 609 } 610 611 int 612 ahci_intr_port(void *v) 613 { 614 struct ahci_channel *achp = v; 615 struct ata_channel *chp = &achp->ata_channel; 616 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 617 uint32_t is, tfd, sact; 618 struct ata_xfer *xfer; 619 int slot = -1; 620 bool recover = false; 621 uint32_t aslots; 622 623 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 624 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 625 626 AHCIDEBUG_PRINT(( 627 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 628 AHCINAME(sc), 629 chp->ch_channel, is, 630 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 631 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 632 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 633 DEBUG_INTR); 634 635 if ((chp->ch_flags & ATACH_NCQ) == 0) { 636 /* Non-NCQ operation */ 637 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 638 } else { 639 /* NCQ operation */ 640 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 641 } 642 643 /* Handle errors */ 644 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 645 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 646 /* Fatal errors */ 647 if (is & AHCI_P_IX_TFES) { 648 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 649 650 if ((chp->ch_flags & ATACH_NCQ) == 0) { 651 /* Slot valid only for Non-NCQ operation */ 652 slot = (AHCI_READ(sc, 653 AHCI_P_CMD(chp->ch_channel)) 654 & AHCI_P_CMD_CCS_MASK) 655 >> AHCI_P_CMD_CCS_SHIFT; 656 } 657 658 AHCIDEBUG_PRINT(( 659 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 660 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 661 DEBUG_INTR); 662 } else { 663 /* mark an error, and set BSY */ 664 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 665 WDCS_ERR | WDCS_BSY; 666 } 667 668 if (is & AHCI_P_IX_IFS) { 669 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 670 AHCINAME(sc), chp->ch_channel, 671 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 672 DEBUG_INTR); 673 } 674 675 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 676 recover = true; 677 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 678 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 679 680 /* D2H Register FIS or Set Device Bits */ 681 if ((tfd & WDCS_ERR) != 0) { 682 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 683 recover = true; 684 685 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 686 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 687 688 } 689 } else { 690 tfd = 0; 691 } 692 693 if (__predict_false(recover)) 694 ata_channel_freeze(chp); 695 696 aslots = ata_queue_active(chp); 697 698 if (slot >= 0) { 699 if ((aslots & __BIT(slot)) != 0 && 700 (sact & __BIT(slot)) == 0) { 701 xfer = ata_queue_hwslot_to_xfer(chp, slot); 702 xfer->ops->c_intr(chp, xfer, tfd); 703 } 704 } else { 705 /* 706 * For NCQ, HBA halts processing when error is notified, 707 * and any further D2H FISes are ignored until the error 708 * condition is cleared. Hence if a command is inactive, 709 * it means it actually already finished successfully. 710 * Note: active slots can change as c_intr() callback 711 * can activate another command(s), so must only process 712 * commands active before we start processing. 713 */ 714 715 for (slot=0; slot < sc->sc_ncmds; slot++) { 716 if ((aslots & __BIT(slot)) != 0 && 717 (sact & __BIT(slot)) == 0) { 718 xfer = ata_queue_hwslot_to_xfer(chp, slot); 719 xfer->ops->c_intr(chp, xfer, tfd); 720 } 721 } 722 } 723 724 if (__predict_false(recover)) { 725 ata_channel_lock(chp); 726 ata_channel_thaw_locked(chp); 727 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 728 ata_channel_unlock(chp); 729 } 730 731 return 1; 732 } 733 734 static void 735 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 736 { 737 struct ata_channel *chp = drvp->chnl_softc; 738 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 739 uint8_t c_slot; 740 741 ata_channel_lock_owned(chp); 742 743 /* get a slot for running the command on */ 744 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 745 panic("%s: %s: failed to get xfer for reset, port %d\n", 746 device_xname(sc->sc_atac.atac_dev), 747 __func__, chp->ch_channel); 748 /* NOTREACHED */ 749 } 750 751 AHCI_WRITE(sc, AHCI_GHC, 752 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 753 ahci_channel_stop(sc, chp, flags); 754 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 755 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 756 757 ata_queue_free_slot(chp, c_slot); 758 } 759 760 /* return error code from ata_bio */ 761 static int 762 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 763 { 764 struct ahci_channel *achp = (struct ahci_channel *)chp; 765 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 766 int i; 767 uint32_t is; 768 769 /* 770 * Base timeout is specified in ms. Delay for 10ms 771 * on each round. 772 */ 773 timeout = timeout / 10; 774 775 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 776 AHCI_CMDH_SYNC(sc, achp, slot, 777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 778 /* start command */ 779 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 780 for (i = 0; i < timeout; i++) { 781 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 782 0) 783 return 0; 784 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 785 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 786 AHCI_P_IX_IFS | 787 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 788 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 789 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 790 /* 791 * we got the D2H FIS anyway, 792 * assume sig is valid. 793 * channel is restarted later 794 */ 795 return ERROR; 796 } 797 aprint_debug("%s port %d: error 0x%x sending FIS\n", 798 AHCINAME(sc), chp->ch_channel, is); 799 return ERR_DF; 800 } 801 ata_delay(chp, 10, "ahcifis", flags); 802 } 803 804 aprint_debug("%s port %d: timeout sending FIS\n", 805 AHCINAME(sc), chp->ch_channel); 806 return TIMEOUT; 807 } 808 809 static int 810 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 811 uint32_t *sigp, uint8_t c_slot) 812 { 813 struct ahci_channel *achp = (struct ahci_channel *)chp; 814 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 815 struct ahci_cmd_tbl *cmd_tbl; 816 struct ahci_cmd_header *cmd_h; 817 int i, error = 0; 818 uint32_t sig, cmd; 819 int noclo_retry = 0, retry; 820 821 ata_channel_lock_owned(chp); 822 823 again: 824 /* clear port interrupt register */ 825 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 826 /* clear SErrors and start operations */ 827 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 828 /* 829 * issue a command list override to clear BSY. 830 * This is needed if there's a PMP with no drive 831 * on port 0 832 */ 833 ahci_channel_start(sc, chp, flags, 1); 834 } else { 835 /* Can't handle command still running without CLO */ 836 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 837 if ((cmd & AHCI_P_CMD_CR) != 0) { 838 ahci_channel_stop(sc, chp, flags); 839 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 840 if ((cmd & AHCI_P_CMD_CR) != 0) { 841 aprint_error("%s port %d: DMA engine busy " 842 "for drive %d\n", AHCINAME(sc), 843 chp->ch_channel, drive); 844 error = EBUSY; 845 goto end; 846 } 847 } 848 849 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 850 851 ahci_channel_start(sc, chp, flags, 0); 852 } 853 if (drive > 0) { 854 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 855 } 856 857 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 858 goto skip_reset; 859 860 /* polled command, assume interrupts are disabled */ 861 862 cmd_h = &achp->ahcic_cmdh[c_slot]; 863 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 864 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 865 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 866 cmd_h->cmdh_prdtl = 0; 867 cmd_h->cmdh_prdbc = 0; 868 memset(cmd_tbl->cmdt_cfis, 0, 64); 869 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 870 cmd_tbl->cmdt_cfis[rhd_c] = drive; 871 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 872 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 873 case ERR_DF: 874 case TIMEOUT: 875 /* 876 * without CLO we can't make sure a software reset will 877 * success, as the drive may still have BSY or DRQ set. 878 * in this case, reset the whole channel and retry the 879 * drive reset. The channel reset should clear BSY and DRQ 880 */ 881 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 882 noclo_retry++; 883 ahci_reset_channel(chp, flags); 884 goto again; 885 } 886 aprint_error("%s port %d: setting WDCTL_RST failed " 887 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 888 error = EBUSY; 889 goto end; 890 default: 891 break; 892 } 893 894 /* 895 * SATA specification has toggle period for SRST bit of 5 usec. Some 896 * controllers fail to process the SRST clear operation unless 897 * we wait for at least this period between the set and clear commands. 898 */ 899 ata_delay(chp, 10, "ahcirstw", flags); 900 901 /* 902 * Try to clear WDCTL_RST a few times before giving up. 903 */ 904 for (error = EBUSY, retry = 0; error != 0 && retry < 5; retry++) { 905 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 906 (drive << AHCI_CMDH_F_PMP_SHIFT)); 907 cmd_h->cmdh_prdbc = 0; 908 memset(cmd_tbl->cmdt_cfis, 0, 64); 909 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 910 cmd_tbl->cmdt_cfis[rhd_c] = drive; 911 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 912 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 913 case ERR_DF: 914 case TIMEOUT: 915 error = EBUSY; 916 break; 917 default: 918 error = 0; 919 break; 920 } 921 if (error == 0) { 922 break; 923 } 924 } 925 if (error == EBUSY) { 926 aprint_error("%s port %d: clearing WDCTL_RST failed " 927 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 928 goto end; 929 } 930 931 skip_reset: 932 /* 933 * wait 31s for BSY to clear 934 * This should not be needed, but some controllers clear the 935 * command slot before receiving the D2H FIS ... 936 */ 937 for (i = 0; i < AHCI_RST_WAIT; i++) { 938 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 939 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 940 break; 941 ata_delay(chp, 10, "ahcid2h", flags); 942 } 943 if (i == AHCI_RST_WAIT) { 944 aprint_error("%s: BSY never cleared, TD 0x%x\n", 945 AHCINAME(sc), sig); 946 goto end; 947 } 948 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 949 DEBUG_PROBE); 950 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 951 if (sigp) 952 *sigp = sig; 953 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 954 AHCINAME(sc), chp->ch_channel, sig, 955 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 956 end: 957 ahci_channel_stop(sc, chp, flags); 958 ata_delay(chp, 500, "ahcirst", flags); 959 /* clear port interrupt register */ 960 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 961 ahci_channel_start(sc, chp, flags, 962 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 963 return error; 964 } 965 966 static void 967 ahci_reset_channel(struct ata_channel *chp, int flags) 968 { 969 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 970 struct ahci_channel *achp = (struct ahci_channel *)chp; 971 int i, tfd; 972 973 ata_channel_lock_owned(chp); 974 975 ahci_channel_stop(sc, chp, flags); 976 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 977 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 978 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 979 /* XXX and then ? */ 980 } 981 ata_kill_active(chp, KILL_RESET, flags); 982 ata_delay(chp, 500, "ahcirst", flags); 983 /* clear port interrupt register */ 984 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 985 /* clear SErrors and start operations */ 986 ahci_channel_start(sc, chp, flags, 987 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 988 /* wait 31s for BSY to clear */ 989 for (i = 0; i < AHCI_RST_WAIT; i++) { 990 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 991 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 992 break; 993 ata_delay(chp, 10, "ahcid2h", flags); 994 } 995 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 996 aprint_error("%s: BSY never cleared, TD 0x%x\n", 997 AHCINAME(sc), tfd); 998 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 999 DEBUG_PROBE); 1000 /* clear port interrupt register */ 1001 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1002 1003 return; 1004 } 1005 1006 static int 1007 ahci_ata_addref(struct ata_drive_datas *drvp) 1008 { 1009 return 0; 1010 } 1011 1012 static void 1013 ahci_ata_delref(struct ata_drive_datas *drvp) 1014 { 1015 return; 1016 } 1017 1018 static void 1019 ahci_killpending(struct ata_drive_datas *drvp) 1020 { 1021 return; 1022 } 1023 1024 static void 1025 ahci_probe_drive(struct ata_channel *chp) 1026 { 1027 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1028 struct ahci_channel *achp = (struct ahci_channel *)chp; 1029 uint32_t sig; 1030 uint8_t c_slot; 1031 int error; 1032 1033 ata_channel_lock(chp); 1034 1035 /* get a slot for running the command on */ 1036 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1037 aprint_error_dev(sc->sc_atac.atac_dev, 1038 "%s: failed to get xfer port %d\n", 1039 __func__, chp->ch_channel); 1040 ata_channel_unlock(chp); 1041 return; 1042 } 1043 1044 /* bring interface up, accept FISs, power up and spin up device */ 1045 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1046 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1047 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1048 /* reset the PHY and bring online */ 1049 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1050 achp->ahcic_sstatus, AT_WAIT)) { 1051 case SStatus_DET_DEV: 1052 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1053 1054 /* Initial value, used in case the soft reset fails */ 1055 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1056 1057 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1058 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1059 &sig, c_slot); 1060 1061 /* If probe for PMP failed, just fallback to drive 0 */ 1062 if (error) { 1063 aprint_error("%s port %d: drive %d reset " 1064 "failed, disabling PMP\n", 1065 AHCINAME(sc), chp->ch_channel, 1066 PMP_PORT_CTL); 1067 1068 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1069 ahci_reset_channel(chp, AT_WAIT); 1070 } 1071 } else { 1072 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1073 } 1074 sata_interpret_sig(chp, 0, sig); 1075 /* if we have a PMP attached, inform the controller */ 1076 if (chp->ch_ndrives > PMP_PORT_CTL && 1077 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1078 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1079 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1080 AHCI_P_CMD_PMA); 1081 } 1082 /* clear port interrupt register */ 1083 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1084 1085 /* and enable interrupts */ 1086 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1087 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1088 AHCI_P_IX_IFS | 1089 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1090 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1091 /* wait 500ms before actually starting operations */ 1092 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1093 break; 1094 1095 default: 1096 break; 1097 } 1098 1099 ata_queue_free_slot(chp, c_slot); 1100 1101 ata_channel_unlock(chp); 1102 } 1103 1104 static void 1105 ahci_setup_channel(struct ata_channel *chp) 1106 { 1107 return; 1108 } 1109 1110 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1111 .c_start = ahci_cmd_start, 1112 .c_poll = ahci_cmd_poll, 1113 .c_abort = ahci_cmd_abort, 1114 .c_intr = ahci_cmd_complete, 1115 .c_kill_xfer = ahci_cmd_kill_xfer, 1116 }; 1117 1118 static void 1119 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1120 { 1121 struct ata_channel *chp = drvp->chnl_softc; 1122 struct ata_command *ata_c = &xfer->c_ata_c; 1123 1124 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1125 chp->ch_channel, 1126 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1127 DEBUG_XFERS); 1128 if (ata_c->flags & AT_POLL) 1129 xfer->c_flags |= C_POLL; 1130 if (ata_c->flags & AT_WAIT) 1131 xfer->c_flags |= C_WAIT; 1132 xfer->c_drive = drvp->drive; 1133 xfer->c_databuf = ata_c->data; 1134 xfer->c_bcount = ata_c->bcount; 1135 xfer->ops = &ahci_cmd_xfer_ops; 1136 1137 ata_exec_xfer(chp, xfer); 1138 } 1139 1140 static int 1141 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1142 { 1143 struct ahci_softc *sc = AHCI_CH2SC(chp); 1144 struct ahci_channel *achp = (struct ahci_channel *)chp; 1145 struct ata_command *ata_c = &xfer->c_ata_c; 1146 int slot = xfer->c_slot; 1147 struct ahci_cmd_tbl *cmd_tbl; 1148 struct ahci_cmd_header *cmd_h; 1149 1150 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1151 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1152 ata_c->timeout, slot), 1153 DEBUG_XFERS); 1154 1155 ata_channel_lock_owned(chp); 1156 1157 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1158 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1159 cmd_tbl), DEBUG_XFERS); 1160 1161 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1162 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1163 1164 cmd_h = &achp->ahcic_cmdh[slot]; 1165 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1166 chp->ch_channel, cmd_h), DEBUG_XFERS); 1167 if (ahci_dma_setup(chp, slot, 1168 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1169 ata_c->data : NULL, 1170 ata_c->bcount, 1171 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1172 ata_c->flags |= AT_DF; 1173 return ATASTART_ABORT; 1174 } 1175 cmd_h->cmdh_flags = htole16( 1176 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1177 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1178 cmd_h->cmdh_prdbc = 0; 1179 AHCI_CMDH_SYNC(sc, achp, slot, 1180 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1181 1182 if (ata_c->flags & AT_POLL) { 1183 /* polled command, disable interrupts */ 1184 AHCI_WRITE(sc, AHCI_GHC, 1185 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1186 } 1187 /* start command */ 1188 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1189 1190 if ((ata_c->flags & AT_POLL) == 0) { 1191 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1192 ata_timeout, chp); 1193 return ATASTART_STARTED; 1194 } else 1195 return ATASTART_POLL; 1196 } 1197 1198 static void 1199 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1200 { 1201 struct ahci_softc *sc = AHCI_CH2SC(chp); 1202 struct ahci_channel *achp = (struct ahci_channel *)chp; 1203 1204 ata_channel_lock(chp); 1205 1206 /* 1207 * Polled command. 1208 */ 1209 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1210 if (xfer->c_ata_c.flags & AT_DONE) 1211 break; 1212 ata_channel_unlock(chp); 1213 ahci_intr_port(achp); 1214 ata_channel_lock(chp); 1215 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1216 } 1217 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1218 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1219 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1220 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1221 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1222 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1223 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1224 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1225 DEBUG_XFERS); 1226 1227 ata_channel_unlock(chp); 1228 1229 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1230 xfer->c_ata_c.flags |= AT_TIMEOU; 1231 xfer->ops->c_intr(chp, xfer, 0); 1232 } 1233 /* reenable interrupts */ 1234 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1235 } 1236 1237 static void 1238 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1239 { 1240 ahci_cmd_complete(chp, xfer, 0); 1241 } 1242 1243 static void 1244 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1245 { 1246 struct ata_command *ata_c = &xfer->c_ata_c; 1247 bool deactivate = true; 1248 1249 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1250 DEBUG_FUNCS); 1251 1252 switch (reason) { 1253 case KILL_GONE_INACTIVE: 1254 deactivate = false; 1255 /* FALLTHROUGH */ 1256 case KILL_GONE: 1257 ata_c->flags |= AT_GONE; 1258 break; 1259 case KILL_RESET: 1260 ata_c->flags |= AT_RESET; 1261 break; 1262 case KILL_REQUEUE: 1263 panic("%s: not supposed to be requeued\n", __func__); 1264 break; 1265 default: 1266 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1267 panic("ahci_cmd_kill_xfer"); 1268 } 1269 1270 ahci_cmd_done_end(chp, xfer); 1271 1272 if (deactivate) 1273 ata_deactivate_xfer(chp, xfer); 1274 } 1275 1276 static int 1277 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1278 { 1279 struct ata_command *ata_c = &xfer->c_ata_c; 1280 struct ahci_channel *achp = (struct ahci_channel *)chp; 1281 struct ahci_softc *sc = AHCI_CH2SC(chp); 1282 1283 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1284 chp->ch_channel, 1285 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1286 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1287 DEBUG_FUNCS); 1288 1289 if (ata_waitdrain_xfer_check(chp, xfer)) 1290 return 0; 1291 1292 if (xfer->c_flags & C_TIMEOU) { 1293 ata_c->flags |= AT_TIMEOU; 1294 } 1295 1296 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1297 ata_c->flags |= AT_TIMEOU; 1298 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1299 ata_c->r_error = AHCI_TFD_ERR(tfd); 1300 ata_c->flags |= AT_ERROR; 1301 } 1302 1303 if (ata_c->flags & AT_READREG) { 1304 AHCI_RFIS_SYNC(sc, achp, BUS_DMASYNC_POSTREAD); 1305 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1306 } 1307 1308 ahci_cmd_done(chp, xfer); 1309 1310 ata_deactivate_xfer(chp, xfer); 1311 1312 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1313 atastart(chp); 1314 1315 return 0; 1316 } 1317 1318 static void 1319 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1320 { 1321 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1322 struct ahci_channel *achp = (struct ahci_channel *)chp; 1323 struct ata_command *ata_c = &xfer->c_ata_c; 1324 uint16_t *idwordbuf; 1325 int i; 1326 1327 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1328 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1329 1330 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1331 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1332 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1333 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1334 BUS_DMASYNC_POSTWRITE); 1335 bus_dmamap_unload(sc->sc_dmat, map); 1336 } 1337 1338 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1339 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1340 1341 /* ata(4) expects IDENTIFY data to be in host endianess */ 1342 if (ata_c->r_command == WDCC_IDENTIFY || 1343 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1344 idwordbuf = xfer->c_databuf; 1345 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1346 idwordbuf[i] = le16toh(idwordbuf[i]); 1347 } 1348 } 1349 1350 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1351 ata_c->flags |= AT_XFDONE; 1352 1353 ahci_cmd_done_end(chp, xfer); 1354 } 1355 1356 static void 1357 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1358 { 1359 struct ata_command *ata_c = &xfer->c_ata_c; 1360 1361 ata_c->flags |= AT_DONE; 1362 } 1363 1364 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1365 .c_start = ahci_bio_start, 1366 .c_poll = ahci_bio_poll, 1367 .c_abort = ahci_bio_abort, 1368 .c_intr = ahci_bio_complete, 1369 .c_kill_xfer = ahci_bio_kill_xfer, 1370 }; 1371 1372 static void 1373 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1374 { 1375 struct ata_channel *chp = drvp->chnl_softc; 1376 struct ata_bio *ata_bio = &xfer->c_bio; 1377 1378 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1379 chp->ch_channel, 1380 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1381 DEBUG_XFERS); 1382 if (ata_bio->flags & ATA_POLL) 1383 xfer->c_flags |= C_POLL; 1384 xfer->c_drive = drvp->drive; 1385 xfer->c_databuf = ata_bio->databuf; 1386 xfer->c_bcount = ata_bio->bcount; 1387 xfer->ops = &ahci_bio_xfer_ops; 1388 ata_exec_xfer(chp, xfer); 1389 } 1390 1391 static int 1392 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1393 { 1394 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1395 struct ahci_channel *achp = (struct ahci_channel *)chp; 1396 struct ata_bio *ata_bio = &xfer->c_bio; 1397 struct ahci_cmd_tbl *cmd_tbl; 1398 struct ahci_cmd_header *cmd_h; 1399 1400 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1401 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1402 1403 ata_channel_lock_owned(chp); 1404 1405 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1406 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1407 cmd_tbl), DEBUG_XFERS); 1408 1409 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1410 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1411 1412 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1413 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1414 chp->ch_channel, cmd_h), DEBUG_XFERS); 1415 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1416 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1417 ata_bio->error = ERR_DMA; 1418 ata_bio->r_error = 0; 1419 return ATASTART_ABORT; 1420 } 1421 cmd_h->cmdh_flags = htole16( 1422 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1423 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1424 cmd_h->cmdh_prdbc = 0; 1425 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1426 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1427 1428 if (xfer->c_flags & C_POLL) { 1429 /* polled command, disable interrupts */ 1430 AHCI_WRITE(sc, AHCI_GHC, 1431 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1432 } 1433 if (xfer->c_flags & C_NCQ) 1434 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1435 /* start command */ 1436 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1437 1438 if ((xfer->c_flags & C_POLL) == 0) { 1439 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1440 ata_timeout, chp); 1441 return ATASTART_STARTED; 1442 } else 1443 return ATASTART_POLL; 1444 } 1445 1446 static void 1447 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1448 { 1449 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1450 struct ahci_channel *achp = (struct ahci_channel *)chp; 1451 1452 /* 1453 * Polled command. 1454 */ 1455 for (int i = 0; i < ATA_DELAY * 10; i++) { 1456 if (xfer->c_bio.flags & ATA_ITSDONE) 1457 break; 1458 ahci_intr_port(achp); 1459 delay(100); 1460 } 1461 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1462 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1463 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1464 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1465 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1466 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1467 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1468 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1469 DEBUG_XFERS); 1470 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1471 xfer->c_bio.error = TIMEOUT; 1472 xfer->ops->c_intr(chp, xfer, 0); 1473 } 1474 /* reenable interrupts */ 1475 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1476 } 1477 1478 static void 1479 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1480 { 1481 ahci_bio_complete(chp, xfer, 0); 1482 } 1483 1484 static void 1485 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1486 { 1487 int drive = xfer->c_drive; 1488 struct ata_bio *ata_bio = &xfer->c_bio; 1489 bool deactivate = true; 1490 1491 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1492 DEBUG_FUNCS); 1493 1494 ata_bio->flags |= ATA_ITSDONE; 1495 switch (reason) { 1496 case KILL_GONE_INACTIVE: 1497 deactivate = false; 1498 /* FALLTHROUGH */ 1499 case KILL_GONE: 1500 ata_bio->error = ERR_NODEV; 1501 break; 1502 case KILL_RESET: 1503 ata_bio->error = ERR_RESET; 1504 break; 1505 case KILL_REQUEUE: 1506 ata_bio->error = REQUEUE; 1507 break; 1508 default: 1509 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1510 panic("ahci_bio_kill_xfer"); 1511 } 1512 ata_bio->r_error = WDCE_ABRT; 1513 1514 if (deactivate) 1515 ata_deactivate_xfer(chp, xfer); 1516 1517 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1518 } 1519 1520 static int 1521 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1522 { 1523 struct ata_bio *ata_bio = &xfer->c_bio; 1524 int drive = xfer->c_drive; 1525 struct ahci_channel *achp = (struct ahci_channel *)chp; 1526 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1527 1528 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1529 DEBUG_FUNCS); 1530 1531 if (ata_waitdrain_xfer_check(chp, xfer)) 1532 return 0; 1533 1534 if (xfer->c_flags & C_TIMEOU) { 1535 ata_bio->error = TIMEOUT; 1536 } 1537 1538 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1539 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1540 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1541 BUS_DMASYNC_POSTWRITE); 1542 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1543 1544 ata_bio->flags |= ATA_ITSDONE; 1545 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1546 ata_bio->error = ERR_DF; 1547 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1548 ata_bio->error = ERROR; 1549 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1550 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1551 ata_bio->flags |= ATA_CORR; 1552 1553 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1554 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1555 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1556 ata_bio->bcount), DEBUG_XFERS); 1557 /* 1558 * If it was a write, complete data buffer may have been transferred 1559 * before error detection; in this case don't use cmdh_prdbc 1560 * as it won't reflect what was written to media. Assume nothing 1561 * was transferred and leave bcount as-is. 1562 * For queued commands, PRD Byte Count should not be used, and is 1563 * not required to be valid; in that case underflow is always illegal. 1564 */ 1565 if ((xfer->c_flags & C_NCQ) != 0) { 1566 if (ata_bio->error == NOERROR) 1567 ata_bio->bcount = 0; 1568 } else { 1569 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1570 ata_bio->bcount -= 1571 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1572 } 1573 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1574 1575 ata_deactivate_xfer(chp, xfer); 1576 1577 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1578 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1579 atastart(chp); 1580 return 0; 1581 } 1582 1583 static void 1584 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1585 { 1586 int i; 1587 /* stop channel */ 1588 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1589 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1590 /* wait 1s for channel to stop */ 1591 for (i = 0; i <100; i++) { 1592 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1593 == 0) 1594 break; 1595 ata_delay(chp, 10, "ahcistop", flags); 1596 } 1597 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1598 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1599 /* XXX controller reset ? */ 1600 return; 1601 } 1602 1603 if (sc->sc_channel_stop) 1604 sc->sc_channel_stop(sc, chp); 1605 } 1606 1607 static void 1608 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1609 int flags, int clo) 1610 { 1611 int i; 1612 uint32_t p_cmd; 1613 /* clear error */ 1614 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1615 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1616 1617 if (clo) { 1618 /* issue command list override */ 1619 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1620 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1621 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1622 /* wait 1s for AHCI_CAP_CLO to clear */ 1623 for (i = 0; i <100; i++) { 1624 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1625 AHCI_P_CMD_CLO) == 0) 1626 break; 1627 ata_delay(chp, 10, "ahciclo", flags); 1628 } 1629 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1630 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1631 /* XXX controller reset ? */ 1632 return; 1633 } 1634 } 1635 1636 if (sc->sc_channel_start) 1637 sc->sc_channel_start(sc, chp); 1638 1639 /* and start controller */ 1640 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1641 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1642 if (chp->ch_ndrives > PMP_PORT_CTL && 1643 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1644 p_cmd |= AHCI_P_CMD_PMA; 1645 } 1646 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1647 } 1648 1649 /* Recover channel after command failure */ 1650 static void 1651 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1652 { 1653 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1654 int drive = ATACH_NODRIVE; 1655 bool reset = false; 1656 1657 ata_channel_lock_owned(chp); 1658 1659 /* 1660 * Read FBS to get the drive which caused the error, if PM is in use. 1661 * According to AHCI 1.3 spec, this register is available regardless 1662 * if FIS-based switching (FBSS) feature is supported, or disabled. 1663 * If FIS-based switching is not in use, it merely maintains single 1664 * pair of DRQ/BSY state, but it is enough since in that case we 1665 * never issue commands for more than one device at the time anyway. 1666 * XXX untested 1667 */ 1668 if (chp->ch_ndrives > PMP_PORT_CTL) { 1669 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1670 if (fbs & AHCI_P_FBS_SDE) { 1671 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1672 1673 /* 1674 * Tell HBA to reset PM port X (value in DWE) state, 1675 * and resume processing commands for other ports. 1676 */ 1677 fbs |= AHCI_P_FBS_DEC; 1678 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1679 for (int i = 0; i < 1000; i++) { 1680 fbs = AHCI_READ(sc, 1681 AHCI_P_FBS(chp->ch_channel)); 1682 if ((fbs & AHCI_P_FBS_DEC) == 0) 1683 break; 1684 DELAY(1000); 1685 } 1686 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1687 /* follow non-device specific recovery */ 1688 drive = ATACH_NODRIVE; 1689 reset = true; 1690 } 1691 } else { 1692 /* not device specific, reset channel */ 1693 drive = ATACH_NODRIVE; 1694 reset = true; 1695 } 1696 } else 1697 drive = 0; 1698 1699 /* 1700 * If BSY or DRQ bits are set, must execute COMRESET to return 1701 * device to idle state. If drive is idle, it's enough to just 1702 * reset CMD.ST, it's not necessary to do software reset. 1703 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1704 * to unblock device processing if COMRESET was not done. 1705 */ 1706 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1707 ahci_reset_channel(chp, flags); 1708 goto out; 1709 } 1710 1711 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1712 ahci_channel_stop(sc, chp, flags); 1713 ahci_channel_start(sc, chp, flags, 1714 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1715 1716 ata_recovery_resume(chp, drive, tfd, flags); 1717 1718 out: 1719 /* Drive unblocked, back to normal operation */ 1720 return; 1721 } 1722 1723 static int 1724 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1725 size_t count, int op) 1726 { 1727 int error, seg; 1728 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1729 struct ahci_channel *achp = (struct ahci_channel *)chp; 1730 struct ahci_cmd_tbl *cmd_tbl; 1731 struct ahci_cmd_header *cmd_h; 1732 1733 cmd_h = &achp->ahcic_cmdh[slot]; 1734 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1735 1736 if (data == NULL) { 1737 cmd_h->cmdh_prdtl = 0; 1738 goto end; 1739 } 1740 1741 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1742 data, count, NULL, 1743 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1744 if (error) { 1745 printf("%s port %d: failed to load xfer: %d\n", 1746 AHCINAME(sc), chp->ch_channel, error); 1747 return error; 1748 } 1749 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1750 achp->ahcic_datad[slot]->dm_mapsize, 1751 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1752 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1753 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1754 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1755 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1756 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1757 } 1758 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1759 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1760 end: 1761 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1762 return 0; 1763 } 1764 1765 #if NATAPIBUS > 0 1766 static void 1767 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1768 { 1769 struct ata_channel *chp = ata_sc->sc_chan; 1770 struct atac_softc *atac = chp->ch_atac; 1771 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1772 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1773 /* 1774 * Fill in the scsipi_adapter. 1775 */ 1776 adapt->adapt_dev = atac->atac_dev; 1777 adapt->adapt_nchannels = atac->atac_nchannels; 1778 adapt->adapt_request = ahci_atapi_scsipi_request; 1779 adapt->adapt_minphys = ahci_atapi_minphys; 1780 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1781 1782 /* 1783 * Fill in the scsipi_channel. 1784 */ 1785 memset(chan, 0, sizeof(*chan)); 1786 chan->chan_adapter = adapt; 1787 chan->chan_bustype = &ahci_atapi_bustype; 1788 chan->chan_channel = chp->ch_channel; 1789 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1790 chan->chan_openings = 1; 1791 chan->chan_max_periph = 1; 1792 chan->chan_ntargets = 1; 1793 chan->chan_nluns = 1; 1794 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1795 atapiprint); 1796 } 1797 1798 static void 1799 ahci_atapi_minphys(struct buf *bp) 1800 { 1801 if (bp->b_bcount > MAXPHYS) 1802 bp->b_bcount = MAXPHYS; 1803 minphys(bp); 1804 } 1805 1806 /* 1807 * Kill off all pending xfers for a periph. 1808 * 1809 * Must be called at splbio(). 1810 */ 1811 static void 1812 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1813 { 1814 struct atac_softc *atac = 1815 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1816 struct ata_channel *chp = 1817 atac->atac_channels[periph->periph_channel->chan_channel]; 1818 1819 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1820 } 1821 1822 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1823 .c_start = ahci_atapi_start, 1824 .c_poll = ahci_atapi_poll, 1825 .c_abort = ahci_atapi_abort, 1826 .c_intr = ahci_atapi_complete, 1827 .c_kill_xfer = ahci_atapi_kill_xfer, 1828 }; 1829 1830 static void 1831 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1832 scsipi_adapter_req_t req, void *arg) 1833 { 1834 struct scsipi_adapter *adapt = chan->chan_adapter; 1835 struct scsipi_periph *periph; 1836 struct scsipi_xfer *sc_xfer; 1837 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1838 struct atac_softc *atac = &sc->sc_atac; 1839 struct ata_xfer *xfer; 1840 int channel = chan->chan_channel; 1841 int drive, s; 1842 1843 switch (req) { 1844 case ADAPTER_REQ_RUN_XFER: 1845 sc_xfer = arg; 1846 periph = sc_xfer->xs_periph; 1847 drive = periph->periph_target; 1848 if (!device_is_active(atac->atac_dev)) { 1849 sc_xfer->error = XS_DRIVER_STUFFUP; 1850 scsipi_done(sc_xfer); 1851 return; 1852 } 1853 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1854 if (xfer == NULL) { 1855 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1856 scsipi_done(sc_xfer); 1857 return; 1858 } 1859 1860 if (sc_xfer->xs_control & XS_CTL_POLL) 1861 xfer->c_flags |= C_POLL; 1862 xfer->c_drive = drive; 1863 xfer->c_flags |= C_ATAPI; 1864 xfer->c_databuf = sc_xfer->data; 1865 xfer->c_bcount = sc_xfer->datalen; 1866 xfer->ops = &ahci_atapi_xfer_ops; 1867 xfer->c_scsipi = sc_xfer; 1868 xfer->c_atapi.c_dscpoll = 0; 1869 s = splbio(); 1870 ata_exec_xfer(atac->atac_channels[channel], xfer); 1871 #ifdef DIAGNOSTIC 1872 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1873 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1874 panic("ahci_atapi_scsipi_request: polled command " 1875 "not done"); 1876 #endif 1877 splx(s); 1878 return; 1879 default: 1880 /* Not supported, nothing to do. */ 1881 ; 1882 } 1883 } 1884 1885 static int 1886 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1887 { 1888 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1889 struct ahci_channel *achp = (struct ahci_channel *)chp; 1890 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1891 struct ahci_cmd_tbl *cmd_tbl; 1892 struct ahci_cmd_header *cmd_h; 1893 1894 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1895 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1896 1897 ata_channel_lock_owned(chp); 1898 1899 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1900 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1901 cmd_tbl), DEBUG_XFERS); 1902 1903 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1904 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1905 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1906 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1907 1908 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1909 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1910 chp->ch_channel, cmd_h), DEBUG_XFERS); 1911 if (ahci_dma_setup(chp, xfer->c_slot, 1912 sc_xfer->datalen ? sc_xfer->data : NULL, 1913 sc_xfer->datalen, 1914 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1915 BUS_DMA_READ : BUS_DMA_WRITE)) { 1916 sc_xfer->error = XS_DRIVER_STUFFUP; 1917 return ATASTART_ABORT; 1918 } 1919 cmd_h->cmdh_flags = htole16( 1920 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1921 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1922 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1923 cmd_h->cmdh_prdbc = 0; 1924 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1926 1927 if (xfer->c_flags & C_POLL) { 1928 /* polled command, disable interrupts */ 1929 AHCI_WRITE(sc, AHCI_GHC, 1930 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1931 } 1932 /* start command */ 1933 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1934 1935 if ((xfer->c_flags & C_POLL) == 0) { 1936 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1937 ata_timeout, chp); 1938 return ATASTART_STARTED; 1939 } else 1940 return ATASTART_POLL; 1941 } 1942 1943 static void 1944 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1945 { 1946 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1947 struct ahci_channel *achp = (struct ahci_channel *)chp; 1948 1949 /* 1950 * Polled command. 1951 */ 1952 for (int i = 0; i < ATA_DELAY / 10; i++) { 1953 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1954 break; 1955 ahci_intr_port(achp); 1956 delay(10000); 1957 } 1958 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1959 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1960 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1961 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1962 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1963 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1964 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1965 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1966 DEBUG_XFERS); 1967 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1968 xfer->c_scsipi->error = XS_TIMEOUT; 1969 xfer->ops->c_intr(chp, xfer, 0); 1970 } 1971 /* reenable interrupts */ 1972 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1973 } 1974 1975 static void 1976 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1977 { 1978 ahci_atapi_complete(chp, xfer, 0); 1979 } 1980 1981 static int 1982 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1983 { 1984 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1985 struct ahci_channel *achp = (struct ahci_channel *)chp; 1986 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1987 1988 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1989 DEBUG_FUNCS); 1990 1991 if (ata_waitdrain_xfer_check(chp, xfer)) 1992 return 0; 1993 1994 if (xfer->c_flags & C_TIMEOU) { 1995 sc_xfer->error = XS_TIMEOUT; 1996 } 1997 1998 if (xfer->c_bcount > 0) { 1999 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2000 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2001 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2002 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2003 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2004 } 2005 2006 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2007 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2008 sc_xfer->resid = sc_xfer->datalen; 2009 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2010 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2011 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2012 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2013 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2014 sc_xfer->resid == sc_xfer->datalen)) { 2015 sc_xfer->error = XS_SHORTSENSE; 2016 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2017 if ((sc_xfer->xs_periph->periph_quirks & 2018 PQUIRK_NOSENSE) == 0) { 2019 /* ask scsipi to send a REQUEST_SENSE */ 2020 sc_xfer->error = XS_BUSY; 2021 sc_xfer->status = SCSI_CHECK; 2022 } 2023 } 2024 2025 ata_deactivate_xfer(chp, xfer); 2026 2027 ata_free_xfer(chp, xfer); 2028 scsipi_done(sc_xfer); 2029 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2030 atastart(chp); 2031 return 0; 2032 } 2033 2034 static void 2035 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2036 { 2037 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2038 bool deactivate = true; 2039 2040 /* remove this command from xfer queue */ 2041 switch (reason) { 2042 case KILL_GONE_INACTIVE: 2043 deactivate = false; 2044 /* FALLTHROUGH */ 2045 case KILL_GONE: 2046 sc_xfer->error = XS_DRIVER_STUFFUP; 2047 break; 2048 case KILL_RESET: 2049 sc_xfer->error = XS_RESET; 2050 break; 2051 case KILL_REQUEUE: 2052 sc_xfer->error = XS_REQUEUE; 2053 break; 2054 default: 2055 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2056 panic("ahci_ata_atapi_kill_xfer"); 2057 } 2058 2059 if (deactivate) 2060 ata_deactivate_xfer(chp, xfer); 2061 2062 ata_free_xfer(chp, xfer); 2063 scsipi_done(sc_xfer); 2064 } 2065 2066 static void 2067 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2068 { 2069 struct scsipi_channel *chan = sc->sc_channel; 2070 struct scsipi_periph *periph; 2071 struct ataparams ids; 2072 struct ataparams *id = &ids; 2073 struct ahci_softc *ahcic = 2074 device_private(chan->chan_adapter->adapt_dev); 2075 struct atac_softc *atac = &ahcic->sc_atac; 2076 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2077 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2078 struct scsipibus_attach_args sa; 2079 char serial_number[21], model[41], firmware_revision[9]; 2080 int s; 2081 2082 /* skip if already attached */ 2083 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2084 return; 2085 2086 /* if no ATAPI device detected at attach time, skip */ 2087 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2088 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2089 "not present\n", target), DEBUG_PROBE); 2090 return; 2091 } 2092 2093 /* Some ATAPI devices need a bit more time after software reset. */ 2094 delay(5000); 2095 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2096 #ifdef ATAPI_DEBUG_PROBE 2097 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2098 AHCINAME(ahcic), target, 2099 id->atap_config & ATAPI_CFG_CMD_MASK, 2100 id->atap_config & ATAPI_CFG_DRQ_MASK); 2101 #endif 2102 periph = scsipi_alloc_periph(M_NOWAIT); 2103 if (periph == NULL) { 2104 aprint_error_dev(sc->sc_dev, 2105 "unable to allocate periph for drive %d\n", 2106 target); 2107 return; 2108 } 2109 periph->periph_dev = NULL; 2110 periph->periph_channel = chan; 2111 periph->periph_switch = &atapi_probe_periphsw; 2112 periph->periph_target = target; 2113 periph->periph_lun = 0; 2114 periph->periph_quirks = PQUIRK_ONLYBIG; 2115 2116 #ifdef SCSIPI_DEBUG 2117 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2118 SCSIPI_DEBUG_TARGET == target) 2119 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2120 #endif 2121 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2122 if (id->atap_config & ATAPI_CFG_REMOV) 2123 periph->periph_flags |= PERIPH_REMOVABLE; 2124 if (periph->periph_type == T_SEQUENTIAL) { 2125 s = splbio(); 2126 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2127 splx(s); 2128 } 2129 2130 sa.sa_periph = periph; 2131 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2132 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2133 T_REMOV : T_FIXED; 2134 strnvisx(model, sizeof(model), id->atap_model, 40, 2135 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2136 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2137 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2138 strnvisx(firmware_revision, sizeof(firmware_revision), 2139 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2140 sa.sa_inqbuf.vendor = model; 2141 sa.sa_inqbuf.product = serial_number; 2142 sa.sa_inqbuf.revision = firmware_revision; 2143 2144 /* 2145 * Determine the operating mode capabilities of the device. 2146 */ 2147 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2148 periph->periph_cap |= PERIPH_CAP_CMD16; 2149 /* XXX This is gross. */ 2150 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2151 2152 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2153 2154 if (drvp->drv_softc) 2155 ata_probe_caps(drvp); 2156 else { 2157 s = splbio(); 2158 drvp->drive_type = ATA_DRIVET_NONE; 2159 splx(s); 2160 } 2161 } else { 2162 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2163 "failed for drive %s:%d:%d\n", 2164 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2165 s = splbio(); 2166 drvp->drive_type = ATA_DRIVET_NONE; 2167 splx(s); 2168 } 2169 } 2170 #endif /* NATAPIBUS */ 2171
Indexes created Fri Sep 26 20:09:58 GMT 2025