ahcisata_core.c revision 1.90
1 /* $NetBSD: ahcisata_core.c,v 1.90 2020/12/27 15:13:07 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.90 2020/12/27 15:13:07 jmcneill Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static void ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static void ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 88 #if NATAPIBUS > 0 89 static void ahci_atapibus_attach(struct atabus_softc *); 90 static void ahci_atapi_kill_pending(struct scsipi_periph *); 91 static void ahci_atapi_minphys(struct buf *); 92 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 93 scsipi_adapter_req_t, void *); 94 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 95 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 97 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 98 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 100 101 static const struct scsipi_bustype ahci_atapi_bustype = { 102 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 103 .bustype_cmd = atapi_scsipi_cmd, 104 .bustype_interpret_sense = atapi_interpret_sense, 105 .bustype_printaddr = atapi_print_addr, 106 .bustype_kill_pending = ahci_atapi_kill_pending, 107 .bustype_async_event_xfer_mode = NULL, 108 }; 109 #endif /* NATAPIBUS */ 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 113 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 114 115 const struct ata_bustype ahci_ata_bustype = { 116 .bustype_type = SCSIPI_BUSTYPE_ATA, 117 .ata_bio = ahci_ata_bio, 118 .ata_reset_drive = ahci_reset_drive, 119 .ata_reset_channel = ahci_reset_channel, 120 .ata_exec_command = ahci_exec_command, 121 .ata_get_params = ata_get_params, 122 .ata_addref = ahci_ata_addref, 123 .ata_delref = ahci_ata_delref, 124 .ata_killpending = ahci_killpending, 125 .ata_recovery = ahci_channel_recover, 126 }; 127 128 static void ahci_setup_port(struct ahci_softc *sc, int i); 129 130 static void 131 ahci_enable(struct ahci_softc *sc) 132 { 133 uint32_t ghc; 134 135 ghc = AHCI_READ(sc, AHCI_GHC); 136 if (!(ghc & AHCI_GHC_AE)) { 137 ghc |= AHCI_GHC_AE; 138 AHCI_WRITE(sc, AHCI_GHC, ghc); 139 } 140 } 141 142 static int 143 ahci_reset(struct ahci_softc *sc) 144 { 145 int i; 146 147 /* reset controller */ 148 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 149 /* wait up to 1s for reset to complete */ 150 for (i = 0; i < 1000; i++) { 151 delay(1000); 152 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 153 break; 154 } 155 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 156 aprint_error("%s: reset failed\n", AHCINAME(sc)); 157 return -1; 158 } 159 /* enable ahci mode */ 160 ahci_enable(sc); 161 162 if (sc->sc_save_init_data) { 163 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 164 if (sc->sc_init_data.cap2) 165 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 166 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 167 } 168 169 /* Check if hardware reverted to single message MSI */ 170 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 171 172 return 0; 173 } 174 175 static void 176 ahci_setup_ports(struct ahci_softc *sc) 177 { 178 int i, port; 179 180 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 181 if ((sc->sc_ahci_ports & (1U << i)) == 0) 182 continue; 183 if (port >= sc->sc_atac.atac_nchannels) { 184 aprint_error("%s: more ports than announced\n", 185 AHCINAME(sc)); 186 break; 187 } 188 ahci_setup_port(sc, i); 189 port++; 190 } 191 } 192 193 static void 194 ahci_reprobe_drives(struct ahci_softc *sc) 195 { 196 int i, port; 197 struct ahci_channel *achp; 198 struct ata_channel *chp; 199 200 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 201 if ((sc->sc_ahci_ports & (1U << i)) == 0) 202 continue; 203 if (port >= sc->sc_atac.atac_nchannels) { 204 aprint_error("%s: more ports than announced\n", 205 AHCINAME(sc)); 206 break; 207 } 208 achp = &sc->sc_channels[i]; 209 chp = &achp->ata_channel; 210 211 ahci_probe_drive(chp); 212 port++; 213 } 214 } 215 216 static void 217 ahci_setup_port(struct ahci_softc *sc, int i) 218 { 219 struct ahci_channel *achp; 220 221 achp = &sc->sc_channels[i]; 222 223 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 224 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 225 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 226 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 227 } 228 229 static void 230 ahci_enable_intrs(struct ahci_softc *sc) 231 { 232 233 /* clear interrupts */ 234 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 235 /* enable interrupts */ 236 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 237 } 238 239 void 240 ahci_attach(struct ahci_softc *sc) 241 { 242 uint32_t ahci_rev; 243 int i, j, port; 244 struct ahci_channel *achp; 245 struct ata_channel *chp; 246 int error; 247 int dmasize; 248 char buf[128]; 249 void *cmdhp; 250 void *cmdtblp; 251 252 if (sc->sc_save_init_data) { 253 ahci_enable(sc); 254 255 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 256 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 257 258 ahci_rev = AHCI_READ(sc, AHCI_VS); 259 if (AHCI_VS_MJR(ahci_rev) > 1 || 260 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 261 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 262 } else { 263 sc->sc_init_data.cap2 = 0; 264 } 265 if (sc->sc_init_data.ports == 0) { 266 sc->sc_init_data.ports = sc->sc_ahci_ports; 267 } 268 } 269 270 if (ahci_reset(sc) != 0) 271 return; 272 273 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 274 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 275 aprint_verbose_dev(sc->sc_atac.atac_dev, 276 "ignoring broken port multiplier support\n"); 277 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 278 } 279 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADNCQ) { 280 aprint_verbose_dev(sc->sc_atac.atac_dev, 281 "ignoring broken NCQ support\n"); 282 sc->sc_ahci_cap &= ~AHCI_CAP_NCQ; 283 } 284 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 285 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 286 ahci_rev = AHCI_READ(sc, AHCI_VS); 287 snprintb(buf, sizeof(buf), "\177\020" 288 /* "f\000\005NP\0" */ 289 "b\005SXS\0" 290 "b\006EMS\0" 291 "b\007CCCS\0" 292 /* "f\010\005NCS\0" */ 293 "b\015PSC\0" 294 "b\016SSC\0" 295 "b\017PMD\0" 296 "b\020FBSS\0" 297 "b\021SPM\0" 298 "b\022SAM\0" 299 "b\023SNZO\0" 300 "f\024\003ISS\0" 301 "=\001Gen1\0" 302 "=\002Gen2\0" 303 "=\003Gen3\0" 304 "b\030SCLO\0" 305 "b\031SAL\0" 306 "b\032SALP\0" 307 "b\033SSS\0" 308 "b\034SMPS\0" 309 "b\035SSNTF\0" 310 "b\036SNCQ\0" 311 "b\037S64A\0" 312 "\0", sc->sc_ahci_cap); 313 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 314 ", %d port%s, %d slot%s, CAP %s\n", 315 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 316 sc->sc_atac.atac_nchannels, 317 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 318 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 319 320 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 321 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 322 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 323 sc->sc_atac.atac_pio_cap = 4; 324 sc->sc_atac.atac_dma_cap = 2; 325 sc->sc_atac.atac_udma_cap = 6; 326 sc->sc_atac.atac_channels = sc->sc_chanarray; 327 sc->sc_atac.atac_probe = ahci_probe_drive; 328 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 329 sc->sc_atac.atac_set_modes = ahci_setup_channel; 330 #if NATAPIBUS > 0 331 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 332 #endif 333 334 dmasize = 335 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 336 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 337 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 338 if (error) { 339 aprint_error("%s: unable to allocate command header memory" 340 ", error=%d\n", AHCINAME(sc), error); 341 return; 342 } 343 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 344 sc->sc_cmd_hdr_nseg, dmasize, 345 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 346 if (error) { 347 aprint_error("%s: unable to map command header memory" 348 ", error=%d\n", AHCINAME(sc), error); 349 return; 350 } 351 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 352 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 353 if (error) { 354 aprint_error("%s: unable to create command header map" 355 ", error=%d\n", AHCINAME(sc), error); 356 return; 357 } 358 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 359 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 360 if (error) { 361 aprint_error("%s: unable to load command header map" 362 ", error=%d\n", AHCINAME(sc), error); 363 return; 364 } 365 sc->sc_cmd_hdr = cmdhp; 366 memset(cmdhp, 0, dmasize); 367 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_hdrd, 0, dmasize, 368 BUS_DMASYNC_PREWRITE); 369 370 ahci_enable_intrs(sc); 371 372 if (sc->sc_ahci_ports == 0) { 373 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 374 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 375 DEBUG_PROBE); 376 } 377 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 378 if ((sc->sc_ahci_ports & (1U << i)) == 0) 379 continue; 380 if (port >= sc->sc_atac.atac_nchannels) { 381 aprint_error("%s: more ports than announced\n", 382 AHCINAME(sc)); 383 break; 384 } 385 386 /* Optional intr establish per active port */ 387 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 388 aprint_error("%s: intr establish hook failed\n", 389 AHCINAME(sc)); 390 break; 391 } 392 393 achp = &sc->sc_channels[i]; 394 chp = &achp->ata_channel; 395 sc->sc_chanarray[i] = chp; 396 chp->ch_channel = i; 397 chp->ch_atac = &sc->sc_atac; 398 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 399 if (chp->ch_queue == NULL) { 400 aprint_error("%s port %d: can't allocate memory for " 401 "command queue", AHCINAME(sc), i); 402 break; 403 } 404 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 405 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 406 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 407 BUS_DMA_NOWAIT); 408 if (error) { 409 aprint_error("%s: unable to allocate command table " 410 "memory, error=%d\n", AHCINAME(sc), error); 411 break; 412 } 413 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 414 achp->ahcic_cmd_tbl_nseg, dmasize, 415 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 416 if (error) { 417 aprint_error("%s: unable to map command table memory" 418 ", error=%d\n", AHCINAME(sc), error); 419 break; 420 } 421 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 422 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 423 if (error) { 424 aprint_error("%s: unable to create command table map" 425 ", error=%d\n", AHCINAME(sc), error); 426 break; 427 } 428 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 429 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 430 if (error) { 431 aprint_error("%s: unable to load command table map" 432 ", error=%d\n", AHCINAME(sc), error); 433 break; 434 } 435 memset(cmdtblp, 0, dmasize); 436 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_cmd_tbld, 0, 437 dmasize, BUS_DMASYNC_PREWRITE); 438 achp->ahcic_cmdh = (struct ahci_cmd_header *) 439 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 440 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 441 AHCI_CMDH_SIZE * port; 442 achp->ahcic_rfis = (struct ahci_r_fis *) 443 ((char *)cmdhp + 444 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 445 AHCI_RFIS_SIZE * port); 446 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 447 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 448 AHCI_RFIS_SIZE * port; 449 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 450 "rfis %p (0x%" PRIx64 ")\n", i, 451 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 452 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 453 DEBUG_PROBE); 454 455 for (j = 0; j < sc->sc_ncmds; j++) { 456 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 457 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 458 achp->ahcic_bus_cmd_tbl[j] = 459 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 460 AHCI_CMDTBL_SIZE * j; 461 achp->ahcic_cmdh[j].cmdh_cmdtba = 462 htole64(achp->ahcic_bus_cmd_tbl[j]); 463 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 464 achp->ahcic_cmd_tbl[j], 465 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 466 /* The xfer DMA map */ 467 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 468 AHCI_NPRD, 0x400000 /* 4MB */, 0, 469 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 470 &achp->ahcic_datad[j]); 471 if (error) { 472 aprint_error("%s: couldn't alloc xfer DMA map, " 473 "error=%d\n", AHCINAME(sc), error); 474 goto end; 475 } 476 } 477 ahci_setup_port(sc, i); 478 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 479 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 480 aprint_error("%s: couldn't map port %d " 481 "sata_status regs\n", AHCINAME(sc), i); 482 break; 483 } 484 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 485 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 486 aprint_error("%s: couldn't map port %d " 487 "sata_control regs\n", AHCINAME(sc), i); 488 break; 489 } 490 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 491 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 492 aprint_error("%s: couldn't map port %d " 493 "sata_error regs\n", AHCINAME(sc), i); 494 break; 495 } 496 ata_channel_attach(chp); 497 port++; 498 end: 499 continue; 500 } 501 } 502 503 void 504 ahci_childdetached(struct ahci_softc *sc, device_t child) 505 { 506 struct ahci_channel *achp; 507 struct ata_channel *chp; 508 509 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 510 achp = &sc->sc_channels[i]; 511 chp = &achp->ata_channel; 512 513 if ((sc->sc_ahci_ports & (1U << i)) == 0) 514 continue; 515 516 if (child == chp->atabus) 517 chp->atabus = NULL; 518 } 519 } 520 521 int 522 ahci_detach(struct ahci_softc *sc, int flags) 523 { 524 struct atac_softc *atac; 525 struct ahci_channel *achp; 526 struct ata_channel *chp; 527 struct scsipi_adapter *adapt; 528 int i, j, port; 529 int error; 530 531 atac = &sc->sc_atac; 532 adapt = &atac->atac_atapi_adapter._generic; 533 534 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 535 achp = &sc->sc_channels[i]; 536 chp = &achp->ata_channel; 537 538 if ((sc->sc_ahci_ports & (1U << i)) == 0) 539 continue; 540 if (port >= sc->sc_atac.atac_nchannels) { 541 aprint_error("%s: more ports than announced\n", 542 AHCINAME(sc)); 543 break; 544 } 545 546 if (chp->atabus != NULL) { 547 if ((error = config_detach(chp->atabus, flags)) != 0) 548 return error; 549 550 KASSERT(chp->atabus == NULL); 551 } 552 553 if (chp->ch_flags & ATACH_DETACHED) 554 continue; 555 556 for (j = 0; j < sc->sc_ncmds; j++) 557 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 558 559 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 560 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 561 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 562 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 563 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 564 achp->ahcic_cmd_tbl_nseg); 565 566 ata_channel_detach(chp); 567 port++; 568 } 569 570 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 571 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 572 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 573 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 574 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 575 576 if (adapt->adapt_refcnt != 0) 577 return EBUSY; 578 579 return 0; 580 } 581 582 void 583 ahci_resume(struct ahci_softc *sc) 584 { 585 ahci_reset(sc); 586 ahci_setup_ports(sc); 587 ahci_reprobe_drives(sc); 588 ahci_enable_intrs(sc); 589 } 590 591 int 592 ahci_intr(void *v) 593 { 594 struct ahci_softc *sc = v; 595 uint32_t is, ports; 596 int bit, r = 0; 597 598 while ((is = AHCI_READ(sc, AHCI_IS))) { 599 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 600 DEBUG_INTR); 601 r = 1; 602 ports = is; 603 while ((bit = ffs(ports)) != 0) { 604 bit--; 605 ahci_intr_port(&sc->sc_channels[bit]); 606 ports &= ~(1U << bit); 607 } 608 AHCI_WRITE(sc, AHCI_IS, is); 609 } 610 611 return r; 612 } 613 614 int 615 ahci_intr_port(void *v) 616 { 617 struct ahci_channel *achp = v; 618 struct ata_channel *chp = &achp->ata_channel; 619 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 620 uint32_t is, tfd, sact; 621 struct ata_xfer *xfer; 622 int slot = -1; 623 bool recover = false; 624 uint32_t aslots; 625 626 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 627 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 628 629 AHCIDEBUG_PRINT(( 630 "ahci_intr_port %s port %d is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 631 AHCINAME(sc), 632 chp->ch_channel, is, 633 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 634 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 635 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 636 DEBUG_INTR); 637 638 if ((chp->ch_flags & ATACH_NCQ) == 0) { 639 /* Non-NCQ operation */ 640 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 641 } else { 642 /* NCQ operation */ 643 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 644 } 645 646 /* Handle errors */ 647 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 648 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 649 /* Fatal errors */ 650 if (is & AHCI_P_IX_TFES) { 651 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 652 653 if ((chp->ch_flags & ATACH_NCQ) == 0) { 654 /* Slot valid only for Non-NCQ operation */ 655 slot = (AHCI_READ(sc, 656 AHCI_P_CMD(chp->ch_channel)) 657 & AHCI_P_CMD_CCS_MASK) 658 >> AHCI_P_CMD_CCS_SHIFT; 659 } 660 661 AHCIDEBUG_PRINT(( 662 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 663 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 664 DEBUG_INTR); 665 } else { 666 /* mark an error, and set BSY */ 667 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 668 WDCS_ERR | WDCS_BSY; 669 } 670 671 if (is & AHCI_P_IX_IFS) { 672 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 673 AHCINAME(sc), chp->ch_channel, 674 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 675 DEBUG_INTR); 676 } 677 678 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 679 recover = true; 680 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 681 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 682 683 /* D2H Register FIS or Set Device Bits */ 684 if ((tfd & WDCS_ERR) != 0) { 685 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 686 recover = true; 687 688 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 689 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 690 691 } 692 } else { 693 tfd = 0; 694 } 695 696 if (__predict_false(recover)) 697 ata_channel_freeze(chp); 698 699 aslots = ata_queue_active(chp); 700 701 if (slot >= 0) { 702 if ((aslots & __BIT(slot)) != 0 && 703 (sact & __BIT(slot)) == 0) { 704 xfer = ata_queue_hwslot_to_xfer(chp, slot); 705 xfer->ops->c_intr(chp, xfer, tfd); 706 } 707 } else { 708 /* 709 * For NCQ, HBA halts processing when error is notified, 710 * and any further D2H FISes are ignored until the error 711 * condition is cleared. Hence if a command is inactive, 712 * it means it actually already finished successfully. 713 * Note: active slots can change as c_intr() callback 714 * can activate another command(s), so must only process 715 * commands active before we start processing. 716 */ 717 718 for (slot=0; slot < sc->sc_ncmds; slot++) { 719 if ((aslots & __BIT(slot)) != 0 && 720 (sact & __BIT(slot)) == 0) { 721 xfer = ata_queue_hwslot_to_xfer(chp, slot); 722 xfer->ops->c_intr(chp, xfer, tfd); 723 } 724 } 725 } 726 727 if (__predict_false(recover)) { 728 ata_channel_lock(chp); 729 ata_channel_thaw_locked(chp); 730 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 731 ata_channel_unlock(chp); 732 } 733 734 return 1; 735 } 736 737 static void 738 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 739 { 740 struct ata_channel *chp = drvp->chnl_softc; 741 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 742 uint8_t c_slot; 743 744 ata_channel_lock_owned(chp); 745 746 /* get a slot for running the command on */ 747 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 748 panic("%s: %s: failed to get xfer for reset, port %d\n", 749 device_xname(sc->sc_atac.atac_dev), 750 __func__, chp->ch_channel); 751 /* NOTREACHED */ 752 } 753 754 AHCI_WRITE(sc, AHCI_GHC, 755 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 756 ahci_channel_stop(sc, chp, flags); 757 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 758 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 759 760 ata_queue_free_slot(chp, c_slot); 761 } 762 763 /* return error code from ata_bio */ 764 static int 765 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 766 { 767 struct ahci_channel *achp = (struct ahci_channel *)chp; 768 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 769 int i; 770 uint32_t is; 771 772 /* 773 * Base timeout is specified in ms. Delay for 10ms 774 * on each round. 775 */ 776 timeout = timeout / 10; 777 778 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 779 AHCI_CMDH_SYNC(sc, achp, slot, 780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 781 /* start command */ 782 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 783 for (i = 0; i < timeout; i++) { 784 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 785 0) 786 return 0; 787 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 788 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 789 AHCI_P_IX_IFS | 790 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 791 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 792 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 793 /* 794 * we got the D2H FIS anyway, 795 * assume sig is valid. 796 * channel is restarted later 797 */ 798 return ERROR; 799 } 800 aprint_debug("%s port %d: error 0x%x sending FIS\n", 801 AHCINAME(sc), chp->ch_channel, is); 802 return ERR_DF; 803 } 804 ata_delay(chp, 10, "ahcifis", flags); 805 } 806 807 aprint_debug("%s port %d: timeout sending FIS\n", 808 AHCINAME(sc), chp->ch_channel); 809 return TIMEOUT; 810 } 811 812 static int 813 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 814 uint32_t *sigp, uint8_t c_slot) 815 { 816 struct ahci_channel *achp = (struct ahci_channel *)chp; 817 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 818 struct ahci_cmd_tbl *cmd_tbl; 819 struct ahci_cmd_header *cmd_h; 820 int i, error = 0; 821 uint32_t sig, cmd; 822 int noclo_retry = 0, retry; 823 824 ata_channel_lock_owned(chp); 825 826 again: 827 /* clear port interrupt register */ 828 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 829 /* clear SErrors and start operations */ 830 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 831 /* 832 * issue a command list override to clear BSY. 833 * This is needed if there's a PMP with no drive 834 * on port 0 835 */ 836 ahci_channel_start(sc, chp, flags, 1); 837 } else { 838 /* Can't handle command still running without CLO */ 839 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 840 if ((cmd & AHCI_P_CMD_CR) != 0) { 841 ahci_channel_stop(sc, chp, flags); 842 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 843 if ((cmd & AHCI_P_CMD_CR) != 0) { 844 aprint_error("%s port %d: DMA engine busy " 845 "for drive %d\n", AHCINAME(sc), 846 chp->ch_channel, drive); 847 error = EBUSY; 848 goto end; 849 } 850 } 851 852 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 853 854 ahci_channel_start(sc, chp, flags, 0); 855 } 856 if (drive > 0) { 857 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 858 } 859 860 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET) 861 goto skip_reset; 862 863 /* polled command, assume interrupts are disabled */ 864 865 cmd_h = &achp->ahcic_cmdh[c_slot]; 866 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 867 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 868 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 869 cmd_h->cmdh_prdtl = 0; 870 cmd_h->cmdh_prdbc = 0; 871 memset(cmd_tbl->cmdt_cfis, 0, 64); 872 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 873 cmd_tbl->cmdt_cfis[rhd_c] = drive; 874 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 875 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 876 case ERR_DF: 877 case TIMEOUT: 878 /* 879 * without CLO we can't make sure a software reset will 880 * success, as the drive may still have BSY or DRQ set. 881 * in this case, reset the whole channel and retry the 882 * drive reset. The channel reset should clear BSY and DRQ 883 */ 884 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 885 noclo_retry++; 886 ahci_reset_channel(chp, flags); 887 goto again; 888 } 889 aprint_error("%s port %d: setting WDCTL_RST failed " 890 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 891 error = EBUSY; 892 goto end; 893 default: 894 break; 895 } 896 897 /* 898 * SATA specification has toggle period for SRST bit of 5 usec. Some 899 * controllers fail to process the SRST clear operation unless 900 * we wait for at least this period between the set and clear commands. 901 */ 902 ata_delay(chp, 10, "ahcirstw", flags); 903 904 /* 905 * Try to clear WDCTL_RST a few times before giving up. 906 */ 907 for (error = EBUSY, retry = 0; error != 0 && retry < 5; retry++) { 908 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 909 (drive << AHCI_CMDH_F_PMP_SHIFT)); 910 cmd_h->cmdh_prdbc = 0; 911 memset(cmd_tbl->cmdt_cfis, 0, 64); 912 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 913 cmd_tbl->cmdt_cfis[rhd_c] = drive; 914 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 915 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 916 case ERR_DF: 917 case TIMEOUT: 918 error = EBUSY; 919 break; 920 default: 921 error = 0; 922 break; 923 } 924 if (error == 0) { 925 break; 926 } 927 } 928 if (error == EBUSY) { 929 aprint_error("%s port %d: clearing WDCTL_RST failed " 930 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 931 goto end; 932 } 933 934 skip_reset: 935 /* 936 * wait 31s for BSY to clear 937 * This should not be needed, but some controllers clear the 938 * command slot before receiving the D2H FIS ... 939 */ 940 for (i = 0; i < AHCI_RST_WAIT; i++) { 941 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 942 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 943 break; 944 ata_delay(chp, 10, "ahcid2h", flags); 945 } 946 if (i == AHCI_RST_WAIT) { 947 aprint_error("%s: BSY never cleared, TD 0x%x\n", 948 AHCINAME(sc), sig); 949 goto end; 950 } 951 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 952 DEBUG_PROBE); 953 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 954 if (sigp) 955 *sigp = sig; 956 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 957 AHCINAME(sc), chp->ch_channel, sig, 958 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 959 end: 960 ahci_channel_stop(sc, chp, flags); 961 ata_delay(chp, 500, "ahcirst", flags); 962 /* clear port interrupt register */ 963 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 964 ahci_channel_start(sc, chp, flags, 965 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 966 return error; 967 } 968 969 static void 970 ahci_reset_channel(struct ata_channel *chp, int flags) 971 { 972 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 973 struct ahci_channel *achp = (struct ahci_channel *)chp; 974 int i, tfd; 975 976 ata_channel_lock_owned(chp); 977 978 ahci_channel_stop(sc, chp, flags); 979 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 980 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 981 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 982 /* XXX and then ? */ 983 } 984 ata_kill_active(chp, KILL_RESET, flags); 985 ata_delay(chp, 500, "ahcirst", flags); 986 /* clear port interrupt register */ 987 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 988 /* clear SErrors and start operations */ 989 ahci_channel_start(sc, chp, flags, 990 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 991 /* wait 31s for BSY to clear */ 992 for (i = 0; i < AHCI_RST_WAIT; i++) { 993 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 994 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 995 break; 996 ata_delay(chp, 10, "ahcid2h", flags); 997 } 998 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 999 aprint_error("%s: BSY never cleared, TD 0x%x\n", 1000 AHCINAME(sc), tfd); 1001 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 1002 DEBUG_PROBE); 1003 /* clear port interrupt register */ 1004 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1005 1006 return; 1007 } 1008 1009 static int 1010 ahci_ata_addref(struct ata_drive_datas *drvp) 1011 { 1012 return 0; 1013 } 1014 1015 static void 1016 ahci_ata_delref(struct ata_drive_datas *drvp) 1017 { 1018 return; 1019 } 1020 1021 static void 1022 ahci_killpending(struct ata_drive_datas *drvp) 1023 { 1024 return; 1025 } 1026 1027 static void 1028 ahci_probe_drive(struct ata_channel *chp) 1029 { 1030 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1031 struct ahci_channel *achp = (struct ahci_channel *)chp; 1032 uint32_t sig; 1033 uint8_t c_slot; 1034 int error; 1035 1036 ata_channel_lock(chp); 1037 1038 /* get a slot for running the command on */ 1039 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1040 aprint_error_dev(sc->sc_atac.atac_dev, 1041 "%s: failed to get xfer port %d\n", 1042 __func__, chp->ch_channel); 1043 ata_channel_unlock(chp); 1044 return; 1045 } 1046 1047 /* bring interface up, accept FISs, power up and spin up device */ 1048 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1049 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1050 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1051 /* reset the PHY and bring online */ 1052 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1053 achp->ahcic_sstatus, AT_WAIT)) { 1054 case SStatus_DET_DEV: 1055 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1056 1057 /* Initial value, used in case the soft reset fails */ 1058 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1059 1060 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1061 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1062 &sig, c_slot); 1063 1064 /* If probe for PMP failed, just fallback to drive 0 */ 1065 if (error) { 1066 aprint_error("%s port %d: drive %d reset " 1067 "failed, disabling PMP\n", 1068 AHCINAME(sc), chp->ch_channel, 1069 PMP_PORT_CTL); 1070 1071 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1072 ahci_reset_channel(chp, AT_WAIT); 1073 } 1074 } else { 1075 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1076 } 1077 sata_interpret_sig(chp, 0, sig); 1078 /* if we have a PMP attached, inform the controller */ 1079 if (chp->ch_ndrives > PMP_PORT_CTL && 1080 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1081 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1082 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1083 AHCI_P_CMD_PMA); 1084 } 1085 /* clear port interrupt register */ 1086 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1087 1088 /* and enable interrupts */ 1089 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1090 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1091 AHCI_P_IX_IFS | 1092 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1093 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1094 /* wait 500ms before actually starting operations */ 1095 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1096 break; 1097 1098 default: 1099 break; 1100 } 1101 1102 ata_queue_free_slot(chp, c_slot); 1103 1104 ata_channel_unlock(chp); 1105 } 1106 1107 static void 1108 ahci_setup_channel(struct ata_channel *chp) 1109 { 1110 return; 1111 } 1112 1113 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1114 .c_start = ahci_cmd_start, 1115 .c_poll = ahci_cmd_poll, 1116 .c_abort = ahci_cmd_abort, 1117 .c_intr = ahci_cmd_complete, 1118 .c_kill_xfer = ahci_cmd_kill_xfer, 1119 }; 1120 1121 static void 1122 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1123 { 1124 struct ata_channel *chp = drvp->chnl_softc; 1125 struct ata_command *ata_c = &xfer->c_ata_c; 1126 1127 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1128 chp->ch_channel, 1129 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1130 DEBUG_XFERS); 1131 if (ata_c->flags & AT_POLL) 1132 xfer->c_flags |= C_POLL; 1133 if (ata_c->flags & AT_WAIT) 1134 xfer->c_flags |= C_WAIT; 1135 xfer->c_drive = drvp->drive; 1136 xfer->c_databuf = ata_c->data; 1137 xfer->c_bcount = ata_c->bcount; 1138 xfer->ops = &ahci_cmd_xfer_ops; 1139 1140 ata_exec_xfer(chp, xfer); 1141 } 1142 1143 static int 1144 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1145 { 1146 struct ahci_softc *sc = AHCI_CH2SC(chp); 1147 struct ahci_channel *achp = (struct ahci_channel *)chp; 1148 struct ata_command *ata_c = &xfer->c_ata_c; 1149 int slot = xfer->c_slot; 1150 struct ahci_cmd_tbl *cmd_tbl; 1151 struct ahci_cmd_header *cmd_h; 1152 1153 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1154 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1155 ata_c->timeout, slot), 1156 DEBUG_XFERS); 1157 1158 ata_channel_lock_owned(chp); 1159 1160 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1161 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1162 cmd_tbl), DEBUG_XFERS); 1163 1164 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1165 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1166 1167 cmd_h = &achp->ahcic_cmdh[slot]; 1168 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1169 chp->ch_channel, cmd_h), DEBUG_XFERS); 1170 if (ahci_dma_setup(chp, slot, 1171 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1172 ata_c->data : NULL, 1173 ata_c->bcount, 1174 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1175 ata_c->flags |= AT_DF; 1176 return ATASTART_ABORT; 1177 } 1178 cmd_h->cmdh_flags = htole16( 1179 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1180 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1181 cmd_h->cmdh_prdbc = 0; 1182 AHCI_CMDH_SYNC(sc, achp, slot, 1183 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1184 1185 if (ata_c->flags & AT_POLL) { 1186 /* polled command, disable interrupts */ 1187 AHCI_WRITE(sc, AHCI_GHC, 1188 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1189 } 1190 /* start command */ 1191 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1192 1193 if ((ata_c->flags & AT_POLL) == 0) { 1194 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1195 ata_timeout, chp); 1196 return ATASTART_STARTED; 1197 } else 1198 return ATASTART_POLL; 1199 } 1200 1201 static void 1202 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1203 { 1204 struct ahci_softc *sc = AHCI_CH2SC(chp); 1205 struct ahci_channel *achp = (struct ahci_channel *)chp; 1206 1207 ata_channel_lock(chp); 1208 1209 /* 1210 * Polled command. 1211 */ 1212 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1213 if (xfer->c_ata_c.flags & AT_DONE) 1214 break; 1215 ata_channel_unlock(chp); 1216 ahci_intr_port(achp); 1217 ata_channel_lock(chp); 1218 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1219 } 1220 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1221 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1222 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1223 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1224 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1225 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1226 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1227 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1228 DEBUG_XFERS); 1229 1230 ata_channel_unlock(chp); 1231 1232 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1233 xfer->c_ata_c.flags |= AT_TIMEOU; 1234 xfer->ops->c_intr(chp, xfer, 0); 1235 } 1236 /* reenable interrupts */ 1237 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1238 } 1239 1240 static void 1241 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1242 { 1243 ahci_cmd_complete(chp, xfer, 0); 1244 } 1245 1246 static void 1247 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1248 { 1249 struct ata_command *ata_c = &xfer->c_ata_c; 1250 bool deactivate = true; 1251 1252 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1253 DEBUG_FUNCS); 1254 1255 switch (reason) { 1256 case KILL_GONE_INACTIVE: 1257 deactivate = false; 1258 /* FALLTHROUGH */ 1259 case KILL_GONE: 1260 ata_c->flags |= AT_GONE; 1261 break; 1262 case KILL_RESET: 1263 ata_c->flags |= AT_RESET; 1264 break; 1265 case KILL_REQUEUE: 1266 panic("%s: not supposed to be requeued\n", __func__); 1267 break; 1268 default: 1269 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1270 panic("ahci_cmd_kill_xfer"); 1271 } 1272 1273 ahci_cmd_done_end(chp, xfer); 1274 1275 if (deactivate) 1276 ata_deactivate_xfer(chp, xfer); 1277 } 1278 1279 static int 1280 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1281 { 1282 struct ata_command *ata_c = &xfer->c_ata_c; 1283 struct ahci_channel *achp = (struct ahci_channel *)chp; 1284 struct ahci_softc *sc = AHCI_CH2SC(chp); 1285 1286 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1287 chp->ch_channel, 1288 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1289 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1290 DEBUG_FUNCS); 1291 1292 if (ata_waitdrain_xfer_check(chp, xfer)) 1293 return 0; 1294 1295 if (xfer->c_flags & C_TIMEOU) { 1296 ata_c->flags |= AT_TIMEOU; 1297 } 1298 1299 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1300 ata_c->flags |= AT_TIMEOU; 1301 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1302 ata_c->r_error = AHCI_TFD_ERR(tfd); 1303 ata_c->flags |= AT_ERROR; 1304 } 1305 1306 if (ata_c->flags & AT_READREG) { 1307 AHCI_RFIS_SYNC(sc, achp, BUS_DMASYNC_POSTREAD); 1308 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1309 } 1310 1311 ahci_cmd_done(chp, xfer); 1312 1313 ata_deactivate_xfer(chp, xfer); 1314 1315 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1316 atastart(chp); 1317 1318 return 0; 1319 } 1320 1321 static void 1322 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1323 { 1324 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1325 struct ahci_channel *achp = (struct ahci_channel *)chp; 1326 struct ata_command *ata_c = &xfer->c_ata_c; 1327 uint16_t *idwordbuf; 1328 int i; 1329 1330 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1331 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1332 1333 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1334 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1335 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1336 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1337 BUS_DMASYNC_POSTWRITE); 1338 bus_dmamap_unload(sc->sc_dmat, map); 1339 } 1340 1341 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1342 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1343 1344 /* ata(4) expects IDENTIFY data to be in host endianess */ 1345 if (ata_c->r_command == WDCC_IDENTIFY || 1346 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1347 idwordbuf = xfer->c_databuf; 1348 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1349 idwordbuf[i] = le16toh(idwordbuf[i]); 1350 } 1351 } 1352 1353 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1354 ata_c->flags |= AT_XFDONE; 1355 1356 ahci_cmd_done_end(chp, xfer); 1357 } 1358 1359 static void 1360 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1361 { 1362 struct ata_command *ata_c = &xfer->c_ata_c; 1363 1364 ata_c->flags |= AT_DONE; 1365 } 1366 1367 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1368 .c_start = ahci_bio_start, 1369 .c_poll = ahci_bio_poll, 1370 .c_abort = ahci_bio_abort, 1371 .c_intr = ahci_bio_complete, 1372 .c_kill_xfer = ahci_bio_kill_xfer, 1373 }; 1374 1375 static void 1376 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1377 { 1378 struct ata_channel *chp = drvp->chnl_softc; 1379 struct ata_bio *ata_bio = &xfer->c_bio; 1380 1381 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1382 chp->ch_channel, 1383 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1384 DEBUG_XFERS); 1385 if (ata_bio->flags & ATA_POLL) 1386 xfer->c_flags |= C_POLL; 1387 xfer->c_drive = drvp->drive; 1388 xfer->c_databuf = ata_bio->databuf; 1389 xfer->c_bcount = ata_bio->bcount; 1390 xfer->ops = &ahci_bio_xfer_ops; 1391 ata_exec_xfer(chp, xfer); 1392 } 1393 1394 static int 1395 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1396 { 1397 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1398 struct ahci_channel *achp = (struct ahci_channel *)chp; 1399 struct ata_bio *ata_bio = &xfer->c_bio; 1400 struct ahci_cmd_tbl *cmd_tbl; 1401 struct ahci_cmd_header *cmd_h; 1402 1403 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1404 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1405 1406 ata_channel_lock_owned(chp); 1407 1408 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1409 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1410 cmd_tbl), DEBUG_XFERS); 1411 1412 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1413 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1414 1415 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1416 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1417 chp->ch_channel, cmd_h), DEBUG_XFERS); 1418 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1419 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1420 ata_bio->error = ERR_DMA; 1421 ata_bio->r_error = 0; 1422 return ATASTART_ABORT; 1423 } 1424 cmd_h->cmdh_flags = htole16( 1425 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1426 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1427 cmd_h->cmdh_prdbc = 0; 1428 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1429 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1430 1431 if (xfer->c_flags & C_POLL) { 1432 /* polled command, disable interrupts */ 1433 AHCI_WRITE(sc, AHCI_GHC, 1434 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1435 } 1436 if (xfer->c_flags & C_NCQ) 1437 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1438 /* start command */ 1439 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1440 1441 if ((xfer->c_flags & C_POLL) == 0) { 1442 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1443 ata_timeout, chp); 1444 return ATASTART_STARTED; 1445 } else 1446 return ATASTART_POLL; 1447 } 1448 1449 static void 1450 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1451 { 1452 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1453 struct ahci_channel *achp = (struct ahci_channel *)chp; 1454 1455 /* 1456 * Polled command. 1457 */ 1458 for (int i = 0; i < ATA_DELAY * 10; i++) { 1459 if (xfer->c_bio.flags & ATA_ITSDONE) 1460 break; 1461 ahci_intr_port(achp); 1462 delay(100); 1463 } 1464 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1465 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1466 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1467 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1468 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1469 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1470 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1471 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1472 DEBUG_XFERS); 1473 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1474 xfer->c_bio.error = TIMEOUT; 1475 xfer->ops->c_intr(chp, xfer, 0); 1476 } 1477 /* reenable interrupts */ 1478 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1479 } 1480 1481 static void 1482 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1483 { 1484 ahci_bio_complete(chp, xfer, 0); 1485 } 1486 1487 static void 1488 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1489 { 1490 int drive = xfer->c_drive; 1491 struct ata_bio *ata_bio = &xfer->c_bio; 1492 bool deactivate = true; 1493 1494 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1495 DEBUG_FUNCS); 1496 1497 ata_bio->flags |= ATA_ITSDONE; 1498 switch (reason) { 1499 case KILL_GONE_INACTIVE: 1500 deactivate = false; 1501 /* FALLTHROUGH */ 1502 case KILL_GONE: 1503 ata_bio->error = ERR_NODEV; 1504 break; 1505 case KILL_RESET: 1506 ata_bio->error = ERR_RESET; 1507 break; 1508 case KILL_REQUEUE: 1509 ata_bio->error = REQUEUE; 1510 break; 1511 default: 1512 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1513 panic("ahci_bio_kill_xfer"); 1514 } 1515 ata_bio->r_error = WDCE_ABRT; 1516 1517 if (deactivate) 1518 ata_deactivate_xfer(chp, xfer); 1519 1520 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1521 } 1522 1523 static int 1524 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1525 { 1526 struct ata_bio *ata_bio = &xfer->c_bio; 1527 int drive = xfer->c_drive; 1528 struct ahci_channel *achp = (struct ahci_channel *)chp; 1529 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1530 1531 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1532 DEBUG_FUNCS); 1533 1534 if (ata_waitdrain_xfer_check(chp, xfer)) 1535 return 0; 1536 1537 if (xfer->c_flags & C_TIMEOU) { 1538 ata_bio->error = TIMEOUT; 1539 } 1540 1541 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1542 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1543 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1544 BUS_DMASYNC_POSTWRITE); 1545 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1546 1547 ata_bio->flags |= ATA_ITSDONE; 1548 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1549 ata_bio->error = ERR_DF; 1550 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1551 ata_bio->error = ERROR; 1552 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1553 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1554 ata_bio->flags |= ATA_CORR; 1555 1556 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1557 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1558 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1559 ata_bio->bcount), DEBUG_XFERS); 1560 /* 1561 * If it was a write, complete data buffer may have been transferred 1562 * before error detection; in this case don't use cmdh_prdbc 1563 * as it won't reflect what was written to media. Assume nothing 1564 * was transferred and leave bcount as-is. 1565 * For queued commands, PRD Byte Count should not be used, and is 1566 * not required to be valid; in that case underflow is always illegal. 1567 */ 1568 if ((xfer->c_flags & C_NCQ) != 0) { 1569 if (ata_bio->error == NOERROR) 1570 ata_bio->bcount = 0; 1571 } else { 1572 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1573 ata_bio->bcount -= 1574 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1575 } 1576 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1577 1578 ata_deactivate_xfer(chp, xfer); 1579 1580 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1581 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1582 atastart(chp); 1583 return 0; 1584 } 1585 1586 static void 1587 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1588 { 1589 int i; 1590 /* stop channel */ 1591 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1592 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1593 /* wait 1s for channel to stop */ 1594 for (i = 0; i <100; i++) { 1595 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1596 == 0) 1597 break; 1598 ata_delay(chp, 10, "ahcistop", flags); 1599 } 1600 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1601 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1602 /* XXX controller reset ? */ 1603 return; 1604 } 1605 1606 if (sc->sc_channel_stop) 1607 sc->sc_channel_stop(sc, chp); 1608 } 1609 1610 static void 1611 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1612 int flags, int clo) 1613 { 1614 int i; 1615 uint32_t p_cmd; 1616 /* clear error */ 1617 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1618 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1619 1620 if (clo) { 1621 /* issue command list override */ 1622 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1623 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1624 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1625 /* wait 1s for AHCI_CAP_CLO to clear */ 1626 for (i = 0; i <100; i++) { 1627 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1628 AHCI_P_CMD_CLO) == 0) 1629 break; 1630 ata_delay(chp, 10, "ahciclo", flags); 1631 } 1632 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1633 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1634 /* XXX controller reset ? */ 1635 return; 1636 } 1637 } 1638 1639 if (sc->sc_channel_start) 1640 sc->sc_channel_start(sc, chp); 1641 1642 /* and start controller */ 1643 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1644 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1645 if (chp->ch_ndrives > PMP_PORT_CTL && 1646 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1647 p_cmd |= AHCI_P_CMD_PMA; 1648 } 1649 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1650 } 1651 1652 /* Recover channel after command failure */ 1653 static void 1654 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1655 { 1656 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1657 int drive = ATACH_NODRIVE; 1658 bool reset = false; 1659 1660 ata_channel_lock_owned(chp); 1661 1662 /* 1663 * Read FBS to get the drive which caused the error, if PM is in use. 1664 * According to AHCI 1.3 spec, this register is available regardless 1665 * if FIS-based switching (FBSS) feature is supported, or disabled. 1666 * If FIS-based switching is not in use, it merely maintains single 1667 * pair of DRQ/BSY state, but it is enough since in that case we 1668 * never issue commands for more than one device at the time anyway. 1669 * XXX untested 1670 */ 1671 if (chp->ch_ndrives > PMP_PORT_CTL) { 1672 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1673 if (fbs & AHCI_P_FBS_SDE) { 1674 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1675 1676 /* 1677 * Tell HBA to reset PM port X (value in DWE) state, 1678 * and resume processing commands for other ports. 1679 */ 1680 fbs |= AHCI_P_FBS_DEC; 1681 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1682 for (int i = 0; i < 1000; i++) { 1683 fbs = AHCI_READ(sc, 1684 AHCI_P_FBS(chp->ch_channel)); 1685 if ((fbs & AHCI_P_FBS_DEC) == 0) 1686 break; 1687 DELAY(1000); 1688 } 1689 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1690 /* follow non-device specific recovery */ 1691 drive = ATACH_NODRIVE; 1692 reset = true; 1693 } 1694 } else { 1695 /* not device specific, reset channel */ 1696 drive = ATACH_NODRIVE; 1697 reset = true; 1698 } 1699 } else 1700 drive = 0; 1701 1702 /* 1703 * If BSY or DRQ bits are set, must execute COMRESET to return 1704 * device to idle state. If drive is idle, it's enough to just 1705 * reset CMD.ST, it's not necessary to do software reset. 1706 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1707 * to unblock device processing if COMRESET was not done. 1708 */ 1709 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1710 ahci_reset_channel(chp, flags); 1711 goto out; 1712 } 1713 1714 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1715 ahci_channel_stop(sc, chp, flags); 1716 ahci_channel_start(sc, chp, flags, 1717 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1718 1719 ata_recovery_resume(chp, drive, tfd, flags); 1720 1721 out: 1722 /* Drive unblocked, back to normal operation */ 1723 return; 1724 } 1725 1726 static int 1727 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1728 size_t count, int op) 1729 { 1730 int error, seg; 1731 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1732 struct ahci_channel *achp = (struct ahci_channel *)chp; 1733 struct ahci_cmd_tbl *cmd_tbl; 1734 struct ahci_cmd_header *cmd_h; 1735 1736 cmd_h = &achp->ahcic_cmdh[slot]; 1737 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1738 1739 if (data == NULL) { 1740 cmd_h->cmdh_prdtl = 0; 1741 goto end; 1742 } 1743 1744 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1745 data, count, NULL, 1746 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1747 if (error) { 1748 printf("%s port %d: failed to load xfer: %d\n", 1749 AHCINAME(sc), chp->ch_channel, error); 1750 return error; 1751 } 1752 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1753 achp->ahcic_datad[slot]->dm_mapsize, 1754 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1755 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1756 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1757 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1758 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1759 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1760 } 1761 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1762 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1763 end: 1764 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1765 return 0; 1766 } 1767 1768 #if NATAPIBUS > 0 1769 static void 1770 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1771 { 1772 struct ata_channel *chp = ata_sc->sc_chan; 1773 struct atac_softc *atac = chp->ch_atac; 1774 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1775 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1776 /* 1777 * Fill in the scsipi_adapter. 1778 */ 1779 adapt->adapt_dev = atac->atac_dev; 1780 adapt->adapt_nchannels = atac->atac_nchannels; 1781 adapt->adapt_request = ahci_atapi_scsipi_request; 1782 adapt->adapt_minphys = ahci_atapi_minphys; 1783 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1784 1785 /* 1786 * Fill in the scsipi_channel. 1787 */ 1788 memset(chan, 0, sizeof(*chan)); 1789 chan->chan_adapter = adapt; 1790 chan->chan_bustype = &ahci_atapi_bustype; 1791 chan->chan_channel = chp->ch_channel; 1792 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1793 chan->chan_openings = 1; 1794 chan->chan_max_periph = 1; 1795 chan->chan_ntargets = 1; 1796 chan->chan_nluns = 1; 1797 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1798 atapiprint); 1799 } 1800 1801 static void 1802 ahci_atapi_minphys(struct buf *bp) 1803 { 1804 if (bp->b_bcount > MAXPHYS) 1805 bp->b_bcount = MAXPHYS; 1806 minphys(bp); 1807 } 1808 1809 /* 1810 * Kill off all pending xfers for a periph. 1811 * 1812 * Must be called at splbio(). 1813 */ 1814 static void 1815 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1816 { 1817 struct atac_softc *atac = 1818 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1819 struct ata_channel *chp = 1820 atac->atac_channels[periph->periph_channel->chan_channel]; 1821 1822 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1823 } 1824 1825 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1826 .c_start = ahci_atapi_start, 1827 .c_poll = ahci_atapi_poll, 1828 .c_abort = ahci_atapi_abort, 1829 .c_intr = ahci_atapi_complete, 1830 .c_kill_xfer = ahci_atapi_kill_xfer, 1831 }; 1832 1833 static void 1834 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1835 scsipi_adapter_req_t req, void *arg) 1836 { 1837 struct scsipi_adapter *adapt = chan->chan_adapter; 1838 struct scsipi_periph *periph; 1839 struct scsipi_xfer *sc_xfer; 1840 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1841 struct atac_softc *atac = &sc->sc_atac; 1842 struct ata_xfer *xfer; 1843 int channel = chan->chan_channel; 1844 int drive, s; 1845 1846 switch (req) { 1847 case ADAPTER_REQ_RUN_XFER: 1848 sc_xfer = arg; 1849 periph = sc_xfer->xs_periph; 1850 drive = periph->periph_target; 1851 if (!device_is_active(atac->atac_dev)) { 1852 sc_xfer->error = XS_DRIVER_STUFFUP; 1853 scsipi_done(sc_xfer); 1854 return; 1855 } 1856 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1857 if (xfer == NULL) { 1858 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1859 scsipi_done(sc_xfer); 1860 return; 1861 } 1862 1863 if (sc_xfer->xs_control & XS_CTL_POLL) 1864 xfer->c_flags |= C_POLL; 1865 xfer->c_drive = drive; 1866 xfer->c_flags |= C_ATAPI; 1867 xfer->c_databuf = sc_xfer->data; 1868 xfer->c_bcount = sc_xfer->datalen; 1869 xfer->ops = &ahci_atapi_xfer_ops; 1870 xfer->c_scsipi = sc_xfer; 1871 xfer->c_atapi.c_dscpoll = 0; 1872 s = splbio(); 1873 ata_exec_xfer(atac->atac_channels[channel], xfer); 1874 #ifdef DIAGNOSTIC 1875 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1876 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1877 panic("ahci_atapi_scsipi_request: polled command " 1878 "not done"); 1879 #endif 1880 splx(s); 1881 return; 1882 default: 1883 /* Not supported, nothing to do. */ 1884 ; 1885 } 1886 } 1887 1888 static int 1889 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1890 { 1891 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1892 struct ahci_channel *achp = (struct ahci_channel *)chp; 1893 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1894 struct ahci_cmd_tbl *cmd_tbl; 1895 struct ahci_cmd_header *cmd_h; 1896 1897 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1898 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1899 1900 ata_channel_lock_owned(chp); 1901 1902 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1903 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1904 cmd_tbl), DEBUG_XFERS); 1905 1906 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1907 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1908 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1909 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1910 1911 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1912 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1913 chp->ch_channel, cmd_h), DEBUG_XFERS); 1914 if (ahci_dma_setup(chp, xfer->c_slot, 1915 sc_xfer->datalen ? sc_xfer->data : NULL, 1916 sc_xfer->datalen, 1917 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1918 BUS_DMA_READ : BUS_DMA_WRITE)) { 1919 sc_xfer->error = XS_DRIVER_STUFFUP; 1920 return ATASTART_ABORT; 1921 } 1922 cmd_h->cmdh_flags = htole16( 1923 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1924 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1925 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1926 cmd_h->cmdh_prdbc = 0; 1927 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1929 1930 if (xfer->c_flags & C_POLL) { 1931 /* polled command, disable interrupts */ 1932 AHCI_WRITE(sc, AHCI_GHC, 1933 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1934 } 1935 /* start command */ 1936 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1937 1938 if ((xfer->c_flags & C_POLL) == 0) { 1939 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1940 ata_timeout, chp); 1941 return ATASTART_STARTED; 1942 } else 1943 return ATASTART_POLL; 1944 } 1945 1946 static void 1947 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1948 { 1949 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1950 struct ahci_channel *achp = (struct ahci_channel *)chp; 1951 1952 /* 1953 * Polled command. 1954 */ 1955 for (int i = 0; i < ATA_DELAY / 10; i++) { 1956 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1957 break; 1958 ahci_intr_port(achp); 1959 delay(10000); 1960 } 1961 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1962 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1963 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1964 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1965 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1966 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1967 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1968 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1969 DEBUG_XFERS); 1970 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1971 xfer->c_scsipi->error = XS_TIMEOUT; 1972 xfer->ops->c_intr(chp, xfer, 0); 1973 } 1974 /* reenable interrupts */ 1975 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1976 } 1977 1978 static void 1979 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1980 { 1981 ahci_atapi_complete(chp, xfer, 0); 1982 } 1983 1984 static int 1985 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1986 { 1987 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1988 struct ahci_channel *achp = (struct ahci_channel *)chp; 1989 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1990 1991 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 1992 DEBUG_FUNCS); 1993 1994 if (ata_waitdrain_xfer_check(chp, xfer)) 1995 return 0; 1996 1997 if (xfer->c_flags & C_TIMEOU) { 1998 sc_xfer->error = XS_TIMEOUT; 1999 } 2000 2001 if (xfer->c_bcount > 0) { 2002 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2003 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2004 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2005 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2006 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2007 } 2008 2009 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2010 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2011 sc_xfer->resid = sc_xfer->datalen; 2012 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2013 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2014 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2015 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2016 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2017 sc_xfer->resid == sc_xfer->datalen)) { 2018 sc_xfer->error = XS_SHORTSENSE; 2019 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2020 if ((sc_xfer->xs_periph->periph_quirks & 2021 PQUIRK_NOSENSE) == 0) { 2022 /* ask scsipi to send a REQUEST_SENSE */ 2023 sc_xfer->error = XS_BUSY; 2024 sc_xfer->status = SCSI_CHECK; 2025 } 2026 } 2027 2028 ata_deactivate_xfer(chp, xfer); 2029 2030 ata_free_xfer(chp, xfer); 2031 scsipi_done(sc_xfer); 2032 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2033 atastart(chp); 2034 return 0; 2035 } 2036 2037 static void 2038 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2039 { 2040 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2041 bool deactivate = true; 2042 2043 /* remove this command from xfer queue */ 2044 switch (reason) { 2045 case KILL_GONE_INACTIVE: 2046 deactivate = false; 2047 /* FALLTHROUGH */ 2048 case KILL_GONE: 2049 sc_xfer->error = XS_DRIVER_STUFFUP; 2050 break; 2051 case KILL_RESET: 2052 sc_xfer->error = XS_RESET; 2053 break; 2054 case KILL_REQUEUE: 2055 sc_xfer->error = XS_REQUEUE; 2056 break; 2057 default: 2058 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2059 panic("ahci_ata_atapi_kill_xfer"); 2060 } 2061 2062 if (deactivate) 2063 ata_deactivate_xfer(chp, xfer); 2064 2065 ata_free_xfer(chp, xfer); 2066 scsipi_done(sc_xfer); 2067 } 2068 2069 static void 2070 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2071 { 2072 struct scsipi_channel *chan = sc->sc_channel; 2073 struct scsipi_periph *periph; 2074 struct ataparams ids; 2075 struct ataparams *id = &ids; 2076 struct ahci_softc *ahcic = 2077 device_private(chan->chan_adapter->adapt_dev); 2078 struct atac_softc *atac = &ahcic->sc_atac; 2079 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2080 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2081 struct scsipibus_attach_args sa; 2082 char serial_number[21], model[41], firmware_revision[9]; 2083 int s; 2084 2085 /* skip if already attached */ 2086 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2087 return; 2088 2089 /* if no ATAPI device detected at attach time, skip */ 2090 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2091 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2092 "not present\n", target), DEBUG_PROBE); 2093 return; 2094 } 2095 2096 /* Some ATAPI devices need a bit more time after software reset. */ 2097 delay(5000); 2098 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2099 #ifdef ATAPI_DEBUG_PROBE 2100 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2101 AHCINAME(ahcic), target, 2102 id->atap_config & ATAPI_CFG_CMD_MASK, 2103 id->atap_config & ATAPI_CFG_DRQ_MASK); 2104 #endif 2105 periph = scsipi_alloc_periph(M_NOWAIT); 2106 if (periph == NULL) { 2107 aprint_error_dev(sc->sc_dev, 2108 "unable to allocate periph for drive %d\n", 2109 target); 2110 return; 2111 } 2112 periph->periph_dev = NULL; 2113 periph->periph_channel = chan; 2114 periph->periph_switch = &atapi_probe_periphsw; 2115 periph->periph_target = target; 2116 periph->periph_lun = 0; 2117 periph->periph_quirks = PQUIRK_ONLYBIG; 2118 2119 #ifdef SCSIPI_DEBUG 2120 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2121 SCSIPI_DEBUG_TARGET == target) 2122 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2123 #endif 2124 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2125 if (id->atap_config & ATAPI_CFG_REMOV) 2126 periph->periph_flags |= PERIPH_REMOVABLE; 2127 if (periph->periph_type == T_SEQUENTIAL) { 2128 s = splbio(); 2129 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2130 splx(s); 2131 } 2132 2133 sa.sa_periph = periph; 2134 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2135 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2136 T_REMOV : T_FIXED; 2137 strnvisx(model, sizeof(model), id->atap_model, 40, 2138 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2139 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2140 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2141 strnvisx(firmware_revision, sizeof(firmware_revision), 2142 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2143 sa.sa_inqbuf.vendor = model; 2144 sa.sa_inqbuf.product = serial_number; 2145 sa.sa_inqbuf.revision = firmware_revision; 2146 2147 /* 2148 * Determine the operating mode capabilities of the device. 2149 */ 2150 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2151 periph->periph_cap |= PERIPH_CAP_CMD16; 2152 /* XXX This is gross. */ 2153 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2154 2155 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2156 2157 if (drvp->drv_softc) 2158 ata_probe_caps(drvp); 2159 else { 2160 s = splbio(); 2161 drvp->drive_type = ATA_DRIVET_NONE; 2162 splx(s); 2163 } 2164 } else { 2165 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2166 "failed for drive %s:%d:%d\n", 2167 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2168 s = splbio(); 2169 drvp->drive_type = ATA_DRIVET_NONE; 2170 splx(s); 2171 } 2172 } 2173 #endif /* NATAPIBUS */ 2174
Indexes created Sat Sep 27 22:09:54 GMT 2025