ahcisata_core.c revision 1.93
1 /* $NetBSD: ahcisata_core.c,v 1.93 2020/12/29 07:56:22 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.93 2020/12/29 07:56:22 skrll Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ata/satapmpreg.h> 46 #include <dev/ic/ahcisatavar.h> 47 #include <dev/ic/wdcreg.h> 48 49 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 50 51 #include "atapibus.h" 52 53 #ifdef AHCI_DEBUG 54 int ahcidebug_mask = 0; 55 #endif 56 57 static void ahci_probe_drive(struct ata_channel *); 58 static void ahci_setup_channel(struct ata_channel *); 59 60 static void ahci_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 61 static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *, 62 uint8_t); 63 static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *); 64 static void ahci_reset_channel(struct ata_channel *, int); 65 static void ahci_exec_command(struct ata_drive_datas *, struct ata_xfer *); 66 static int ahci_ata_addref(struct ata_drive_datas *); 67 static void ahci_ata_delref(struct ata_drive_datas *); 68 static void ahci_killpending(struct ata_drive_datas *); 69 70 static int ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_cmd_poll(struct ata_channel *, struct ata_xfer *); 73 static void ahci_cmd_abort(struct ata_channel *, struct ata_xfer *); 74 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *); 75 static void ahci_cmd_done_end(struct ata_channel *, struct ata_xfer *); 76 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 77 static int ahci_bio_start(struct ata_channel *, struct ata_xfer *); 78 static void ahci_bio_poll(struct ata_channel *, struct ata_xfer *); 79 static void ahci_bio_abort(struct ata_channel *, struct ata_xfer *); 80 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 81 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 82 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 83 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *, 84 int, int); 85 static void ahci_channel_recover(struct ata_channel *, int, uint32_t); 86 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 87 static int ahci_intr_port_common(struct ata_channel *); 88 89 #if NATAPIBUS > 0 90 static void ahci_atapibus_attach(struct atabus_softc *); 91 static void ahci_atapi_kill_pending(struct scsipi_periph *); 92 static void ahci_atapi_minphys(struct buf *); 93 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 94 scsipi_adapter_req_t, void *); 95 static int ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 96 static void ahci_atapi_poll(struct ata_channel *, struct ata_xfer *); 97 static void ahci_atapi_abort(struct ata_channel *, struct ata_xfer *); 98 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 99 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 100 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 101 102 static const struct scsipi_bustype ahci_atapi_bustype = { 103 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 104 .bustype_cmd = atapi_scsipi_cmd, 105 .bustype_interpret_sense = atapi_interpret_sense, 106 .bustype_printaddr = atapi_print_addr, 107 .bustype_kill_pending = ahci_atapi_kill_pending, 108 .bustype_async_event_xfer_mode = NULL, 109 }; 110 #endif /* NATAPIBUS */ 111 112 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 113 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 114 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 115 116 const struct ata_bustype ahci_ata_bustype = { 117 .bustype_type = SCSIPI_BUSTYPE_ATA, 118 .ata_bio = ahci_ata_bio, 119 .ata_reset_drive = ahci_reset_drive, 120 .ata_reset_channel = ahci_reset_channel, 121 .ata_exec_command = ahci_exec_command, 122 .ata_get_params = ata_get_params, 123 .ata_addref = ahci_ata_addref, 124 .ata_delref = ahci_ata_delref, 125 .ata_killpending = ahci_killpending, 126 .ata_recovery = ahci_channel_recover, 127 }; 128 129 static void ahci_setup_port(struct ahci_softc *sc, int i); 130 131 static void 132 ahci_enable(struct ahci_softc *sc) 133 { 134 uint32_t ghc; 135 136 ghc = AHCI_READ(sc, AHCI_GHC); 137 if (!(ghc & AHCI_GHC_AE)) { 138 ghc |= AHCI_GHC_AE; 139 AHCI_WRITE(sc, AHCI_GHC, ghc); 140 } 141 } 142 143 static int 144 ahci_reset(struct ahci_softc *sc) 145 { 146 int i; 147 148 /* reset controller */ 149 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 150 /* wait up to 1s for reset to complete */ 151 for (i = 0; i < 1000; i++) { 152 delay(1000); 153 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 154 break; 155 } 156 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 157 aprint_error("%s: reset failed\n", AHCINAME(sc)); 158 return -1; 159 } 160 /* enable ahci mode */ 161 ahci_enable(sc); 162 163 if (sc->sc_save_init_data) { 164 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap); 165 if (sc->sc_init_data.cap2) 166 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2); 167 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports); 168 } 169 170 /* Check if hardware reverted to single message MSI */ 171 sc->sc_ghc_mrsm = ISSET(AHCI_READ(sc, AHCI_GHC), AHCI_GHC_MRSM); 172 173 return 0; 174 } 175 176 static void 177 ahci_setup_ports(struct ahci_softc *sc) 178 { 179 int i, port; 180 181 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 182 if ((sc->sc_ahci_ports & (1U << i)) == 0) 183 continue; 184 if (port >= sc->sc_atac.atac_nchannels) { 185 aprint_error("%s: more ports than announced\n", 186 AHCINAME(sc)); 187 break; 188 } 189 ahci_setup_port(sc, i); 190 port++; 191 } 192 } 193 194 static void 195 ahci_reprobe_drives(struct ahci_softc *sc) 196 { 197 int i, port; 198 struct ahci_channel *achp; 199 struct ata_channel *chp; 200 201 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 202 if ((sc->sc_ahci_ports & (1U << i)) == 0) 203 continue; 204 if (port >= sc->sc_atac.atac_nchannels) { 205 aprint_error("%s: more ports than announced\n", 206 AHCINAME(sc)); 207 break; 208 } 209 achp = &sc->sc_channels[i]; 210 chp = &achp->ata_channel; 211 212 ahci_probe_drive(chp); 213 port++; 214 } 215 } 216 217 static void 218 ahci_setup_port(struct ahci_softc *sc, int i) 219 { 220 struct ahci_channel *achp; 221 222 achp = &sc->sc_channels[i]; 223 224 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 225 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 226 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 227 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 228 } 229 230 static void 231 ahci_enable_intrs(struct ahci_softc *sc) 232 { 233 234 /* clear interrupts */ 235 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 236 /* enable interrupts */ 237 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 238 } 239 240 void 241 ahci_attach(struct ahci_softc *sc) 242 { 243 uint32_t ahci_rev; 244 int i, j, port; 245 struct ahci_channel *achp; 246 struct ata_channel *chp; 247 int error; 248 int dmasize; 249 char buf[128]; 250 void *cmdhp; 251 void *cmdtblp; 252 253 if (sc->sc_save_init_data) { 254 ahci_enable(sc); 255 256 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP); 257 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI); 258 259 ahci_rev = AHCI_READ(sc, AHCI_VS); 260 if (AHCI_VS_MJR(ahci_rev) > 1 || 261 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) { 262 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2); 263 } else { 264 sc->sc_init_data.cap2 = 0; 265 } 266 if (sc->sc_init_data.ports == 0) { 267 sc->sc_init_data.ports = sc->sc_ahci_ports; 268 } 269 } 270 271 if (ahci_reset(sc) != 0) 272 return; 273 274 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP); 275 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) { 276 aprint_verbose_dev(sc->sc_atac.atac_dev, 277 "ignoring broken port multiplier support\n"); 278 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 279 } 280 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADNCQ) { 281 aprint_verbose_dev(sc->sc_atac.atac_dev, 282 "ignoring broken NCQ support\n"); 283 sc->sc_ahci_cap &= ~AHCI_CAP_NCQ; 284 } 285 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1; 286 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 287 ahci_rev = AHCI_READ(sc, AHCI_VS); 288 snprintb(buf, sizeof(buf), "\177\020" 289 /* "f\000\005NP\0" */ 290 "b\005SXS\0" 291 "b\006EMS\0" 292 "b\007CCCS\0" 293 /* "f\010\005NCS\0" */ 294 "b\015PSC\0" 295 "b\016SSC\0" 296 "b\017PMD\0" 297 "b\020FBSS\0" 298 "b\021SPM\0" 299 "b\022SAM\0" 300 "b\023SNZO\0" 301 "f\024\003ISS\0" 302 "=\001Gen1\0" 303 "=\002Gen2\0" 304 "=\003Gen3\0" 305 "b\030SCLO\0" 306 "b\031SAL\0" 307 "b\032SALP\0" 308 "b\033SSS\0" 309 "b\034SMPS\0" 310 "b\035SSNTF\0" 311 "b\036SNCQ\0" 312 "b\037S64A\0" 313 "\0", sc->sc_ahci_cap); 314 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u" 315 ", %d port%s, %d slot%s, CAP %s\n", 316 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev), 317 sc->sc_atac.atac_nchannels, 318 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"), 319 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf); 320 321 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA 322 | ((sc->sc_ahci_cap & AHCI_CAP_NCQ) ? ATAC_CAP_NCQ : 0); 323 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 324 sc->sc_atac.atac_pio_cap = 4; 325 sc->sc_atac.atac_dma_cap = 2; 326 sc->sc_atac.atac_udma_cap = 6; 327 sc->sc_atac.atac_channels = sc->sc_chanarray; 328 sc->sc_atac.atac_probe = ahci_probe_drive; 329 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 330 sc->sc_atac.atac_set_modes = ahci_setup_channel; 331 #if NATAPIBUS > 0 332 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 333 #endif 334 335 dmasize = 336 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 337 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 338 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 339 if (error) { 340 aprint_error("%s: unable to allocate command header memory" 341 ", error=%d\n", AHCINAME(sc), error); 342 return; 343 } 344 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 345 sc->sc_cmd_hdr_nseg, dmasize, 346 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 347 if (error) { 348 aprint_error("%s: unable to map command header memory" 349 ", error=%d\n", AHCINAME(sc), error); 350 return; 351 } 352 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 353 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 354 if (error) { 355 aprint_error("%s: unable to create command header map" 356 ", error=%d\n", AHCINAME(sc), error); 357 return; 358 } 359 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 360 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 361 if (error) { 362 aprint_error("%s: unable to load command header map" 363 ", error=%d\n", AHCINAME(sc), error); 364 return; 365 } 366 sc->sc_cmd_hdr = cmdhp; 367 memset(cmdhp, 0, dmasize); 368 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_hdrd, 0, dmasize, 369 BUS_DMASYNC_PREWRITE); 370 371 ahci_enable_intrs(sc); 372 373 if (sc->sc_ahci_ports == 0) { 374 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI); 375 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports), 376 DEBUG_PROBE); 377 } 378 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 379 if ((sc->sc_ahci_ports & (1U << i)) == 0) 380 continue; 381 if (port >= sc->sc_atac.atac_nchannels) { 382 aprint_error("%s: more ports than announced\n", 383 AHCINAME(sc)); 384 break; 385 } 386 387 /* Optional intr establish per active port */ 388 if (sc->sc_intr_establish && sc->sc_intr_establish(sc, i) != 0){ 389 aprint_error("%s: intr establish hook failed\n", 390 AHCINAME(sc)); 391 break; 392 } 393 394 achp = &sc->sc_channels[i]; 395 chp = &achp->ata_channel; 396 sc->sc_chanarray[i] = chp; 397 chp->ch_channel = i; 398 chp->ch_atac = &sc->sc_atac; 399 chp->ch_queue = ata_queue_alloc(sc->sc_ncmds); 400 if (chp->ch_queue == NULL) { 401 aprint_error("%s port %d: can't allocate memory for " 402 "command queue", AHCINAME(sc), i); 403 break; 404 } 405 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 406 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 407 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 408 BUS_DMA_NOWAIT); 409 if (error) { 410 aprint_error("%s: unable to allocate command table " 411 "memory, error=%d\n", AHCINAME(sc), error); 412 break; 413 } 414 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 415 achp->ahcic_cmd_tbl_nseg, dmasize, 416 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 417 if (error) { 418 aprint_error("%s: unable to map command table memory" 419 ", error=%d\n", AHCINAME(sc), error); 420 break; 421 } 422 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 423 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 424 if (error) { 425 aprint_error("%s: unable to create command table map" 426 ", error=%d\n", AHCINAME(sc), error); 427 break; 428 } 429 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 430 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 431 if (error) { 432 aprint_error("%s: unable to load command table map" 433 ", error=%d\n", AHCINAME(sc), error); 434 break; 435 } 436 memset(cmdtblp, 0, dmasize); 437 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_cmd_tbld, 0, 438 dmasize, BUS_DMASYNC_PREWRITE); 439 achp->ahcic_cmdh = (struct ahci_cmd_header *) 440 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 441 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 442 AHCI_CMDH_SIZE * port; 443 achp->ahcic_rfis = (struct ahci_r_fis *) 444 ((char *)cmdhp + 445 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 446 AHCI_RFIS_SIZE * port); 447 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 448 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 449 AHCI_RFIS_SIZE * port; 450 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 451 "rfis %p (0x%" PRIx64 ")\n", i, 452 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 453 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 454 DEBUG_PROBE); 455 456 for (j = 0; j < sc->sc_ncmds; j++) { 457 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 458 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 459 achp->ahcic_bus_cmd_tbl[j] = 460 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 461 AHCI_CMDTBL_SIZE * j; 462 achp->ahcic_cmdh[j].cmdh_cmdtba = 463 htole64(achp->ahcic_bus_cmd_tbl[j]); 464 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 465 achp->ahcic_cmd_tbl[j], 466 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 467 /* The xfer DMA map */ 468 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 469 AHCI_NPRD, 0x400000 /* 4MB */, 0, 470 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 471 &achp->ahcic_datad[j]); 472 if (error) { 473 aprint_error("%s: couldn't alloc xfer DMA map, " 474 "error=%d\n", AHCINAME(sc), error); 475 goto end; 476 } 477 } 478 ahci_setup_port(sc, i); 479 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 480 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 481 aprint_error("%s: couldn't map port %d " 482 "sata_status regs\n", AHCINAME(sc), i); 483 break; 484 } 485 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 486 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 487 aprint_error("%s: couldn't map port %d " 488 "sata_control regs\n", AHCINAME(sc), i); 489 break; 490 } 491 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 492 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 493 aprint_error("%s: couldn't map port %d " 494 "sata_error regs\n", AHCINAME(sc), i); 495 break; 496 } 497 ata_channel_attach(chp); 498 port++; 499 end: 500 continue; 501 } 502 } 503 504 void 505 ahci_childdetached(struct ahci_softc *sc, device_t child) 506 { 507 struct ahci_channel *achp; 508 struct ata_channel *chp; 509 510 for (int i = 0; i < AHCI_MAX_PORTS; i++) { 511 achp = &sc->sc_channels[i]; 512 chp = &achp->ata_channel; 513 514 if ((sc->sc_ahci_ports & (1U << i)) == 0) 515 continue; 516 517 if (child == chp->atabus) 518 chp->atabus = NULL; 519 } 520 } 521 522 int 523 ahci_detach(struct ahci_softc *sc, int flags) 524 { 525 struct atac_softc *atac; 526 struct ahci_channel *achp; 527 struct ata_channel *chp; 528 struct scsipi_adapter *adapt; 529 int i, j, port; 530 int error; 531 532 atac = &sc->sc_atac; 533 adapt = &atac->atac_atapi_adapter._generic; 534 535 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 536 achp = &sc->sc_channels[i]; 537 chp = &achp->ata_channel; 538 539 if ((sc->sc_ahci_ports & (1U << i)) == 0) 540 continue; 541 if (port >= sc->sc_atac.atac_nchannels) { 542 aprint_error("%s: more ports than announced\n", 543 AHCINAME(sc)); 544 break; 545 } 546 547 if (chp->atabus != NULL) { 548 if ((error = config_detach(chp->atabus, flags)) != 0) 549 return error; 550 551 KASSERT(chp->atabus == NULL); 552 } 553 554 if (chp->ch_flags & ATACH_DETACHED) 555 continue; 556 557 for (j = 0; j < sc->sc_ncmds; j++) 558 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 559 560 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 561 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 562 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 563 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 564 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 565 achp->ahcic_cmd_tbl_nseg); 566 567 ata_channel_detach(chp); 568 port++; 569 } 570 571 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 572 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 573 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 574 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 575 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 576 577 if (adapt->adapt_refcnt != 0) 578 return EBUSY; 579 580 return 0; 581 } 582 583 void 584 ahci_resume(struct ahci_softc *sc) 585 { 586 ahci_reset(sc); 587 ahci_setup_ports(sc); 588 ahci_reprobe_drives(sc); 589 ahci_enable_intrs(sc); 590 } 591 592 int 593 ahci_intr(void *v) 594 { 595 struct ahci_softc *sc = v; 596 uint32_t is, ports; 597 int bit, r = 0; 598 599 while ((is = AHCI_READ(sc, AHCI_IS))) { 600 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 601 DEBUG_INTR); 602 r = 1; 603 ports = is; 604 while ((bit = ffs(ports)) != 0) { 605 bit--; 606 ahci_intr_port_common(&sc->sc_channels[bit].ata_channel); 607 ports &= ~(1U << bit); 608 } 609 AHCI_WRITE(sc, AHCI_IS, is); 610 } 611 612 return r; 613 } 614 615 int 616 ahci_intr_port(void *v) 617 { 618 struct ahci_channel *achp = v; 619 struct ata_channel *chp = &achp->ata_channel; 620 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 621 int ret; 622 623 ret = ahci_intr_port_common(chp); 624 if (ret) { 625 AHCI_WRITE(sc, AHCI_IS, 1U << chp->ch_channel); 626 } 627 628 return ret; 629 } 630 631 static int 632 ahci_intr_port_common(struct ata_channel *chp) 633 { 634 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 635 uint32_t is, tfd, sact; 636 struct ata_xfer *xfer; 637 int slot = -1; 638 bool recover = false; 639 uint32_t aslots; 640 641 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 642 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 643 644 AHCIDEBUG_PRINT(("ahci_intr_port_common %s port %d " 645 "is 0x%x CI 0x%x SACT 0x%x TFD 0x%x\n", 646 AHCINAME(sc), 647 chp->ch_channel, is, 648 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 649 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)), 650 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))), 651 DEBUG_INTR); 652 653 if ((chp->ch_flags & ATACH_NCQ) == 0) { 654 /* Non-NCQ operation */ 655 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)); 656 } else { 657 /* NCQ operation */ 658 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)); 659 } 660 661 /* Handle errors */ 662 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 663 AHCI_P_IX_IFS | AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 664 /* Fatal errors */ 665 if (is & AHCI_P_IX_TFES) { 666 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 667 668 if ((chp->ch_flags & ATACH_NCQ) == 0) { 669 /* Slot valid only for Non-NCQ operation */ 670 slot = (AHCI_READ(sc, 671 AHCI_P_CMD(chp->ch_channel)) 672 & AHCI_P_CMD_CCS_MASK) 673 >> AHCI_P_CMD_CCS_SHIFT; 674 } 675 676 AHCIDEBUG_PRINT(( 677 "%s port %d: TFE: sact 0x%x is 0x%x tfd 0x%x\n", 678 AHCINAME(sc), chp->ch_channel, sact, is, tfd), 679 DEBUG_INTR); 680 } else { 681 /* mark an error, and set BSY */ 682 tfd = (WDCE_ABRT << AHCI_P_TFD_ERR_SHIFT) | 683 WDCS_ERR | WDCS_BSY; 684 } 685 686 if (is & AHCI_P_IX_IFS) { 687 AHCIDEBUG_PRINT(("%s port %d: SERR 0x%x\n", 688 AHCINAME(sc), chp->ch_channel, 689 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))), 690 DEBUG_INTR); 691 } 692 693 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 694 recover = true; 695 } else if (is & (AHCI_P_IX_DHRS|AHCI_P_IX_SDBS)) { 696 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 697 698 /* D2H Register FIS or Set Device Bits */ 699 if ((tfd & WDCS_ERR) != 0) { 700 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 701 recover = true; 702 703 AHCIDEBUG_PRINT(("%s port %d: transfer aborted 0x%x\n", 704 AHCINAME(sc), chp->ch_channel, tfd), DEBUG_INTR); 705 706 } 707 } else { 708 tfd = 0; 709 } 710 711 if (__predict_false(recover)) 712 ata_channel_freeze(chp); 713 714 aslots = ata_queue_active(chp); 715 716 if (slot >= 0) { 717 if ((aslots & __BIT(slot)) != 0 && 718 (sact & __BIT(slot)) == 0) { 719 xfer = ata_queue_hwslot_to_xfer(chp, slot); 720 xfer->ops->c_intr(chp, xfer, tfd); 721 } 722 } else { 723 /* 724 * For NCQ, HBA halts processing when error is notified, 725 * and any further D2H FISes are ignored until the error 726 * condition is cleared. Hence if a command is inactive, 727 * it means it actually already finished successfully. 728 * Note: active slots can change as c_intr() callback 729 * can activate another command(s), so must only process 730 * commands active before we start processing. 731 */ 732 733 for (slot=0; slot < sc->sc_ncmds; slot++) { 734 if ((aslots & __BIT(slot)) != 0 && 735 (sact & __BIT(slot)) == 0) { 736 xfer = ata_queue_hwslot_to_xfer(chp, slot); 737 xfer->ops->c_intr(chp, xfer, tfd); 738 } 739 } 740 } 741 742 if (__predict_false(recover)) { 743 ata_channel_lock(chp); 744 ata_channel_thaw_locked(chp); 745 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 746 ata_channel_unlock(chp); 747 } 748 749 return 1; 750 } 751 752 static void 753 ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 754 { 755 struct ata_channel *chp = drvp->chnl_softc; 756 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 757 uint8_t c_slot; 758 759 ata_channel_lock_owned(chp); 760 761 /* get a slot for running the command on */ 762 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 763 panic("%s: %s: failed to get xfer for reset, port %d\n", 764 device_xname(sc->sc_atac.atac_dev), 765 __func__, chp->ch_channel); 766 /* NOTREACHED */ 767 } 768 769 AHCI_WRITE(sc, AHCI_GHC, 770 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 771 ahci_channel_stop(sc, chp, flags); 772 ahci_do_reset_drive(chp, drvp->drive, flags, sigp, c_slot); 773 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 774 775 ata_queue_free_slot(chp, c_slot); 776 } 777 778 /* return error code from ata_bio */ 779 static int 780 ahci_exec_fis(struct ata_channel *chp, int timeout, int flags, int slot) 781 { 782 struct ahci_channel *achp = (struct ahci_channel *)chp; 783 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 784 int i; 785 uint32_t is; 786 787 /* 788 * Base timeout is specified in ms. Delay for 10ms 789 * on each round. 790 */ 791 timeout = timeout / 10; 792 793 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 794 AHCI_CMDH_SYNC(sc, achp, slot, 795 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 796 /* start command */ 797 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 798 for (i = 0; i < timeout; i++) { 799 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1U << slot)) == 800 0) 801 return 0; 802 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 803 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 804 AHCI_P_IX_IFS | 805 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 806 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) == 807 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) { 808 /* 809 * we got the D2H FIS anyway, 810 * assume sig is valid. 811 * channel is restarted later 812 */ 813 return ERROR; 814 } 815 aprint_debug("%s port %d: error 0x%x sending FIS\n", 816 AHCINAME(sc), chp->ch_channel, is); 817 return ERR_DF; 818 } 819 ata_delay(chp, 10, "ahcifis", flags); 820 } 821 822 aprint_debug("%s port %d: timeout sending FIS\n", 823 AHCINAME(sc), chp->ch_channel); 824 return TIMEOUT; 825 } 826 827 static int 828 ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags, 829 uint32_t *sigp, uint8_t c_slot) 830 { 831 struct ahci_channel *achp = (struct ahci_channel *)chp; 832 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 833 struct ahci_cmd_tbl *cmd_tbl; 834 struct ahci_cmd_header *cmd_h; 835 int i, error = 0; 836 uint32_t sig, cmd; 837 int noclo_retry = 0, retry; 838 839 ata_channel_lock_owned(chp); 840 841 again: 842 /* clear port interrupt register */ 843 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 844 /* clear SErrors and start operations */ 845 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) { 846 /* 847 * issue a command list override to clear BSY. 848 * This is needed if there's a PMP with no drive 849 * on port 0 850 */ 851 ahci_channel_start(sc, chp, flags, 1); 852 } else { 853 /* Can't handle command still running without CLO */ 854 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 855 if ((cmd & AHCI_P_CMD_CR) != 0) { 856 ahci_channel_stop(sc, chp, flags); 857 cmd = AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)); 858 if ((cmd & AHCI_P_CMD_CR) != 0) { 859 aprint_error("%s port %d: DMA engine busy " 860 "for drive %d\n", AHCINAME(sc), 861 chp->ch_channel, drive); 862 error = EBUSY; 863 goto end; 864 } 865 } 866 867 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0); 868 869 ahci_channel_start(sc, chp, flags, 0); 870 } 871 if (drive > 0) { 872 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM); 873 } 874 875 /* polled command, assume interrupts are disabled */ 876 877 cmd_h = &achp->ahcic_cmdh[c_slot]; 878 cmd_tbl = achp->ahcic_cmd_tbl[c_slot]; 879 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY | 880 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); 881 cmd_h->cmdh_prdtl = 0; 882 cmd_h->cmdh_prdbc = 0; 883 memset(cmd_tbl->cmdt_cfis, 0, 64); 884 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 885 cmd_tbl->cmdt_cfis[rhd_c] = drive; 886 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST | WDCTL_4BIT; 887 switch (ahci_exec_fis(chp, 100, flags, c_slot)) { 888 case ERR_DF: 889 case TIMEOUT: 890 /* 891 * without CLO we can't make sure a software reset will 892 * success, as the drive may still have BSY or DRQ set. 893 * in this case, reset the whole channel and retry the 894 * drive reset. The channel reset should clear BSY and DRQ 895 */ 896 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == 0 && noclo_retry == 0) { 897 noclo_retry++; 898 ahci_reset_channel(chp, flags); 899 goto again; 900 } 901 aprint_error("%s port %d: setting WDCTL_RST failed " 902 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 903 error = EBUSY; 904 goto end; 905 default: 906 break; 907 } 908 909 /* 910 * SATA specification has toggle period for SRST bit of 5 usec. Some 911 * controllers fail to process the SRST clear operation unless 912 * we wait for at least this period between the set and clear commands. 913 */ 914 ata_delay(chp, 10, "ahcirstw", flags); 915 916 /* 917 * Try to clear WDCTL_RST a few times before giving up. 918 */ 919 for (error = EBUSY, retry = 0; error != 0 && retry < 5; retry++) { 920 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | 921 (drive << AHCI_CMDH_F_PMP_SHIFT)); 922 cmd_h->cmdh_prdbc = 0; 923 memset(cmd_tbl->cmdt_cfis, 0, 64); 924 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE; 925 cmd_tbl->cmdt_cfis[rhd_c] = drive; 926 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_4BIT; 927 switch (ahci_exec_fis(chp, 310, flags, c_slot)) { 928 case ERR_DF: 929 case TIMEOUT: 930 error = EBUSY; 931 break; 932 default: 933 error = 0; 934 break; 935 } 936 if (error == 0) { 937 break; 938 } 939 } 940 if (error == EBUSY) { 941 aprint_error("%s port %d: clearing WDCTL_RST failed " 942 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive); 943 goto end; 944 } 945 946 /* 947 * wait 31s for BSY to clear 948 * This should not be needed, but some controllers clear the 949 * command slot before receiving the D2H FIS ... 950 */ 951 for (i = 0; i < AHCI_RST_WAIT; i++) { 952 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 953 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0) 954 break; 955 ata_delay(chp, 10, "ahcid2h", flags); 956 } 957 if (i == AHCI_RST_WAIT) { 958 aprint_error("%s: BSY never cleared, TD 0x%x\n", 959 AHCINAME(sc), sig); 960 goto end; 961 } 962 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 963 DEBUG_PROBE); 964 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 965 if (sigp) 966 *sigp = sig; 967 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 968 AHCINAME(sc), chp->ch_channel, sig, 969 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 970 end: 971 ahci_channel_stop(sc, chp, flags); 972 ata_delay(chp, 500, "ahcirst", flags); 973 /* clear port interrupt register */ 974 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 975 ahci_channel_start(sc, chp, flags, 976 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 977 return error; 978 } 979 980 static void 981 ahci_reset_channel(struct ata_channel *chp, int flags) 982 { 983 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 984 struct ahci_channel *achp = (struct ahci_channel *)chp; 985 int i, tfd; 986 987 ata_channel_lock_owned(chp); 988 989 ahci_channel_stop(sc, chp, flags); 990 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 991 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) { 992 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel); 993 /* XXX and then ? */ 994 } 995 ata_kill_active(chp, KILL_RESET, flags); 996 ata_delay(chp, 500, "ahcirst", flags); 997 /* clear port interrupt register */ 998 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 999 /* clear SErrors and start operations */ 1000 ahci_channel_start(sc, chp, flags, 1001 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1002 /* wait 31s for BSY to clear */ 1003 for (i = 0; i < AHCI_RST_WAIT; i++) { 1004 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 1005 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0) 1006 break; 1007 ata_delay(chp, 10, "ahcid2h", flags); 1008 } 1009 if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0) 1010 aprint_error("%s: BSY never cleared, TD 0x%x\n", 1011 AHCINAME(sc), tfd); 1012 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 1013 DEBUG_PROBE); 1014 /* clear port interrupt register */ 1015 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1016 1017 return; 1018 } 1019 1020 static int 1021 ahci_ata_addref(struct ata_drive_datas *drvp) 1022 { 1023 return 0; 1024 } 1025 1026 static void 1027 ahci_ata_delref(struct ata_drive_datas *drvp) 1028 { 1029 return; 1030 } 1031 1032 static void 1033 ahci_killpending(struct ata_drive_datas *drvp) 1034 { 1035 return; 1036 } 1037 1038 static void 1039 ahci_probe_drive(struct ata_channel *chp) 1040 { 1041 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1042 struct ahci_channel *achp = (struct ahci_channel *)chp; 1043 uint32_t sig; 1044 uint8_t c_slot; 1045 int error; 1046 1047 ata_channel_lock(chp); 1048 1049 /* get a slot for running the command on */ 1050 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 1051 aprint_error_dev(sc->sc_atac.atac_dev, 1052 "%s: failed to get xfer port %d\n", 1053 __func__, chp->ch_channel); 1054 ata_channel_unlock(chp); 1055 return; 1056 } 1057 1058 /* bring interface up, accept FISs, power up and spin up device */ 1059 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1060 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 1061 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 1062 /* reset the PHY and bring online */ 1063 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 1064 achp->ahcic_sstatus, AT_WAIT)) { 1065 case SStatus_DET_DEV: 1066 ata_delay(chp, 500, "ahcidv", AT_WAIT); 1067 1068 /* Initial value, used in case the soft reset fails */ 1069 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 1070 1071 if (sc->sc_ahci_cap & AHCI_CAP_SPM) { 1072 error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, 1073 &sig, c_slot); 1074 1075 /* If probe for PMP failed, just fallback to drive 0 */ 1076 if (error) { 1077 aprint_error("%s port %d: drive %d reset " 1078 "failed, disabling PMP\n", 1079 AHCINAME(sc), chp->ch_channel, 1080 PMP_PORT_CTL); 1081 1082 sc->sc_ahci_cap &= ~AHCI_CAP_SPM; 1083 ahci_reset_channel(chp, AT_WAIT); 1084 } 1085 } else { 1086 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig, c_slot); 1087 } 1088 sata_interpret_sig(chp, 0, sig); 1089 /* if we have a PMP attached, inform the controller */ 1090 if (chp->ch_ndrives > PMP_PORT_CTL && 1091 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1092 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1093 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | 1094 AHCI_P_CMD_PMA); 1095 } 1096 /* clear port interrupt register */ 1097 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 1098 1099 /* and enable interrupts */ 1100 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 1101 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS | 1102 AHCI_P_IX_IFS | 1103 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 1104 AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS); 1105 /* wait 500ms before actually starting operations */ 1106 ata_delay(chp, 500, "ahciprb", AT_WAIT); 1107 break; 1108 1109 default: 1110 break; 1111 } 1112 1113 ata_queue_free_slot(chp, c_slot); 1114 1115 ata_channel_unlock(chp); 1116 } 1117 1118 static void 1119 ahci_setup_channel(struct ata_channel *chp) 1120 { 1121 return; 1122 } 1123 1124 static const struct ata_xfer_ops ahci_cmd_xfer_ops = { 1125 .c_start = ahci_cmd_start, 1126 .c_poll = ahci_cmd_poll, 1127 .c_abort = ahci_cmd_abort, 1128 .c_intr = ahci_cmd_complete, 1129 .c_kill_xfer = ahci_cmd_kill_xfer, 1130 }; 1131 1132 static void 1133 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1134 { 1135 struct ata_channel *chp = drvp->chnl_softc; 1136 struct ata_command *ata_c = &xfer->c_ata_c; 1137 1138 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 1139 chp->ch_channel, 1140 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1141 DEBUG_XFERS); 1142 if (ata_c->flags & AT_POLL) 1143 xfer->c_flags |= C_POLL; 1144 if (ata_c->flags & AT_WAIT) 1145 xfer->c_flags |= C_WAIT; 1146 xfer->c_drive = drvp->drive; 1147 xfer->c_databuf = ata_c->data; 1148 xfer->c_bcount = ata_c->bcount; 1149 xfer->ops = &ahci_cmd_xfer_ops; 1150 1151 ata_exec_xfer(chp, xfer); 1152 } 1153 1154 static int 1155 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1156 { 1157 struct ahci_softc *sc = AHCI_CH2SC(chp); 1158 struct ahci_channel *achp = (struct ahci_channel *)chp; 1159 struct ata_command *ata_c = &xfer->c_ata_c; 1160 int slot = xfer->c_slot; 1161 struct ahci_cmd_tbl *cmd_tbl; 1162 struct ahci_cmd_header *cmd_h; 1163 1164 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n slot %d", 1165 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), 1166 ata_c->timeout, slot), 1167 DEBUG_XFERS); 1168 1169 ata_channel_lock_owned(chp); 1170 1171 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1172 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1173 cmd_tbl), DEBUG_XFERS); 1174 1175 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 1176 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1177 1178 cmd_h = &achp->ahcic_cmdh[slot]; 1179 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1180 chp->ch_channel, cmd_h), DEBUG_XFERS); 1181 if (ahci_dma_setup(chp, slot, 1182 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 1183 ata_c->data : NULL, 1184 ata_c->bcount, 1185 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1186 ata_c->flags |= AT_DF; 1187 return ATASTART_ABORT; 1188 } 1189 cmd_h->cmdh_flags = htole16( 1190 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 1191 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1192 cmd_h->cmdh_prdbc = 0; 1193 AHCI_CMDH_SYNC(sc, achp, slot, 1194 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1195 1196 if (ata_c->flags & AT_POLL) { 1197 /* polled command, disable interrupts */ 1198 AHCI_WRITE(sc, AHCI_GHC, 1199 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1200 } 1201 /* start command */ 1202 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << slot); 1203 1204 if ((ata_c->flags & AT_POLL) == 0) { 1205 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1206 ata_timeout, chp); 1207 return ATASTART_STARTED; 1208 } else 1209 return ATASTART_POLL; 1210 } 1211 1212 static void 1213 ahci_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1214 { 1215 struct ahci_softc *sc = AHCI_CH2SC(chp); 1216 struct ahci_channel *achp = (struct ahci_channel *)chp; 1217 1218 ata_channel_lock(chp); 1219 1220 /* 1221 * Polled command. 1222 */ 1223 for (int i = 0; i < xfer->c_ata_c.timeout / 10; i++) { 1224 if (xfer->c_ata_c.flags & AT_DONE) 1225 break; 1226 ata_channel_unlock(chp); 1227 ahci_intr_port(achp); 1228 ata_channel_lock(chp); 1229 ata_delay(chp, 10, "ahcipl", xfer->c_ata_c.flags); 1230 } 1231 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1232 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1233 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1234 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1235 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1236 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1237 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1238 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1239 DEBUG_XFERS); 1240 1241 ata_channel_unlock(chp); 1242 1243 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1244 xfer->c_ata_c.flags |= AT_TIMEOU; 1245 xfer->ops->c_intr(chp, xfer, 0); 1246 } 1247 /* reenable interrupts */ 1248 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1249 } 1250 1251 static void 1252 ahci_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1253 { 1254 ahci_cmd_complete(chp, xfer, 0); 1255 } 1256 1257 static void 1258 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1259 { 1260 struct ata_command *ata_c = &xfer->c_ata_c; 1261 bool deactivate = true; 1262 1263 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer port %d\n", chp->ch_channel), 1264 DEBUG_FUNCS); 1265 1266 switch (reason) { 1267 case KILL_GONE_INACTIVE: 1268 deactivate = false; 1269 /* FALLTHROUGH */ 1270 case KILL_GONE: 1271 ata_c->flags |= AT_GONE; 1272 break; 1273 case KILL_RESET: 1274 ata_c->flags |= AT_RESET; 1275 break; 1276 case KILL_REQUEUE: 1277 panic("%s: not supposed to be requeued\n", __func__); 1278 break; 1279 default: 1280 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 1281 panic("ahci_cmd_kill_xfer"); 1282 } 1283 1284 ahci_cmd_done_end(chp, xfer); 1285 1286 if (deactivate) 1287 ata_deactivate_xfer(chp, xfer); 1288 } 1289 1290 static int 1291 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1292 { 1293 struct ata_command *ata_c = &xfer->c_ata_c; 1294 struct ahci_channel *achp = (struct ahci_channel *)chp; 1295 struct ahci_softc *sc = AHCI_CH2SC(chp); 1296 1297 AHCIDEBUG_PRINT(("ahci_cmd_complete port %d CMD 0x%x CI 0x%x\n", 1298 chp->ch_channel, 1299 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CMD(chp->ch_channel)), 1300 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1301 DEBUG_FUNCS); 1302 1303 if (ata_waitdrain_xfer_check(chp, xfer)) 1304 return 0; 1305 1306 if (xfer->c_flags & C_TIMEOU) { 1307 ata_c->flags |= AT_TIMEOU; 1308 } 1309 1310 if (AHCI_TFD_ST(tfd) & WDCS_BSY) { 1311 ata_c->flags |= AT_TIMEOU; 1312 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1313 ata_c->r_error = AHCI_TFD_ERR(tfd); 1314 ata_c->flags |= AT_ERROR; 1315 } 1316 1317 if (ata_c->flags & AT_READREG) { 1318 AHCI_RFIS_SYNC(sc, achp, BUS_DMASYNC_POSTREAD); 1319 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 1320 } 1321 1322 ahci_cmd_done(chp, xfer); 1323 1324 ata_deactivate_xfer(chp, xfer); 1325 1326 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1327 atastart(chp); 1328 1329 return 0; 1330 } 1331 1332 static void 1333 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1334 { 1335 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1336 struct ahci_channel *achp = (struct ahci_channel *)chp; 1337 struct ata_command *ata_c = &xfer->c_ata_c; 1338 uint16_t *idwordbuf; 1339 int i; 1340 1341 AHCIDEBUG_PRINT(("ahci_cmd_done port %d flags %#x/%#x\n", 1342 chp->ch_channel, xfer->c_flags, ata_c->flags), DEBUG_FUNCS); 1343 1344 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 1345 bus_dmamap_t map = achp->ahcic_datad[xfer->c_slot]; 1346 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1347 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1348 BUS_DMASYNC_POSTWRITE); 1349 bus_dmamap_unload(sc->sc_dmat, map); 1350 } 1351 1352 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1353 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1354 1355 /* ata(4) expects IDENTIFY data to be in host endianess */ 1356 if (ata_c->r_command == WDCC_IDENTIFY || 1357 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1358 idwordbuf = xfer->c_databuf; 1359 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1360 idwordbuf[i] = le16toh(idwordbuf[i]); 1361 } 1362 } 1363 1364 if (achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc) 1365 ata_c->flags |= AT_XFDONE; 1366 1367 ahci_cmd_done_end(chp, xfer); 1368 } 1369 1370 static void 1371 ahci_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1372 { 1373 struct ata_command *ata_c = &xfer->c_ata_c; 1374 1375 ata_c->flags |= AT_DONE; 1376 } 1377 1378 static const struct ata_xfer_ops ahci_bio_xfer_ops = { 1379 .c_start = ahci_bio_start, 1380 .c_poll = ahci_bio_poll, 1381 .c_abort = ahci_bio_abort, 1382 .c_intr = ahci_bio_complete, 1383 .c_kill_xfer = ahci_bio_kill_xfer, 1384 }; 1385 1386 static void 1387 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1388 { 1389 struct ata_channel *chp = drvp->chnl_softc; 1390 struct ata_bio *ata_bio = &xfer->c_bio; 1391 1392 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 1393 chp->ch_channel, 1394 AHCI_READ(AHCI_CH2SC(chp), AHCI_P_CI(chp->ch_channel))), 1395 DEBUG_XFERS); 1396 if (ata_bio->flags & ATA_POLL) 1397 xfer->c_flags |= C_POLL; 1398 xfer->c_drive = drvp->drive; 1399 xfer->c_databuf = ata_bio->databuf; 1400 xfer->c_bcount = ata_bio->bcount; 1401 xfer->ops = &ahci_bio_xfer_ops; 1402 ata_exec_xfer(chp, xfer); 1403 } 1404 1405 static int 1406 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1407 { 1408 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1409 struct ahci_channel *achp = (struct ahci_channel *)chp; 1410 struct ata_bio *ata_bio = &xfer->c_bio; 1411 struct ahci_cmd_tbl *cmd_tbl; 1412 struct ahci_cmd_header *cmd_h; 1413 1414 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 1415 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1416 1417 ata_channel_lock_owned(chp); 1418 1419 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1420 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1421 cmd_tbl), DEBUG_XFERS); 1422 1423 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 1424 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1425 1426 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1427 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1428 chp->ch_channel, cmd_h), DEBUG_XFERS); 1429 if (ahci_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1430 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1431 ata_bio->error = ERR_DMA; 1432 ata_bio->r_error = 0; 1433 return ATASTART_ABORT; 1434 } 1435 cmd_h->cmdh_flags = htole16( 1436 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1437 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1438 cmd_h->cmdh_prdbc = 0; 1439 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1440 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1441 1442 if (xfer->c_flags & C_POLL) { 1443 /* polled command, disable interrupts */ 1444 AHCI_WRITE(sc, AHCI_GHC, 1445 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1446 } 1447 if (xfer->c_flags & C_NCQ) 1448 AHCI_WRITE(sc, AHCI_P_SACT(chp->ch_channel), 1U << xfer->c_slot); 1449 /* start command */ 1450 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1451 1452 if ((xfer->c_flags & C_POLL) == 0) { 1453 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1454 ata_timeout, chp); 1455 return ATASTART_STARTED; 1456 } else 1457 return ATASTART_POLL; 1458 } 1459 1460 static void 1461 ahci_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1462 { 1463 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1464 struct ahci_channel *achp = (struct ahci_channel *)chp; 1465 1466 /* 1467 * Polled command. 1468 */ 1469 for (int i = 0; i < ATA_DELAY * 10; i++) { 1470 if (xfer->c_bio.flags & ATA_ITSDONE) 1471 break; 1472 ahci_intr_port(achp); 1473 delay(100); 1474 } 1475 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1476 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1477 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1478 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1479 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1480 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1481 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1482 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1483 DEBUG_XFERS); 1484 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1485 xfer->c_bio.error = TIMEOUT; 1486 xfer->ops->c_intr(chp, xfer, 0); 1487 } 1488 /* reenable interrupts */ 1489 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1490 } 1491 1492 static void 1493 ahci_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1494 { 1495 ahci_bio_complete(chp, xfer, 0); 1496 } 1497 1498 static void 1499 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1500 { 1501 int drive = xfer->c_drive; 1502 struct ata_bio *ata_bio = &xfer->c_bio; 1503 bool deactivate = true; 1504 1505 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer port %d\n", chp->ch_channel), 1506 DEBUG_FUNCS); 1507 1508 ata_bio->flags |= ATA_ITSDONE; 1509 switch (reason) { 1510 case KILL_GONE_INACTIVE: 1511 deactivate = false; 1512 /* FALLTHROUGH */ 1513 case KILL_GONE: 1514 ata_bio->error = ERR_NODEV; 1515 break; 1516 case KILL_RESET: 1517 ata_bio->error = ERR_RESET; 1518 break; 1519 case KILL_REQUEUE: 1520 ata_bio->error = REQUEUE; 1521 break; 1522 default: 1523 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1524 panic("ahci_bio_kill_xfer"); 1525 } 1526 ata_bio->r_error = WDCE_ABRT; 1527 1528 if (deactivate) 1529 ata_deactivate_xfer(chp, xfer); 1530 1531 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1532 } 1533 1534 static int 1535 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1536 { 1537 struct ata_bio *ata_bio = &xfer->c_bio; 1538 int drive = xfer->c_drive; 1539 struct ahci_channel *achp = (struct ahci_channel *)chp; 1540 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1541 1542 AHCIDEBUG_PRINT(("ahci_bio_complete port %d\n", chp->ch_channel), 1543 DEBUG_FUNCS); 1544 1545 if (ata_waitdrain_xfer_check(chp, xfer)) 1546 return 0; 1547 1548 if (xfer->c_flags & C_TIMEOU) { 1549 ata_bio->error = TIMEOUT; 1550 } 1551 1552 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 1553 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 1554 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1555 BUS_DMASYNC_POSTWRITE); 1556 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 1557 1558 ata_bio->flags |= ATA_ITSDONE; 1559 if (AHCI_TFD_ERR(tfd) & WDCS_DWF) { 1560 ata_bio->error = ERR_DF; 1561 } else if (AHCI_TFD_ST(tfd) & WDCS_ERR) { 1562 ata_bio->error = ERROR; 1563 ata_bio->r_error = AHCI_TFD_ERR(tfd); 1564 } else if (AHCI_TFD_ST(tfd) & WDCS_CORR) 1565 ata_bio->flags |= ATA_CORR; 1566 1567 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1568 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1569 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1570 ata_bio->bcount), DEBUG_XFERS); 1571 /* 1572 * If it was a write, complete data buffer may have been transferred 1573 * before error detection; in this case don't use cmdh_prdbc 1574 * as it won't reflect what was written to media. Assume nothing 1575 * was transferred and leave bcount as-is. 1576 * For queued commands, PRD Byte Count should not be used, and is 1577 * not required to be valid; in that case underflow is always illegal. 1578 */ 1579 if ((xfer->c_flags & C_NCQ) != 0) { 1580 if (ata_bio->error == NOERROR) 1581 ata_bio->bcount = 0; 1582 } else { 1583 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1584 ata_bio->bcount -= 1585 le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 1586 } 1587 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1588 1589 ata_deactivate_xfer(chp, xfer); 1590 1591 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1592 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 1593 atastart(chp); 1594 return 0; 1595 } 1596 1597 static void 1598 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1599 { 1600 int i; 1601 /* stop channel */ 1602 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1603 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1604 /* wait 1s for channel to stop */ 1605 for (i = 0; i <100; i++) { 1606 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1607 == 0) 1608 break; 1609 ata_delay(chp, 10, "ahcistop", flags); 1610 } 1611 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1612 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1613 /* XXX controller reset ? */ 1614 return; 1615 } 1616 1617 if (sc->sc_channel_stop) 1618 sc->sc_channel_stop(sc, chp); 1619 } 1620 1621 static void 1622 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp, 1623 int flags, int clo) 1624 { 1625 int i; 1626 uint32_t p_cmd; 1627 /* clear error */ 1628 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1629 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1630 1631 if (clo) { 1632 /* issue command list override */ 1633 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO); 1634 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1635 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO); 1636 /* wait 1s for AHCI_CAP_CLO to clear */ 1637 for (i = 0; i <100; i++) { 1638 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & 1639 AHCI_P_CMD_CLO) == 0) 1640 break; 1641 ata_delay(chp, 10, "ahciclo", flags); 1642 } 1643 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) { 1644 printf("%s: channel wouldn't CLO\n", AHCINAME(sc)); 1645 /* XXX controller reset ? */ 1646 return; 1647 } 1648 } 1649 1650 if (sc->sc_channel_start) 1651 sc->sc_channel_start(sc, chp); 1652 1653 /* and start controller */ 1654 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1655 AHCI_P_CMD_FRE | AHCI_P_CMD_ST; 1656 if (chp->ch_ndrives > PMP_PORT_CTL && 1657 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) { 1658 p_cmd |= AHCI_P_CMD_PMA; 1659 } 1660 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd); 1661 } 1662 1663 /* Recover channel after command failure */ 1664 static void 1665 ahci_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 1666 { 1667 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1668 int drive = ATACH_NODRIVE; 1669 bool reset = false; 1670 1671 ata_channel_lock_owned(chp); 1672 1673 /* 1674 * Read FBS to get the drive which caused the error, if PM is in use. 1675 * According to AHCI 1.3 spec, this register is available regardless 1676 * if FIS-based switching (FBSS) feature is supported, or disabled. 1677 * If FIS-based switching is not in use, it merely maintains single 1678 * pair of DRQ/BSY state, but it is enough since in that case we 1679 * never issue commands for more than one device at the time anyway. 1680 * XXX untested 1681 */ 1682 if (chp->ch_ndrives > PMP_PORT_CTL) { 1683 uint32_t fbs = AHCI_READ(sc, AHCI_P_FBS(chp->ch_channel)); 1684 if (fbs & AHCI_P_FBS_SDE) { 1685 drive = (fbs & AHCI_P_FBS_DWE) >> AHCI_P_FBS_DWE_SHIFT; 1686 1687 /* 1688 * Tell HBA to reset PM port X (value in DWE) state, 1689 * and resume processing commands for other ports. 1690 */ 1691 fbs |= AHCI_P_FBS_DEC; 1692 AHCI_WRITE(sc, AHCI_P_FBS(chp->ch_channel), fbs); 1693 for (int i = 0; i < 1000; i++) { 1694 fbs = AHCI_READ(sc, 1695 AHCI_P_FBS(chp->ch_channel)); 1696 if ((fbs & AHCI_P_FBS_DEC) == 0) 1697 break; 1698 DELAY(1000); 1699 } 1700 if ((fbs & AHCI_P_FBS_DEC) != 0) { 1701 /* follow non-device specific recovery */ 1702 drive = ATACH_NODRIVE; 1703 reset = true; 1704 } 1705 } else { 1706 /* not device specific, reset channel */ 1707 drive = ATACH_NODRIVE; 1708 reset = true; 1709 } 1710 } else 1711 drive = 0; 1712 1713 /* 1714 * If BSY or DRQ bits are set, must execute COMRESET to return 1715 * device to idle state. If drive is idle, it's enough to just 1716 * reset CMD.ST, it's not necessary to do software reset. 1717 * After resetting CMD.ST, need to execute READ LOG EXT for NCQ 1718 * to unblock device processing if COMRESET was not done. 1719 */ 1720 if (reset || (AHCI_TFD_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 1721 ahci_reset_channel(chp, flags); 1722 goto out; 1723 } 1724 1725 KASSERT(drive != ATACH_NODRIVE && drive >= 0); 1726 ahci_channel_stop(sc, chp, flags); 1727 ahci_channel_start(sc, chp, flags, 1728 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0); 1729 1730 ata_recovery_resume(chp, drive, tfd, flags); 1731 1732 out: 1733 /* Drive unblocked, back to normal operation */ 1734 return; 1735 } 1736 1737 static int 1738 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1739 size_t count, int op) 1740 { 1741 int error, seg; 1742 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1743 struct ahci_channel *achp = (struct ahci_channel *)chp; 1744 struct ahci_cmd_tbl *cmd_tbl; 1745 struct ahci_cmd_header *cmd_h; 1746 1747 cmd_h = &achp->ahcic_cmdh[slot]; 1748 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1749 1750 if (data == NULL) { 1751 cmd_h->cmdh_prdtl = 0; 1752 goto end; 1753 } 1754 1755 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1756 data, count, NULL, 1757 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1758 if (error) { 1759 printf("%s port %d: failed to load xfer: %d\n", 1760 AHCINAME(sc), chp->ch_channel, error); 1761 return error; 1762 } 1763 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1764 achp->ahcic_datad[slot]->dm_mapsize, 1765 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1766 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1767 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1768 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1769 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1770 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1771 } 1772 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1773 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1774 end: 1775 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1776 return 0; 1777 } 1778 1779 #if NATAPIBUS > 0 1780 static void 1781 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1782 { 1783 struct ata_channel *chp = ata_sc->sc_chan; 1784 struct atac_softc *atac = chp->ch_atac; 1785 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1786 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1787 /* 1788 * Fill in the scsipi_adapter. 1789 */ 1790 adapt->adapt_dev = atac->atac_dev; 1791 adapt->adapt_nchannels = atac->atac_nchannels; 1792 adapt->adapt_request = ahci_atapi_scsipi_request; 1793 adapt->adapt_minphys = ahci_atapi_minphys; 1794 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1795 1796 /* 1797 * Fill in the scsipi_channel. 1798 */ 1799 memset(chan, 0, sizeof(*chan)); 1800 chan->chan_adapter = adapt; 1801 chan->chan_bustype = &ahci_atapi_bustype; 1802 chan->chan_channel = chp->ch_channel; 1803 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1804 chan->chan_openings = 1; 1805 chan->chan_max_periph = 1; 1806 chan->chan_ntargets = 1; 1807 chan->chan_nluns = 1; 1808 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1809 atapiprint); 1810 } 1811 1812 static void 1813 ahci_atapi_minphys(struct buf *bp) 1814 { 1815 if (bp->b_bcount > MAXPHYS) 1816 bp->b_bcount = MAXPHYS; 1817 minphys(bp); 1818 } 1819 1820 /* 1821 * Kill off all pending xfers for a periph. 1822 * 1823 * Must be called at splbio(). 1824 */ 1825 static void 1826 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1827 { 1828 struct atac_softc *atac = 1829 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1830 struct ata_channel *chp = 1831 atac->atac_channels[periph->periph_channel->chan_channel]; 1832 1833 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1834 } 1835 1836 static const struct ata_xfer_ops ahci_atapi_xfer_ops = { 1837 .c_start = ahci_atapi_start, 1838 .c_poll = ahci_atapi_poll, 1839 .c_abort = ahci_atapi_abort, 1840 .c_intr = ahci_atapi_complete, 1841 .c_kill_xfer = ahci_atapi_kill_xfer, 1842 }; 1843 1844 static void 1845 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1846 scsipi_adapter_req_t req, void *arg) 1847 { 1848 struct scsipi_adapter *adapt = chan->chan_adapter; 1849 struct scsipi_periph *periph; 1850 struct scsipi_xfer *sc_xfer; 1851 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1852 struct atac_softc *atac = &sc->sc_atac; 1853 struct ata_xfer *xfer; 1854 int channel = chan->chan_channel; 1855 int drive, s; 1856 1857 switch (req) { 1858 case ADAPTER_REQ_RUN_XFER: 1859 sc_xfer = arg; 1860 periph = sc_xfer->xs_periph; 1861 drive = periph->periph_target; 1862 if (!device_is_active(atac->atac_dev)) { 1863 sc_xfer->error = XS_DRIVER_STUFFUP; 1864 scsipi_done(sc_xfer); 1865 return; 1866 } 1867 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1868 if (xfer == NULL) { 1869 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1870 scsipi_done(sc_xfer); 1871 return; 1872 } 1873 1874 if (sc_xfer->xs_control & XS_CTL_POLL) 1875 xfer->c_flags |= C_POLL; 1876 xfer->c_drive = drive; 1877 xfer->c_flags |= C_ATAPI; 1878 xfer->c_databuf = sc_xfer->data; 1879 xfer->c_bcount = sc_xfer->datalen; 1880 xfer->ops = &ahci_atapi_xfer_ops; 1881 xfer->c_scsipi = sc_xfer; 1882 xfer->c_atapi.c_dscpoll = 0; 1883 s = splbio(); 1884 ata_exec_xfer(atac->atac_channels[channel], xfer); 1885 #ifdef DIAGNOSTIC 1886 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1887 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1888 panic("ahci_atapi_scsipi_request: polled command " 1889 "not done"); 1890 #endif 1891 splx(s); 1892 return; 1893 default: 1894 /* Not supported, nothing to do. */ 1895 ; 1896 } 1897 } 1898 1899 static int 1900 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1901 { 1902 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1903 struct ahci_channel *achp = (struct ahci_channel *)chp; 1904 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1905 struct ahci_cmd_tbl *cmd_tbl; 1906 struct ahci_cmd_header *cmd_h; 1907 1908 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1909 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1910 1911 ata_channel_lock_owned(chp); 1912 1913 cmd_tbl = achp->ahcic_cmd_tbl[xfer->c_slot]; 1914 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1915 cmd_tbl), DEBUG_XFERS); 1916 1917 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1918 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive; 1919 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1920 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1921 1922 cmd_h = &achp->ahcic_cmdh[xfer->c_slot]; 1923 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1924 chp->ch_channel, cmd_h), DEBUG_XFERS); 1925 if (ahci_dma_setup(chp, xfer->c_slot, 1926 sc_xfer->datalen ? sc_xfer->data : NULL, 1927 sc_xfer->datalen, 1928 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1929 BUS_DMA_READ : BUS_DMA_WRITE)) { 1930 sc_xfer->error = XS_DRIVER_STUFFUP; 1931 return ATASTART_ABORT; 1932 } 1933 cmd_h->cmdh_flags = htole16( 1934 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1935 RHD_FISLEN / 4 | AHCI_CMDH_F_A | 1936 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT)); 1937 cmd_h->cmdh_prdbc = 0; 1938 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 1939 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1940 1941 if (xfer->c_flags & C_POLL) { 1942 /* polled command, disable interrupts */ 1943 AHCI_WRITE(sc, AHCI_GHC, 1944 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1945 } 1946 /* start command */ 1947 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1U << xfer->c_slot); 1948 1949 if ((xfer->c_flags & C_POLL) == 0) { 1950 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1951 ata_timeout, chp); 1952 return ATASTART_STARTED; 1953 } else 1954 return ATASTART_POLL; 1955 } 1956 1957 static void 1958 ahci_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1959 { 1960 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1961 struct ahci_channel *achp = (struct ahci_channel *)chp; 1962 1963 /* 1964 * Polled command. 1965 */ 1966 for (int i = 0; i < ATA_DELAY / 10; i++) { 1967 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1968 break; 1969 ahci_intr_port(achp); 1970 delay(10000); 1971 } 1972 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), chp->ch_channel, 1973 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1974 AHCI_READ(sc, AHCI_P_CLBU(chp->ch_channel)), 1975 AHCI_READ(sc, AHCI_P_CLB(chp->ch_channel)), 1976 AHCI_READ(sc, AHCI_P_FBU(chp->ch_channel)), 1977 AHCI_READ(sc, AHCI_P_FB(chp->ch_channel)), 1978 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 1979 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 1980 DEBUG_XFERS); 1981 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1982 xfer->c_scsipi->error = XS_TIMEOUT; 1983 xfer->ops->c_intr(chp, xfer, 0); 1984 } 1985 /* reenable interrupts */ 1986 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1987 } 1988 1989 static void 1990 ahci_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1991 { 1992 ahci_atapi_complete(chp, xfer, 0); 1993 } 1994 1995 static int 1996 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1997 { 1998 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1999 struct ahci_channel *achp = (struct ahci_channel *)chp; 2000 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 2001 2002 AHCIDEBUG_PRINT(("ahci_atapi_complete port %d\n", chp->ch_channel), 2003 DEBUG_FUNCS); 2004 2005 if (ata_waitdrain_xfer_check(chp, xfer)) 2006 return 0; 2007 2008 if (xfer->c_flags & C_TIMEOU) { 2009 sc_xfer->error = XS_TIMEOUT; 2010 } 2011 2012 if (xfer->c_bcount > 0) { 2013 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot], 0, 2014 achp->ahcic_datad[xfer->c_slot]->dm_mapsize, 2015 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 2016 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2017 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[xfer->c_slot]); 2018 } 2019 2020 AHCI_CMDH_SYNC(sc, achp, xfer->c_slot, 2021 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2022 sc_xfer->resid = sc_xfer->datalen; 2023 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[xfer->c_slot].cmdh_prdbc); 2024 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 2025 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 2026 if (AHCI_TFD_ST(tfd) & WDCS_ERR && 2027 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2028 sc_xfer->resid == sc_xfer->datalen)) { 2029 sc_xfer->error = XS_SHORTSENSE; 2030 sc_xfer->sense.atapi_sense = AHCI_TFD_ERR(tfd); 2031 if ((sc_xfer->xs_periph->periph_quirks & 2032 PQUIRK_NOSENSE) == 0) { 2033 /* ask scsipi to send a REQUEST_SENSE */ 2034 sc_xfer->error = XS_BUSY; 2035 sc_xfer->status = SCSI_CHECK; 2036 } 2037 } 2038 2039 ata_deactivate_xfer(chp, xfer); 2040 2041 ata_free_xfer(chp, xfer); 2042 scsipi_done(sc_xfer); 2043 if ((AHCI_TFD_ST(tfd) & WDCS_ERR) == 0) 2044 atastart(chp); 2045 return 0; 2046 } 2047 2048 static void 2049 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 2050 { 2051 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2052 bool deactivate = true; 2053 2054 /* remove this command from xfer queue */ 2055 switch (reason) { 2056 case KILL_GONE_INACTIVE: 2057 deactivate = false; 2058 /* FALLTHROUGH */ 2059 case KILL_GONE: 2060 sc_xfer->error = XS_DRIVER_STUFFUP; 2061 break; 2062 case KILL_RESET: 2063 sc_xfer->error = XS_RESET; 2064 break; 2065 case KILL_REQUEUE: 2066 sc_xfer->error = XS_REQUEUE; 2067 break; 2068 default: 2069 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 2070 panic("ahci_ata_atapi_kill_xfer"); 2071 } 2072 2073 if (deactivate) 2074 ata_deactivate_xfer(chp, xfer); 2075 2076 ata_free_xfer(chp, xfer); 2077 scsipi_done(sc_xfer); 2078 } 2079 2080 static void 2081 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 2082 { 2083 struct scsipi_channel *chan = sc->sc_channel; 2084 struct scsipi_periph *periph; 2085 struct ataparams ids; 2086 struct ataparams *id = &ids; 2087 struct ahci_softc *ahcic = 2088 device_private(chan->chan_adapter->adapt_dev); 2089 struct atac_softc *atac = &ahcic->sc_atac; 2090 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2091 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 2092 struct scsipibus_attach_args sa; 2093 char serial_number[21], model[41], firmware_revision[9]; 2094 int s; 2095 2096 /* skip if already attached */ 2097 if (scsipi_lookup_periph(chan, target, 0) != NULL) 2098 return; 2099 2100 /* if no ATAPI device detected at attach time, skip */ 2101 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 2102 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 2103 "not present\n", target), DEBUG_PROBE); 2104 return; 2105 } 2106 2107 /* Some ATAPI devices need a bit more time after software reset. */ 2108 delay(5000); 2109 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 2110 #ifdef ATAPI_DEBUG_PROBE 2111 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 2112 AHCINAME(ahcic), target, 2113 id->atap_config & ATAPI_CFG_CMD_MASK, 2114 id->atap_config & ATAPI_CFG_DRQ_MASK); 2115 #endif 2116 periph = scsipi_alloc_periph(M_NOWAIT); 2117 if (periph == NULL) { 2118 aprint_error_dev(sc->sc_dev, 2119 "unable to allocate periph for drive %d\n", 2120 target); 2121 return; 2122 } 2123 periph->periph_dev = NULL; 2124 periph->periph_channel = chan; 2125 periph->periph_switch = &atapi_probe_periphsw; 2126 periph->periph_target = target; 2127 periph->periph_lun = 0; 2128 periph->periph_quirks = PQUIRK_ONLYBIG; 2129 2130 #ifdef SCSIPI_DEBUG 2131 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 2132 SCSIPI_DEBUG_TARGET == target) 2133 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 2134 #endif 2135 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 2136 if (id->atap_config & ATAPI_CFG_REMOV) 2137 periph->periph_flags |= PERIPH_REMOVABLE; 2138 if (periph->periph_type == T_SEQUENTIAL) { 2139 s = splbio(); 2140 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 2141 splx(s); 2142 } 2143 2144 sa.sa_periph = periph; 2145 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 2146 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 2147 T_REMOV : T_FIXED; 2148 strnvisx(model, sizeof(model), id->atap_model, 40, 2149 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2150 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 2151 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2152 strnvisx(firmware_revision, sizeof(firmware_revision), 2153 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 2154 sa.sa_inqbuf.vendor = model; 2155 sa.sa_inqbuf.product = serial_number; 2156 sa.sa_inqbuf.revision = firmware_revision; 2157 2158 /* 2159 * Determine the operating mode capabilities of the device. 2160 */ 2161 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 2162 periph->periph_cap |= PERIPH_CAP_CMD16; 2163 /* XXX This is gross. */ 2164 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 2165 2166 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 2167 2168 if (drvp->drv_softc) 2169 ata_probe_caps(drvp); 2170 else { 2171 s = splbio(); 2172 drvp->drive_type = ATA_DRIVET_NONE; 2173 splx(s); 2174 } 2175 } else { 2176 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 2177 "failed for drive %s:%d:%d\n", 2178 AHCINAME(ahcic), chp->ch_channel, target), DEBUG_PROBE); 2179 s = splbio(); 2180 drvp->drive_type = ATA_DRIVET_NONE; 2181 splx(s); 2182 } 2183 } 2184 #endif /* NATAPIBUS */ 2185
Indexes created Thu Sep 25 16:09:42 GMT 2025