ahcisatavar.h revision 1.1.4.2 1 1.1.4.2 ad /* $NetBSD: ahcisatavar.h,v 1.1.4.2 2007/06/09 21:37:13 ad Exp $ */
2 1.1.4.2 ad
3 1.1.4.2 ad /*
4 1.1.4.2 ad * Copyright (c) 2006 Manuel Bouyer.
5 1.1.4.2 ad *
6 1.1.4.2 ad * Redistribution and use in source and binary forms, with or without
7 1.1.4.2 ad * modification, are permitted provided that the following conditions
8 1.1.4.2 ad * are met:
9 1.1.4.2 ad * 1. Redistributions of source code must retain the above copyright
10 1.1.4.2 ad * notice, this list of conditions and the following disclaimer.
11 1.1.4.2 ad * 2. Redistributions in binary form must reproduce the above copyright
12 1.1.4.2 ad * notice, this list of conditions and the following disclaimer in the
13 1.1.4.2 ad * documentation and/or other materials provided with the distribution.
14 1.1.4.2 ad * 3. All advertising materials mentioning features or use of this software
15 1.1.4.2 ad * must display the following acknowledgement:
16 1.1.4.2 ad * This product includes software developed by Manuel Bouyer.
17 1.1.4.2 ad * 4. The name of the author may not be used to endorse or promote products
18 1.1.4.2 ad * derived from this software without specific prior written permission.
19 1.1.4.2 ad *
20 1.1.4.2 ad * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1.4.2 ad * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1.4.2 ad * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1.4.2 ad * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1.4.2 ad * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1.4.2 ad * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1.4.2 ad * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1.4.2 ad * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1.4.2 ad * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1.4.2 ad * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1.4.2 ad *
31 1.1.4.2 ad */
32 1.1.4.2 ad
33 1.1.4.2 ad #include <dev/ic/ahcisatareg.h>
34 1.1.4.2 ad
35 1.1.4.2 ad #define AHCI_DEBUG
36 1.1.4.2 ad
37 1.1.4.2 ad #define DEBUG_INTR 0x01
38 1.1.4.2 ad #define DEBUG_XFERS 0x02
39 1.1.4.2 ad #define DEBUG_FUNCS 0x08
40 1.1.4.2 ad #define DEBUG_PROBE 0x10
41 1.1.4.2 ad #define DEBUG_DETACH 0x20
42 1.1.4.2 ad #ifdef AHCI_DEBUG
43 1.1.4.2 ad extern int ahcidebug_mask;
44 1.1.4.2 ad #define AHCIDEBUG_PRINT(args, level) \
45 1.1.4.2 ad if (ahcidebug_mask & (level)) \
46 1.1.4.2 ad printf args
47 1.1.4.2 ad #else
48 1.1.4.2 ad #define AHCIDEBUG_PRINT(args, level)
49 1.1.4.2 ad #endif
50 1.1.4.2 ad
51 1.1.4.2 ad struct ahci_softc {
52 1.1.4.2 ad struct atac_softc sc_atac;
53 1.1.4.2 ad bus_space_tag_t sc_ahcit; /* ahci registers mapping */
54 1.1.4.2 ad bus_space_handle_t sc_ahcih;
55 1.1.4.2 ad bus_dma_tag_t sc_dmat; /* DMA memory mappings: */
56 1.1.4.2 ad void *sc_cmd_hdr; /* command tables and received FIS */
57 1.1.4.2 ad bus_dmamap_t sc_cmd_hdrd;
58 1.1.4.2 ad
59 1.1.4.2 ad int sc_ncmds; /* number of command slots */
60 1.1.4.2 ad struct ata_channel *sc_chanarray[AHCI_MAX_PORTS];
61 1.1.4.2 ad struct ahci_channel {
62 1.1.4.2 ad struct ata_channel ata_channel; /* generic part */
63 1.1.4.2 ad bus_space_handle_t ahcic_scontrol;
64 1.1.4.2 ad bus_space_handle_t ahcic_sstatus;
65 1.1.4.2 ad bus_space_handle_t ahcic_serror;
66 1.1.4.2 ad /* pointers allocated from sc_cmd_hdrd */
67 1.1.4.2 ad struct ahci_r_fis *ahcic_rfis; /* received FIS */
68 1.1.4.2 ad bus_addr_t ahcic_bus_rfis;
69 1.1.4.2 ad struct ahci_cmd_header *ahcic_cmdh; /* command headers */
70 1.1.4.2 ad bus_addr_t ahcic_bus_cmdh;
71 1.1.4.2 ad /* command tables (allocated per-channel) */
72 1.1.4.2 ad bus_dmamap_t ahcic_cmd_tbld;
73 1.1.4.2 ad struct ahci_cmd_tbl *ahcic_cmd_tbl[AHCI_MAX_CMDS];
74 1.1.4.2 ad bus_addr_t ahcic_bus_cmd_tbl[AHCI_MAX_CMDS];
75 1.1.4.2 ad bus_dmamap_t ahcic_datad[AHCI_MAX_CMDS];
76 1.1.4.2 ad u_int32_t ahcic_cmds_active; /* active commands */
77 1.1.4.2 ad } sc_channels[AHCI_MAX_PORTS];
78 1.1.4.2 ad };
79 1.1.4.2 ad
80 1.1.4.2 ad #define AHCINAME(sc) ((sc)->sc_atac.atac_dev.dv_xname)
81 1.1.4.2 ad
82 1.1.4.2 ad #define AHCI_CMDH_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
83 1.1.4.2 ad (sc)->sc_cmd_hdrd, \
84 1.1.4.2 ad (char *)(&(achp)->ahcic_cmdh[(cmd)]) - (char *)(sc)->sc_cmd_hdr, \
85 1.1.4.2 ad sizeof(struct ahci_cmd_header), (op))
86 1.1.4.2 ad #define AHCI_RFIS_SYNC(sc, achp, op) bus_dmamap_sync((sc)->sc_dmat, \
87 1.1.4.2 ad (sc)->sc_cmd_hdrd, (void *)(achp)->ahcic_rfis - (sc)->sc_cmd_hdr, \
88 1.1.4.2 ad AHCI_RFIS_SIZE, (op))
89 1.1.4.2 ad #define AHCI_CMDTBL_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
90 1.1.4.2 ad (achp)->ahcic_cmd_tbld, AHCI_CMDTBL_SIZE * (cmd), \
91 1.1.4.2 ad AHCI_CMDTBL_SIZE, (op))
92 1.1.4.2 ad
93 1.1.4.2 ad #define AHCI_READ(sc, reg) bus_space_read_4((sc)->sc_ahcit, \
94 1.1.4.2 ad (sc)->sc_ahcih, (reg))
95 1.1.4.2 ad #define AHCI_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_ahcit, \
96 1.1.4.2 ad (sc)->sc_ahcih, (reg), (val))
97 1.1.4.2 ad
98 1.1.4.2 ad
99 1.1.4.2 ad void ahci_attach(struct ahci_softc *);
100 1.1.4.2 ad
101 1.1.4.2 ad int ahci_intr(void *);
102