aic6360.c revision 1.2
1 /* 2 * Copyright (c) 1994 Jarle Greipsland 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Jarle Greipsland 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * $Id: aic6360.c,v 1.2 1994/04/26 03:43:26 mycroft Exp $ 34 * 35 * Acknowledgements: Many of the algorithms used in this driver are 36 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 37 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 38 */ 39 40 /* TODO list: 41 * 1) Get the DMA stuff working. 42 * 2) Get the iov/uio stuff working. Is this a good thing ??? 43 * 3) Get the synch stuff working. 44 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 45 */ 46 47 /* 48 * A few customizable items: 49 */ 50 51 /* The SCSI ID of the host adapter/computer */ 52 #define AIC_SCSI_HOSTID 7 53 54 /* Use doubleword transfers to/from SCSI chip. Note: This requires 55 * motherboard support. Basicly, some motherboard chipsets are able to 56 * split a 32 bit I/O operation into two 16 bit I/O operations, 57 * transparently to the processor. This speeds up some things, notably long 58 * data transfers. 59 */ 60 #define AIC_USE_DWORDS 1 61 62 /* Allow disconnects? Was mainly used in an early phase of the driver when 63 * the message system was very flaky. Should go away soon. 64 */ 65 #define AIC_ALLOW_DISCONNECT 1 66 67 /* Synchronous data transfers? (does not work yet!) XXX */ 68 #define AIC_USE_SYNCHRONOUS 0 /* Enable/disable (1/0) */ 69 #define AIC_SYNC_PERIOD 200 70 #define AIC_SYNC_REQ_ACK_OFS 8 71 72 /* Max attempts made to transmit a message */ 73 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 74 75 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 76 #define AIC_USE_EISA_DMA 0 77 #define AIC_USE_ISA_DMA 0 78 79 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 80 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 81 82 /* Some spin loop parameters (essentially how long to wait some places) 83 * The problem(?) is that sometimes we expect either to be able to transmit a 84 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 85 * returning from the interrupt just to get yanked back for the next byte we 86 * may spin in the interrupt routine waiting for this byte to come. How long? 87 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 88 */ 89 #define AIC_MSGI_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 90 #define AIC_MSGO_SPIN 1 91 92 /* Include debug functions? At the end of this file there are a bunch of 93 * functions that will print out various information regarding queued SCSI 94 * commands, driver state and chip contents. You can call them from the 95 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 96 * kernel uses less memory) but you lose the debugging facilities. 97 */ 98 #define AIC_DEBUG 1 99 100 /* End of customizable parameters */ 101 102 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 103 #error "I said not yet! Start paying attention... grumble" 104 #endif 105 106 #include <sys/types.h> 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/kernel.h> 110 #include <sys/errno.h> 111 #include <sys/ioctl.h> 112 #include <sys/device.h> 113 #include <sys/buf.h> 114 #include <sys/proc.h> 115 #include <sys/user.h> 116 #include <sys/queue.h> 117 118 #include <machine/pio.h> 119 120 #include <scsi/scsi_all.h> 121 #include <scsi/scsiconf.h> 122 123 #include <i386/isa/isavar.h> 124 #include <i386/isa/icu.h> 125 126 /* Definitions, most of them has turned out to be unneccesary, but here they 127 * are anyway. 128 */ 129 130 /* 131 * Generic SCSI messages. For now we reject most of them. 132 */ 133 /* Messages (1 byte) */ /* I/T M(andatory) or (O)ptional */ 134 #define MSG_CMDCOMPLETE 0x00 /* M/M */ 135 #define MSG_EXTENDED 0x01 /* O/O */ 136 #define MSG_SAVEDATAPOINTER 0x02 /* O/O */ 137 #define MSG_RESTOREPOINTERS 0x03 /* O/O */ 138 #define MSG_DISCONNECT 0x04 /* O/O */ 139 #define MSG_INITIATOR_DET_ERR 0x05 /* M/M */ 140 #define MSG_ABORT 0x06 /* O/M */ 141 #define MSG_MESSAGE_REJECT 0x07 /* M/M */ 142 #define MSG_NOOP 0x08 /* M/M */ 143 #define MSG_PARITY_ERR 0x09 /* M/M */ 144 #define MSG_LINK_CMD_COMPLETE 0x0a /* O/O */ 145 #define MSG_LINK_CMD_COMPLETEF 0x0b /* O/O */ 146 #define MSG_BUS_DEV_RESET 0x0c /* O/M */ 147 #define MSG_ABORT_TAG 0x0d /* O/O */ 148 #define MSG_CLEAR_QUEUE 0x0e /* O/O */ 149 #define MSG_INIT_RECOVERY 0x0f /* O/O */ 150 #define MSG_REL_RECOVERY 0x10 /* O/O */ 151 #define MSG_TERM_IO_PROC 0x11 /* O/O */ 152 153 /* Messages (2 byte) */ 154 #define MSG_SIMPLE_Q_TAG 0x20 /* O/O */ 155 #define MSG_HEAD_OF_Q_TAG 0x21 /* O/O */ 156 #define MSG_ORDERED_Q_TAG 0x22 /* O/O */ 157 #define MSG_IGN_WIDE_RESIDUE 0x23 /* O/O */ 158 159 /* Identify message */ 160 #define MSG_IDENTIFY(lun) ((AIC_ALLOW_DISCONNECT ? 0xc0 : 0x80)|((lun) & 0x7)) 161 #define MSG_ISIDENT(m) ((m) & 0x80) 162 163 /* Extended messages (opcode) */ 164 #define MSG_EXT_SDTR 0x01 165 166 /* SCSI Status codes */ 167 #define ST_GOOD 0x00 168 #define ST_CHKCOND 0x02 169 #define ST_CONDMET 0x04 170 #define ST_BUSY 0x08 171 #define ST_INTERMED 0x10 172 #define ST_INTERMED_CONDMET 0x14 173 #define ST_RESERVATION_CONFLICT 0x18 174 #define ST_CMD_TERM 0x22 175 #define ST_QUEUE_FULL 0x28 176 177 #define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 178 179 /* AIC6360 definitions */ 180 #define SCSISEQ (iobase + 0x00) /* SCSI sequence control */ 181 #define SXFRCTL0 (iobase + 0x01) /* SCSI transfer control 0 */ 182 #define SXFRCTL1 (iobase + 0x02) /* SCSI transfer control 1 */ 183 #define SCSISIGI (iobase + 0x03) /* SCSI signal in */ 184 #define SCSISIGO (iobase + 0x03) /* SCSI signal out */ 185 #define SCSIRATE (iobase + 0x04) /* SCSI rate control */ 186 #define SCSIID (iobase + 0x05) /* SCSI ID */ 187 #define SELID (iobase + 0x05) /* Selection/Reselection ID */ 188 #define SCSIDAT (iobase + 0x06) /* SCSI Latched Data */ 189 #define SCSIBUS (iobase + 0x07) /* SCSI Data Bus*/ 190 #define STCNT0 (iobase + 0x08) /* SCSI transfer count */ 191 #define STCNT1 (iobase + 0x09) 192 #define STCNT2 (iobase + 0x0a) 193 #define CLRSINT0 (iobase + 0x0b) /* Clear SCSI interrupts 0 */ 194 #define SSTAT0 (iobase + 0x0b) /* SCSI interrupt status 0 */ 195 #define CLRSINT1 (iobase + 0x0c) /* Clear SCSI interrupts 1 */ 196 #define SSTAT1 (iobase + 0x0c) /* SCSI status 1 */ 197 #define SSTAT2 (iobase + 0x0d) /* SCSI status 2 */ 198 #define SCSITEST (iobase + 0x0e) /* SCSI test control */ 199 #define SSTAT3 (iobase + 0x0e) /* SCSI status 3 */ 200 #define CLRSERR (iobase + 0x0f) /* Clear SCSI errors */ 201 #define SSTAT4 (iobase + 0x0f) /* SCSI status 4 */ 202 #define SIMODE0 (iobase + 0x10) /* SCSI interrupt mode 0 */ 203 #define SIMODE1 (iobase + 0x11) /* SCSI interrupt mode 1 */ 204 #define DMACNTRL0 (iobase + 0x12) /* DMA control 0 */ 205 #define DMACNTRL1 (iobase + 0x13) /* DMA control 1 */ 206 #define DMASTAT (iobase + 0x14) /* DMA status */ 207 #define FIFOSTAT (iobase + 0x15) /* FIFO status */ 208 #define DMADATA (iobase + 0x16) /* DMA data */ 209 #define DMADATAL (iobase + 0x16) /* DMA data low byte */ 210 #define DMADATAH (iobase + 0x17) /* DMA data high byte */ 211 #define BRSTCNTRL (iobase + 0x18) /* Burst Control */ 212 #define DMADATALONG (iobase + 0x18) 213 #define PORTA (iobase + 0x1a) /* Port A */ 214 #define PORTB (iobase + 0x1b) /* Port B */ 215 #define REV (iobase + 0x1c) /* Revision (001 for 6360) */ 216 #define STACK (iobase + 0x1d) /* Stack */ 217 #define TEST (iobase + 0x1e) /* Test register */ 218 #define ID (iobase + 0x1f) /* ID register */ 219 220 #define IDSTRING "(C)1991ADAPTECAIC6360 " 221 222 /* What all the bits do */ 223 224 /* SCSISEQ */ 225 #define TEMODEO 0x80 226 #define ENSELO 0x40 227 #define ENSELI 0x20 228 #define ENRESELI 0x10 229 #define ENAUTOATNO 0x08 230 #define ENAUTOATNI 0x04 231 #define ENAUTOATNP 0x02 232 #define SCSIRSTO 0x01 233 234 /* SXFRCTL0 */ 235 #define SCSIEN 0x80 236 #define DMAEN 0x40 237 #define CHEN 0x20 238 #define CLRSTCNT 0x10 239 #define SPIOEN 0x08 240 #define CLRCH 0x02 241 242 /* SXFRCTL1 */ 243 #define BITBUCKET 0x80 244 #define SWRAPEN 0x40 245 #define ENSPCHK 0x20 246 #define STIMESEL1 0x10 247 #define STIMESEL0 0x08 248 #define STIMO_256ms 0x00 249 #define STIMO_128ms 0x08 250 #define STIMO_64ms 0x10 251 #define STIMO_32ms 0x18 252 #define ENSTIMER 0x04 253 #define BYTEALIGN 0x02 254 255 /* SCSISIGI */ 256 #define CDI 0x80 257 #define IOI 0x40 258 #define MSGI 0x20 259 #define ATNI 0x10 260 #define SELI 0x08 261 #define BSYI 0x04 262 #define REQI 0x02 263 #define ACKI 0x01 264 265 /* Important! The 3 most significant bits of this register, in initiator mode, 266 * represents the "expected" SCSI bus phase and can be used to trigger phase 267 * mismatch and phase change interrupts. But more important: If there is a 268 * phase mismatch the chip will not transfer any data! This is actually a nice 269 * feature as it gives us a bit more control over what is happening when we are 270 * bursting data (in) through the FIFOs and the phase suddenly changes from 271 * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 272 * proper phase to be set in this register instead of dumping the bits into the 273 * FIFOs. 274 */ 275 /* SCSISIGO */ 276 #define CDO 0x80 277 #define CDEXP (CDO) 278 #define IOO 0x40 279 #define IOEXP (IOO) 280 #define MSGO 0x20 281 #define MSGEXP (MSGO) 282 #define ATNO 0x10 283 #define SELO 0x08 284 #define BSYO 0x04 285 #define REQO 0x02 286 #define ACKO 0x01 287 288 /* Information transfer phases */ 289 #define PH_DOUT (0) 290 #define PH_DIN (IOI) 291 #define PH_CMD (CDI) 292 #define PH_STAT (CDI|IOI) 293 #define PH_MSGO (MSGI|CDI) 294 #define PH_MSGI (MSGI|CDI|IOI) 295 296 #define PH_MASK 0xe0 297 298 /* Some pseudo phases for getphase()*/ 299 #define PH_BUSFREE 0x100 /* (Re)Selection no longer valid */ 300 #define PH_INVALID 0x101 /* (Re)Selection valid, but no REQ yet */ 301 #define PH_PSBIT 0x100 /* "pseudo" bit */ 302 303 /* SCSIRATE */ 304 #define SXFR2 0x40 305 #define SXFR1 0x20 306 #define SXFR0 0x10 307 #define SOFS3 0x08 308 #define SOFS2 0x04 309 #define SOFS1 0x02 310 #define SOFS0 0x01 311 312 /* SCSI ID */ 313 #define OID2 0x40 314 #define OID1 0x20 315 #define OID0 0x10 316 #define OID_S 4 /* shift value */ 317 #define TID2 0x04 318 #define TID1 0x02 319 #define TID0 0x01 320 #define SCSI_ID_MASK 0x7 321 322 /* SCSI selection/reselection ID (both target *and* initiator) */ 323 #define SELID7 0x80 324 #define SELID6 0x40 325 #define SELID5 0x20 326 #define SELID4 0x10 327 #define SELID3 0x08 328 #define SELID2 0x04 329 #define SELID1 0x02 330 #define SELID0 0x01 331 332 /* CLRSINT0 Clears what? (interrupt and/or status bit) */ 333 #define SETSDONE 0x80 334 #define CLRSELDO 0x40 /* I */ 335 #define CLRSELDI 0x20 /* I+ */ 336 #define CLRSELINGO 0x10 /* I */ 337 #define CLRSWRAP 0x08 /* I+S */ 338 #define CLRSDONE 0x04 /* I+S */ 339 #define CLRSPIORDY 0x02 /* I */ 340 #define CLRDMADONE 0x01 /* I */ 341 342 /* SSTAT0 Howto clear */ 343 #define TARGET 0x80 344 #define SELDO 0x40 /* Selfclearing */ 345 #define SELDI 0x20 /* Selfclearing when CLRSELDI is set */ 346 #define SELINGO 0x10 /* Selfclearing */ 347 #define SWRAP 0x08 /* CLRSWAP */ 348 #define SDONE 0x04 /* Not used in initiator mode */ 349 #define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */ 350 #define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */ 351 352 /* CLRSINT1 Clears what? */ 353 #define CLRSELTIMO 0x80 /* I+S */ 354 #define CLRATNO 0x40 355 #define CLRSCSIRSTI 0x20 /* I+S */ 356 #define CLRBUSFREE 0x08 /* I+S */ 357 #define CLRSCSIPERR 0x04 /* I+S */ 358 #define CLRPHASECHG 0x02 /* I+S */ 359 #define CLRREQINIT 0x01 /* I+S */ 360 361 /* SSTAT1 How to clear? When set?*/ 362 #define SELTO 0x80 /* C select out timeout */ 363 #define ATNTARG 0x40 /* Not used in initiator mode */ 364 #define SCSIRSTI 0x20 /* C RST asserted */ 365 #define PHASEMIS 0x10 /* Selfclearing */ 366 #define BUSFREE 0x08 /* C bus free condition */ 367 #define SCSIPERR 0x04 /* C parity error on inbound data */ 368 #define PHASECHG 0x02 /* C phase in SCSISIGI doesn't match */ 369 #define REQINIT 0x01 /* C or ACK asserting edge of REQ */ 370 371 /* SSTAT2 */ 372 #define SOFFSET 0x20 373 #define SEMPTY 0x10 374 #define SFULL 0x08 375 #define SFCNT2 0x04 376 #define SFCNT1 0x02 377 #define SFCNT0 0x01 378 379 /* SCSITEST */ 380 #define SCTESTU 0x08 381 #define SCTESTD 0x04 382 #define STCTEST 0x01 383 384 /* SSTAT3 */ 385 #define SCSICNT3 0x80 386 #define SCSICNT2 0x40 387 #define SCSICNT1 0x20 388 #define SCSICNT0 0x10 389 #define OFFCNT3 0x08 390 #define OFFCNT2 0x04 391 #define OFFCNT1 0x02 392 #define OFFCNT0 0x01 393 394 /* CLRSERR */ 395 #define CLRSYNCERR 0x04 396 #define CLRFWERR 0x02 397 #define CLRFRERR 0x01 398 399 /* SSTAT4 */ 400 #define SYNCERR 0x04 401 #define FWERR 0x02 402 #define FRERR 0x01 403 404 /* SIMODE0 */ 405 #define ENSELDO 0x40 406 #define ENSELDI 0x20 407 #define ENSELINGO 0x10 408 #define ENSWRAP 0x08 409 #define ENSDONE 0x04 410 #define ENSPIORDY 0x02 411 #define ENDMADONE 0x01 412 413 /* SIMODE1 */ 414 #define ENSELTIMO 0x80 415 #define ENATNTARG 0x40 416 #define ENSCSIRST 0x20 417 #define ENPHASEMIS 0x10 418 #define ENBUSFREE 0x08 419 #define ENSCSIPERR 0x04 420 #define ENPHASECHG 0x02 421 #define ENREQINIT 0x01 422 423 /* DMACNTRL0 */ 424 #define ENDMA 0x80 425 #define B8MODE 0x40 426 #define DMA 0x20 427 #define DWORDPIO 0x10 428 #define WRITE 0x08 429 #define INTEN 0x04 430 #define RSTFIFO 0x02 431 #define SWINT 0x01 432 433 /* DMACNTRL1 */ 434 #define PWRDWN 0x80 435 #define ENSTK32 0x40 436 #define STK4 0x10 437 #define STK3 0x08 438 #define STK2 0x04 439 #define STK1 0x02 440 #define STK0 0x01 441 442 /* DMASTAT */ 443 #define ATDONE 0x80 444 #define WORDRDY 0x40 445 #define INTSTAT 0x20 446 #define DFIFOFULL 0x10 447 #define DFIFOEMP 0x08 448 #define DFIFOHF 0x04 449 #define DWORDRDY 0x02 450 451 /* BRSTCNTRL */ 452 #define BON3 0x80 453 #define BON2 0x40 454 #define BON1 0x20 455 #define BON0 0x10 456 #define BOFF3 0x08 457 #define BOFF2 0x04 458 #define BOFF1 0x02 459 #define BOFF0 0x01 460 461 /* TEST */ 462 #define BOFFTMR 0x40 463 #define BONTMR 0x20 464 #define STCNTH 0x10 465 #define STCNTM 0x08 466 #define STCNTL 0x04 467 #define SCSIBLK 0x02 468 #define DMABLK 0x01 469 470 471 #define orreg(reg, val) outb((reg), inb(reg)| (val)) 472 #define andreg(reg, val) outb((reg), inb(reg)& (val)) 473 #define nandreg(reg, val) outb((reg), inb(reg)&~(val)) 474 475 476 478 /* Grabbed from Julians SCSI aha-drivers */ 479 #ifdef DDB 480 int Debugger(); 481 #else DDB 482 #define Debugger() panic("should call debugger here (aic6360.c)") 483 #endif DDB 484 485 typedef u_long physaddr; 486 487 struct aic_dma_seg { 488 physaddr addr; 489 long len; 490 }; 491 492 extern int delaycount; 493 #define FUDGE(X) ((X)>>1) /* get 1 ms spincount */ 494 #define MINIFUDGE(X) ((X)>>4) /* get (approx) 125us spincount */ 495 #define AIC_NSEG 16 496 #define NUM_CONCURRENT 7 /* Only one per target for now */ 497 498 /* 499 * ACB. Holds additional information for each SCSI command Comments: We 500 * need a separate scsi command block because we may need to overwrite it 501 * with a request sense command. Basicly, we refrain from fiddling with 502 * the scsi_xfer struct (except do the expected updating of return values). 503 * We'll generally update: xs->{flags,resid,error,sense,status} and 504 * occasionally xs->retries. 505 */ 506 struct acb { 507 TAILQ_ENTRY(acb) chain; 508 struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */ 509 int flags; /* Status */ 510 #define ACB_FREE 0x00 511 #define ACB_ACTIVE 0x01 512 #define ACB_DONE 0x04 513 #define ACB_CHKSENSE 0x08 514 /* struct aic_dma_seg dma[AIC_NSEG]; /* Physical addresses+len */ 515 struct scsi_generic cmd; /* SCSI command block */ 516 int clen; 517 char *daddr; /* Saved data pointer */ 518 int dleft; /* Residue */ 519 int stat; /* SCSI status byte */ 520 }; 521 522 /* 523 * Some info about each (possible) target on the SCSI bus. This should 524 * probably have been a "per target+lunit" structure, but we'll leave it at 525 * this for now. Is there a way to reliably hook it up to sc->fordriver?? 526 */ 527 struct aic_tinfo { 528 int cmds; /* #commands processed */ 529 int dconns; /* #disconnects */ 530 int touts; /* #timeouts */ 531 int perrs; /* #parity errors */ 532 int senses; /* #request sense commands sent */ 533 ushort lubusy; /* What local units/subr. are busy? */ 534 u_char flags; 535 #define NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */ 536 #define DO_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */ 537 #define TARGET_BUSY 0x04 /* Target is busy, i.e. cmd in progress */ 538 u_char persgst; /* Period suggestion */ 539 u_char offsgst; /* Offset suggestion */ 540 u_char syncdata; /* True negotiated synch parameters */ 541 } tinfo_t; 542 543 /* Register a linenumber (for debugging) */ 544 #if AIC_DEBUG 545 #define LOGLINE(p) \ 546 do { \ 547 p->history[p->hp] = __LINE__; \ 548 p->hp = ++p->hp % AIC_HSIZE; \ 549 } while (0) 550 #else 551 #define LOGLINE(p) 552 #endif 553 554 struct aic_softc { /* One of these per adapter */ 555 /* Auto config stuff */ 556 struct device sc_dev; /* This one has to go first! */ 557 struct isadev sc_id; 558 struct intrhand sc_ih; 559 struct scsi_link sc_link; /* prototype for subdevs */ 560 int id_irq; /* IRQ on the EISA bus */ 561 int id_drq; /* DRQ on the EISA bus */ 562 u_short iobase; /* Base I/O port */ 563 /* Lists of command blocks */ 564 TAILQ_HEAD(acb_list, acb) free_list, ready_list, nexus_list; 565 struct acb *nexus; /* current command */ 566 /* Command blocks and target info */ 567 struct acb acb[NUM_CONCURRENT]; 568 struct aic_tinfo tinfo[8]; 569 /* Data about the current nexus (updated for every cmd switch) */ 570 u_char *dp; /* Current data pointer */ 571 int dleft; /* Data left to transfer */ 572 /* Adapter state */ 573 short phase; /* Copy of what bus phase we are in */ 574 short prevphase; /* Copy of what bus phase we were in */ 575 short state; /* State applicable to the adapter */ 576 #define AIC_IDLE 0x01 577 #define AIC_TMP_UNAVAIL 0x02 /* Don't accept SCSI commands */ 578 #define AIC_SELECTING 0x03 /* SCSI command is arbiting */ 579 #define AIC_RESELECTED 0x04 /* Has been reselected */ 580 #define AIC_HASNEXUS 0x05 /* Actively using the SCSI bus */ 581 #define AIC_CLEANING 0x06 582 short flags; 583 #define AIC_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 584 #define AIC_DOINGDMA 0x02 /* The FIFO data path is active! */ 585 #define AIC_BUSFREE_OK 0x04 /* Bus free phase is OK. */ 586 #define AIC_SYNCHNEGO 0x08 /* Synch negotiation in progress. */ 587 #define AIC_BLOCKED 0x10 /* Don't schedule new scsi bus operations */ 588 /* Debugging stuff */ 589 #define AIC_HSIZE 8 590 short history[AIC_HSIZE]; /* Store line numbers here. */ 591 short hp; 592 u_char progress; /* Set if interrupt has achieved progress */ 593 /* Message stuff */ 594 u_char msgpriq; /* One or more messages to send (encoded) */ 595 u_char msgout; /* What message is on its way out? */ 596 #define SEND_DEV_RESET 0x01 597 #define SEND_PARITY_ERROR 0x02 598 #define SEND_ABORT 0x04 599 #define SEND_REJECT 0x08 600 #define SEND_INIT_DET_ERR 0x10 601 #define SEND_IDENTIFY 0x20 602 #define SEND_SDTR 0x40 603 #define AIC_MAX_MSG_LEN 8 604 u_char omess[AIC_MAX_MSG_LEN]; /* Scratch area for messages */ 605 u_char *omp; /* Message pointer (for multibyte messages) */ 606 u_char omlen; 607 u_char imess[AIC_MAX_MSG_LEN + 1]; 608 u_char *imp; /* Message pointer (for multibyte messages) */ 609 u_char imlen; 610 }; 611 612 #define AIC_SHOWACBS 0x01 613 #define AIC_SHOWINTS 0x02 614 #define AIC_SHOWCMDS 0x04 615 #define AIC_SHOWMISC 0x08 616 #define AIC_SHOWTRAC 0x10 617 #define AIC_SHOWSTART 0x20 618 int aic_debug = 0; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRAC; /**/ 619 620 #if AIC_DEBUG 621 #define AIC_ACBS(str) do {if (aic_debug & AIC_SHOWACBS) printf str;} while (0) 622 #define AIC_MISC(str) do {if (aic_debug & AIC_SHOWMISC) printf str;} while (0) 623 #define AIC_INTS(str) do {if (aic_debug & AIC_SHOWINTS) printf str;} while (0) 624 #define AIC_TRACE(str) do {if (aic_debug & AIC_SHOWTRAC) printf str;} while (0) 625 #define AIC_CMDS(str) do {if (aic_debug & AIC_SHOWCMDS) printf str;} while (0) 626 #define AIC_START(str) do {if (aic_debug & AIC_SHOWSTART) printf str;}while (0) 627 #else 628 #define AIC_ACBS(str) 629 #define AIC_MISC(str) 630 #define AIC_INTS(str) 631 #define AIC_TRACE(str) 632 #define AIC_CMDS(str) 633 #define AIC_START(str) 634 #endif 635 636 int aicprobe __P((struct device *, struct device *, void *)); 637 void aicattach __P((struct device *, struct device *, void *)); 638 void aic_minphys __P((struct buf *)); 639 u_int aic_adapter_info __P((struct aic_softc *)); 640 int aicintr __P((struct aic_softc *)); 641 void aic_init __P((struct aic_softc *)); 642 void aic_done __P((struct acb *)); 643 int aic_scsi_cmd __P((struct scsi_xfer *)); 644 int aic_poll __P((struct aic_softc *, struct acb *)); 645 void aic_add_timeout __P((struct acb *, int)); 646 void aic_remove_timeout __P((struct acb *)); 647 void aic_timeout __P((caddr_t)); 648 int aic_find __P((struct aic_softc *)); 649 void aic_sched __P((struct aic_softc *)); 650 void aic_scsi_reset __P((struct aic_softc *)); 651 #if AIC_DEBUG 652 void aic_print_active_acb(); 653 void aic_dump_driver(); 654 void aic_dump6360(); 655 #endif 656 657 /* Linkup to the rest of the kernel */ 658 struct cfdriver aiccd = { 659 NULL, "aic", aicprobe, aicattach, DV_DULL, sizeof(struct aic_softc) 660 }; 661 662 struct scsi_adapter aic_switch = { 663 aic_scsi_cmd, 664 aic_minphys, 665 0, 666 0, 667 aic_adapter_info, 668 "aic" 669 }; 670 671 struct scsi_device aic_dev = { 672 NULL, /* Use default error handler */ 673 NULL, /* have a queue, served by this */ 674 NULL, /* have no async handler */ 675 NULL, /* Use default 'done' routine */ 676 "aic", 677 0 678 }; 679 680 /* 682 * INITIALIZATION ROUTINES (probe, attach ++) 683 */ 684 685 /* 686 * aicprobe: probe for AIC6360 SCSI-controller 687 * returns non-zero value if a controller is found. 688 */ 689 int 690 aicprobe(parent, self, aux) 691 struct device *parent, *self; 692 void *aux; 693 { 694 struct aic_softc *aic = (void *)self; 695 struct isa_attach_args *ia = aux; 696 int i, len, ic; 697 698 #ifdef NEWCONFIG 699 if (ia->ia_iobase == IOBASEUNK) 700 return 0; 701 #endif 702 aic->iobase = ia->ia_iobase; 703 if (aic_find(aic) != 0) 704 return 0; 705 #ifdef NEWCONFIG 706 if (ia->ia_irq == IRQUNK) 707 ia->ia_irq = (1 << aic->aic_int); 708 else if (ia->ia_irq != (1 << aic->aic_int)) { 709 printf("aic%d: irq mismatch, %x != %x\n", 710 aic->sc_dev.dv_unit, ia->ia_irq, 1 << aic->aic_int); 711 return 0; 712 } 713 714 if (ia->ia_drq == DRQUNK) 715 ia->ia_drq = aic->aic_dma; 716 else if (ia->ia_drq != aic->aic_dma) { 717 printf("aic%d: drq mismatch, %x != %x\n", 718 aic->sc_dev.dv_unit, ia->ia_drq, aic->aic_dma); 719 return 0; 720 } 721 #endif 722 ia->ia_msize = 0; 723 ia->ia_iosize = 0x20; 724 return 1; 725 } 726 727 /* Do the real search-for-device. 728 * Prerequisite: aic->iobase should be set to the proper value 729 */ 730 int 731 aic_find(aic) 732 struct aic_softc *aic; 733 { 734 u_short iobase = aic->iobase; 735 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 736 char *start; 737 int i; 738 739 /* Remove aic6360 from possible powerdown mode */ 740 outb(DMACNTRL0, 0); 741 742 /* Thanks to mark (at) aggregate.com for the new method for detecting 743 * whether the chip is present or not. Bonus: may also work for 744 * the AIC-6260! 745 */ 746 AIC_TRACE(("aic: probing for aic-chip at port 0x%x\n",(int)iobase)); 747 /* 748 * Linux also init's the stack to 1-16 and then clears it, 749 * 6260's don't appear to have an ID reg - mpg 750 */ 751 /* Push the sequence 0,1,..,15 on the stack */ 752 #define STSIZE 16 753 outb(DMACNTRL1, 0); /* Reset stack pointer */ 754 for (i = 0; i < STSIZE; i++) 755 outb(STACK, i); 756 757 /* See if we can pull out the same sequence */ 758 outb(DMACNTRL1, 0); 759 for (i = 0; i < STSIZE && inb(STACK) == i; i++) 760 ; 761 if (i != STSIZE) { 762 AIC_START(("STACK futzed at %d.\n", i)); 763 return ENXIO; 764 } 765 766 /* See if we can pull the id string out of the ID register, 767 * now only used for informational purposes. 768 */ 769 bzero(chip_id, sizeof(chip_id)); 770 insb(ID, chip_id, sizeof(IDSTRING)-1); 771 AIC_START(("AIC found at 0x%x ", (int)aic->iobase)); 772 AIC_START(("ID: %s ",chip_id)); 773 AIC_START(("chip revision %d\n",(int)inb(REV))); 774 return 0; 775 } 776 777 int 778 aicprint() 779 { 780 } 781 782 /* 783 * Attach the AIC6360, fill out some high and low level data structures 784 */ 785 void 786 aicattach(parent, self, aux) 787 struct device *parent, *self; 788 void *aux; 789 { 790 struct isa_attach_args *ia = aux; 791 struct aic_softc *aic = (void *)self; 792 793 AIC_TRACE(("aicattach\n")); 794 aic->state = 0; 795 aic_scsi_reset(aic); 796 aic_init(aic); /* Init chip and driver */ 797 798 /* 799 * Fill in the prototype scsi_link 800 */ 801 aic->sc_link.adapter_softc = aic; 802 aic->sc_link.adapter_targ = AIC_SCSI_HOSTID; 803 aic->sc_link.adapter = &aic_switch; 804 aic->sc_link.device = &aic_dev; 805 printf("\n"); 806 807 #ifdef NEWCONFIG 808 isa_establish(&aic->sc_id, &aic->sc_dev); 809 #endif 810 aic->sc_ih.ih_fun = aicintr; 811 aic->sc_ih.ih_arg = aic; 812 aic->sc_ih.ih_level = IPL_BIO; 813 intr_establish(ia->ia_irq, &aic->sc_ih); 814 815 config_found(self, &aic->sc_link, aicprint); 816 } 817 818 819 /* Initialize AIC6360 chip itself 820 * The following conditions should hold: 821 * aicprobe should have succeeded, i.e. the iobase address in aic_softc must 822 * be valid. 823 */ 824 static void 825 aic6360_reset(aic) 826 struct aic_softc *aic; 827 { 828 u_short iobase = aic->iobase; 829 830 outb(SCSITEST, 0); /* Doc. recommends to clear these two */ 831 outb(TEST, 0); /* registers before operations commence */ 832 833 /* Reset SCSI-FIFO and abort any transfers */ 834 outb(SXFRCTL0, CHEN|CLRCH|CLRSTCNT); 835 836 /* Reset DMA-FIFO */ 837 outb(DMACNTRL0, RSTFIFO); 838 outb(DMACNTRL1, 0); 839 840 outb(SCSISEQ, 0); /* Disable all selection features */ 841 outb(SXFRCTL1, 0); 842 843 outb(SIMODE0, 0x00); /* Disable some interrupts */ 844 outb(CLRSINT0, 0x7f); /* Clear a slew of interrupts */ 845 846 outb(SIMODE1, 0x00); /* Disable some more interrupts */ 847 outb(CLRSINT1, 0xef); /* Clear another slew of interrupts */ 848 849 outb(SCSIRATE, 0); /* Disable synchronous transfers */ 850 851 outb(CLRSERR, 0x07); /* Haven't seen ant errors (yet) */ 852 853 outb(SCSIID, AIC_SCSI_HOSTID << OID_S); /* Set our SCSI-ID */ 854 outb(BRSTCNTRL, EISA_BRST_TIM); 855 } 856 857 /* Pull the SCSI RST line for 500 us */ 858 void 859 aic_scsi_reset(aic) 860 struct aic_softc *aic; 861 { 862 u_short iobase = aic->iobase; 863 864 printf("aic: resetting SCSI bus\n"); 865 outb(SCSISEQ, SCSIRSTO); 866 delay(500); 867 outb(SCSISEQ, 0); 868 delay(50); 869 } 870 871 /* 872 * Initialize aic SCSI driver, also (conditonally) reset the SCSI bus. 873 * The reinitialization is still buggy (e.g. on SCSI resets). 874 */ 875 void 876 aic_init(aic) 877 struct aic_softc *aic; 878 { 879 u_short iobase = aic->iobase; 880 struct acb *acb; 881 int r; 882 883 if (!(inb(SSTAT1) & SCSIRSTI)) /* Reset the SCSI-bus itself */ 884 aic_scsi_reset(aic); 885 886 aic6360_reset(aic); /* Clean up our own hardware */ 887 888 /*XXX*/ /* If not the first time (probably a reset condition), 889 * we should clean queues with active commands 890 */ 891 if (aic->state == 0) { /* First time through */ 892 TAILQ_INIT(&aic->ready_list); 893 TAILQ_INIT(&aic->nexus_list); 894 TAILQ_INIT(&aic->free_list); 895 aic->nexus = 0; 896 acb = aic->acb; 897 bzero(acb, sizeof(aic->acb)); 898 for (r = 0; r < sizeof(aic->acb) / sizeof(*acb); r++) { 899 TAILQ_INSERT_TAIL(&aic->free_list, acb, chain); 900 acb++; 901 } 902 bzero(&aic->tinfo, sizeof(aic->tinfo)); 903 } else { 904 aic->state = AIC_CLEANING; 905 if (aic->nexus != NULL) { 906 aic->nexus->xs->error = XS_DRIVER_STUFFUP; 907 untimeout(aic_timeout, (caddr_t)aic->nexus); 908 aic_done(aic->nexus); 909 } 910 aic->nexus = NULL; 911 while (acb = aic->nexus_list.tqh_first) { 912 acb->xs->error = XS_DRIVER_STUFFUP; 913 untimeout(aic_timeout, (caddr_t)acb); 914 aic_done(acb); 915 } 916 } 917 918 aic->phase = aic->prevphase = PH_INVALID; 919 aic->hp = 0; 920 for (r = 0; r < 7; r++) { 921 struct aic_tinfo *tp = &aic->tinfo[r]; 922 tp->flags = AIC_USE_SYNCHRONOUS ? DO_NEGOTIATE : 0; 923 tp->flags |= NEED_TO_RESET; 924 tp->persgst = AIC_SYNC_PERIOD; 925 tp->offsgst = AIC_SYNC_REQ_ACK_OFS; 926 tp->syncdata = 0; 927 } 928 aic->state = AIC_IDLE; 929 outb(DMACNTRL0, INTEN); 930 return; 931 } 932 933 /* 935 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 936 */ 937 938 /* 939 * Expected sequence: 940 * 1) Command inserted into ready list 941 * 2) Command selected for execution 942 * 3) Command won arbitration and has selected target device 943 * 4) Send message out (identify message, eventually also sync.negotiations) 944 * 5) Send command 945 * 5a) Receive disconnect message, disconnect. 946 * 5b) Reselected by target 947 * 5c) Receive identify message from target. 948 * 6) Send or receive data 949 * 7) Receive status 950 * 8) Receive message (command complete etc.) 951 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 952 * Repeat 2-8 (no disconnects please...) 953 */ 954 955 /* 956 * Start a SCSI-command 957 * This function is called by the higher level SCSI-driver to queue/run 958 * SCSI-commands. 959 */ 960 int 961 aic_scsi_cmd(xs) 962 struct scsi_xfer *xs; 963 { 964 struct scsi_link *sc = xs->sc_link; 965 struct aic_softc *aic = sc->adapter_softc; 966 struct acb *acb; 967 int s, flags; 968 u_short iobase = aic->iobase; 969 970 SC_DEBUG(sc, SDEV_DB2, ("aic_scsi_cmd\n")); 971 AIC_TRACE(("aic_scsi_cmd\n")); 972 AIC_MISC(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 973 sc->target)); 974 975 flags = xs->flags; 976 977 /* Get a aic command block */ 978 if (!(flags & SCSI_NOMASK)) { 979 /* Critical region */ 980 s = splbio(); 981 acb = aic->free_list.tqh_first; 982 if (acb) { 983 TAILQ_REMOVE(&aic->free_list, acb, chain); 984 } 985 splx(s); 986 } else { 987 acb = aic->free_list.tqh_first; 988 if (acb) { 989 TAILQ_REMOVE(&aic->free_list, acb, chain); 990 } 991 } 992 993 if (acb == NULL) { 994 xs->error = XS_DRIVER_STUFFUP; 995 AIC_MISC(("TRY_AGAIN_LATER")); 996 return TRY_AGAIN_LATER; 997 } 998 999 /* Initialize acb */ 1000 acb->flags = ACB_ACTIVE; 1001 acb->xs = xs; 1002 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 1003 acb->clen = xs->cmdlen; 1004 acb->daddr = xs->data; 1005 acb->dleft = xs->datalen; 1006 acb->stat = 0; 1007 1008 if (!(flags & SCSI_NOMASK)) 1009 s = splbio(); 1010 1011 TAILQ_INSERT_TAIL(&aic->ready_list, acb, chain); 1012 timeout(aic_timeout, (caddr_t)acb, (xs->timeout*hz)/1000); 1013 1014 if (aic->state == AIC_IDLE) 1015 aic_sched(aic); 1016 1017 if (!(flags & SCSI_NOMASK)) { /* Almost done. Wait outside */ 1018 splx(s); 1019 AIC_MISC(("SUCCESSFULLY_QUEUED")); 1020 return SUCCESSFULLY_QUEUED; 1021 } 1022 1023 /* Not allowed to use interrupts, use polling instead */ 1024 return aic_poll(aic, acb); 1025 } 1026 1027 /* 1028 * Adjust transfer size in buffer structure 1029 */ 1030 void 1031 aic_minphys(bp) 1032 struct buf *bp; 1033 { 1034 1035 AIC_TRACE(("aic_minphys\n")); 1036 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 1037 bp->b_bcount = (AIC_NSEG << PGSHIFT); 1038 } 1039 1040 1041 u_int 1042 aic_adapter_info(aic) 1043 struct aic_softc *aic; 1044 { 1045 1046 AIC_TRACE(("aic_adapter_info\n")); 1047 return 2; /* One outstanding command per target */ 1048 } 1049 1050 /* 1051 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 1052 */ 1053 int 1054 aic_poll(aic, acb) 1055 struct aic_softc *aic; 1056 struct acb *acb; 1057 { 1058 register u_short iobase = aic->iobase; 1059 struct scsi_xfer *xs = acb->xs; 1060 int count = xs->timeout * 10; 1061 1062 AIC_TRACE(("aic_poll\n")); 1063 while (count) { 1064 if (inb(DMASTAT) & INTSTAT) 1065 aicintr(aic); 1066 if (xs->flags & ITSDONE) 1067 break; 1068 delay(100); 1069 count--; 1070 } 1071 if (count == 0) { 1072 AIC_MISC(("aic_poll: timeout")); 1073 aic_timeout((caddr_t)acb); 1074 } 1075 if (xs->error) 1076 return HAD_ERROR; 1077 return COMPLETE; 1078 } 1079 1080 /* LOW LEVEL SCSI UTILITIES */ 1082 1083 /* Determine the SCSI bus phase, return either a real SCSI bus phase or some 1084 * pseudo phase we use to detect certain exceptions. This one is a bit tricky. 1085 * The bits we peek at: 1086 * CDI, MSGI and DI is the 3 SCSI signals determining the bus phase. 1087 * These should be qualified by REQI high and ACKI low. 1088 * Also peek at SSTAT0[SELDO|SELDI] to detect a passing BUSFREE condition. 1089 * No longer detect SCSI RESET or PERR here. They are tested for separately 1090 * in the interrupt handler. 1091 * Note: If an exception occur at some critical time during the phase 1092 * determination we'll most likely return something wildly erronous.... 1093 */ 1094 static inline u_short 1095 aicphase(aic) 1096 struct aic_softc *aic; 1097 { 1098 register u_short iobase = aic->iobase; 1099 register u_char sstat0, sstat1, scsisig; 1100 1101 sstat1 = inb(SSTAT1); /* Look for REQINIT (REQ asserted) */ 1102 scsisig = inb(SCSISIGI); /* Get the SCSI bus signals */ 1103 sstat0 = inb(SSTAT0); /* Get the selection valid status bits */ 1104 1105 if (!(inb(SSTAT0) & (SELDO|SELDI))) /* Selection became invalid? */ 1106 return PH_BUSFREE; 1107 1108 /* Selection is still valid */ 1109 if (!(sstat1 & REQINIT)) /* REQ not asserted ? */ 1110 return PH_INVALID; 1111 1112 /* REQ is asserted, (and ACK is not) */ 1113 return scsisig & PH_MASK; 1114 } 1115 1116 1117 /* Schedule a scsi operation. This has now been pulled out of the interrupt 1119 * handler so that we may call it from aic_scsi_cmd and aic_done. This may 1120 * save us an unecessary interrupt just to get things going. Should only be 1121 * called when state == AIC_IDLE and at bio pl. 1122 */ 1123 void 1124 aic_sched(aic) 1125 register struct aic_softc *aic; 1126 { 1127 struct scsi_xfer *xs; 1128 struct scsi_link *sc; 1129 struct acb *acb; 1130 u_short iobase = aic->iobase; 1131 int t, l; 1132 u_char simode0, simode1, scsiseq; 1133 1134 AIC_TRACE(("aic_sched\n")); 1135 simode0 = ENSELDI; 1136 simode1 = ENSCSIRST|ENSCSIPERR|ENREQINIT; 1137 scsiseq = ENRESELI; 1138 /* 1139 * Find first acb in rdy queue that is for a target/lunit 1140 * combinations that is not busy. 1141 */ 1142 outb(CLRSINT1, CLRSELTIMO|CLRBUSFREE|CLRSCSIPERR); 1143 for (acb = aic->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 1144 sc = acb->xs->sc_link; 1145 t = sc->target; 1146 if (!(aic->tinfo[t].lubusy & (1 << sc->lun))) { 1147 TAILQ_REMOVE(&aic->ready_list, acb, chain); 1148 aic->nexus = acb; 1149 aic->state = AIC_SELECTING; 1150 /* 1151 * Start selection process. Always enable 1152 * reselections. Note: we don't have a nexus yet, so 1153 * cannot set aic->state = AIC_HASNEXUS. 1154 */ 1155 simode0 = ENSELDI|ENSELDO; 1156 simode1 = ENSCSIRST|ENSCSIPERR| 1157 ENREQINIT|ENSELTIMO; 1158 scsiseq = ENRESELI|ENSELO|ENAUTOATNO; 1159 outb(SCSIID, AIC_SCSI_HOSTID << OID_S | t); 1160 outb(SXFRCTL1, STIMO_256ms|ENSTIMER); 1161 outb(CLRSINT0, CLRSELDO); 1162 break; 1163 } else 1164 AIC_MISC(("%d:%d busy\n", t, sc->lun)); 1165 } 1166 AIC_MISC(("%sselecting\n",scsiseq&ENSELO?"":"re")); 1167 outb(SIMODE0, simode0); 1168 outb(SIMODE1, simode1); 1169 outb(SCSISEQ, scsiseq); 1170 } 1171 1172 1173 /* 1175 * POST PROCESSING OF SCSI_CMD (usually current) 1176 */ 1177 void 1178 aic_done(acb) 1179 struct acb *acb; 1180 { 1181 struct scsi_xfer *xs = acb->xs; 1182 struct scsi_link *sc = xs->sc_link; 1183 struct aic_softc *aic = sc->adapter_softc; 1184 u_short iobase = aic->iobase; 1185 struct acb *acb2; 1186 1187 AIC_TRACE(("aic_done ")); 1188 1189 /* 1190 * Now, if we've come here with no error code, i.e. we've kept the 1191 * initial XS_NOERROR, and the status code signals that we should 1192 * check sense, we'll need to set up a request sense cmd block and 1193 * push the command back into the ready queue *before* any other 1194 * commands for this target/lunit, else we lose the sense info. 1195 * We don't support chk sense conditions for the request sense cmd. 1196 */ 1197 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 1198 if ((acb->stat & ST_MASK)==SCSI_CHECK) { 1199 struct scsi_sense *ss = (void *)&acb->cmd; 1200 AIC_MISC(("requesting sense ")); 1201 /* First, save the return values */ 1202 xs->resid = acb->dleft; 1203 xs->status = acb->stat; 1204 /* Next, setup a request sense command block */ 1205 bzero(ss, sizeof(*ss)); 1206 ss->op_code = REQUEST_SENSE; 1207 ss->byte2 = sc->lun << 5; 1208 ss->length = sizeof(struct scsi_sense_data); 1209 acb->clen = sizeof(*ss); 1210 acb->daddr = (char *)&xs->sense; 1211 acb->dleft = sizeof(struct scsi_sense_data); 1212 acb->flags = ACB_ACTIVE|ACB_CHKSENSE; 1213 TAILQ_INSERT_HEAD(&aic->ready_list, acb, chain); 1214 aic->tinfo[sc->target].lubusy &= ~(1<<sc->lun); 1215 aic->tinfo[sc->target].senses++; 1216 if (aic->nexus == acb) { 1217 aic->nexus = NULL; 1218 aic->state = AIC_IDLE; 1219 aic_sched(aic); 1220 } 1221 return; 1222 } 1223 } 1224 1225 if (xs->flags & SCSI_ERR_OK) { 1226 xs->resid = 0; 1227 xs->error = XS_NOERROR; 1228 } else if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 1229 xs->error = XS_SENSE; 1230 } else { 1231 xs->resid = acb->dleft; 1232 } 1233 xs->flags |= ITSDONE; 1234 1235 #if AIC_DEBUG 1236 if (aic_debug & AIC_SHOWMISC) { 1237 printf("err=0x%02x ",xs->error); 1238 if (xs->error == XS_SENSE) 1239 printf("sense=%2x\n", xs->sense.error_code); 1240 } 1241 if ((xs->resid || xs->error > XS_SENSE) && aic_debug & AIC_SHOWMISC) { 1242 if (xs->resid) 1243 printf("aic_done: resid=%d\n", xs->resid); 1244 if (xs->error) 1245 printf("aic_done: error=%d\n", xs->error); 1246 } 1247 #endif 1248 1249 /* 1250 * Remove the ACB from whatever queue it's on. We have to do a bit of 1251 * a hack to figure out which queue it's on. Note that it is *not* 1252 * necessary to cdr down the ready queue, but we must cdr down the 1253 * nexus queue and see if it's there, so we can mark the unit as no 1254 * longer busy. This code is sickening, but it works. 1255 */ 1256 if (acb == aic->nexus) { 1257 aic->state = AIC_IDLE; 1258 aic->tinfo[sc->target].lubusy &= ~(1<<sc->lun); 1259 aic_sched(aic); 1260 } else if (aic->ready_list.tqh_last == &acb->chain.tqe_next) { 1261 TAILQ_REMOVE(&aic->ready_list, acb, chain); 1262 } else { 1263 register struct acb *acb2; 1264 for (acb2 = aic->nexus_list.tqh_first; acb2; 1265 acb2 = acb2->chain.tqe_next) 1266 if (acb2 == acb) { 1267 TAILQ_REMOVE(&aic->nexus_list, acb, chain); 1268 aic->tinfo[sc->target].lubusy &= ~(1<<sc->lun); 1269 /* XXXX Should we call aic_sched() here? */ 1270 break; 1271 } 1272 if (acb2) 1273 ; 1274 else if (acb->chain.tqe_next) { 1275 TAILQ_REMOVE(&aic->ready_list, acb, chain); 1276 } else { 1277 printf("%s: can't find matching acb\n", 1278 aic->sc_dev.dv_xname); 1279 Debugger(); 1280 } 1281 } 1282 /* Put it on the free list. */ 1283 acb->flags = ACB_FREE; 1284 TAILQ_INSERT_HEAD(&aic->free_list, acb, chain); 1285 1286 aic->tinfo[sc->target].cmds++; 1287 scsi_done(xs); 1288 return; 1289 } 1290 1291 /* 1293 * INTERRUPT/PROTOCOL ENGINE 1294 */ 1295 1296 /* The message system: 1297 * This is a revamped message system that now should easier accomodate new 1298 * messages, if necessary. 1299 * Currently we accept these messages: 1300 * IDENTIFY (when reselecting) 1301 * COMMAND COMPLETE # (expect bus free after messages marked #) 1302 * NOOP 1303 * MESSAGE REJECT 1304 * SYNCHRONOUS DATA TRANSFER REQUEST 1305 * SAVE DATA POINTER 1306 * RESTORE POINTERS 1307 * DISCONNECT # 1308 * 1309 * We may send these messages in prioritized order: 1310 * BUS DEVICE RESET # if SCSI_RESET & xs->flags (or in weird sits.) 1311 * MESSAGE PARITY ERROR par. err. during MSGI 1312 * MESSAGE REJECT If we get a message we don't know how to handle 1313 * ABORT # send on errors 1314 * INITIATOR DETECTED ERROR also on errors (SCSI2) (during info xfer) 1315 * IDENTIFY At the start of each transfer 1316 * SYNCHRONOUS DATA TRANSFER REQUEST if appropriate 1317 * NOOP if nothing else fits the bill ... 1318 */ 1319 1320 #define aic_sched_msgout(m) \ 1321 do { \ 1322 orreg(SCSISIGO, ATNO); \ 1323 aic->msgpriq |= (m); \ 1324 } while (0) 1325 1326 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) >= 0x80) 1327 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1328 #define ISEXTMSG(m) ((m) == 1) 1329 /* Precondition: 1330 * The SCSI bus is already in the MSGI phase and there is a message byte 1331 * on the bus, along with an asserted REQ signal. 1332 */ 1333 static void 1334 aic_msgin(aic) 1335 register struct aic_softc *aic; 1336 { 1337 register u_short iobase = aic->iobase; 1338 int spincount, extlen; 1339 u_char sstat1; 1340 1341 AIC_TRACE(("aic_msgin ")); 1342 outb(SCSISIGO, PH_MSGI); 1343 /* Prepare for a new message. A message should (according to the SCSI 1344 * standard) be transmitted in one single message_in phase. 1345 * If we have been in some other phase, then this is a new message. 1346 */ 1347 if (aic->prevphase != PH_MSGI) { 1348 aic->flags &= ~AIC_DROP_MSGI; 1349 aic->imlen = 0; 1350 } 1351 /* 1352 * Read a whole message but the last byte. If we shall reject the 1353 * message, we shall have to do it, by asserting ATNO, during the 1354 * message transfer phase itself. 1355 */ 1356 for (;;) { 1357 sstat1 = inb(SSTAT1); 1358 /* If parity errors just dump everything on the floor, also 1359 * a parity error automatically sets ATNO 1360 */ 1361 if (sstat1 & SCSIPERR) { 1362 aic_sched_msgout(SEND_PARITY_ERROR); 1363 aic->flags |= AIC_DROP_MSGI; 1364 } 1365 /* 1366 * If we're going to reject the message, don't bother storing 1367 * the incoming bytes. But still, we need to ACK them. 1368 */ 1369 if (!(aic->flags & AIC_DROP_MSGI)) { 1370 /* Get next message byte */ 1371 aic->imess[aic->imlen] = inb(SCSIDAT); 1372 /* 1373 * This testing is suboptimal, but most messages will 1374 * be of the one byte variety, so it should not effect 1375 * performance significantly. 1376 */ 1377 if (IS1BYTEMSG(aic->imess[0])) 1378 break; 1379 if (IS2BYTEMSG(aic->imess[0]) && aic->imlen == 1) 1380 break; 1381 if (ISEXTMSG(aic->imess[0]) && aic->imlen > 0) { 1382 if (aic->imlen == AIC_MAX_MSG_LEN) { 1383 aic->flags |= AIC_DROP_MSGI; 1384 aic_sched_msgout(SEND_REJECT); 1385 } 1386 extlen = aic->imess[1] ? aic->imess[1] : 256; 1387 if (aic->imlen == extlen + 2) 1388 break; /* Got it all */ 1389 } 1390 } 1391 /* If we reach this spot we're either: 1392 * a) in the middle of a multi-byte message or 1393 * b) we're dropping bytes 1394 */ 1395 outb(SXFRCTL0, CHEN|SPIOEN); 1396 inb(SCSIDAT); /* Really read it (ACK it, that is) */ 1397 outb(SXFRCTL0, CHEN); 1398 aic->imlen++; 1399 1400 /* 1401 * We expect the bytes in a multibyte message to arrive 1402 * relatively close in time, a few microseconds apart. 1403 * Therefore we will spinwait for some small amount of time 1404 * waiting for the next byte. 1405 */ 1406 spincount = MINIFUDGE(delaycount) * AIC_MSGI_SPIN; 1407 LOGLINE(aic); 1408 while (spincount-- && !((sstat1 = inb(SSTAT1)) & REQINIT)) 1409 ; 1410 if (spincount == -1 || sstat1 & (PHASEMIS|BUSFREE)) 1411 return; 1412 } 1413 /* Now we should have a complete message (1 byte, 2 byte and moderately 1414 * long extended messages). We only handle extended messages which 1415 * total length is shorter than AIC_MAX_MSG_LEN. Longer messages will 1416 * be amputated. (Return XS_BOBBITT ?) 1417 */ 1418 if (aic->state == AIC_HASNEXUS) { 1419 struct acb *acb = aic->nexus; 1420 struct aic_tinfo *ti = &aic->tinfo[acb->xs->sc_link->target]; 1421 int offs, per, rate; 1422 1423 outb(SIMODE1, ENSCSIRST|ENPHASEMIS|ENBUSFREE|ENSCSIPERR); 1424 switch (aic->imess[0]) { 1425 case MSG_CMDCOMPLETE: 1426 if (!acb) { 1427 aic_sched_msgout(MSG_ABORT); 1428 printf("aic: CMDCOMPLETE but no command?\n"); 1429 break; 1430 } 1431 if (aic->dleft < 0) { 1432 struct scsi_link *sc = acb->xs->sc_link; 1433 printf("aic: %d extra bytes from %d:%d\n", 1434 -aic->dleft, sc->target, sc->lun); 1435 acb->dleft = 0; 1436 } 1437 acb->xs->resid = acb->dleft = aic->dleft; 1438 aic->flags |= AIC_BUSFREE_OK; 1439 untimeout(aic_timeout, (caddr_t)acb); 1440 aic_done(acb); 1441 break; 1442 case MSG_MESSAGE_REJECT: 1443 if (aic_debug & AIC_SHOWMISC) 1444 printf("aic: our msg rejected by target\n"); 1445 if (aic->flags & AIC_SYNCHNEGO) { 1446 ti->syncdata = 0; 1447 ti->persgst = ti->offsgst = 0; 1448 aic->flags &= ~AIC_SYNCHNEGO; 1449 ti->flags &= ~DO_NEGOTIATE; 1450 } 1451 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1452 if (aic->msgout == SEND_INIT_DET_ERR) 1453 aic_sched_msgout(SEND_ABORT); 1454 break; 1455 case MSG_NOOP: /* Will do! Immediately, sir!*/ 1456 break; /* Hah, that was easy! */ 1457 case MSG_DISCONNECT: 1458 if (!acb) { 1459 aic_sched_msgout(MSG_ABORT); 1460 printf("aic: nothing to DISCONNECT\n"); 1461 break; 1462 } 1463 ti->dconns++; 1464 TAILQ_INSERT_HEAD(&aic->nexus_list, acb, chain); 1465 acb = aic->nexus = NULL; 1466 aic->state = AIC_IDLE; 1467 aic->flags |= AIC_BUSFREE_OK; 1468 break; 1469 case MSG_SAVEDATAPOINTER: 1470 if (!acb) { 1471 aic_sched_msgout(MSG_ABORT); 1472 printf("aic: no DATAPOINTERs to save\n"); 1473 break; 1474 } 1475 acb->dleft = aic->dleft; 1476 acb->daddr = aic->dp; 1477 break; 1478 case MSG_RESTOREPOINTERS: 1479 if (!acb) { 1480 aic_sched_msgout(MSG_ABORT); 1481 printf("aic: no DATAPOINTERs to restore\n"); 1482 break; 1483 } 1484 aic->dp = acb->daddr; 1485 aic->dleft = acb->dleft; 1486 break; 1487 case MSG_EXTENDED: 1488 switch (aic->imess[2]) { 1489 case MSG_EXT_SDTR: 1490 per = aic->imess[3] * 4; 1491 rate = (per + 49 - 100)/50; 1492 offs = aic->imess[4]; 1493 if (offs == 0) 1494 ti->syncdata = 0; 1495 else if (rate > 7) { 1496 /* Too slow for aic6360. Do asynch 1497 * instead. Renegotiate the deal. 1498 */ 1499 ti->persgst = 0; 1500 ti->offsgst = 0; 1501 aic_sched_msgout(SEND_SDTR); 1502 } else { 1503 rate = rate<<4 | offs; 1504 ti->syncdata = rate; 1505 } 1506 break; 1507 default: /* Extended messages we don't handle */ 1508 aic_sched_msgout(MSG_MESSAGE_REJECT); 1509 break; 1510 } 1511 break; 1512 default: 1513 aic_sched_msgout(MSG_MESSAGE_REJECT); 1514 break; 1515 } 1516 /* Don't forget to acknowledge the byte */ 1517 outb(SXFRCTL0, CHEN|SPIOEN); 1518 inb(SCSIDAT); 1519 outb(SXFRCTL0, CHEN); 1520 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 1521 return; 1522 } 1523 else if (aic->state == AIC_RESELECTED) { 1524 struct scsi_link *sc; 1525 struct acb *acb; 1526 u_char selid, lunit; 1527 /* 1528 * Which target is reselecting us? (The ID bit really) 1529 */ 1530 selid = inb(SELID) & ~(1<<AIC_SCSI_HOSTID); 1531 if (MSG_ISIDENT(aic->imess[0])) { /* Identify? */ 1532 AIC_MISC(("searching ")); 1533 /* Search wait queue for disconnected cmd 1534 * The list should be short, so I haven't bothered with 1535 * any more sophisticated structures than a simple 1536 * singly linked list. 1537 */ 1538 lunit = aic->imess[0] & 0x07; 1539 for (acb = aic->nexus_list.tqh_first; acb; 1540 acb = acb->chain.tqe_next) { 1541 sc = acb->xs->sc_link; 1542 if (sc->lun == lunit && 1543 selid == (1<<sc->target)) { 1544 TAILQ_REMOVE(&aic->nexus_list, acb, 1545 chain); 1546 break; 1547 } 1548 } 1549 if (!acb) { /* Invalid reselection! */ 1550 aic_sched_msgout(SEND_ABORT); 1551 printf("aic: invalid reselect (idbit=0x%2x)\n", 1552 selid); 1553 } else { /* Reestablish nexus */ 1554 /* Setup driver data structures and 1555 * do an implicit RESTORE POINTERS 1556 */ 1557 aic->nexus = acb; 1558 aic->dp = acb->daddr; 1559 aic->dleft = acb->dleft; 1560 aic->tinfo[sc->target].lubusy |= (1<<sc->lun); 1561 outb(SCSIRATE,aic->tinfo[sc->target].syncdata); 1562 AIC_MISC(("... found acb")); 1563 aic->state = AIC_HASNEXUS; 1564 } 1565 } else { 1566 printf("aic: bogus reselect (no IDENTIFY) %0x2x\n", 1567 selid); 1568 aic_sched_msgout(SEND_DEV_RESET); 1569 } 1570 /* Must not forget to ACK the last message byte ... */ 1571 outb(SXFRCTL0, CHEN|SPIOEN); 1572 inb(SCSIDAT); 1573 outb(SXFRCTL0, CHEN); 1574 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 1575 return; 1576 } else { /* Neither AIC_HASNEXUS nor AIC_RESELECTED! */ 1577 printf("aic: unexpected message in; will send DEV_RESET\n"); 1578 aic_sched_msgout(SEND_DEV_RESET); 1579 outb(SXFRCTL0, CHEN|SPIOEN); 1580 inb(SCSIDAT); 1581 outb(SXFRCTL0, CHEN); 1582 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 1583 return; 1584 } 1585 } 1586 1587 1588 /* The message out (and in) stuff is a bit complicated: 1589 * If the target requests another message (sequence) without 1590 * having changed phase in between it really asks for a 1591 * retransmit, probably due to parity error(s). 1592 * The following messages can be sent: 1593 * IDENTIFY @ These 3 stems from scsi command activity 1594 * BUS_DEV_RESET @ 1595 * IDENTIFY + SDTR @ 1596 * MESSAGE_REJECT if MSGI doesn't make sense 1597 * MESSAGE_PARITY_ERROR if MSGI spots a parity error 1598 * NOOP if asked for a message and there's nothing to send 1599 */ 1600 static void 1601 aic_msgout(aic) 1602 register struct aic_softc *aic; 1603 { 1604 register u_short iobase = aic->iobase; 1605 struct aic_tinfo *ti; 1606 struct acb *acb; 1607 u_char dmastat, scsisig; 1608 1609 /* First determine what to send. If we haven't seen a 1610 * phasechange this is a retransmission request. 1611 */ 1612 outb(SCSISIGO, PH_MSGO); 1613 if (aic->prevphase != PH_MSGO) { /* NOT a retransmit */ 1614 /* Pick up highest priority message */ 1615 aic->msgout = aic->msgpriq & -aic->msgpriq; /* What message? */ 1616 aic->omlen = 1; /* "Default" message len */ 1617 switch (aic->msgout) { 1618 case SEND_SDTR: /* Also implies an IDENTIFY message */ 1619 acb = aic->nexus; 1620 ti = &aic->tinfo[acb->xs->sc_link->target]; 1621 aic->omess[1] = MSG_EXTENDED; 1622 aic->omess[2] = 3; 1623 aic->omess[3] = MSG_EXT_SDTR; 1624 aic->omess[4] = ti->persgst >> 2; 1625 aic->omess[5] = ti->offsgst; 1626 aic->omlen = 6; 1627 /* Fallthrough! */ 1628 case SEND_IDENTIFY: 1629 if (aic->state != AIC_HASNEXUS) { 1630 printf("aic at line %d: no nexus", __LINE__); 1631 Debugger(); 1632 } 1633 acb = aic->nexus; 1634 aic->omess[0] = MSG_IDENTIFY(acb->xs->sc_link->lun); 1635 break; 1636 case SEND_DEV_RESET: 1637 aic->omess[0] = MSG_BUS_DEV_RESET; 1638 aic->flags |= AIC_BUSFREE_OK; 1639 break; 1640 case SEND_PARITY_ERROR: 1641 aic->omess[0] = MSG_PARITY_ERR; 1642 break; 1643 case SEND_ABORT: 1644 aic->omess[0] = MSG_ABORT; 1645 aic->flags |= AIC_BUSFREE_OK; 1646 break; 1647 case SEND_INIT_DET_ERR: 1648 aic->omess[0] = MSG_INITIATOR_DET_ERR; 1649 break; 1650 case SEND_REJECT: 1651 aic->omess[0] = MSG_MESSAGE_REJECT; 1652 break; 1653 default: 1654 aic->omess[0] = MSG_NOOP; 1655 break; 1656 } 1657 aic->omp = aic->omess; 1658 } 1659 else if (aic->omp == &aic->omess[aic->omlen]) { 1660 /* Have sent the message at least once, this is a retransmit. 1661 */ 1662 AIC_MISC(("retransmitting ")); 1663 if (aic->omlen > 1) 1664 outb(SCSISIGO, PH_MSGO|ATNO); 1665 } 1666 /* else, we're in the middle of a multi-byte message */ 1667 outb(SXFRCTL0, CHEN|SPIOEN); 1668 outb(DMACNTRL0, INTEN|RSTFIFO); 1669 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 1670 do { 1671 LOGLINE(aic); 1672 do { 1673 aic->phase = aicphase(aic); 1674 } while (aic->phase == PH_INVALID); 1675 if (aic->phase != PH_MSGO) 1676 /* Target left MSGO, possibly to reject our 1677 * message 1678 */ 1679 break; 1680 /* Clear ATN before last byte */ 1681 if (aic->omp == &aic->omess[aic->omlen-1]) 1682 outb(CLRSINT1, CLRATNO); 1683 outb(SCSIDAT, *aic->omp++); /* Send MSG */ 1684 LOGLINE(aic); 1685 while (inb(SCSISIGI) & ACKO) 1686 ; 1687 } while (aic->omp != &aic->omess[aic->omlen]); 1688 aic->progress = aic->omp != aic->omess; 1689 /* We get here in two ways: 1690 * a) phase != MSGO. Target is probably going to reject our message 1691 * b) aic->omp == &aic->omess[aic->omlen], i.e. the message has been 1692 * transmitted correctly and accepted by the target. 1693 */ 1694 if (aic->phase == PH_MSGO) { /* Message accepted by target! */ 1695 aic->msgpriq &= ~aic->msgout; 1696 aic->msgout = 0; 1697 } 1698 outb(SXFRCTL0, CHEN); /* Disable SPIO */ 1699 outb(SIMODE0, 0); /* Setup interrupts before leaving */ 1700 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 1701 /* Enabled ints: SCSIPERR, SCSIRSTI (unexpected) 1702 * REQINIT (expected) BUSFREE (possibly expected) 1703 */ 1704 } 1705 1706 /* aic_dataout: perform a data transfer using the FIFO datapath in the aic6360 1707 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1708 * and ACK deasserted (i.e. waiting for a data byte) 1709 * This new revision has been optimized (I tried) to make the common case fast, 1710 * and the rarer cases (as a result) somewhat more comlex 1711 */ 1712 void 1713 aic_dataout(aic) 1714 register struct aic_softc *aic; 1715 { 1716 register u_short iobase = aic->iobase; 1717 register unsigned xfers; 1718 register u_char dmastat; 1719 struct acb *acb = aic->nexus; 1720 int amount, olddleft = aic->dleft; 1721 #if AIC_USE_DWORDS 1722 #define B_MASK 3 1723 #define C_SHIFT 2 1724 #else 1725 #define B_MASK 1 1726 #define C_SHIFT 1 1727 #endif 1728 #define DOUTAMOUNT 64 /* Half a FIFO */ 1729 1730 AIC_TRACE(("aic_dataout\n")); 1731 /* Setup for normal mode transfers, p6-5 in doc. */ 1732 /* 1) Set DOUT phase in SCSISIG register 1733 * 2) Turn off data path 1734 * 3) Reset all FIFOs and counters 1735 * 4) Enable the datachannel 1736 */ 1737 outb(SCSISIGO, PH_DOUT); 1738 outb(CLRSINT1, CLRPHASECHG); 1739 outb(DMACNTRL0, WRITE|INTEN|RSTFIFO); 1740 outb(SXFRCTL0, CHEN|CLRCH|CLRSTCNT); 1741 outb(SXFRCTL0, SCSIEN|DMAEN|CHEN); 1742 outb(DMACNTRL0, ENDMA|DWORDPIO|WRITE|INTEN); 1743 1744 /* Setup to detect: 1745 * PHASEMIS & PHASECHG: target has left the DOUT phase 1746 * SCSIRST: something just pulled the RST line. 1747 * BUSFREE: target has unexpectedly left the DOUT phase 1748 */ 1749 outb(SIMODE1, ENPHASEMIS|ENSCSIRST|ENBUSFREE|ENPHASECHG); 1750 1751 /* I have tried to make the main loop as tight as possible. This 1752 * means that some of the code following the loop is a bit more 1753 * complex than otherwise. 1754 */ 1755 amount = (min(DOUTAMOUNT, aic->dleft)) & ~B_MASK; 1756 xfers = amount >> C_SHIFT; 1757 while (xfers) { 1758 /* First wait for FIFO less than halffull, or a phasechange */ 1759 LOGLINE(aic); 1760 do { 1761 dmastat = inb(DMASTAT); 1762 } while ((dmastat & DFIFOHF) && !(dmastat & INTSTAT)); 1763 1764 if (dmastat & DFIFOHF) /* Fifo more than halffull? */ 1765 break; 1766 #if AIC_USE_DWORDS 1767 outsl(DMADATALONG, aic->dp, xfers); 1768 #else 1769 outsw(DMADATA, aic->dp, xfers); 1770 #endif 1771 aic->dleft -= amount; 1772 aic->dp += amount; 1773 /* AIC_MISC(("-%d ", amount)); */ 1774 amount = (min(DOUTAMOUNT, aic->dleft)) & ~B_MASK; 1775 xfers = amount >> C_SHIFT; 1776 } 1777 /* State: phasechange || less than 4 bytes left 1778 * to transfer. Note: resets and unexpected busfrees are handled as 1779 * phasechanges. These conditions will be handled on a later 1780 * interrupt by the main interrupt routine. 1781 */ 1782 /* Handle the last few bytes */ 1783 while (!(dmastat & INTSTAT) && aic->dleft > 0) { 1784 LOGLINE(aic); 1785 do { 1786 dmastat = inb(DMASTAT); 1787 } while ((dmastat & DFIFOFULL) && !(dmastat & INTSTAT)); 1788 1789 if (dmastat & DFIFOFULL) /* Fifo still full? */ 1790 break; 1791 outb(DMADATA, *aic->dp); 1792 AIC_MISC(("-1 ")); 1793 aic->dp++; 1794 aic->dleft--; 1795 } 1796 /* State: reset || busfree || phasechange || 0 bytes left */ 1797 /* See the bytes off chip */ 1798 do { 1799 dmastat = inb(DMASTAT); 1800 } while (!(dmastat & INTSTAT) && 1801 (!(dmastat & DFIFOEMP) || !(inb(SSTAT2) & SEMPTY))); 1802 1803 /* We now have either a phasechange or the data are off chip. */ 1804 outb(SXFRCTL0, CHEN); 1805 if (dmastat & INTSTAT) { /* Some sort of phasechange */ 1806 register u_char sstat2; 1807 /* Stop transfers, do some accounting */ 1808 amount = inb(FIFOSTAT); 1809 sstat2 = inb(SSTAT2); 1810 if ((sstat2 & 7) == 0) 1811 amount += sstat2 & SFULL ? 8 : 0; 1812 else 1813 amount += sstat2 & 7; 1814 aic->dp -= amount; 1815 aic->dleft += amount; 1816 AIC_MISC(("+%d ", amount)); 1817 } 1818 1819 outb(DMACNTRL0, RSTFIFO|INTEN); 1820 LOGLINE(aic); 1821 while (inb(SXFRCTL0) & SCSIEN) 1822 ; 1823 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 1824 /* Enabled ints: BUSFREE, SCSIPERR, SCSIRSTI (unexpected) 1825 * REQINIT (expected) 1826 */ 1827 aic->progress = olddleft != aic->dleft; 1828 return; 1829 } 1830 1831 /* aic_datain: perform data transfers using the FIFO datapath in the aic6360 1832 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1833 * and ACK deasserted (i.e. at least one byte is ready). 1834 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1835 * transferred. This, is OK for fast targets, but not so smart for slow 1836 * targets which don't disconnect or for huge transfers. 1837 */ 1838 void 1839 aic_datain(aic) 1840 register struct aic_softc *aic; 1841 { 1842 register u_short iobase = aic->iobase; 1843 register u_char dmastat; 1844 struct acb *acb = aic->nexus; 1845 int amount, olddleft = aic->dleft; 1846 #define DINAMOUNT 64 /* Default amount of data to transfer */ 1847 1848 /* Enable DATA IN transfers */ 1849 outb(SCSISIGO, PH_DIN); 1850 outb(CLRSINT1, CLRPHASECHG); 1851 /* Clear FIFOs and counters */ 1852 outb(SXFRCTL0, CHEN|CLRSTCNT|CLRCH); 1853 outb(DMACNTRL0, INTEN|RSTFIFO); 1854 /* Enable FIFOs */ 1855 outb(SXFRCTL0, SCSIEN|DMAEN|CHEN); 1856 outb(DMACNTRL0, ENDMA|DWORDPIO|INTEN); 1857 1858 outb(SIMODE1, ENSCSIRST|ENPHASEMIS|ENBUSFREE|ENPHASECHG); 1859 /* We leave this loop if one or more of the following is true: 1860 * a) phase != PH_DIN && FIFOs are empty 1861 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 1862 */ 1863 while (aic->dleft >= DINAMOUNT) { 1864 LOGLINE(aic); 1865 do { /* Wait for fifo half full or phase mismatch */ 1866 dmastat = inb(DMASTAT); 1867 } while (!(dmastat & (DFIFOHF|INTSTAT))); 1868 1869 /* If FIFO isn't half full (probably because target left the 1870 * DIN phase) we should adjust amount 1871 */ 1872 if (!(dmastat & DFIFOHF)) /* Must be an interrupt */ 1873 break; 1874 #if AIC_USE_DWORDS 1875 insl(DMADATALONG, aic->dp, DINAMOUNT/4); 1876 #else 1877 insw(DMADATA, aic->dp, DINAMOUNT/2); 1878 #endif 1879 aic->dp += DINAMOUNT; 1880 aic->dleft -= DINAMOUNT; 1881 } 1882 /* One (or more) of the following has occured: 1883 * phasechg (including reset and busfree) || 1884 * dleft < DINAMOUNT. Let's sort it out. 1885 */ 1886 /* First, let's pull out any leftover data from the FIFO */ 1887 while (aic->dleft > 0) { 1888 LOGLINE(aic); 1889 do { 1890 dmastat = inb(DMASTAT); 1891 } while (!(dmastat & (DFIFOEMP|INTSTAT))); 1892 if ((dmastat & (DFIFOEMP|INTSTAT)) == (DFIFOEMP|INTSTAT)) 1893 break; 1894 *aic->dp++ = inb(DMADATA); 1895 aic->dleft--; 1896 } 1897 /* Now, either dleft == 0 || phasechg */ 1898 aic->progress = olddleft != aic->dleft; 1899 /* Some SCSI-devices are rude enough to transfer more data than what 1900 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1901 * requested 512. Test for progress, i.e. real transfers. If no real 1902 * transfers have been performed (acb->dleft is probably already zero) 1903 * and the FIFO is not empty, waste some bytes.... 1904 */ 1905 if (!aic->progress) { 1906 int extra = 0; 1907 LOGLINE(aic); 1908 while (!((dmastat = inb(DMASTAT)) & DFIFOEMP)) { 1909 inb(DMADATA); /* Throw it away */ 1910 extra++; 1911 } 1912 AIC_MISC(("aic: %d extra bytes from %d:%d\n", extra, 1913 acb->xs->sc_link->target, acb->xs->sc_link->lun)); 1914 aic->progress = extra; 1915 } 1916 /* Stop the FIFO data path */ 1917 outb(SXFRCTL0, CHEN); 1918 outb(DMACNTRL0, RSTFIFO|INTEN); 1919 /* Come back when REQ is set again */ 1920 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 1921 LOGLINE(aic); 1922 } 1923 1924 1925 /* 1926 * This is the workhorse routine of the driver. 1927 * Deficiencies (for now): 1928 * 1) always uses programmed I/O 1929 * 2) doesn't support synchronous transfers properly (yet) 1930 */ 1931 1932 int 1933 aicintr(aic) 1934 register struct aic_softc *aic; 1935 { 1936 register struct acb *acb; 1937 register struct scsi_link *sc; 1938 register u_short iobase = aic->iobase; 1939 struct scsi_xfer *xs; 1940 struct aic_tinfo *ti; 1941 int done, amount; 1942 u_char sstat0, sstat1, scsisig, dmastat, sstat2; 1943 u_char scsiseq, simode0, simode1, sxfrctl0; 1944 1945 LOGLINE(aic); 1946 /* Clear INTEN. This is important if we're running with edge 1947 * triggered interrupts as we don't guarantee that all interrupts will 1948 * be served during one single invocation of this routine, i.e. we may 1949 * need another edge. 1950 */ 1951 outb(DMACNTRL0, 0); 1952 AIC_TRACE(("aicintr\n")); 1953 1954 /* 1955 * 1st check for abnormal conditions, such as reset or parity errors 1956 */ 1957 sstat1 = inb(SSTAT1); 1958 AIC_MISC(("s1:0x%02x ", sstat1)); 1959 if (sstat1 & (SCSIRSTI|SCSIPERR)) { 1960 if (sstat1 & SCSIRSTI) { 1961 printf("aic: reset in -- reinitializing....\n"); 1962 aic_init(aic); /* Restart everything */ 1963 LOGLINE(aic); 1964 outb(DMACNTRL0, INTEN); 1965 return 1; 1966 } else { 1967 printf("aic: SCSI bus parity error\n"); 1968 outb(CLRSINT1, CLRSCSIPERR); 1969 if (aic->prevphase == PH_MSGI) 1970 aic_sched_msgout(SEND_PARITY_ERROR); 1971 else 1972 aic_sched_msgout(SEND_INIT_DET_ERR); 1973 } 1974 } 1975 1976 /* 1977 * If we're not already busy doing something test for the following 1978 * conditions: 1979 * 1) We have been reselected by something 1980 * 2) We have selected something successfully 1981 * 3) Our selection process has timed out 1982 * 4) This is really a bus free interrupt just to get a new command 1983 * going? 1984 * 5) Spurious interrupt? 1985 */ 1986 sstat0 = inb(SSTAT0); 1987 AIC_MISC(("s0:0x%02x ", sstat0)); 1988 if (aic->state != AIC_HASNEXUS) { /* No nexus yet */ 1989 if (sstat0 & SELDI) { 1990 LOGLINE(aic); 1991 /* We have been reselected. Things to do: 1992 * a) If we're trying to select something ourselves 1993 * back off the current command. 1994 * b) "Wait" for a message in phase (IDENTIFY) 1995 * c) Call aic_msgin() to get the identify message and 1996 * retrieve the disconnected command from the wait 1997 * queue. 1998 */ 1999 AIC_MISC(("reselect ")); 2000 /* If we're trying to select a target ourselves, 2001 * push our command back into the rdy list. 2002 */ 2003 if (aic->state == AIC_SELECTING) { 2004 AIC_MISC(("backoff selector ")); 2005 TAILQ_INSERT_HEAD(&aic->ready_list, aic->nexus, 2006 chain); 2007 aic->nexus = NULL; 2008 } 2009 aic->state = AIC_RESELECTED; 2010 /* Clear interrupts, disable future selection stuff 2011 * including select interrupts and timeouts 2012 */ 2013 outb(CLRSINT0, CLRSELDI); 2014 outb(SCSISEQ, 0); 2015 outb(SIMODE0, 0); 2016 /* Setup chip so we may detect spurious busfree 2017 * conditions later. 2018 */ 2019 outb(CLRSINT1, CLRBUSFREE); 2020 outb(SIMODE1, ENSCSIRST|ENBUSFREE| 2021 ENSCSIPERR|ENREQINIT); 2022 /* Now, we're expecting an IDENTIFY message. */ 2023 aic->phase = aicphase(aic); 2024 if (aic->phase & PH_PSBIT) { 2025 LOGLINE(aic); 2026 outb(DMACNTRL0, INTEN); 2027 return 1; /* Come back when REQ is set */ 2028 } 2029 if (aic->phase == PH_MSGI) 2030 aic_msgin(aic); /* Handle identify message */ 2031 else { 2032 /* Things are seriously fucked up. 2033 * Pull the brakes, i.e. RST 2034 */ 2035 printf("aic at line %d: target didn't identify\n", __LINE__); 2036 Debugger(); 2037 aic_init(aic); 2038 return 1; 2039 } 2040 if (aic->state != AIC_HASNEXUS) {/* IDENTIFY fail?! */ 2041 printf("aic at line %d: identify failed\n", 2042 __LINE__); 2043 aic_init(aic); 2044 return 1; 2045 } else { 2046 outb(SIMODE1, 2047 ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 2048 /* Fallthrough to HASNEXUS part of aicintr */ 2049 } 2050 } else if (sstat0 & SELDO) { 2051 LOGLINE(aic); 2052 /* We have selected a target. Things to do: 2053 * a) Determine what message(s) to send. 2054 * b) Verify that we're still selecting the target. 2055 * c) Mark device as busy. 2056 */ 2057 acb = aic->nexus; 2058 if (!acb) { 2059 printf("aic at line %d: missing acb", __LINE__); 2060 Debugger(); 2061 } 2062 sc = acb->xs->sc_link; 2063 ti = &aic->tinfo[sc->target]; 2064 if (acb->xs->flags & SCSI_RESET) 2065 aic->msgpriq = SEND_DEV_RESET; 2066 else if (ti->flags & DO_NEGOTIATE) 2067 aic->msgpriq = SEND_IDENTIFY|SEND_SDTR; 2068 else 2069 aic->msgpriq = SEND_IDENTIFY; 2070 /* Setup chip to enable later testing for busfree 2071 * conditions 2072 */ 2073 outb(CLRSINT1, CLRBUSFREE); 2074 outb(SCSISEQ, 0); /* Stop selection stuff */ 2075 nandreg(SIMODE0, ENSELDO); /* No more selectout ints */ 2076 sstat0 = inb(SSTAT0); 2077 if (sstat0 & SELDO) { /* Still selected!? */ 2078 outb(SIMODE0, 0); 2079 outb(SIMODE1, ENSCSIRST|ENSCSIPERR| 2080 ENBUSFREE|ENREQINIT); 2081 aic->state = AIC_HASNEXUS; 2082 aic->flags = 0; 2083 aic->prevphase = PH_INVALID; 2084 aic->dp = acb->daddr; 2085 aic->dleft = acb->dleft; 2086 ti->lubusy |= (1<<sc->lun); 2087 AIC_MISC(("select ok ")); 2088 } else { 2089 /* Has seen busfree since selection, i.e. 2090 * a "spurious" selection. Shouldn't happen. 2091 */ 2092 printf("aic: unexpected busfree\n"); 2093 xs->error = XS_DRIVER_STUFFUP; 2094 untimeout(aic_timeout, (caddr_t)acb); 2095 aic_done(acb); 2096 } 2097 LOGLINE(aic); 2098 outb(DMACNTRL0, INTEN); 2099 return 1; 2100 } else if (sstat1 & SELTO) { 2101 /* Selection timed out. What to do: 2102 * Disable selections out and fail the command with 2103 * code XS_TIMEOUT. 2104 */ 2105 acb = aic->nexus; 2106 if (!acb) { 2107 printf("aic at line %d: missing acb", __LINE__); 2108 Debugger(); 2109 } 2110 outb(SCSISEQ, ENRESELI|ENAUTOATNP); 2111 outb(SXFRCTL1, 0); 2112 outb(CLRSINT1, CLRSELTIMO); 2113 aic->state = AIC_IDLE; 2114 acb->xs->error = XS_TIMEOUT; 2115 untimeout(aic_timeout, (caddr_t)acb); 2116 aic_done(acb); 2117 LOGLINE(aic); 2118 outb(DMACNTRL0, INTEN); 2119 return 1; 2120 } else { 2121 /* Assume a bus free interrupt. What to do: 2122 * Start selecting. 2123 */ 2124 if (aic->state == AIC_IDLE) 2125 aic_sched(aic); 2126 else 2127 AIC_MISC(("Extra aic6360 interrupt.")); 2128 LOGLINE(aic); 2129 outb(DMACNTRL0, INTEN); 2130 return 1; 2131 } 2132 } 2133 /* Driver is now in state AIC_HASNEXUS, i.e. we have a current command 2134 * working the SCSI bus. 2135 */ 2136 acb = aic->nexus; 2137 if (aic->state != AIC_HASNEXUS || acb == NULL) { 2138 printf("aic: no nexus!!\n"); 2139 Debugger(); 2140 } 2141 2142 /* What sort of transfer does the bus signal? */ 2143 aic->phase = aicphase(aic); 2144 if (!(aic->phase & PH_PSBIT)) /* not a pseudo phase */ 2145 outb(SCSISIGO, aic->phase); 2146 outb(CLRSINT1, CLRPHASECHG); 2147 /* These interrupts are enabled by default: 2148 * SCSIRSTI, SCSIPERR, BUSFREE, REQINIT 2149 */ 2150 switch (aic->phase) { 2151 case PH_MSGO: 2152 LOGLINE(aic); 2153 if (aic_debug & AIC_SHOWMISC) 2154 printf("PH_MSGO "); 2155 aic_msgout(aic); 2156 aic->prevphase = PH_MSGO; 2157 /* Setup interrupts before leaving */ 2158 outb(SIMODE0, 0); 2159 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 2160 /* Enabled ints: SCSIPERR, SCSIRSTI (unexpected) 2161 * REQINIT (expected) BUSFREE (possibly expected) 2162 */ 2163 break; 2164 case PH_CMD: /* CMD phase & REQ asserted */ 2165 LOGLINE(aic); 2166 if (aic_debug & AIC_SHOWMISC) 2167 printf("PH_CMD 0x%02x (%d) ", 2168 acb->cmd.opcode, acb->clen); 2169 outb(SCSISIGO, PH_CMD); 2170 /* Use FIFO for CMDs. Assumes that no cmd > 128 bytes. OK? */ 2171 /* Clear hostFIFO and enable EISA-hostFIFO transfers */ 2172 outb(DMACNTRL0, WRITE|RSTFIFO|INTEN); /* 3(4) */ 2173 /* Clear scsiFIFO and enable SCSI-interface 2174 & hostFIFO-scsiFIFO transfers */ 2175 outb(SXFRCTL0, CHEN|CLRCH|CLRSTCNT); /* 4 */ 2176 outb(SXFRCTL0, SCSIEN|DMAEN|CHEN); /* 5 */ 2177 outb(DMACNTRL0, ENDMA|WRITE|INTEN); /* 3+6 */ 2178 /* What (polled) interrupts to enable */ 2179 outb(SIMODE1, ENPHASEMIS|ENSCSIRST|ENBUSFREE|ENSCSIPERR); 2180 /* DFIFOEMP is set, FIFO (128 byte) is always big enough */ 2181 outsw(DMADATA, (short *)&acb->cmd, acb->clen>>1); 2182 2183 /* Wait for SCSI FIFO to drain */ 2184 LOGLINE(aic); 2185 do { 2186 sstat2 = inb(SSTAT2); 2187 } while (!(sstat2 & SEMPTY) && !(inb(DMASTAT) & INTSTAT)); 2188 if (!(inb(SSTAT2) & SEMPTY)) { 2189 printf("aic at line %d: SCSI-FIFO didn't drain\n", 2190 __LINE__); 2191 Debugger(); 2192 acb->xs->error = XS_DRIVER_STUFFUP; 2193 untimeout(aic_timeout, (caddr_t)acb); 2194 aic_done(acb); 2195 aic_init(aic); 2196 return 1; 2197 } 2198 outb(SXFRCTL0, CHEN); /* Clear SCSIEN & DMAEN */ 2199 outb(SIMODE0, 0); 2200 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR); 2201 LOGLINE(aic); 2202 do { 2203 sxfrctl0 = inb(SXFRCTL0); 2204 } while (sxfrctl0 & SCSIEN && !(inb(DMASTAT) & INTSTAT)); 2205 if (sxfrctl0 & SCSIEN) { 2206 printf("aic at line %d: scsi xfer never finished\n", 2207 __LINE__); 2208 Debugger(); 2209 acb->xs->error = XS_DRIVER_STUFFUP; 2210 untimeout(aic_timeout, (caddr_t)acb); 2211 aic_done(acb); 2212 aic_init(aic); 2213 return 1; 2214 } 2215 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 2216 /* Enabled ints: BUSFREE, SCSIPERR, SCSIRSTI (unexpected) 2217 * REQINIT (expected) 2218 */ 2219 aic->prevphase = PH_CMD; 2220 break; 2221 case PH_DOUT: 2222 LOGLINE(aic); 2223 AIC_MISC(("PH_DOUT [%d] ",aic->dleft)); 2224 aic_dataout(aic); 2225 aic->prevphase = PH_DOUT; 2226 break; 2227 case PH_MSGI: 2228 LOGLINE(aic); 2229 if (aic_debug & AIC_SHOWMISC) 2230 printf("PH_MSGI "); 2231 aic_msgin(aic); 2232 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 2233 aic->prevphase = PH_MSGI; 2234 break; 2235 case PH_DIN: 2236 LOGLINE(aic); 2237 if (aic_debug & AIC_SHOWMISC) 2238 printf("PH_DIN "); 2239 aic_datain(aic); 2240 aic->prevphase = PH_DIN; 2241 break; 2242 case PH_STAT: 2243 LOGLINE(aic); 2244 if (aic_debug & AIC_SHOWMISC) 2245 printf("PH_STAT "); 2246 outb(SCSISIGO, PH_STAT); 2247 outb(SXFRCTL0, CHEN|SPIOEN); 2248 outb(DMACNTRL0, RSTFIFO|INTEN); 2249 outb(SIMODE1, ENSCSIRST|ENPHASEMIS|ENBUSFREE|ENSCSIPERR); 2250 acb->stat = inb(SCSIDAT); 2251 outb(SXFRCTL0, CHEN); 2252 if (aic_debug & AIC_SHOWMISC) 2253 printf("0x%02x ", acb->stat); 2254 outb(SIMODE1, ENSCSIRST|ENBUSFREE|ENSCSIPERR|ENREQINIT); 2255 aic->prevphase = PH_STAT; 2256 break; 2257 case PH_INVALID: 2258 LOGLINE(aic); 2259 break; 2260 case PH_BUSFREE: 2261 LOGLINE(aic); 2262 if (aic->flags & AIC_BUSFREE_OK) { /*It's fun the 1st time.. */ 2263 aic->flags &= ~AIC_BUSFREE_OK; 2264 } else { 2265 printf("aic at line %d: unexpected busfree phase\n", 2266 __LINE__); 2267 Debugger(); 2268 } 2269 break; 2270 default: 2271 printf("aic at line %d: bogus bus phase\n", __LINE__); 2272 Debugger(); 2273 break; 2274 } 2275 LOGLINE(aic); 2276 outb(DMACNTRL0, INTEN); 2277 return 1; 2278 } 2279 2280 void 2281 aic_timeout(arg) 2282 caddr_t arg; 2283 { 2284 int s = splbio(); 2285 struct acb *acb = (void *)arg; 2286 struct aic_softc *aic; 2287 2288 aic = acb->xs->sc_link->adapter_softc; 2289 sc_print_addr(acb->xs->sc_link); 2290 acb->xs->error = XS_TIMEOUT; 2291 printf("timed out\n"); 2292 2293 aic_done(acb); 2294 splx(s); 2295 } 2296 2297 #ifdef AIC_DEBUG 2299 /* 2300 * The following functions are mostly used for debugging purposes, either 2301 * directly called from the driver or from the kernel debugger. 2302 */ 2303 2304 void 2305 aic_show_scsi_cmd(acb) 2306 struct acb *acb; 2307 { 2308 u_char *b = (u_char *)&acb->cmd; 2309 struct scsi_link *sc = acb->xs->sc_link; 2310 int i; 2311 2312 sc_print_addr(sc); 2313 if (!(acb->xs->flags & SCSI_RESET)) { 2314 for (i = 0; i < acb->clen; i++) { 2315 if (i) 2316 printf(","); 2317 printf("%x", b[i]); 2318 } 2319 printf("\n"); 2320 } else 2321 printf("RESET\n"); 2322 } 2323 2324 void 2325 aic_print_acb(acb) 2326 struct acb *acb; 2327 { 2328 2329 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2330 printf(" daddr=%x dleft=%d stat=%x\n", 2331 (long)acb->daddr, acb->dleft, acb->stat); 2332 aic_show_scsi_cmd(acb); 2333 } 2334 2335 void 2336 aic_print_active_acb() 2337 { 2338 struct acb *acb; 2339 struct aic_softc *aic = aiccd.cd_devs[0]; 2340 2341 printf("ready list:\n"); 2342 for (acb = aic->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) 2343 aic_print_acb(acb); 2344 printf("nexus:\n"); 2345 if (aic->nexus) 2346 aic_print_acb(aic->nexus); 2347 printf("nexus list:\n"); 2348 for (acb = aic->nexus_list.tqh_first; acb; acb = acb->chain.tqe_next) 2349 aic_print_acb(acb); 2350 } 2351 2352 void 2353 aic_dump6360() 2354 { 2355 u_short iobase = 0x340; 2356 2357 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIGI=%x\n", 2358 inb(SCSISEQ), inb(SXFRCTL0), inb(SXFRCTL1), inb(SCSISIGI)); 2359 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2360 inb(SSTAT0), inb(SSTAT1), inb(SSTAT2), inb(SSTAT3), inb(SSTAT4)); 2361 printf(" SIMODE0=%x SIMODE1=%x DMACNTRL0=%x DMACNTRL1=%x DMASTAT=%x\n", 2362 inb(SIMODE0), inb(SIMODE1), inb(DMACNTRL0), inb(DMACNTRL1), 2363 inb(DMASTAT)); 2364 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2365 inb(FIFOSTAT), inb(SCSIBUS)); 2366 } 2367 2368 void 2369 aic_dump_driver() 2370 { 2371 struct aic_softc *aic = aiccd.cd_devs[0]; 2372 struct aic_tinfo *ti; 2373 int i; 2374 2375 printf("nexus=%x phase=%x prevphase=%x\n", aic->nexus, aic->phase, 2376 aic->prevphase); 2377 printf("state=%x msgin=%x msgpriq=%x msgout=%x imlen=%d omlen=%d\n", 2378 aic->state, aic->imess[0], aic->msgpriq, aic->msgout, aic->imlen, 2379 aic->omlen); 2380 printf("history:"); 2381 i = aic->hp; 2382 do { 2383 printf(" %d", aic->history[i]); 2384 i = (i + 1) % AIC_HSIZE; 2385 } while (i != aic->hp); 2386 printf("*\n"); 2387 for (i = 0; i < 7; i++) { 2388 ti = &aic->tinfo[i]; 2389 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2390 i, ti->cmds, ti->dconns, ti->touts); 2391 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2392 } 2393 } 2394 #endif 2395
Indexes created Sat Oct 25 16:10:12 GMT 2025