aic6360.c revision 1.63
1 /* $NetBSD: aic6360.c,v 1.63 1999/09/30 23:04:40 thorpej Exp $ */ 2 3 #include "opt_ddb.h" 4 #ifdef DDB 5 #define integrate 6 #else 7 #define integrate static inline 8 #endif 9 10 /* 11 * Copyright (c) 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Charles M. Hannum. 24 * 4. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * Copyright (c) 1994 Jarle Greipsland 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 43 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 50 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 51 * POSSIBILITY OF SUCH DAMAGE. 52 */ 53 54 /* 55 * Acknowledgements: Many of the algorithms used in this driver are 56 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 57 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 58 */ 59 60 /* TODO list: 61 * 1) Get the DMA stuff working. 62 * 2) Get the iov/uio stuff working. Is this a good thing ??? 63 * 3) Get the synch stuff working. 64 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 65 */ 66 67 /* 68 * A few customizable items: 69 */ 70 71 /* Use doubleword transfers to/from SCSI chip. Note: This requires 72 * motherboard support. Basicly, some motherboard chipsets are able to 73 * split a 32 bit I/O operation into two 16 bit I/O operations, 74 * transparently to the processor. This speeds up some things, notably long 75 * data transfers. 76 */ 77 #define AIC_USE_DWORDS 0 78 79 /* Synchronous data transfers? */ 80 #define AIC_USE_SYNCHRONOUS 0 81 #define AIC_SYNC_REQ_ACK_OFS 8 82 83 /* Wide data transfers? */ 84 #define AIC_USE_WIDE 0 85 #define AIC_MAX_WIDTH 0 86 87 /* Max attempts made to transmit a message */ 88 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 89 90 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 91 #define AIC_USE_EISA_DMA 0 92 #define AIC_USE_ISA_DMA 0 93 94 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 95 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 96 97 /* Some spin loop parameters (essentially how long to wait some places) 98 * The problem(?) is that sometimes we expect either to be able to transmit a 99 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 100 * returning from the interrupt just to get yanked back for the next byte we 101 * may spin in the interrupt routine waiting for this byte to come. How long? 102 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 103 */ 104 #define AIC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 105 #define AIC_MSGOUT_SPIN 1 106 107 /* Include debug functions? At the end of this file there are a bunch of 108 * functions that will print out various information regarding queued SCSI 109 * commands, driver state and chip contents. You can call them from the 110 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 111 * kernel uses less memory) but you lose the debugging facilities. 112 */ 113 #define AIC_DEBUG 1 114 115 #define AIC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 116 117 /* End of customizable parameters */ 118 119 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 120 #error "I said not yet! Start paying attention... grumble" 121 #endif 122 123 #include <sys/types.h> 124 #include <sys/param.h> 125 #include <sys/systm.h> 126 #include <sys/kernel.h> 127 #include <sys/errno.h> 128 #include <sys/ioctl.h> 129 #include <sys/device.h> 130 #include <sys/buf.h> 131 #include <sys/proc.h> 132 #include <sys/user.h> 133 #include <sys/queue.h> 134 135 #include <machine/bus.h> 136 #include <machine/intr.h> 137 138 #include <dev/scsipi/scsi_all.h> 139 #include <dev/scsipi/scsipi_all.h> 140 #include <dev/scsipi/scsi_message.h> 141 #include <dev/scsipi/scsiconf.h> 142 143 #include <dev/ic/aic6360reg.h> 144 #include <dev/ic/aic6360var.h> 145 146 147 #ifndef DDB 149 #define Debugger() panic("should call debugger here (aic6360.c)") 150 #endif /* ! DDB */ 151 152 #if AIC_DEBUG 153 int aic_debug = 0x00; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRACE; */ 154 #endif 155 156 void aicattach __P((struct aic_softc *)); 157 void aic_minphys __P((struct buf *)); 158 void aic_done __P((struct aic_softc *, struct aic_acb *)); 159 void aic_dequeue __P((struct aic_softc *, struct aic_acb *)); 160 int aic_scsi_cmd __P((struct scsipi_xfer *)); 161 int aic_poll __P((struct aic_softc *, struct scsipi_xfer *, int)); 162 integrate void aic_sched_msgout __P((struct aic_softc *, u_char)); 163 integrate void aic_setsync __P((struct aic_softc *, struct aic_tinfo *)); 164 void aic_select __P((struct aic_softc *, struct aic_acb *)); 165 void aic_timeout __P((void *)); 166 void aic_sched __P((struct aic_softc *)); 167 void aic_scsi_reset __P((struct aic_softc *)); 168 void aic_reset __P((struct aic_softc *)); 169 void aic_free_acb __P((struct aic_softc *, struct aic_acb *, int)); 170 struct aic_acb* aic_get_acb __P((struct aic_softc *, int)); 171 int aic_reselect __P((struct aic_softc *, int)); 172 void aic_sense __P((struct aic_softc *, struct aic_acb *)); 173 void aic_msgin __P((struct aic_softc *)); 174 void aic_abort __P((struct aic_softc *, struct aic_acb *)); 175 void aic_msgout __P((struct aic_softc *)); 176 int aic_dataout_pio __P((struct aic_softc *, u_char *, int)); 177 int aic_datain_pio __P((struct aic_softc *, u_char *, int)); 178 #if AIC_DEBUG 179 void aic_print_acb __P((struct aic_acb *)); 180 void aic_dump_driver __P((struct aic_softc *)); 181 void aic_dump6360 __P((struct aic_softc *)); 182 void aic_show_scsi_cmd __P((struct aic_acb *)); 183 void aic_print_active_acb __P((void)); 184 #endif 185 186 struct scsipi_device aic_dev = { 187 NULL, /* Use default error handler */ 188 NULL, /* have a queue, served by this */ 189 NULL, /* have no async handler */ 190 NULL, /* Use default 'done' routine */ 191 }; 192 193 /* 195 * INITIALIZATION ROUTINES (probe, attach ++) 196 */ 197 198 /* Do the real search-for-device. 199 * Prerequisite: sc->sc_iobase should be set to the proper value 200 */ 201 int 202 aic_find(iot, ioh) 203 bus_space_tag_t iot; 204 bus_space_handle_t ioh; 205 { 206 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 207 int i; 208 209 /* Remove aic6360 from possible powerdown mode */ 210 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 211 212 /* Thanks to mark (at) aggregate.com for the new method for detecting 213 * whether the chip is present or not. Bonus: may also work for 214 * the AIC-6260! 215 */ 216 AIC_TRACE(("aic: probing for aic-chip\n")); 217 /* 218 * Linux also init's the stack to 1-16 and then clears it, 219 * 6260's don't appear to have an ID reg - mpg 220 */ 221 /* Push the sequence 0,1,..,15 on the stack */ 222 #define STSIZE 16 223 bus_space_write_1(iot, ioh, DMACNTRL1, 0); /* Reset stack pointer */ 224 for (i = 0; i < STSIZE; i++) 225 bus_space_write_1(iot, ioh, STACK, i); 226 227 /* See if we can pull out the same sequence */ 228 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 229 for (i = 0; i < STSIZE && bus_space_read_1(iot, ioh, STACK) == i; i++) 230 ; 231 if (i != STSIZE) { 232 AIC_START(("STACK futzed at %d.\n", i)); 233 return 0; 234 } 235 236 /* See if we can pull the id string out of the ID register, 237 * now only used for informational purposes. 238 */ 239 bzero(chip_id, sizeof(chip_id)); 240 bus_space_read_multi_1(iot, ioh, ID, chip_id, sizeof(IDSTRING) - 1); 241 AIC_START(("AIC found ID: %s ",chip_id)); 242 AIC_START(("chip revision %d\n", 243 (int)bus_space_read_1(iot, ioh, REV))); 244 245 return 1; 246 } 247 248 /* 249 * Attach the AIC6360, fill out some high and low level data structures 250 */ 251 void 252 aicattach(sc) 253 struct aic_softc *sc; 254 { 255 256 AIC_TRACE(("aicattach ")); 257 sc->sc_state = AIC_INIT; 258 259 sc->sc_initiator = 7; 260 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 261 262 /* 263 * These are the bounds of the sync period, based on the frequency of 264 * the chip's clock input and the size and offset of the sync period 265 * register. 266 * 267 * For a 20Mhz clock, this gives us 25, or 100nS, or 10MB/s, as a 268 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 269 * minimum transfer rate. 270 */ 271 sc->sc_minsync = (2 * 250) / sc->sc_freq; 272 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 273 274 aic_init(sc, 1); /* Init chip and driver */ 275 276 /* 277 * Fill in the adapter. 278 */ 279 sc->sc_adapter.scsipi_cmd = aic_scsi_cmd; 280 sc->sc_adapter.scsipi_minphys = aic_minphys; 281 282 /* 283 * Fill in the prototype scsipi_link 284 */ 285 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 286 sc->sc_link.adapter_softc = sc; 287 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_initiator; 288 sc->sc_link.adapter = &sc->sc_adapter; 289 sc->sc_link.device = &aic_dev; 290 sc->sc_link.openings = 2; 291 sc->sc_link.scsipi_scsi.max_target = 7; 292 sc->sc_link.scsipi_scsi.max_lun = 7; 293 sc->sc_link.type = BUS_SCSI; 294 295 /* 296 * ask the adapter what subunits are present 297 */ 298 sc->sc_child = config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 299 } 300 301 int 302 aic_activate(self, act) 303 struct device *self; 304 enum devact act; 305 { 306 struct aic_softc *sc = (struct aic_softc *) self; 307 int s, rv = 0; 308 309 s = splhigh(); 310 switch (act) { 311 case DVACT_ACTIVATE: 312 rv = EOPNOTSUPP; 313 break; 314 315 case DVACT_DEACTIVATE: 316 if (sc->sc_child != NULL) 317 rv = config_deactivate(sc->sc_child); 318 break; 319 } 320 splx(s); 321 322 return (rv); 323 } 324 325 int 326 aic_detach(self, flags) 327 struct device *self; 328 int flags; 329 { 330 struct aic_softc *sc = (struct aic_softc *) self; 331 int rv = 0; 332 333 if (sc->sc_child != NULL) 334 rv = config_detach(sc->sc_child, flags); 335 336 return (rv); 337 } 338 339 /* Initialize AIC6360 chip itself 340 * The following conditions should hold: 341 * aic_isa_probe should have succeeded, i.e. the iobase address in aic_softc 342 * must be valid. 343 */ 344 void 345 aic_reset(sc) 346 struct aic_softc *sc; 347 { 348 bus_space_tag_t iot = sc->sc_iot; 349 bus_space_handle_t ioh = sc->sc_ioh; 350 351 /* 352 * Doc. recommends to clear these two registers before 353 * operations commence 354 */ 355 bus_space_write_1(iot, ioh, SCSITEST, 0); 356 bus_space_write_1(iot, ioh, TEST, 0); 357 358 /* Reset SCSI-FIFO and abort any transfers */ 359 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH | CLRSTCNT); 360 361 /* Reset DMA-FIFO */ 362 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 363 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 364 365 /* Disable all selection features */ 366 bus_space_write_1(iot, ioh, SCSISEQ, 0); 367 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 368 369 /* Disable some interrupts */ 370 bus_space_write_1(iot, ioh, SIMODE0, 0x00); 371 /* Clear a slew of interrupts */ 372 bus_space_write_1(iot, ioh, CLRSINT0, 0x7f); 373 374 /* Disable some more interrupts */ 375 bus_space_write_1(iot, ioh, SIMODE1, 0x00); 376 /* Clear another slew of interrupts */ 377 bus_space_write_1(iot, ioh, CLRSINT1, 0xef); 378 379 /* Disable synchronous transfers */ 380 bus_space_write_1(iot, ioh, SCSIRATE, 0); 381 382 /* Haven't seen ant errors (yet) */ 383 bus_space_write_1(iot, ioh, CLRSERR, 0x07); 384 385 /* Set our SCSI-ID */ 386 bus_space_write_1(iot, ioh, SCSIID, sc->sc_initiator << OID_S); 387 bus_space_write_1(iot, ioh, BRSTCNTRL, EISA_BRST_TIM); 388 } 389 390 /* Pull the SCSI RST line for 500 us */ 391 void 392 aic_scsi_reset(sc) 393 struct aic_softc *sc; 394 { 395 bus_space_tag_t iot = sc->sc_iot; 396 bus_space_handle_t ioh = sc->sc_ioh; 397 398 bus_space_write_1(iot, ioh, SCSISEQ, SCSIRSTO); 399 delay(500); 400 bus_space_write_1(iot, ioh, SCSISEQ, 0); 401 delay(50); 402 } 403 404 /* 405 * Initialize aic SCSI driver. 406 */ 407 void 408 aic_init(sc, bus_reset) 409 struct aic_softc *sc; 410 int bus_reset; 411 { 412 struct aic_acb *acb; 413 int r; 414 415 if (bus_reset) { 416 aic_reset(sc); 417 aic_scsi_reset(sc); 418 } 419 aic_reset(sc); 420 421 if (sc->sc_state == AIC_INIT) { 422 /* First time through; initialize. */ 423 TAILQ_INIT(&sc->ready_list); 424 TAILQ_INIT(&sc->nexus_list); 425 TAILQ_INIT(&sc->free_list); 426 sc->sc_nexus = NULL; 427 acb = sc->sc_acb; 428 bzero(acb, sizeof(sc->sc_acb)); 429 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 430 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 431 acb++; 432 } 433 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 434 } else { 435 /* Cancel any active commands. */ 436 sc->sc_state = AIC_CLEANING; 437 if ((acb = sc->sc_nexus) != NULL) { 438 acb->xs->error = XS_DRIVER_STUFFUP; 439 untimeout(aic_timeout, acb); 440 aic_done(sc, acb); 441 } 442 while ((acb = sc->nexus_list.tqh_first) != NULL) { 443 acb->xs->error = XS_DRIVER_STUFFUP; 444 untimeout(aic_timeout, acb); 445 aic_done(sc, acb); 446 } 447 } 448 449 sc->sc_prevphase = PH_INVALID; 450 for (r = 0; r < 8; r++) { 451 struct aic_tinfo *ti = &sc->sc_tinfo[r]; 452 453 ti->flags = 0; 454 #if AIC_USE_SYNCHRONOUS 455 ti->flags |= DO_SYNC; 456 ti->period = sc->sc_minsync; 457 ti->offset = AIC_SYNC_REQ_ACK_OFS; 458 #else 459 ti->period = ti->offset = 0; 460 #endif 461 #if AIC_USE_WIDE 462 ti->flags |= DO_WIDE; 463 ti->width = AIC_MAX_WIDTH; 464 #else 465 ti->width = 0; 466 #endif 467 } 468 469 sc->sc_state = AIC_IDLE; 470 bus_space_write_1(sc->sc_iot, sc->sc_ioh, DMACNTRL0, INTEN); 471 } 472 473 void 474 aic_free_acb(sc, acb, flags) 475 struct aic_softc *sc; 476 struct aic_acb *acb; 477 int flags; 478 { 479 int s; 480 481 s = splbio(); 482 483 acb->flags = 0; 484 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 485 486 /* 487 * If there were none, wake anybody waiting for one to come free, 488 * starting with queued entries. 489 */ 490 if (acb->chain.tqe_next == 0) 491 wakeup(&sc->free_list); 492 493 splx(s); 494 } 495 496 struct aic_acb * 497 aic_get_acb(sc, flags) 498 struct aic_softc *sc; 499 int flags; 500 { 501 struct aic_acb *acb; 502 int s; 503 504 s = splbio(); 505 506 while ((acb = sc->free_list.tqh_first) == NULL && 507 (flags & XS_CTL_NOSLEEP) == 0) 508 tsleep(&sc->free_list, PRIBIO, "aicacb", 0); 509 if (acb) { 510 TAILQ_REMOVE(&sc->free_list, acb, chain); 511 acb->flags |= ACB_ALLOC; 512 } 513 514 splx(s); 515 return acb; 516 } 517 518 /* 520 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 521 */ 522 523 /* 524 * Expected sequence: 525 * 1) Command inserted into ready list 526 * 2) Command selected for execution 527 * 3) Command won arbitration and has selected target device 528 * 4) Send message out (identify message, eventually also sync.negotiations) 529 * 5) Send command 530 * 5a) Receive disconnect message, disconnect. 531 * 5b) Reselected by target 532 * 5c) Receive identify message from target. 533 * 6) Send or receive data 534 * 7) Receive status 535 * 8) Receive message (command complete etc.) 536 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 537 * Repeat 2-8 (no disconnects please...) 538 */ 539 540 /* 541 * Start a SCSI-command 542 * This function is called by the higher level SCSI-driver to queue/run 543 * SCSI-commands. 544 */ 545 int 546 aic_scsi_cmd(xs) 547 struct scsipi_xfer *xs; 548 { 549 struct scsipi_link *sc_link = xs->sc_link; 550 struct aic_softc *sc = sc_link->adapter_softc; 551 struct aic_acb *acb; 552 int s, flags; 553 554 AIC_TRACE(("aic_scsi_cmd ")); 555 AIC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 556 sc_link->scsipi_scsi.target)); 557 558 flags = xs->xs_control; 559 if ((acb = aic_get_acb(sc, flags)) == NULL) { 560 xs->error = XS_DRIVER_STUFFUP; 561 return TRY_AGAIN_LATER; 562 } 563 564 /* Initialize acb */ 565 acb->xs = xs; 566 acb->timeout = xs->timeout; 567 568 if (xs->xs_control & XS_CTL_RESET) { 569 acb->flags |= ACB_RESET; 570 acb->scsipi_cmd_length = 0; 571 acb->data_length = 0; 572 } else { 573 bcopy(xs->cmd, &acb->scsipi_cmd, xs->cmdlen); 574 acb->scsipi_cmd_length = xs->cmdlen; 575 acb->data_addr = xs->data; 576 acb->data_length = xs->datalen; 577 } 578 acb->target_stat = 0; 579 580 s = splbio(); 581 582 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 583 if (sc->sc_state == AIC_IDLE) 584 aic_sched(sc); 585 586 splx(s); 587 588 if ((flags & XS_CTL_POLL) == 0) 589 return SUCCESSFULLY_QUEUED; 590 591 /* Not allowed to use interrupts, use polling instead */ 592 if (aic_poll(sc, xs, acb->timeout)) { 593 aic_timeout(acb); 594 if (aic_poll(sc, xs, acb->timeout)) 595 aic_timeout(acb); 596 } 597 return COMPLETE; 598 } 599 600 /* 601 * Adjust transfer size in buffer structure 602 */ 603 void 604 aic_minphys(bp) 605 struct buf *bp; 606 { 607 608 AIC_TRACE(("aic_minphys ")); 609 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 610 bp->b_bcount = (AIC_NSEG << PGSHIFT); 611 minphys(bp); 612 } 613 614 /* 615 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 616 */ 617 int 618 aic_poll(sc, xs, count) 619 struct aic_softc *sc; 620 struct scsipi_xfer *xs; 621 int count; 622 { 623 bus_space_tag_t iot = sc->sc_iot; 624 bus_space_handle_t ioh = sc->sc_ioh; 625 626 AIC_TRACE(("aic_poll ")); 627 while (count) { 628 /* 629 * If we had interrupts enabled, would we 630 * have got an interrupt? 631 */ 632 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 0) 633 aicintr(sc); 634 if ((xs->xs_status & XS_STS_DONE) != 0) 635 return 0; 636 delay(1000); 637 count--; 638 } 639 return 1; 640 } 641 642 /* 644 * LOW LEVEL SCSI UTILITIES 645 */ 646 647 integrate void 648 aic_sched_msgout(sc, m) 649 struct aic_softc *sc; 650 u_char m; 651 { 652 bus_space_tag_t iot = sc->sc_iot; 653 bus_space_handle_t ioh = sc->sc_ioh; 654 655 if (sc->sc_msgpriq == 0) 656 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase | ATNO); 657 sc->sc_msgpriq |= m; 658 } 659 660 /* 661 * Set synchronous transfer offset and period. 662 */ 663 integrate void 664 aic_setsync(sc, ti) 665 struct aic_softc *sc; 666 struct aic_tinfo *ti; 667 { 668 #if AIC_USE_SYNCHRONOUS 669 bus_space_tag_t iot = sc->sc_iot; 670 bus_space_handle_t ioh = sc->sc_ioh; 671 672 if (ti->offset != 0) 673 bus_space_write_1(iot, ioh, SCSIRATE, 674 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 675 else 676 bus_space_write_1(iot, ioh, SCSIRATE, 0); 677 #endif 678 } 679 680 /* 681 * Start a selection. This is used by aic_sched() to select an idle target, 682 * and by aic_done() to immediately reselect a target to get sense information. 683 */ 684 void 685 aic_select(sc, acb) 686 struct aic_softc *sc; 687 struct aic_acb *acb; 688 { 689 struct scsipi_link *sc_link = acb->xs->sc_link; 690 int target = sc_link->scsipi_scsi.target; 691 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 692 bus_space_tag_t iot = sc->sc_iot; 693 bus_space_handle_t ioh = sc->sc_ioh; 694 695 bus_space_write_1(iot, ioh, SCSIID, 696 sc->sc_initiator << OID_S | target); 697 aic_setsync(sc, ti); 698 bus_space_write_1(iot, ioh, SXFRCTL1, STIMO_256ms | ENSTIMER); 699 700 /* Always enable reselections. */ 701 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI | ENSELDO); 702 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSELTIMO); 703 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI | ENSELO | ENAUTOATNO); 704 705 sc->sc_state = AIC_SELECTING; 706 } 707 708 int 709 aic_reselect(sc, message) 710 struct aic_softc *sc; 711 int message; 712 { 713 u_char selid, target, lun; 714 struct aic_acb *acb; 715 struct scsipi_link *sc_link; 716 struct aic_tinfo *ti; 717 718 /* 719 * The SCSI chip made a snapshot of the data bus while the reselection 720 * was being negotiated. This enables us to determine which target did 721 * the reselect. 722 */ 723 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 724 if (selid & (selid - 1)) { 725 printf("%s: reselect with invalid selid %02x; " 726 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 727 AIC_BREAK(); 728 goto reset; 729 } 730 731 /* Search wait queue for disconnected cmd 732 * The list should be short, so I haven't bothered with 733 * any more sophisticated structures than a simple 734 * singly linked list. 735 */ 736 target = ffs(selid) - 1; 737 lun = message & 0x07; 738 for (acb = sc->nexus_list.tqh_first; acb != NULL; 739 acb = acb->chain.tqe_next) { 740 sc_link = acb->xs->sc_link; 741 if (sc_link->scsipi_scsi.target == target && sc_link->scsipi_scsi.lun == lun) 742 break; 743 } 744 if (acb == NULL) { 745 printf("%s: reselect from target %d lun %d with no nexus; " 746 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 747 AIC_BREAK(); 748 goto abort; 749 } 750 751 /* Make this nexus active again. */ 752 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 753 sc->sc_state = AIC_CONNECTED; 754 sc->sc_nexus = acb; 755 ti = &sc->sc_tinfo[target]; 756 ti->lubusy |= (1 << lun); 757 aic_setsync(sc, ti); 758 759 if (acb->flags & ACB_RESET) 760 aic_sched_msgout(sc, SEND_DEV_RESET); 761 else if (acb->flags & ACB_ABORT) 762 aic_sched_msgout(sc, SEND_ABORT); 763 764 /* Do an implicit RESTORE POINTERS. */ 765 sc->sc_dp = acb->data_addr; 766 sc->sc_dleft = acb->data_length; 767 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 768 sc->sc_cleft = acb->scsipi_cmd_length; 769 770 return (0); 771 772 reset: 773 aic_sched_msgout(sc, SEND_DEV_RESET); 774 return (1); 775 776 abort: 777 aic_sched_msgout(sc, SEND_ABORT); 778 return (1); 779 } 780 781 /* 783 * Schedule a SCSI operation. This has now been pulled out of the interrupt 784 * handler so that we may call it from aic_scsi_cmd and aic_done. This may 785 * save us an unecessary interrupt just to get things going. Should only be 786 * called when state == AIC_IDLE and at bio pl. 787 */ 788 void 789 aic_sched(sc) 790 register struct aic_softc *sc; 791 { 792 struct aic_acb *acb; 793 struct scsipi_link *sc_link; 794 struct aic_tinfo *ti; 795 bus_space_tag_t iot = sc->sc_iot; 796 bus_space_handle_t ioh = sc->sc_ioh; 797 798 /* 799 * Find first acb in ready queue that is for a target/lunit pair that 800 * is not busy. 801 */ 802 bus_space_write_1(iot, ioh, CLRSINT1, 803 CLRSELTIMO | CLRBUSFREE | CLRSCSIPERR); 804 for (acb = sc->ready_list.tqh_first; acb != NULL; 805 acb = acb->chain.tqe_next) { 806 sc_link = acb->xs->sc_link; 807 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 808 if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) { 809 AIC_MISC(("selecting %d:%d ", 810 sc_link->scsipi_scsi.target, sc_link->scsipi_scsi.lun)); 811 TAILQ_REMOVE(&sc->ready_list, acb, chain); 812 sc->sc_nexus = acb; 813 aic_select(sc, acb); 814 return; 815 } else 816 AIC_MISC(("%d:%d busy\n", 817 sc_link->scsipi_scsi.target, sc_link->scsipi_scsi.lun)); 818 } 819 AIC_MISC(("idle ")); 820 /* Nothing to start; just enable reselections and wait. */ 821 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI); 822 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST); 823 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 824 } 825 826 void 828 aic_sense(sc, acb) 829 struct aic_softc *sc; 830 struct aic_acb *acb; 831 { 832 struct scsipi_xfer *xs = acb->xs; 833 struct scsipi_link *sc_link = xs->sc_link; 834 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 835 struct scsipi_sense *ss = (void *)&acb->scsipi_cmd; 836 837 AIC_MISC(("requesting sense ")); 838 /* Next, setup a request sense command block */ 839 bzero(ss, sizeof(*ss)); 840 ss->opcode = REQUEST_SENSE; 841 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 842 ss->length = sizeof(struct scsipi_sense_data); 843 acb->scsipi_cmd_length = sizeof(*ss); 844 acb->data_addr = (char *)&xs->sense.scsi_sense; 845 acb->data_length = sizeof(struct scsipi_sense_data); 846 acb->flags |= ACB_SENSE; 847 ti->senses++; 848 if (acb->flags & ACB_NEXUS) 849 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 850 if (acb == sc->sc_nexus) { 851 aic_select(sc, acb); 852 } else { 853 aic_dequeue(sc, acb); 854 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 855 if (sc->sc_state == AIC_IDLE) 856 aic_sched(sc); 857 } 858 } 859 860 /* 861 * POST PROCESSING OF SCSI_CMD (usually current) 862 */ 863 void 864 aic_done(sc, acb) 865 struct aic_softc *sc; 866 struct aic_acb *acb; 867 { 868 struct scsipi_xfer *xs = acb->xs; 869 struct scsipi_link *sc_link = xs->sc_link; 870 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 871 872 AIC_TRACE(("aic_done ")); 873 874 /* 875 * Now, if we've come here with no error code, i.e. we've kept the 876 * initial XS_NOERROR, and the status code signals that we should 877 * check sense, we'll need to set up a request sense cmd block and 878 * push the command back into the ready queue *before* any other 879 * commands for this target/lunit, else we lose the sense info. 880 * We don't support chk sense conditions for the request sense cmd. 881 */ 882 if (xs->error == XS_NOERROR) { 883 if (acb->flags & ACB_ABORT) { 884 xs->error = XS_DRIVER_STUFFUP; 885 } else if (acb->flags & ACB_SENSE) { 886 xs->error = XS_SENSE; 887 } else if (acb->target_stat == SCSI_CHECK) { 888 /* First, save the return values */ 889 xs->resid = acb->data_length; 890 xs->status = acb->target_stat; 891 aic_sense(sc, acb); 892 return; 893 } else { 894 xs->resid = acb->data_length; 895 } 896 } 897 898 xs->xs_status |= XS_STS_DONE; 899 900 #if AIC_DEBUG 901 if ((aic_debug & AIC_SHOWMISC) != 0) { 902 if (xs->resid != 0) 903 printf("resid=%d ", xs->resid); 904 if (xs->error == XS_SENSE) 905 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 906 else 907 printf("error=%d\n", xs->error); 908 } 909 #endif 910 911 /* 912 * Remove the ACB from whatever queue it happens to be on. 913 */ 914 if (acb->flags & ACB_NEXUS) 915 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 916 if (acb == sc->sc_nexus) { 917 sc->sc_nexus = NULL; 918 sc->sc_state = AIC_IDLE; 919 aic_sched(sc); 920 } else 921 aic_dequeue(sc, acb); 922 923 aic_free_acb(sc, acb, xs->xs_control); 924 ti->cmds++; 925 scsipi_done(xs); 926 } 927 928 void 929 aic_dequeue(sc, acb) 930 struct aic_softc *sc; 931 struct aic_acb *acb; 932 { 933 934 if (acb->flags & ACB_NEXUS) { 935 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 936 } else { 937 TAILQ_REMOVE(&sc->ready_list, acb, chain); 938 } 939 } 940 941 /* 943 * INTERRUPT/PROTOCOL ENGINE 944 */ 945 946 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 947 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 948 #define ISEXTMSG(m) ((m) == 0x01) 949 950 /* 951 * Precondition: 952 * The SCSI bus is already in the MSGI phase and there is a message byte 953 * on the bus, along with an asserted REQ signal. 954 */ 955 void 956 aic_msgin(sc) 957 register struct aic_softc *sc; 958 { 959 bus_space_tag_t iot = sc->sc_iot; 960 bus_space_handle_t ioh = sc->sc_ioh; 961 u_char sstat1; 962 int n; 963 964 AIC_TRACE(("aic_msgin ")); 965 966 if (sc->sc_prevphase == PH_MSGIN) { 967 /* This is a continuation of the previous message. */ 968 n = sc->sc_imp - sc->sc_imess; 969 goto nextbyte; 970 } 971 972 /* This is a new MESSAGE IN phase. Clean up our state. */ 973 sc->sc_flags &= ~AIC_DROP_MSGIN; 974 975 nextmsg: 976 n = 0; 977 sc->sc_imp = &sc->sc_imess[n]; 978 979 nextbyte: 980 /* 981 * Read a whole message, but don't ack the last byte. If we reject the 982 * message, we have to assert ATN during the message transfer phase 983 * itself. 984 */ 985 for (;;) { 986 for (;;) { 987 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 988 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 989 break; 990 /* Wait for REQINIT. XXX Need timeout. */ 991 } 992 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 993 /* 994 * Target left MESSAGE IN, probably because it 995 * a) noticed our ATN signal, or 996 * b) ran out of messages. 997 */ 998 goto out; 999 } 1000 1001 /* If parity error, just dump everything on the floor. */ 1002 if ((sstat1 & SCSIPERR) != 0) { 1003 sc->sc_flags |= AIC_DROP_MSGIN; 1004 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1005 } 1006 1007 /* Gather incoming message bytes if needed. */ 1008 if ((sc->sc_flags & AIC_DROP_MSGIN) == 0) { 1009 if (n >= AIC_MAX_MSG_LEN) { 1010 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1011 sc->sc_flags |= AIC_DROP_MSGIN; 1012 aic_sched_msgout(sc, SEND_REJECT); 1013 } else { 1014 *sc->sc_imp++ = bus_space_read_1(iot, ioh, 1015 SCSIDAT); 1016 n++; 1017 /* 1018 * This testing is suboptimal, but most 1019 * messages will be of the one byte variety, so 1020 * it should not affect performance 1021 * significantly. 1022 */ 1023 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1024 break; 1025 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1026 break; 1027 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1028 n == sc->sc_imess[1] + 2) 1029 break; 1030 } 1031 } else 1032 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1033 1034 /* 1035 * If we reach this spot we're either: 1036 * a) in the middle of a multi-byte message, or 1037 * b) dropping bytes. 1038 */ 1039 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1040 /* Ack the last byte read. */ 1041 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1042 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1043 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1044 ; 1045 } 1046 1047 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1048 1049 /* We now have a complete message. Parse it. */ 1050 switch (sc->sc_state) { 1051 struct aic_acb *acb; 1052 struct scsipi_link *sc_link; 1053 struct aic_tinfo *ti; 1054 1055 case AIC_CONNECTED: 1056 AIC_ASSERT(sc->sc_nexus != NULL); 1057 acb = sc->sc_nexus; 1058 ti = &sc->sc_tinfo[acb->xs->sc_link->scsipi_scsi.target]; 1059 1060 switch (sc->sc_imess[0]) { 1061 case MSG_CMDCOMPLETE: 1062 if (sc->sc_dleft < 0) { 1063 sc_link = acb->xs->sc_link; 1064 printf("%s: %d extra bytes from %d:%d\n", 1065 sc->sc_dev.dv_xname, -sc->sc_dleft, 1066 sc_link->scsipi_scsi.target, sc_link->scsipi_scsi.lun); 1067 acb->data_length = 0; 1068 } 1069 acb->xs->resid = acb->data_length = sc->sc_dleft; 1070 sc->sc_state = AIC_CMDCOMPLETE; 1071 break; 1072 1073 case MSG_PARITY_ERROR: 1074 /* Resend the last message. */ 1075 aic_sched_msgout(sc, sc->sc_lastmsg); 1076 break; 1077 1078 case MSG_MESSAGE_REJECT: 1079 AIC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1080 switch (sc->sc_lastmsg) { 1081 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1082 case SEND_IDENTIFY: 1083 ti->flags &= ~(DO_SYNC | DO_WIDE); 1084 ti->period = ti->offset = 0; 1085 aic_setsync(sc, ti); 1086 ti->width = 0; 1087 break; 1088 #endif 1089 #if AIC_USE_SYNCHRONOUS 1090 case SEND_SDTR: 1091 ti->flags &= ~DO_SYNC; 1092 ti->period = ti->offset = 0; 1093 aic_setsync(sc, ti); 1094 break; 1095 #endif 1096 #if AIC_USE_WIDE 1097 case SEND_WDTR: 1098 ti->flags &= ~DO_WIDE; 1099 ti->width = 0; 1100 break; 1101 #endif 1102 case SEND_INIT_DET_ERR: 1103 aic_sched_msgout(sc, SEND_ABORT); 1104 break; 1105 } 1106 break; 1107 1108 case MSG_NOOP: 1109 break; 1110 1111 case MSG_DISCONNECT: 1112 ti->dconns++; 1113 sc->sc_state = AIC_DISCONNECT; 1114 break; 1115 1116 case MSG_SAVEDATAPOINTER: 1117 acb->data_addr = sc->sc_dp; 1118 acb->data_length = sc->sc_dleft; 1119 break; 1120 1121 case MSG_RESTOREPOINTERS: 1122 sc->sc_dp = acb->data_addr; 1123 sc->sc_dleft = acb->data_length; 1124 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1125 sc->sc_cleft = acb->scsipi_cmd_length; 1126 break; 1127 1128 case MSG_EXTENDED: 1129 switch (sc->sc_imess[2]) { 1130 #if AIC_USE_SYNCHRONOUS 1131 case MSG_EXT_SDTR: 1132 if (sc->sc_imess[1] != 3) 1133 goto reject; 1134 ti->period = sc->sc_imess[3]; 1135 ti->offset = sc->sc_imess[4]; 1136 ti->flags &= ~DO_SYNC; 1137 if (ti->offset == 0) { 1138 } else if (ti->period < sc->sc_minsync || 1139 ti->period > sc->sc_maxsync || 1140 ti->offset > 8) { 1141 ti->period = ti->offset = 0; 1142 aic_sched_msgout(sc, SEND_SDTR); 1143 } else { 1144 scsi_print_addr(acb->xs->sc_link); 1145 printf("sync, offset %d, " 1146 "period %dnsec\n", 1147 ti->offset, ti->period * 4); 1148 } 1149 aic_setsync(sc, ti); 1150 break; 1151 #endif 1152 1153 #if AIC_USE_WIDE 1154 case MSG_EXT_WDTR: 1155 if (sc->sc_imess[1] != 2) 1156 goto reject; 1157 ti->width = sc->sc_imess[3]; 1158 ti->flags &= ~DO_WIDE; 1159 if (ti->width == 0) { 1160 } else if (ti->width > AIC_MAX_WIDTH) { 1161 ti->width = 0; 1162 aic_sched_msgout(sc, SEND_WDTR); 1163 } else { 1164 scsi_print_addr(acb->xs->sc_link); 1165 printf("wide, width %d\n", 1166 1 << (3 + ti->width)); 1167 } 1168 break; 1169 #endif 1170 1171 default: 1172 printf("%s: unrecognized MESSAGE EXTENDED; " 1173 "sending REJECT\n", sc->sc_dev.dv_xname); 1174 AIC_BREAK(); 1175 goto reject; 1176 } 1177 break; 1178 1179 default: 1180 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1181 sc->sc_dev.dv_xname); 1182 AIC_BREAK(); 1183 reject: 1184 aic_sched_msgout(sc, SEND_REJECT); 1185 break; 1186 } 1187 break; 1188 1189 case AIC_RESELECTED: 1190 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1191 printf("%s: reselect without IDENTIFY; " 1192 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1193 AIC_BREAK(); 1194 goto reset; 1195 } 1196 1197 (void) aic_reselect(sc, sc->sc_imess[0]); 1198 break; 1199 1200 default: 1201 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1202 sc->sc_dev.dv_xname); 1203 AIC_BREAK(); 1204 reset: 1205 aic_sched_msgout(sc, SEND_DEV_RESET); 1206 break; 1207 1208 #ifdef notdef 1209 abort: 1210 aic_sched_msgout(sc, SEND_ABORT); 1211 break; 1212 #endif 1213 } 1214 1215 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1216 /* Ack the last message byte. */ 1217 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1218 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1219 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1220 ; 1221 1222 /* Go get the next message, if any. */ 1223 goto nextmsg; 1224 1225 out: 1226 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1227 } 1228 1229 /* 1230 * Send the highest priority, scheduled message. 1231 */ 1232 void 1233 aic_msgout(sc) 1234 register struct aic_softc *sc; 1235 { 1236 bus_space_tag_t iot = sc->sc_iot; 1237 bus_space_handle_t ioh = sc->sc_ioh; 1238 #if AIC_USE_SYNCHRONOUS 1239 struct aic_tinfo *ti; 1240 #endif 1241 u_char sstat1; 1242 int n; 1243 1244 AIC_TRACE(("aic_msgout ")); 1245 1246 /* Reset the FIFO. */ 1247 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1248 /* Enable REQ/ACK protocol. */ 1249 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1250 1251 if (sc->sc_prevphase == PH_MSGOUT) { 1252 if (sc->sc_omp == sc->sc_omess) { 1253 /* 1254 * This is a retransmission. 1255 * 1256 * We get here if the target stayed in MESSAGE OUT 1257 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1258 * that all of the previously transmitted messages must 1259 * be sent again, in the same order. Therefore, we 1260 * requeue all the previously transmitted messages, and 1261 * start again from the top. Our simple priority 1262 * scheme keeps the messages in the right order. 1263 */ 1264 AIC_MISC(("retransmitting ")); 1265 sc->sc_msgpriq |= sc->sc_msgoutq; 1266 /* 1267 * Set ATN. If we're just sending a trivial 1-byte 1268 * message, we'll clear ATN later on anyway. 1269 */ 1270 bus_space_write_1(iot, ioh, SCSISIG, PH_MSGOUT | ATNO); 1271 } else { 1272 /* This is a continuation of the previous message. */ 1273 n = sc->sc_omp - sc->sc_omess; 1274 goto nextbyte; 1275 } 1276 } 1277 1278 /* No messages transmitted so far. */ 1279 sc->sc_msgoutq = 0; 1280 sc->sc_lastmsg = 0; 1281 1282 nextmsg: 1283 /* Pick up highest priority message. */ 1284 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1285 sc->sc_msgpriq &= ~sc->sc_currmsg; 1286 sc->sc_msgoutq |= sc->sc_currmsg; 1287 1288 /* Build the outgoing message data. */ 1289 switch (sc->sc_currmsg) { 1290 case SEND_IDENTIFY: 1291 AIC_ASSERT(sc->sc_nexus != NULL); 1292 sc->sc_omess[0] = 1293 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->scsipi_scsi.lun, 1); 1294 n = 1; 1295 break; 1296 1297 #if AIC_USE_SYNCHRONOUS 1298 case SEND_SDTR: 1299 AIC_ASSERT(sc->sc_nexus != NULL); 1300 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1301 sc->sc_omess[4] = MSG_EXTENDED; 1302 sc->sc_omess[3] = 3; 1303 sc->sc_omess[2] = MSG_EXT_SDTR; 1304 sc->sc_omess[1] = ti->period >> 2; 1305 sc->sc_omess[0] = ti->offset; 1306 n = 5; 1307 break; 1308 #endif 1309 1310 #if AIC_USE_WIDE 1311 case SEND_WDTR: 1312 AIC_ASSERT(sc->sc_nexus != NULL); 1313 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1314 sc->sc_omess[3] = MSG_EXTENDED; 1315 sc->sc_omess[2] = 2; 1316 sc->sc_omess[1] = MSG_EXT_WDTR; 1317 sc->sc_omess[0] = ti->width; 1318 n = 4; 1319 break; 1320 #endif 1321 1322 case SEND_DEV_RESET: 1323 sc->sc_flags |= AIC_ABORTING; 1324 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1325 n = 1; 1326 break; 1327 1328 case SEND_REJECT: 1329 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1330 n = 1; 1331 break; 1332 1333 case SEND_PARITY_ERROR: 1334 sc->sc_omess[0] = MSG_PARITY_ERROR; 1335 n = 1; 1336 break; 1337 1338 case SEND_INIT_DET_ERR: 1339 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1340 n = 1; 1341 break; 1342 1343 case SEND_ABORT: 1344 sc->sc_flags |= AIC_ABORTING; 1345 sc->sc_omess[0] = MSG_ABORT; 1346 n = 1; 1347 break; 1348 1349 default: 1350 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1351 sc->sc_dev.dv_xname); 1352 AIC_BREAK(); 1353 sc->sc_omess[0] = MSG_NOOP; 1354 n = 1; 1355 break; 1356 } 1357 sc->sc_omp = &sc->sc_omess[n]; 1358 1359 nextbyte: 1360 /* Send message bytes. */ 1361 for (;;) { 1362 for (;;) { 1363 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1364 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1365 break; 1366 /* Wait for REQINIT. XXX Need timeout. */ 1367 } 1368 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1369 /* 1370 * Target left MESSAGE OUT, possibly to reject 1371 * our message. 1372 * 1373 * If this is the last message being sent, then we 1374 * deassert ATN, since either the target is going to 1375 * ignore this message, or it's going to ask for a 1376 * retransmission via MESSAGE PARITY ERROR (in which 1377 * case we reassert ATN anyway). 1378 */ 1379 if (sc->sc_msgpriq == 0) 1380 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1381 goto out; 1382 } 1383 1384 /* Clear ATN before last byte if this is the last message. */ 1385 if (n == 1 && sc->sc_msgpriq == 0) 1386 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1387 /* Send message byte. */ 1388 bus_space_write_1(iot, ioh, SCSIDAT, *--sc->sc_omp); 1389 --n; 1390 /* Keep track of the last message we've sent any bytes of. */ 1391 sc->sc_lastmsg = sc->sc_currmsg; 1392 /* Wait for ACK to be negated. XXX Need timeout. */ 1393 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1394 ; 1395 1396 if (n == 0) 1397 break; 1398 } 1399 1400 /* We get here only if the entire message has been transmitted. */ 1401 if (sc->sc_msgpriq != 0) { 1402 /* There are more outgoing messages. */ 1403 goto nextmsg; 1404 } 1405 1406 /* 1407 * The last message has been transmitted. We need to remember the last 1408 * message transmitted (in case the target switches to MESSAGE IN phase 1409 * and sends a MESSAGE REJECT), and the list of messages transmitted 1410 * this time around (in case the target stays in MESSAGE OUT phase to 1411 * request a retransmit). 1412 */ 1413 1414 out: 1415 /* Disable REQ/ACK protocol. */ 1416 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1417 } 1418 1419 /* aic_dataout_pio: perform a data transfer using the FIFO datapath in the 1421 * aic6360 1422 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1423 * and ACK deasserted (i.e. waiting for a data byte) 1424 * This new revision has been optimized (I tried) to make the common case fast, 1425 * and the rarer cases (as a result) somewhat more comlex 1426 */ 1427 int 1428 aic_dataout_pio(sc, p, n) 1429 register struct aic_softc *sc; 1430 u_char *p; 1431 int n; 1432 { 1433 bus_space_tag_t iot = sc->sc_iot; 1434 bus_space_handle_t ioh = sc->sc_ioh; 1435 register u_char dmastat = 0; 1436 int out = 0; 1437 #define DOUTAMOUNT 128 /* Full FIFO */ 1438 1439 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1440 bus_space_read_1(iot, ioh, SSTAT2))); 1441 1442 /* Clear host FIFO and counter. */ 1443 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO | WRITE); 1444 /* Enable FIFOs. */ 1445 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1446 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1447 1448 /* Turn off ENREQINIT for now. */ 1449 bus_space_write_1(iot, ioh, SIMODE1, 1450 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1451 1452 /* I have tried to make the main loop as tight as possible. This 1453 * means that some of the code following the loop is a bit more 1454 * complex than otherwise. 1455 */ 1456 while (n > 0) { 1457 for (;;) { 1458 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1459 if ((dmastat & (DFIFOEMP | INTSTAT)) != 0) 1460 break; 1461 } 1462 1463 if ((dmastat & INTSTAT) != 0) 1464 goto phasechange; 1465 1466 if (n >= DOUTAMOUNT) { 1467 n -= DOUTAMOUNT; 1468 out += DOUTAMOUNT; 1469 1470 #if AIC_USE_DWORDS 1471 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1472 (u_int32_t *) p, DOUTAMOUNT >> 2); 1473 #else 1474 bus_space_write_multi_2(iot, ioh, DMADATA, 1475 (u_int16_t *) p, DOUTAMOUNT >> 1); 1476 #endif 1477 1478 p += DOUTAMOUNT; 1479 } else { 1480 register int xfer; 1481 1482 xfer = n; 1483 AIC_MISC(("%d> ", xfer)); 1484 1485 n -= xfer; 1486 out += xfer; 1487 1488 #if AIC_USE_DWORDS 1489 if (xfer >= 12) { 1490 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1491 (u_int32_t *) p, xfer >> 2); 1492 p += xfer & ~3; 1493 xfer &= 3; 1494 } 1495 #else 1496 if (xfer >= 8) { 1497 bus_space_write_multi_2(iot, ioh, DMADATA, 1498 (u_int16_t *) p, xfer >> 1); 1499 p += xfer & ~1; 1500 xfer &= 1; 1501 } 1502 #endif 1503 1504 if (xfer > 0) { 1505 bus_space_write_1(iot, ioh, DMACNTRL0, 1506 ENDMA | B8MODE | WRITE); 1507 bus_space_write_multi_1(iot, ioh, DMADATA, 1508 p, xfer); 1509 p += xfer; 1510 bus_space_write_1(iot, ioh, DMACNTRL0, 1511 ENDMA | DWORDPIO | WRITE); 1512 } 1513 } 1514 } 1515 1516 if (out == 0) { 1517 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1518 for (;;) { 1519 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1520 != 0) 1521 break; 1522 } 1523 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1524 AIC_MISC(("extra data ")); 1525 } else { 1526 /* See the bytes off chip */ 1527 for (;;) { 1528 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1529 if ((dmastat & INTSTAT) != 0) 1530 goto phasechange; 1531 if ((dmastat & DFIFOEMP) != 0 && 1532 (bus_space_read_1(iot, ioh, SSTAT2) & SEMPTY) != 0) 1533 break; 1534 } 1535 } 1536 1537 phasechange: 1538 if ((dmastat & INTSTAT) != 0) { 1539 /* Some sort of phase change. */ 1540 int amount; 1541 1542 /* Stop transfers, do some accounting */ 1543 amount = bus_space_read_1(iot, ioh, FIFOSTAT) 1544 + (bus_space_read_1(iot, ioh, SSTAT2) & 15); 1545 if (amount > 0) { 1546 out -= amount; 1547 bus_space_write_1(iot, ioh, DMACNTRL0, 1548 RSTFIFO | WRITE); 1549 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH); 1550 AIC_MISC(("+%d ", amount)); 1551 } 1552 } 1553 1554 /* Turn on ENREQINIT again. */ 1555 bus_space_write_1(iot, ioh, SIMODE1, 1556 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1557 1558 /* Stop the FIFO data path. */ 1559 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1560 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1561 1562 return out; 1563 } 1564 1565 /* aic_datain_pio: perform data transfers using the FIFO datapath in the 1567 * aic6360 1568 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1569 * and ACK deasserted (i.e. at least one byte is ready). 1570 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1571 * transferred. This, is OK for fast targets, but not so smart for slow 1572 * targets which don't disconnect or for huge transfers. 1573 */ 1574 int 1575 aic_datain_pio(sc, p, n) 1576 register struct aic_softc *sc; 1577 u_char *p; 1578 int n; 1579 { 1580 bus_space_tag_t iot = sc->sc_iot; 1581 bus_space_handle_t ioh = sc->sc_ioh; 1582 register u_char dmastat; 1583 int in = 0; 1584 #define DINAMOUNT 128 /* Full FIFO */ 1585 1586 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1587 bus_space_read_1(iot, ioh, SSTAT2))); 1588 1589 /* Clear host FIFO and counter. */ 1590 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1591 /* Enable FIFOs. */ 1592 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO); 1593 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1594 1595 /* Turn off ENREQINIT for now. */ 1596 bus_space_write_1(iot, ioh, SIMODE1, 1597 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1598 1599 /* We leave this loop if one or more of the following is true: 1600 * a) phase != PH_DATAIN && FIFOs are empty 1601 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 1602 */ 1603 while (n > 0) { 1604 /* Wait for fifo half full or phase mismatch */ 1605 for (;;) { 1606 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1607 if ((dmastat & (DFIFOFULL | INTSTAT)) != 0) 1608 break; 1609 } 1610 1611 if ((dmastat & DFIFOFULL) != 0) { 1612 n -= DINAMOUNT; 1613 in += DINAMOUNT; 1614 1615 #if AIC_USE_DWORDS 1616 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1617 (u_int32_t *) p, DINAMOUNT >> 2); 1618 #else 1619 bus_space_read_multi_2(iot, ioh, DMADATA, 1620 (u_int16_t *) p, DINAMOUNT >> 1); 1621 #endif 1622 1623 p += DINAMOUNT; 1624 } else { 1625 register int xfer; 1626 1627 xfer = min(bus_space_read_1(iot, ioh, FIFOSTAT), n); 1628 AIC_MISC((">%d ", xfer)); 1629 1630 n -= xfer; 1631 in += xfer; 1632 1633 #if AIC_USE_DWORDS 1634 if (xfer >= 12) { 1635 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1636 (u_int32_t *) p, xfer >> 2); 1637 p += xfer & ~3; 1638 xfer &= 3; 1639 } 1640 #else 1641 if (xfer >= 8) { 1642 bus_space_read_multi_2(iot, ioh, DMADATA, 1643 (u_int16_t *) p, xfer >> 1); 1644 p += xfer & ~1; 1645 xfer &= 1; 1646 } 1647 #endif 1648 1649 if (xfer > 0) { 1650 bus_space_write_1(iot, ioh, DMACNTRL0, 1651 ENDMA | B8MODE); 1652 bus_space_read_multi_1(iot, ioh, DMADATA, 1653 p, xfer); 1654 p += xfer; 1655 bus_space_write_1(iot, ioh, DMACNTRL0, 1656 ENDMA | DWORDPIO); 1657 } 1658 } 1659 1660 if ((dmastat & INTSTAT) != 0) 1661 goto phasechange; 1662 } 1663 1664 /* Some SCSI-devices are rude enough to transfer more data than what 1665 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1666 * requested 512. Test for progress, i.e. real transfers. If no real 1667 * transfers have been performed (n is probably already zero) and the 1668 * FIFO is not empty, waste some bytes.... 1669 */ 1670 if (in == 0) { 1671 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1672 for (;;) { 1673 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1674 != 0) 1675 break; 1676 } 1677 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1678 AIC_MISC(("extra data ")); 1679 } 1680 1681 phasechange: 1682 /* Turn on ENREQINIT again. */ 1683 bus_space_write_1(iot, ioh, SIMODE1, 1684 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1685 1686 /* Stop the FIFO data path. */ 1687 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1688 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1689 1690 return in; 1691 } 1692 1693 /* 1695 * This is the workhorse routine of the driver. 1696 * Deficiencies (for now): 1697 * 1) always uses programmed I/O 1698 */ 1699 int 1700 aicintr(arg) 1701 void *arg; 1702 { 1703 register struct aic_softc *sc = arg; 1704 bus_space_tag_t iot = sc->sc_iot; 1705 bus_space_handle_t ioh = sc->sc_ioh; 1706 u_char sstat0, sstat1; 1707 register struct aic_acb *acb; 1708 register struct scsipi_link *sc_link; 1709 struct aic_tinfo *ti; 1710 int n; 1711 1712 /* 1713 * Clear INTEN. We enable it again before returning. This makes the 1714 * interrupt esssentially level-triggered. 1715 */ 1716 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1717 1718 AIC_TRACE(("aicintr ")); 1719 1720 loop: 1721 /* 1722 * First check for abnormal conditions, such as reset. 1723 */ 1724 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1725 AIC_MISC(("sstat1:0x%02x ", sstat1)); 1726 1727 if ((sstat1 & SCSIRSTI) != 0) { 1728 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1729 goto reset; 1730 } 1731 1732 /* 1733 * Check for less serious errors. 1734 */ 1735 if ((sstat1 & SCSIPERR) != 0) { 1736 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1737 bus_space_write_1(iot, ioh, CLRSINT1, CLRSCSIPERR); 1738 if (sc->sc_prevphase == PH_MSGIN) { 1739 sc->sc_flags |= AIC_DROP_MSGIN; 1740 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1741 } else 1742 aic_sched_msgout(sc, SEND_INIT_DET_ERR); 1743 } 1744 1745 /* 1746 * If we're not already busy doing something test for the following 1747 * conditions: 1748 * 1) We have been reselected by something 1749 * 2) We have selected something successfully 1750 * 3) Our selection process has timed out 1751 * 4) This is really a bus free interrupt just to get a new command 1752 * going? 1753 * 5) Spurious interrupt? 1754 */ 1755 switch (sc->sc_state) { 1756 case AIC_IDLE: 1757 case AIC_SELECTING: 1758 sstat0 = bus_space_read_1(iot, ioh, SSTAT0); 1759 AIC_MISC(("sstat0:0x%02x ", sstat0)); 1760 1761 if ((sstat0 & TARGET) != 0) { 1762 /* 1763 * We don't currently support target mode. 1764 */ 1765 printf("%s: target mode selected; going to BUS FREE\n", 1766 sc->sc_dev.dv_xname); 1767 bus_space_write_1(iot, ioh, SCSISIG, 0); 1768 1769 goto sched; 1770 } else if ((sstat0 & SELDI) != 0) { 1771 AIC_MISC(("reselected ")); 1772 1773 /* 1774 * If we're trying to select a target ourselves, 1775 * push our command back into the ready list. 1776 */ 1777 if (sc->sc_state == AIC_SELECTING) { 1778 AIC_MISC(("backoff selector ")); 1779 AIC_ASSERT(sc->sc_nexus != NULL); 1780 acb = sc->sc_nexus; 1781 sc->sc_nexus = NULL; 1782 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1783 } 1784 1785 /* Save reselection ID. */ 1786 sc->sc_selid = bus_space_read_1(iot, ioh, SELID); 1787 1788 sc->sc_state = AIC_RESELECTED; 1789 } else if ((sstat0 & SELDO) != 0) { 1790 AIC_MISC(("selected ")); 1791 1792 /* We have selected a target. Things to do: 1793 * a) Determine what message(s) to send. 1794 * b) Verify that we're still selecting the target. 1795 * c) Mark device as busy. 1796 */ 1797 if (sc->sc_state != AIC_SELECTING) { 1798 printf("%s: selection out while idle; " 1799 "resetting\n", sc->sc_dev.dv_xname); 1800 AIC_BREAK(); 1801 goto reset; 1802 } 1803 AIC_ASSERT(sc->sc_nexus != NULL); 1804 acb = sc->sc_nexus; 1805 sc_link = acb->xs->sc_link; 1806 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1807 1808 sc->sc_msgpriq = SEND_IDENTIFY; 1809 if (acb->flags & ACB_RESET) 1810 sc->sc_msgpriq |= SEND_DEV_RESET; 1811 else if (acb->flags & ACB_ABORT) 1812 sc->sc_msgpriq |= SEND_ABORT; 1813 else { 1814 #if AIC_USE_SYNCHRONOUS 1815 if ((ti->flags & DO_SYNC) != 0) 1816 sc->sc_msgpriq |= SEND_SDTR; 1817 #endif 1818 #if AIC_USE_WIDE 1819 if ((ti->flags & DO_WIDE) != 0) 1820 sc->sc_msgpriq |= SEND_WDTR; 1821 #endif 1822 } 1823 1824 acb->flags |= ACB_NEXUS; 1825 ti->lubusy |= (1 << sc_link->scsipi_scsi.lun); 1826 1827 /* Do an implicit RESTORE POINTERS. */ 1828 sc->sc_dp = acb->data_addr; 1829 sc->sc_dleft = acb->data_length; 1830 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1831 sc->sc_cleft = acb->scsipi_cmd_length; 1832 1833 /* On our first connection, schedule a timeout. */ 1834 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1835 timeout(aic_timeout, acb, 1836 (acb->timeout * hz) / 1000); 1837 1838 sc->sc_state = AIC_CONNECTED; 1839 } else if ((sstat1 & SELTO) != 0) { 1840 AIC_MISC(("selection timeout ")); 1841 1842 if (sc->sc_state != AIC_SELECTING) { 1843 printf("%s: selection timeout while idle; " 1844 "resetting\n", sc->sc_dev.dv_xname); 1845 AIC_BREAK(); 1846 goto reset; 1847 } 1848 AIC_ASSERT(sc->sc_nexus != NULL); 1849 acb = sc->sc_nexus; 1850 1851 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1852 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 1853 bus_space_write_1(iot, ioh, CLRSINT1, CLRSELTIMO); 1854 delay(250); 1855 1856 acb->xs->error = XS_SELTIMEOUT; 1857 goto finish; 1858 } else { 1859 if (sc->sc_state != AIC_IDLE) { 1860 printf("%s: BUS FREE while not idle; " 1861 "state=%d\n", 1862 sc->sc_dev.dv_xname, sc->sc_state); 1863 AIC_BREAK(); 1864 goto out; 1865 } 1866 1867 goto sched; 1868 } 1869 1870 /* 1871 * Turn off selection stuff, and prepare to catch bus free 1872 * interrupts, parity errors, and phase changes. 1873 */ 1874 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRSTCNT | CLRCH); 1875 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1876 bus_space_write_1(iot, ioh, SCSISEQ, ENAUTOATNP); 1877 bus_space_write_1(iot, ioh, CLRSINT0, CLRSELDI | CLRSELDO); 1878 bus_space_write_1(iot, ioh, CLRSINT1, 1879 CLRBUSFREE | CLRPHASECHG); 1880 bus_space_write_1(iot, ioh, SIMODE0, 0); 1881 bus_space_write_1(iot, ioh, SIMODE1, 1882 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | 1883 ENPHASECHG); 1884 1885 sc->sc_flags = 0; 1886 sc->sc_prevphase = PH_INVALID; 1887 goto dophase; 1888 } 1889 1890 if ((sstat1 & BUSFREE) != 0) { 1891 /* We've gone to BUS FREE phase. */ 1892 bus_space_write_1(iot, ioh, CLRSINT1, 1893 CLRBUSFREE | CLRPHASECHG); 1894 1895 switch (sc->sc_state) { 1896 case AIC_RESELECTED: 1897 goto sched; 1898 1899 case AIC_CONNECTED: 1900 AIC_ASSERT(sc->sc_nexus != NULL); 1901 acb = sc->sc_nexus; 1902 1903 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1904 if (sc->sc_prevphase == PH_MSGOUT) { 1905 /* 1906 * If the target went to BUS FREE phase during 1907 * or immediately after sending a SDTR or WDTR 1908 * message, disable negotiation. 1909 */ 1910 sc_link = acb->xs->sc_link; 1911 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1912 switch (sc->sc_lastmsg) { 1913 #if AIC_USE_SYNCHRONOUS 1914 case SEND_SDTR: 1915 ti->flags &= ~DO_SYNC; 1916 ti->period = ti->offset = 0; 1917 break; 1918 #endif 1919 #if AIC_USE_WIDE 1920 case SEND_WDTR: 1921 ti->flags &= ~DO_WIDE; 1922 ti->width = 0; 1923 break; 1924 #endif 1925 } 1926 } 1927 #endif 1928 1929 if ((sc->sc_flags & AIC_ABORTING) == 0) { 1930 /* 1931 * Section 5.1.1 of the SCSI 2 spec suggests 1932 * issuing a REQUEST SENSE following an 1933 * unexpected disconnect. Some devices go into 1934 * a contingent allegiance condition when 1935 * disconnecting, and this is necessary to 1936 * clean up their state. 1937 */ 1938 printf("%s: unexpected disconnect; " 1939 "sending REQUEST SENSE\n", 1940 sc->sc_dev.dv_xname); 1941 AIC_BREAK(); 1942 aic_sense(sc, acb); 1943 goto out; 1944 } 1945 1946 acb->xs->error = XS_DRIVER_STUFFUP; 1947 goto finish; 1948 1949 case AIC_DISCONNECT: 1950 AIC_ASSERT(sc->sc_nexus != NULL); 1951 acb = sc->sc_nexus; 1952 #if 1 /* XXXX */ 1953 acb->data_addr = sc->sc_dp; 1954 acb->data_length = sc->sc_dleft; 1955 #endif 1956 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1957 sc->sc_nexus = NULL; 1958 goto sched; 1959 1960 case AIC_CMDCOMPLETE: 1961 AIC_ASSERT(sc->sc_nexus != NULL); 1962 acb = sc->sc_nexus; 1963 goto finish; 1964 } 1965 } 1966 1967 bus_space_write_1(iot, ioh, CLRSINT1, CLRPHASECHG); 1968 1969 dophase: 1970 if ((sstat1 & REQINIT) == 0) { 1971 /* Wait for REQINIT. */ 1972 goto out; 1973 } 1974 1975 sc->sc_phase = bus_space_read_1(iot, ioh, SCSISIG) & PH_MASK; 1976 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase); 1977 1978 switch (sc->sc_phase) { 1979 case PH_MSGOUT: 1980 if (sc->sc_state != AIC_CONNECTED && 1981 sc->sc_state != AIC_RESELECTED) 1982 break; 1983 aic_msgout(sc); 1984 sc->sc_prevphase = PH_MSGOUT; 1985 goto loop; 1986 1987 case PH_MSGIN: 1988 if (sc->sc_state != AIC_CONNECTED && 1989 sc->sc_state != AIC_RESELECTED) 1990 break; 1991 aic_msgin(sc); 1992 sc->sc_prevphase = PH_MSGIN; 1993 goto loop; 1994 1995 case PH_CMD: 1996 if (sc->sc_state != AIC_CONNECTED) 1997 break; 1998 #if AIC_DEBUG 1999 if ((aic_debug & AIC_SHOWMISC) != 0) { 2000 AIC_ASSERT(sc->sc_nexus != NULL); 2001 acb = sc->sc_nexus; 2002 printf("cmd=0x%02x+%d ", 2003 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length-1); 2004 } 2005 #endif 2006 n = aic_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 2007 sc->sc_cp += n; 2008 sc->sc_cleft -= n; 2009 sc->sc_prevphase = PH_CMD; 2010 goto loop; 2011 2012 case PH_DATAOUT: 2013 if (sc->sc_state != AIC_CONNECTED) 2014 break; 2015 AIC_MISC(("dataout %d ", sc->sc_dleft)); 2016 n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 2017 sc->sc_dp += n; 2018 sc->sc_dleft -= n; 2019 sc->sc_prevphase = PH_DATAOUT; 2020 goto loop; 2021 2022 case PH_DATAIN: 2023 if (sc->sc_state != AIC_CONNECTED) 2024 break; 2025 AIC_MISC(("datain %d ", sc->sc_dleft)); 2026 n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 2027 sc->sc_dp += n; 2028 sc->sc_dleft -= n; 2029 sc->sc_prevphase = PH_DATAIN; 2030 goto loop; 2031 2032 case PH_STAT: 2033 if (sc->sc_state != AIC_CONNECTED) 2034 break; 2035 AIC_ASSERT(sc->sc_nexus != NULL); 2036 acb = sc->sc_nexus; 2037 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 2038 acb->target_stat = bus_space_read_1(iot, ioh, SCSIDAT); 2039 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 2040 AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2041 sc->sc_prevphase = PH_STAT; 2042 goto loop; 2043 } 2044 2045 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2046 AIC_BREAK(); 2047 reset: 2048 aic_init(sc, 1); 2049 return 1; 2050 2051 finish: 2052 untimeout(aic_timeout, acb); 2053 aic_done(sc, acb); 2054 goto out; 2055 2056 sched: 2057 sc->sc_state = AIC_IDLE; 2058 aic_sched(sc); 2059 goto out; 2060 2061 out: 2062 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 2063 return 1; 2064 } 2065 2066 void 2067 aic_abort(sc, acb) 2068 struct aic_softc *sc; 2069 struct aic_acb *acb; 2070 { 2071 2072 /* 2 secs for the abort */ 2073 acb->timeout = AIC_ABORT_TIMEOUT; 2074 acb->flags |= ACB_ABORT; 2075 2076 if (acb == sc->sc_nexus) { 2077 /* 2078 * If we're still selecting, the message will be scheduled 2079 * after selection is complete. 2080 */ 2081 if (sc->sc_state == AIC_CONNECTED) 2082 aic_sched_msgout(sc, SEND_ABORT); 2083 } else { 2084 aic_dequeue(sc, acb); 2085 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2086 if (sc->sc_state == AIC_IDLE) 2087 aic_sched(sc); 2088 } 2089 } 2090 2091 void 2092 aic_timeout(arg) 2093 void *arg; 2094 { 2095 struct aic_acb *acb = arg; 2096 struct scsipi_xfer *xs = acb->xs; 2097 struct scsipi_link *sc_link = xs->sc_link; 2098 struct aic_softc *sc = sc_link->adapter_softc; 2099 int s; 2100 2101 scsi_print_addr(sc_link); 2102 printf("timed out"); 2103 2104 s = splbio(); 2105 2106 if (acb->flags & ACB_ABORT) { 2107 /* abort timed out */ 2108 printf(" AGAIN\n"); 2109 /* XXX Must reset! */ 2110 } else { 2111 /* abort the operation that has timed out */ 2112 printf("\n"); 2113 acb->xs->error = XS_TIMEOUT; 2114 aic_abort(sc, acb); 2115 } 2116 2117 splx(s); 2118 } 2119 2120 #ifdef AIC_DEBUG 2122 /* 2123 * The following functions are mostly used for debugging purposes, either 2124 * directly called from the driver or from the kernel debugger. 2125 */ 2126 2127 void 2128 aic_show_scsi_cmd(acb) 2129 struct aic_acb *acb; 2130 { 2131 u_char *b = (u_char *)&acb->scsipi_cmd; 2132 struct scsipi_link *sc_link = acb->xs->sc_link; 2133 int i; 2134 2135 scsi_print_addr(sc_link); 2136 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2137 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2138 if (i) 2139 printf(","); 2140 printf("%x", b[i]); 2141 } 2142 printf("\n"); 2143 } else 2144 printf("RESET\n"); 2145 } 2146 2147 void 2148 aic_print_acb(acb) 2149 struct aic_acb *acb; 2150 { 2151 2152 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2153 printf(" dp=%p dleft=%d target_stat=%x\n", 2154 acb->data_addr, acb->data_length, acb->target_stat); 2155 aic_show_scsi_cmd(acb); 2156 } 2157 2158 void 2159 aic_print_active_acb() 2160 { 2161 extern struct cfdriver aic_cd; 2162 struct aic_acb *acb; 2163 struct aic_softc *sc = aic_cd.cd_devs[0]; 2164 2165 printf("ready list:\n"); 2166 for (acb = sc->ready_list.tqh_first; acb != NULL; 2167 acb = acb->chain.tqe_next) 2168 aic_print_acb(acb); 2169 printf("nexus:\n"); 2170 if (sc->sc_nexus != NULL) 2171 aic_print_acb(sc->sc_nexus); 2172 printf("nexus list:\n"); 2173 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2174 acb = acb->chain.tqe_next) 2175 aic_print_acb(acb); 2176 } 2177 2178 void 2179 aic_dump6360(sc) 2180 struct aic_softc *sc; 2181 { 2182 bus_space_tag_t iot = sc->sc_iot; 2183 bus_space_handle_t ioh = sc->sc_ioh; 2184 2185 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIG=%x\n", 2186 bus_space_read_1(iot, ioh, SCSISEQ), 2187 bus_space_read_1(iot, ioh, SXFRCTL0), 2188 bus_space_read_1(iot, ioh, SXFRCTL1), 2189 bus_space_read_1(iot, ioh, SCSISIG)); 2190 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2191 bus_space_read_1(iot, ioh, SSTAT0), 2192 bus_space_read_1(iot, ioh, SSTAT1), 2193 bus_space_read_1(iot, ioh, SSTAT2), 2194 bus_space_read_1(iot, ioh, SSTAT3), 2195 bus_space_read_1(iot, ioh, SSTAT4)); 2196 printf(" SIMODE0=%x SIMODE1=%x DMACNTRL0=%x DMACNTRL1=%x " 2197 "DMASTAT=%x\n", 2198 bus_space_read_1(iot, ioh, SIMODE0), 2199 bus_space_read_1(iot, ioh, SIMODE1), 2200 bus_space_read_1(iot, ioh, DMACNTRL0), 2201 bus_space_read_1(iot, ioh, DMACNTRL1), 2202 bus_space_read_1(iot, ioh, DMASTAT)); 2203 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2204 bus_space_read_1(iot, ioh, FIFOSTAT), 2205 bus_space_read_1(iot, ioh, SCSIBUS)); 2206 } 2207 2208 void 2209 aic_dump_driver(sc) 2210 struct aic_softc *sc; 2211 { 2212 struct aic_tinfo *ti; 2213 int i; 2214 2215 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2216 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2217 "currmsg=%x\n", 2218 sc->sc_state, sc->sc_imess[0], 2219 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2220 for (i = 0; i < 7; i++) { 2221 ti = &sc->sc_tinfo[i]; 2222 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2223 i, ti->cmds, ti->dconns, ti->touts); 2224 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2225 } 2226 } 2227 #endif 2228
Indexes created Mon Oct 27 17:09:47 GMT 2025