aic6360.c revision 1.73
1 /* $NetBSD: aic6360.c,v 1.73 2001/07/07 15:53:14 thorpej Exp $ */ 2 3 #include "opt_ddb.h" 4 #ifdef DDB 5 #define integrate 6 #else 7 #define integrate static inline 8 #endif 9 10 /* 11 * Copyright (c) 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Charles M. Hannum. 24 * 4. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * Copyright (c) 1994 Jarle Greipsland 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 43 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 50 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 51 * POSSIBILITY OF SUCH DAMAGE. 52 */ 53 54 /* 55 * Acknowledgements: Many of the algorithms used in this driver are 56 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 57 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 58 */ 59 60 /* TODO list: 61 * 1) Get the DMA stuff working. 62 * 2) Get the iov/uio stuff working. Is this a good thing ??? 63 * 3) Get the synch stuff working. 64 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 65 */ 66 67 /* 68 * A few customizable items: 69 */ 70 71 /* Use doubleword transfers to/from SCSI chip. Note: This requires 72 * motherboard support. Basicly, some motherboard chipsets are able to 73 * split a 32 bit I/O operation into two 16 bit I/O operations, 74 * transparently to the processor. This speeds up some things, notably long 75 * data transfers. 76 */ 77 #define AIC_USE_DWORDS 0 78 79 /* Synchronous data transfers? */ 80 #define AIC_USE_SYNCHRONOUS 0 81 #define AIC_SYNC_REQ_ACK_OFS 8 82 83 /* Wide data transfers? */ 84 #define AIC_USE_WIDE 0 85 #define AIC_MAX_WIDTH 0 86 87 /* Max attempts made to transmit a message */ 88 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 89 90 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 91 #define AIC_USE_EISA_DMA 0 92 #define AIC_USE_ISA_DMA 0 93 94 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 95 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 96 97 /* Some spin loop parameters (essentially how long to wait some places) 98 * The problem(?) is that sometimes we expect either to be able to transmit a 99 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 100 * returning from the interrupt just to get yanked back for the next byte we 101 * may spin in the interrupt routine waiting for this byte to come. How long? 102 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 103 */ 104 #define AIC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 105 #define AIC_MSGOUT_SPIN 1 106 107 /* Include debug functions? At the end of this file there are a bunch of 108 * functions that will print out various information regarding queued SCSI 109 * commands, driver state and chip contents. You can call them from the 110 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 111 * kernel uses less memory) but you lose the debugging facilities. 112 */ 113 #define AIC_DEBUG 1 114 115 #define AIC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 116 117 /* End of customizable parameters */ 118 119 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 120 #error "I said not yet! Start paying attention... grumble" 121 #endif 122 123 #include <sys/types.h> 124 #include <sys/param.h> 125 #include <sys/systm.h> 126 #include <sys/callout.h> 127 #include <sys/kernel.h> 128 #include <sys/errno.h> 129 #include <sys/ioctl.h> 130 #include <sys/device.h> 131 #include <sys/buf.h> 132 #include <sys/proc.h> 133 #include <sys/user.h> 134 #include <sys/queue.h> 135 136 #include <machine/bus.h> 137 #include <machine/intr.h> 138 139 #include <dev/scsipi/scsi_all.h> 140 #include <dev/scsipi/scsipi_all.h> 141 #include <dev/scsipi/scsi_message.h> 142 #include <dev/scsipi/scsiconf.h> 143 144 #include <dev/ic/aic6360reg.h> 145 #include <dev/ic/aic6360var.h> 146 147 #ifndef DDB 148 #define Debugger() panic("should call debugger here (aic6360.c)") 149 #endif /* ! DDB */ 150 151 #if AIC_DEBUG 152 int aic_debug = 0x00; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRACE; */ 153 #endif 154 155 void aic_minphys(struct buf *); 156 void aic_done(struct aic_softc *, struct aic_acb *); 157 void aic_dequeue(struct aic_softc *, struct aic_acb *); 158 void aic_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 159 void *); 160 int aic_poll(struct aic_softc *, struct scsipi_xfer *, int); 161 integrate void aic_sched_msgout(struct aic_softc *, u_char); 162 integrate void aic_setsync(struct aic_softc *, struct aic_tinfo *); 163 void aic_select(struct aic_softc *, struct aic_acb *); 164 void aic_timeout(void *); 165 void aic_sched(struct aic_softc *); 166 void aic_scsi_reset(struct aic_softc *); 167 void aic_reset(struct aic_softc *); 168 void aic_free_acb(struct aic_softc *, struct aic_acb *); 169 struct aic_acb* aic_get_acb(struct aic_softc *); 170 int aic_reselect(struct aic_softc *, int); 171 void aic_sense(struct aic_softc *, struct aic_acb *); 172 void aic_msgin(struct aic_softc *); 173 void aic_abort(struct aic_softc *, struct aic_acb *); 174 void aic_msgout(struct aic_softc *); 175 int aic_dataout_pio(struct aic_softc *, u_char *, int); 176 int aic_datain_pio(struct aic_softc *, u_char *, int); 177 void aic_update_xfer_mode(struct aic_softc *, int); 178 #if AIC_DEBUG 179 void aic_print_acb(struct aic_acb *); 180 void aic_dump_driver(struct aic_softc *); 181 void aic_dump6360(struct aic_softc *); 182 void aic_show_scsi_cmd(struct aic_acb *); 183 void aic_print_active_acb(void); 184 #endif 185 186 /* 187 * INITIALIZATION ROUTINES (probe, attach ++) 188 */ 189 190 /* Do the real search-for-device. 191 * Prerequisite: sc->sc_iobase should be set to the proper value 192 */ 193 int 194 aic_find(bus_space_tag_t iot, bus_space_handle_t ioh) 195 { 196 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 197 int i; 198 199 /* Remove aic6360 from possible powerdown mode */ 200 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 201 202 /* Thanks to mark (at) aggregate.com for the new method for detecting 203 * whether the chip is present or not. Bonus: may also work for 204 * the AIC-6260! 205 */ 206 AIC_TRACE(("aic: probing for aic-chip\n")); 207 /* 208 * Linux also init's the stack to 1-16 and then clears it, 209 * 6260's don't appear to have an ID reg - mpg 210 */ 211 /* Push the sequence 0,1,..,15 on the stack */ 212 #define STSIZE 16 213 bus_space_write_1(iot, ioh, DMACNTRL1, 0); /* Reset stack pointer */ 214 for (i = 0; i < STSIZE; i++) 215 bus_space_write_1(iot, ioh, STACK, i); 216 217 /* See if we can pull out the same sequence */ 218 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 219 for (i = 0; i < STSIZE && bus_space_read_1(iot, ioh, STACK) == i; i++) 220 ; 221 if (i != STSIZE) { 222 AIC_START(("STACK futzed at %d.\n", i)); 223 return 0; 224 } 225 226 /* See if we can pull the id string out of the ID register, 227 * now only used for informational purposes. 228 */ 229 bzero(chip_id, sizeof(chip_id)); 230 bus_space_read_multi_1(iot, ioh, ID, chip_id, sizeof(IDSTRING) - 1); 231 AIC_START(("AIC found ID: %s ",chip_id)); 232 AIC_START(("chip revision %d\n", 233 (int)bus_space_read_1(iot, ioh, REV))); 234 235 return 1; 236 } 237 238 /* 239 * Attach the AIC6360, fill out some high and low level data structures 240 */ 241 void 242 aicattach(struct aic_softc *sc) 243 { 244 struct scsipi_adapter *adapt = &sc->sc_adapter; 245 struct scsipi_channel *chan = &sc->sc_channel; 246 247 AIC_TRACE(("aicattach ")); 248 sc->sc_state = AIC_INIT; 249 250 sc->sc_initiator = 7; 251 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 252 253 /* 254 * These are the bounds of the sync period, based on the frequency of 255 * the chip's clock input and the size and offset of the sync period 256 * register. 257 * 258 * For a 20Mhz clock, this gives us 25, or 100nS, or 10MB/s, as a 259 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 260 * minimum transfer rate. 261 */ 262 sc->sc_minsync = (2 * 250) / sc->sc_freq; 263 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 264 265 /* 266 * Fill in the scsipi_adapter. 267 */ 268 adapt->adapt_dev = &sc->sc_dev; 269 adapt->adapt_nchannels = 1; 270 adapt->adapt_openings = 8; 271 adapt->adapt_max_periph = 1; 272 adapt->adapt_request = aic_scsipi_request; 273 adapt->adapt_minphys = aic_minphys; 274 275 /* 276 * Fill in the scsipi_channel. 277 */ 278 chan->chan_adapter = adapt; 279 chan->chan_bustype = &scsi_bustype; 280 chan->chan_channel = 0; 281 chan->chan_ntargets = 8; 282 chan->chan_nluns = 8; 283 chan->chan_id = sc->sc_initiator; 284 285 /* 286 * Add reference to adapter so that we drop the reference after 287 * config_found() to make sure the adatper is disabled. 288 */ 289 if (scsipi_adapter_addref(adapt) != 0) { 290 printf("%s: unable to enable controller\n", 291 sc->sc_dev.dv_xname); 292 return; 293 } 294 295 aic_init(sc, 1); /* Init chip and driver */ 296 297 /* 298 * Ask the adapter what subunits are present 299 */ 300 sc->sc_child = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 301 scsipi_adapter_delref(adapt); 302 } 303 304 int 305 aic_activate(struct device *self, enum devact act) 306 { 307 struct aic_softc *sc = (struct aic_softc *) self; 308 int s, rv = 0; 309 310 s = splhigh(); 311 switch (act) { 312 case DVACT_ACTIVATE: 313 rv = EOPNOTSUPP; 314 break; 315 316 case DVACT_DEACTIVATE: 317 if (sc->sc_child != NULL) 318 rv = config_deactivate(sc->sc_child); 319 break; 320 } 321 splx(s); 322 323 return (rv); 324 } 325 326 int 327 aic_detach(struct device *self, int flags) 328 { 329 struct aic_softc *sc = (struct aic_softc *) self; 330 int rv = 0; 331 332 if (sc->sc_child != NULL) 333 rv = config_detach(sc->sc_child, flags); 334 335 return (rv); 336 } 337 338 /* Initialize AIC6360 chip itself 339 * The following conditions should hold: 340 * aic_isa_probe should have succeeded, i.e. the iobase address in aic_softc 341 * must be valid. 342 */ 343 void 344 aic_reset(struct aic_softc *sc) 345 { 346 bus_space_tag_t iot = sc->sc_iot; 347 bus_space_handle_t ioh = sc->sc_ioh; 348 349 /* 350 * Doc. recommends to clear these two registers before 351 * operations commence 352 */ 353 bus_space_write_1(iot, ioh, SCSITEST, 0); 354 bus_space_write_1(iot, ioh, TEST, 0); 355 356 /* Reset SCSI-FIFO and abort any transfers */ 357 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH | CLRSTCNT); 358 359 /* Reset DMA-FIFO */ 360 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 361 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 362 363 /* Disable all selection features */ 364 bus_space_write_1(iot, ioh, SCSISEQ, 0); 365 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 366 367 /* Disable some interrupts */ 368 bus_space_write_1(iot, ioh, SIMODE0, 0x00); 369 /* Clear a slew of interrupts */ 370 bus_space_write_1(iot, ioh, CLRSINT0, 0x7f); 371 372 /* Disable some more interrupts */ 373 bus_space_write_1(iot, ioh, SIMODE1, 0x00); 374 /* Clear another slew of interrupts */ 375 bus_space_write_1(iot, ioh, CLRSINT1, 0xef); 376 377 /* Disable synchronous transfers */ 378 bus_space_write_1(iot, ioh, SCSIRATE, 0); 379 380 /* Haven't seen ant errors (yet) */ 381 bus_space_write_1(iot, ioh, CLRSERR, 0x07); 382 383 /* Set our SCSI-ID */ 384 bus_space_write_1(iot, ioh, SCSIID, sc->sc_initiator << OID_S); 385 bus_space_write_1(iot, ioh, BRSTCNTRL, EISA_BRST_TIM); 386 } 387 388 /* Pull the SCSI RST line for 500 us */ 389 void 390 aic_scsi_reset(struct aic_softc *sc) 391 { 392 bus_space_tag_t iot = sc->sc_iot; 393 bus_space_handle_t ioh = sc->sc_ioh; 394 395 bus_space_write_1(iot, ioh, SCSISEQ, SCSIRSTO); 396 delay(500); 397 bus_space_write_1(iot, ioh, SCSISEQ, 0); 398 delay(50); 399 } 400 401 /* 402 * Initialize aic SCSI driver. 403 */ 404 void 405 aic_init(struct aic_softc *sc, int bus_reset) 406 { 407 struct aic_acb *acb; 408 int r; 409 410 if (bus_reset) { 411 aic_reset(sc); 412 aic_scsi_reset(sc); 413 } 414 aic_reset(sc); 415 416 if (sc->sc_state == AIC_INIT) { 417 /* First time through; initialize. */ 418 TAILQ_INIT(&sc->ready_list); 419 TAILQ_INIT(&sc->nexus_list); 420 TAILQ_INIT(&sc->free_list); 421 sc->sc_nexus = NULL; 422 acb = sc->sc_acb; 423 bzero(acb, sizeof(sc->sc_acb)); 424 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 425 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 426 acb++; 427 } 428 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 429 } else { 430 /* Cancel any active commands. */ 431 sc->sc_state = AIC_CLEANING; 432 if ((acb = sc->sc_nexus) != NULL) { 433 acb->xs->error = XS_DRIVER_STUFFUP; 434 callout_stop(&acb->xs->xs_callout); 435 aic_done(sc, acb); 436 } 437 while ((acb = sc->nexus_list.tqh_first) != NULL) { 438 acb->xs->error = XS_DRIVER_STUFFUP; 439 callout_stop(&acb->xs->xs_callout); 440 aic_done(sc, acb); 441 } 442 } 443 444 sc->sc_prevphase = PH_INVALID; 445 for (r = 0; r < 8; r++) { 446 struct aic_tinfo *ti = &sc->sc_tinfo[r]; 447 448 ti->flags = 0; 449 ti->period = ti->offset = 0; 450 ti->width = 0; 451 } 452 453 sc->sc_state = AIC_IDLE; 454 bus_space_write_1(sc->sc_iot, sc->sc_ioh, DMACNTRL0, INTEN); 455 } 456 457 void 458 aic_free_acb(struct aic_softc *sc, struct aic_acb *acb) 459 { 460 int s; 461 462 s = splbio(); 463 acb->flags = 0; 464 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 465 splx(s); 466 } 467 468 struct aic_acb * 469 aic_get_acb(struct aic_softc *sc) 470 { 471 struct aic_acb *acb; 472 int s; 473 474 s = splbio(); 475 acb = TAILQ_FIRST(&sc->free_list); 476 if (acb != NULL) { 477 TAILQ_REMOVE(&sc->free_list, acb, chain); 478 acb->flags |= ACB_ALLOC; 479 } 480 splx(s); 481 return (acb); 482 } 483 484 /* 485 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 486 */ 487 488 /* 489 * Expected sequence: 490 * 1) Command inserted into ready list 491 * 2) Command selected for execution 492 * 3) Command won arbitration and has selected target device 493 * 4) Send message out (identify message, eventually also sync.negotiations) 494 * 5) Send command 495 * 5a) Receive disconnect message, disconnect. 496 * 5b) Reselected by target 497 * 5c) Receive identify message from target. 498 * 6) Send or receive data 499 * 7) Receive status 500 * 8) Receive message (command complete etc.) 501 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 502 * Repeat 2-8 (no disconnects please...) 503 */ 504 505 /* 506 * Perform a request from the SCSIPI midlayer. 507 */ 508 void 509 aic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 510 void *arg) 511 { 512 struct scsipi_xfer *xs; 513 struct scsipi_periph *periph; 514 struct aic_softc *sc = (void *)chan->chan_adapter->adapt_dev; 515 struct aic_acb *acb; 516 int s, flags; 517 518 AIC_TRACE(("aic_request ")); 519 520 switch (req) { 521 case ADAPTER_REQ_RUN_XFER: 522 xs = arg; 523 periph = xs->xs_periph; 524 525 AIC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 526 periph->periph_target)); 527 528 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 529 xs->error = XS_DRIVER_STUFFUP; 530 scsipi_done(xs); 531 return; 532 } 533 534 flags = xs->xs_control; 535 acb = aic_get_acb(sc); 536 #ifdef DIAGNOSTIC 537 /* 538 * This should never happen as we track the resources 539 * in the mid-layer. 540 */ 541 if (acb == NULL) { 542 scsipi_printaddr(periph); 543 printf("unable to allocate acb\n"); 544 panic("aic_scsipi_request"); 545 } 546 #endif 547 548 /* Initialize acb */ 549 acb->xs = xs; 550 acb->timeout = xs->timeout; 551 552 if (xs->xs_control & XS_CTL_RESET) { 553 acb->flags |= ACB_RESET; 554 acb->scsipi_cmd_length = 0; 555 acb->data_length = 0; 556 } else { 557 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen); 558 acb->scsipi_cmd_length = xs->cmdlen; 559 acb->data_addr = xs->data; 560 acb->data_length = xs->datalen; 561 } 562 acb->target_stat = 0; 563 564 s = splbio(); 565 566 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 567 if (sc->sc_state == AIC_IDLE) 568 aic_sched(sc); 569 570 splx(s); 571 572 if ((flags & XS_CTL_POLL) == 0) 573 return; 574 575 /* Not allowed to use interrupts, use polling instead */ 576 if (aic_poll(sc, xs, acb->timeout)) { 577 aic_timeout(acb); 578 if (aic_poll(sc, xs, acb->timeout)) 579 aic_timeout(acb); 580 } 581 return; 582 583 case ADAPTER_REQ_GROW_RESOURCES: 584 /* XXX Not supported. */ 585 return; 586 587 case ADAPTER_REQ_SET_XFER_MODE: 588 { 589 struct aic_tinfo *ti; 590 struct scsipi_xfer_mode *xm = arg; 591 592 ti = &sc->sc_tinfo[xm->xm_target]; 593 ti->flags &= ~(DO_SYNC|DO_WIDE); 594 ti->period = 0; 595 ti->offset = 0; 596 597 #if AIC_USE_SYNCHRONOUS 598 if (xm->xm_mode & PERIPH_CAP_SYNC) { 599 ti->flags |= DO_SYNC; 600 ti->period = sc->sc_minsync; 601 ti->offset = AIC_SYNC_REQ_ACK_OFS; 602 } 603 #endif 604 #if AIC_USE_WIDE 605 if (xm->xm_mode & PERIPH_CAP_WIDE16) { 606 ti->flags |= DO_WIDE; 607 ti->width = AIC_MAX_WIDTH; 608 } 609 #endif 610 /* 611 * If we're not going to negotiate, send the notification 612 * now, since it won't happen later. 613 */ 614 if ((ti->flags & (DO_SYNC|DO_WIDE)) == 0) 615 aic_update_xfer_mode(sc, xm->xm_target); 616 return; 617 } 618 } 619 } 620 621 void 622 aic_update_xfer_mode(struct aic_softc *sc, int target) 623 { 624 struct scsipi_xfer_mode xm; 625 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 626 627 xm.xm_target = target; 628 xm.xm_mode = 0; 629 xm.xm_period = 0; 630 xm.xm_offset = 0; 631 632 if (ti->offset != 0) { 633 xm.xm_mode |= PERIPH_CAP_SYNC; 634 xm.xm_period = ti->period; 635 xm.xm_offset = ti->offset; 636 } 637 switch (ti->width) { 638 case 2: 639 xm.xm_mode |= PERIPH_CAP_WIDE32; 640 break; 641 case 1: 642 xm.xm_mode |= PERIPH_CAP_WIDE16; 643 break; 644 } 645 646 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 647 } 648 649 /* 650 * Adjust transfer size in buffer structure 651 */ 652 void 653 aic_minphys(struct buf *bp) 654 { 655 656 AIC_TRACE(("aic_minphys ")); 657 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 658 bp->b_bcount = (AIC_NSEG << PGSHIFT); 659 minphys(bp); 660 } 661 662 /* 663 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 664 */ 665 int 666 aic_poll(struct aic_softc *sc, struct scsipi_xfer *xs, int count) 667 { 668 bus_space_tag_t iot = sc->sc_iot; 669 bus_space_handle_t ioh = sc->sc_ioh; 670 671 AIC_TRACE(("aic_poll ")); 672 while (count) { 673 /* 674 * If we had interrupts enabled, would we 675 * have got an interrupt? 676 */ 677 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 0) 678 aicintr(sc); 679 if ((xs->xs_status & XS_STS_DONE) != 0) 680 return 0; 681 delay(1000); 682 count--; 683 } 684 return 1; 685 } 686 687 /* 688 * LOW LEVEL SCSI UTILITIES 689 */ 690 691 integrate void 692 aic_sched_msgout(struct aic_softc *sc, u_char m) 693 { 694 bus_space_tag_t iot = sc->sc_iot; 695 bus_space_handle_t ioh = sc->sc_ioh; 696 697 if (sc->sc_msgpriq == 0) 698 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase | ATNO); 699 sc->sc_msgpriq |= m; 700 } 701 702 /* 703 * Set synchronous transfer offset and period. 704 */ 705 #if !AIC_USE_SYNCHRONOUS 706 /* ARGSUSED */ 707 #endif 708 integrate void 709 aic_setsync(struct aic_softc *sc, struct aic_tinfo *ti) 710 { 711 #if AIC_USE_SYNCHRONOUS 712 bus_space_tag_t iot = sc->sc_iot; 713 bus_space_handle_t ioh = sc->sc_ioh; 714 715 if (ti->offset != 0) 716 bus_space_write_1(iot, ioh, SCSIRATE, 717 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 718 else 719 bus_space_write_1(iot, ioh, SCSIRATE, 0); 720 #endif 721 } 722 723 /* 724 * Start a selection. This is used by aic_sched() to select an idle target, 725 * and by aic_done() to immediately reselect a target to get sense information. 726 */ 727 void 728 aic_select(struct aic_softc *sc, struct aic_acb *acb) 729 { 730 struct scsipi_periph *periph = acb->xs->xs_periph; 731 int target = periph->periph_target; 732 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 733 bus_space_tag_t iot = sc->sc_iot; 734 bus_space_handle_t ioh = sc->sc_ioh; 735 736 bus_space_write_1(iot, ioh, SCSIID, 737 sc->sc_initiator << OID_S | target); 738 aic_setsync(sc, ti); 739 bus_space_write_1(iot, ioh, SXFRCTL1, STIMO_256ms | ENSTIMER); 740 741 /* Always enable reselections. */ 742 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI | ENSELDO); 743 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSELTIMO); 744 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI | ENSELO | ENAUTOATNO); 745 746 sc->sc_state = AIC_SELECTING; 747 } 748 749 int 750 aic_reselect(struct aic_softc *sc, int message) 751 { 752 u_char selid, target, lun; 753 struct aic_acb *acb; 754 struct scsipi_periph *periph; 755 struct aic_tinfo *ti; 756 757 /* 758 * The SCSI chip made a snapshot of the data bus while the reselection 759 * was being negotiated. This enables us to determine which target did 760 * the reselect. 761 */ 762 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 763 if (selid & (selid - 1)) { 764 printf("%s: reselect with invalid selid %02x; " 765 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 766 AIC_BREAK(); 767 goto reset; 768 } 769 770 /* Search wait queue for disconnected cmd 771 * The list should be short, so I haven't bothered with 772 * any more sophisticated structures than a simple 773 * singly linked list. 774 */ 775 target = ffs(selid) - 1; 776 lun = message & 0x07; 777 for (acb = sc->nexus_list.tqh_first; acb != NULL; 778 acb = acb->chain.tqe_next) { 779 periph = acb->xs->xs_periph; 780 if (periph->periph_target == target && 781 periph->periph_lun == lun) 782 break; 783 } 784 if (acb == NULL) { 785 printf("%s: reselect from target %d lun %d with no nexus; " 786 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 787 AIC_BREAK(); 788 goto abort; 789 } 790 791 /* Make this nexus active again. */ 792 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 793 sc->sc_state = AIC_CONNECTED; 794 sc->sc_nexus = acb; 795 ti = &sc->sc_tinfo[target]; 796 ti->lubusy |= (1 << lun); 797 aic_setsync(sc, ti); 798 799 if (acb->flags & ACB_RESET) 800 aic_sched_msgout(sc, SEND_DEV_RESET); 801 else if (acb->flags & ACB_ABORT) 802 aic_sched_msgout(sc, SEND_ABORT); 803 804 /* Do an implicit RESTORE POINTERS. */ 805 sc->sc_dp = acb->data_addr; 806 sc->sc_dleft = acb->data_length; 807 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 808 sc->sc_cleft = acb->scsipi_cmd_length; 809 810 return (0); 811 812 reset: 813 aic_sched_msgout(sc, SEND_DEV_RESET); 814 return (1); 815 816 abort: 817 aic_sched_msgout(sc, SEND_ABORT); 818 return (1); 819 } 820 821 /* 822 * Schedule a SCSI operation. This has now been pulled out of the interrupt 823 * handler so that we may call it from aic_scsipi_request and aic_done. This 824 * may save us an unecessary interrupt just to get things going. Should only 825 * be called when state == AIC_IDLE and at bio pl. 826 */ 827 void 828 aic_sched(struct aic_softc *sc) 829 { 830 struct aic_acb *acb; 831 struct scsipi_periph *periph; 832 struct aic_tinfo *ti; 833 bus_space_tag_t iot = sc->sc_iot; 834 bus_space_handle_t ioh = sc->sc_ioh; 835 836 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 837 return; 838 839 /* 840 * Find first acb in ready queue that is for a target/lunit pair that 841 * is not busy. 842 */ 843 bus_space_write_1(iot, ioh, CLRSINT1, 844 CLRSELTIMO | CLRBUSFREE | CLRSCSIPERR); 845 for (acb = sc->ready_list.tqh_first; acb != NULL; 846 acb = acb->chain.tqe_next) { 847 periph = acb->xs->xs_periph; 848 ti = &sc->sc_tinfo[periph->periph_target]; 849 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 850 AIC_MISC(("selecting %d:%d ", 851 periph->periph_target, periph->periph_lun)); 852 TAILQ_REMOVE(&sc->ready_list, acb, chain); 853 sc->sc_nexus = acb; 854 aic_select(sc, acb); 855 return; 856 } else 857 AIC_MISC(("%d:%d busy\n", 858 periph->periph_target, periph->periph_lun)); 859 } 860 AIC_MISC(("idle ")); 861 /* Nothing to start; just enable reselections and wait. */ 862 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI); 863 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST); 864 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 865 } 866 867 void 868 aic_sense(struct aic_softc *sc, struct aic_acb *acb) 869 { 870 struct scsipi_xfer *xs = acb->xs; 871 struct scsipi_periph *periph = xs->xs_periph; 872 struct aic_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 873 struct scsipi_sense *ss = (void *)&acb->scsipi_cmd; 874 875 AIC_MISC(("requesting sense ")); 876 /* Next, setup a request sense command block */ 877 bzero(ss, sizeof(*ss)); 878 ss->opcode = REQUEST_SENSE; 879 ss->byte2 = periph->periph_lun << 5; 880 ss->length = sizeof(struct scsipi_sense_data); 881 acb->scsipi_cmd_length = sizeof(*ss); 882 acb->data_addr = (char *)&xs->sense.scsi_sense; 883 acb->data_length = sizeof(struct scsipi_sense_data); 884 acb->flags |= ACB_SENSE; 885 ti->senses++; 886 if (acb->flags & ACB_NEXUS) 887 ti->lubusy &= ~(1 << periph->periph_lun); 888 if (acb == sc->sc_nexus) { 889 aic_select(sc, acb); 890 } else { 891 aic_dequeue(sc, acb); 892 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 893 if (sc->sc_state == AIC_IDLE) 894 aic_sched(sc); 895 } 896 } 897 898 /* 899 * POST PROCESSING OF SCSI_CMD (usually current) 900 */ 901 void 902 aic_done(struct aic_softc *sc, struct aic_acb *acb) 903 { 904 struct scsipi_xfer *xs = acb->xs; 905 struct scsipi_periph *periph = xs->xs_periph; 906 struct aic_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 907 908 AIC_TRACE(("aic_done ")); 909 910 /* 911 * Now, if we've come here with no error code, i.e. we've kept the 912 * initial XS_NOERROR, and the status code signals that we should 913 * check sense, we'll need to set up a request sense cmd block and 914 * push the command back into the ready queue *before* any other 915 * commands for this target/lunit, else we lose the sense info. 916 * We don't support chk sense conditions for the request sense cmd. 917 */ 918 if (xs->error == XS_NOERROR) { 919 if (acb->flags & ACB_ABORT) { 920 xs->error = XS_DRIVER_STUFFUP; 921 } else if (acb->flags & ACB_SENSE) { 922 xs->error = XS_SENSE; 923 } else if (acb->target_stat == SCSI_CHECK) { 924 /* First, save the return values */ 925 xs->resid = acb->data_length; 926 xs->status = acb->target_stat; 927 aic_sense(sc, acb); 928 return; 929 } else { 930 xs->resid = acb->data_length; 931 } 932 } 933 934 #if AIC_DEBUG 935 if ((aic_debug & AIC_SHOWMISC) != 0) { 936 if (xs->resid != 0) 937 printf("resid=%d ", xs->resid); 938 if (xs->error == XS_SENSE) 939 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 940 else 941 printf("error=%d\n", xs->error); 942 } 943 #endif 944 945 /* 946 * Remove the ACB from whatever queue it happens to be on. 947 */ 948 if (acb->flags & ACB_NEXUS) 949 ti->lubusy &= ~(1 << periph->periph_lun); 950 if (acb == sc->sc_nexus) { 951 sc->sc_nexus = NULL; 952 sc->sc_state = AIC_IDLE; 953 aic_sched(sc); 954 } else 955 aic_dequeue(sc, acb); 956 957 aic_free_acb(sc, acb); 958 ti->cmds++; 959 scsipi_done(xs); 960 } 961 962 void 963 aic_dequeue(struct aic_softc *sc, struct aic_acb *acb) 964 { 965 966 if (acb->flags & ACB_NEXUS) { 967 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 968 } else { 969 TAILQ_REMOVE(&sc->ready_list, acb, chain); 970 } 971 } 972 973 /* 974 * INTERRUPT/PROTOCOL ENGINE 975 */ 976 977 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 978 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 979 #define ISEXTMSG(m) ((m) == 0x01) 980 981 /* 982 * Precondition: 983 * The SCSI bus is already in the MSGI phase and there is a message byte 984 * on the bus, along with an asserted REQ signal. 985 */ 986 void 987 aic_msgin(struct aic_softc *sc) 988 { 989 bus_space_tag_t iot = sc->sc_iot; 990 bus_space_handle_t ioh = sc->sc_ioh; 991 u_char sstat1; 992 int n; 993 994 AIC_TRACE(("aic_msgin ")); 995 996 if (sc->sc_prevphase == PH_MSGIN) { 997 /* This is a continuation of the previous message. */ 998 n = sc->sc_imp - sc->sc_imess; 999 goto nextbyte; 1000 } 1001 1002 /* This is a new MESSAGE IN phase. Clean up our state. */ 1003 sc->sc_flags &= ~AIC_DROP_MSGIN; 1004 1005 nextmsg: 1006 n = 0; 1007 sc->sc_imp = &sc->sc_imess[n]; 1008 1009 nextbyte: 1010 /* 1011 * Read a whole message, but don't ack the last byte. If we reject the 1012 * message, we have to assert ATN during the message transfer phase 1013 * itself. 1014 */ 1015 for (;;) { 1016 for (;;) { 1017 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1018 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1019 break; 1020 /* Wait for REQINIT. XXX Need timeout. */ 1021 } 1022 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1023 /* 1024 * Target left MESSAGE IN, probably because it 1025 * a) noticed our ATN signal, or 1026 * b) ran out of messages. 1027 */ 1028 goto out; 1029 } 1030 1031 /* If parity error, just dump everything on the floor. */ 1032 if ((sstat1 & SCSIPERR) != 0) { 1033 sc->sc_flags |= AIC_DROP_MSGIN; 1034 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1035 } 1036 1037 /* Gather incoming message bytes if needed. */ 1038 if ((sc->sc_flags & AIC_DROP_MSGIN) == 0) { 1039 if (n >= AIC_MAX_MSG_LEN) { 1040 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1041 sc->sc_flags |= AIC_DROP_MSGIN; 1042 aic_sched_msgout(sc, SEND_REJECT); 1043 } else { 1044 *sc->sc_imp++ = bus_space_read_1(iot, ioh, 1045 SCSIDAT); 1046 n++; 1047 /* 1048 * This testing is suboptimal, but most 1049 * messages will be of the one byte variety, so 1050 * it should not affect performance 1051 * significantly. 1052 */ 1053 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1054 break; 1055 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1056 break; 1057 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1058 n == sc->sc_imess[1] + 2) 1059 break; 1060 } 1061 } else 1062 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1063 1064 /* 1065 * If we reach this spot we're either: 1066 * a) in the middle of a multi-byte message, or 1067 * b) dropping bytes. 1068 */ 1069 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1070 /* Ack the last byte read. */ 1071 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1072 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1073 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1074 ; 1075 } 1076 1077 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1078 1079 /* We now have a complete message. Parse it. */ 1080 switch (sc->sc_state) { 1081 struct aic_acb *acb; 1082 struct scsipi_periph *periph; 1083 struct aic_tinfo *ti; 1084 1085 case AIC_CONNECTED: 1086 AIC_ASSERT(sc->sc_nexus != NULL); 1087 acb = sc->sc_nexus; 1088 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1089 1090 switch (sc->sc_imess[0]) { 1091 case MSG_CMDCOMPLETE: 1092 if (sc->sc_dleft < 0) { 1093 periph = acb->xs->xs_periph; 1094 printf("%s: %ld extra bytes from %d:%d\n", 1095 sc->sc_dev.dv_xname, (long)-sc->sc_dleft, 1096 periph->periph_target, 1097 periph->periph_lun); 1098 acb->data_length = 0; 1099 } 1100 acb->xs->resid = acb->data_length = sc->sc_dleft; 1101 sc->sc_state = AIC_CMDCOMPLETE; 1102 break; 1103 1104 case MSG_PARITY_ERROR: 1105 /* Resend the last message. */ 1106 aic_sched_msgout(sc, sc->sc_lastmsg); 1107 break; 1108 1109 case MSG_MESSAGE_REJECT: 1110 AIC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1111 switch (sc->sc_lastmsg) { 1112 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1113 case SEND_IDENTIFY: 1114 ti->flags &= ~(DO_SYNC | DO_WIDE); 1115 ti->period = ti->offset = 0; 1116 aic_setsync(sc, ti); 1117 ti->width = 0; 1118 break; 1119 #endif 1120 #if AIC_USE_SYNCHRONOUS 1121 case SEND_SDTR: 1122 ti->flags &= ~DO_SYNC; 1123 ti->period = ti->offset = 0; 1124 aic_setsync(sc, ti); 1125 aic_update_xfer_mode(sc, 1126 acb->xs->xs_periph->periph_target); 1127 break; 1128 #endif 1129 #if AIC_USE_WIDE 1130 case SEND_WDTR: 1131 ti->flags &= ~DO_WIDE; 1132 ti->width = 0; 1133 aic_update_xfer_mode(sc, 1134 acb->xs->xs_periph->periph_target); 1135 break; 1136 #endif 1137 case SEND_INIT_DET_ERR: 1138 aic_sched_msgout(sc, SEND_ABORT); 1139 break; 1140 } 1141 break; 1142 1143 case MSG_NOOP: 1144 break; 1145 1146 case MSG_DISCONNECT: 1147 ti->dconns++; 1148 sc->sc_state = AIC_DISCONNECT; 1149 break; 1150 1151 case MSG_SAVEDATAPOINTER: 1152 acb->data_addr = sc->sc_dp; 1153 acb->data_length = sc->sc_dleft; 1154 break; 1155 1156 case MSG_RESTOREPOINTERS: 1157 sc->sc_dp = acb->data_addr; 1158 sc->sc_dleft = acb->data_length; 1159 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1160 sc->sc_cleft = acb->scsipi_cmd_length; 1161 break; 1162 1163 case MSG_EXTENDED: 1164 switch (sc->sc_imess[2]) { 1165 #if AIC_USE_SYNCHRONOUS 1166 case MSG_EXT_SDTR: 1167 if (sc->sc_imess[1] != 3) 1168 goto reject; 1169 ti->period = sc->sc_imess[3]; 1170 ti->offset = sc->sc_imess[4]; 1171 ti->flags &= ~DO_SYNC; 1172 if (ti->offset == 0) { 1173 } else if (ti->period < sc->sc_minsync || 1174 ti->period > sc->sc_maxsync || 1175 ti->offset > 8) { 1176 ti->period = ti->offset = 0; 1177 aic_sched_msgout(sc, SEND_SDTR); 1178 } else { 1179 aic_update_xfer_mode(sc, 1180 acb->xs->xs_periph->periph_target); 1181 } 1182 aic_setsync(sc, ti); 1183 break; 1184 #endif 1185 1186 #if AIC_USE_WIDE 1187 case MSG_EXT_WDTR: 1188 if (sc->sc_imess[1] != 2) 1189 goto reject; 1190 ti->width = sc->sc_imess[3]; 1191 ti->flags &= ~DO_WIDE; 1192 if (ti->width == 0) { 1193 } else if (ti->width > AIC_MAX_WIDTH) { 1194 ti->width = 0; 1195 aic_sched_msgout(sc, SEND_WDTR); 1196 } else { 1197 aic_update_xfer_mode(sc, 1198 acb->xs->xs_periph->periph_target); 1199 } 1200 break; 1201 #endif 1202 1203 default: 1204 printf("%s: unrecognized MESSAGE EXTENDED; " 1205 "sending REJECT\n", sc->sc_dev.dv_xname); 1206 AIC_BREAK(); 1207 goto reject; 1208 } 1209 break; 1210 1211 default: 1212 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1213 sc->sc_dev.dv_xname); 1214 AIC_BREAK(); 1215 reject: 1216 aic_sched_msgout(sc, SEND_REJECT); 1217 break; 1218 } 1219 break; 1220 1221 case AIC_RESELECTED: 1222 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1223 printf("%s: reselect without IDENTIFY; " 1224 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1225 AIC_BREAK(); 1226 goto reset; 1227 } 1228 1229 (void) aic_reselect(sc, sc->sc_imess[0]); 1230 break; 1231 1232 default: 1233 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1234 sc->sc_dev.dv_xname); 1235 AIC_BREAK(); 1236 reset: 1237 aic_sched_msgout(sc, SEND_DEV_RESET); 1238 break; 1239 1240 #ifdef notdef 1241 abort: 1242 aic_sched_msgout(sc, SEND_ABORT); 1243 break; 1244 #endif 1245 } 1246 1247 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1248 /* Ack the last message byte. */ 1249 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1250 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1251 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1252 ; 1253 1254 /* Go get the next message, if any. */ 1255 goto nextmsg; 1256 1257 out: 1258 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1259 } 1260 1261 /* 1262 * Send the highest priority, scheduled message. 1263 */ 1264 void 1265 aic_msgout(struct aic_softc *sc) 1266 { 1267 bus_space_tag_t iot = sc->sc_iot; 1268 bus_space_handle_t ioh = sc->sc_ioh; 1269 #if AIC_USE_SYNCHRONOUS 1270 struct aic_tinfo *ti; 1271 #endif 1272 u_char sstat1; 1273 int n; 1274 1275 AIC_TRACE(("aic_msgout ")); 1276 1277 /* Reset the FIFO. */ 1278 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1279 /* Enable REQ/ACK protocol. */ 1280 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1281 1282 if (sc->sc_prevphase == PH_MSGOUT) { 1283 if (sc->sc_omp == sc->sc_omess) { 1284 /* 1285 * This is a retransmission. 1286 * 1287 * We get here if the target stayed in MESSAGE OUT 1288 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1289 * that all of the previously transmitted messages must 1290 * be sent again, in the same order. Therefore, we 1291 * requeue all the previously transmitted messages, and 1292 * start again from the top. Our simple priority 1293 * scheme keeps the messages in the right order. 1294 */ 1295 AIC_MISC(("retransmitting ")); 1296 sc->sc_msgpriq |= sc->sc_msgoutq; 1297 /* 1298 * Set ATN. If we're just sending a trivial 1-byte 1299 * message, we'll clear ATN later on anyway. 1300 */ 1301 bus_space_write_1(iot, ioh, SCSISIG, PH_MSGOUT | ATNO); 1302 } else { 1303 /* This is a continuation of the previous message. */ 1304 n = sc->sc_omp - sc->sc_omess; 1305 goto nextbyte; 1306 } 1307 } 1308 1309 /* No messages transmitted so far. */ 1310 sc->sc_msgoutq = 0; 1311 sc->sc_lastmsg = 0; 1312 1313 nextmsg: 1314 /* Pick up highest priority message. */ 1315 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1316 sc->sc_msgpriq &= ~sc->sc_currmsg; 1317 sc->sc_msgoutq |= sc->sc_currmsg; 1318 1319 /* Build the outgoing message data. */ 1320 switch (sc->sc_currmsg) { 1321 case SEND_IDENTIFY: 1322 AIC_ASSERT(sc->sc_nexus != NULL); 1323 sc->sc_omess[0] = 1324 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1325 n = 1; 1326 break; 1327 1328 #if AIC_USE_SYNCHRONOUS 1329 case SEND_SDTR: 1330 AIC_ASSERT(sc->sc_nexus != NULL); 1331 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1332 sc->sc_omess[4] = MSG_EXTENDED; 1333 sc->sc_omess[3] = 3; 1334 sc->sc_omess[2] = MSG_EXT_SDTR; 1335 sc->sc_omess[1] = ti->period >> 2; 1336 sc->sc_omess[0] = ti->offset; 1337 n = 5; 1338 break; 1339 #endif 1340 1341 #if AIC_USE_WIDE 1342 case SEND_WDTR: 1343 AIC_ASSERT(sc->sc_nexus != NULL); 1344 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1345 sc->sc_omess[3] = MSG_EXTENDED; 1346 sc->sc_omess[2] = 2; 1347 sc->sc_omess[1] = MSG_EXT_WDTR; 1348 sc->sc_omess[0] = ti->width; 1349 n = 4; 1350 break; 1351 #endif 1352 1353 case SEND_DEV_RESET: 1354 sc->sc_flags |= AIC_ABORTING; 1355 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1356 n = 1; 1357 break; 1358 1359 case SEND_REJECT: 1360 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1361 n = 1; 1362 break; 1363 1364 case SEND_PARITY_ERROR: 1365 sc->sc_omess[0] = MSG_PARITY_ERROR; 1366 n = 1; 1367 break; 1368 1369 case SEND_INIT_DET_ERR: 1370 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1371 n = 1; 1372 break; 1373 1374 case SEND_ABORT: 1375 sc->sc_flags |= AIC_ABORTING; 1376 sc->sc_omess[0] = MSG_ABORT; 1377 n = 1; 1378 break; 1379 1380 default: 1381 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1382 sc->sc_dev.dv_xname); 1383 AIC_BREAK(); 1384 sc->sc_omess[0] = MSG_NOOP; 1385 n = 1; 1386 break; 1387 } 1388 sc->sc_omp = &sc->sc_omess[n]; 1389 1390 nextbyte: 1391 /* Send message bytes. */ 1392 for (;;) { 1393 for (;;) { 1394 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1395 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1396 break; 1397 /* Wait for REQINIT. XXX Need timeout. */ 1398 } 1399 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1400 /* 1401 * Target left MESSAGE OUT, possibly to reject 1402 * our message. 1403 * 1404 * If this is the last message being sent, then we 1405 * deassert ATN, since either the target is going to 1406 * ignore this message, or it's going to ask for a 1407 * retransmission via MESSAGE PARITY ERROR (in which 1408 * case we reassert ATN anyway). 1409 */ 1410 if (sc->sc_msgpriq == 0) 1411 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1412 goto out; 1413 } 1414 1415 /* Clear ATN before last byte if this is the last message. */ 1416 if (n == 1 && sc->sc_msgpriq == 0) 1417 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1418 /* Send message byte. */ 1419 bus_space_write_1(iot, ioh, SCSIDAT, *--sc->sc_omp); 1420 --n; 1421 /* Keep track of the last message we've sent any bytes of. */ 1422 sc->sc_lastmsg = sc->sc_currmsg; 1423 /* Wait for ACK to be negated. XXX Need timeout. */ 1424 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1425 ; 1426 1427 if (n == 0) 1428 break; 1429 } 1430 1431 /* We get here only if the entire message has been transmitted. */ 1432 if (sc->sc_msgpriq != 0) { 1433 /* There are more outgoing messages. */ 1434 goto nextmsg; 1435 } 1436 1437 /* 1438 * The last message has been transmitted. We need to remember the last 1439 * message transmitted (in case the target switches to MESSAGE IN phase 1440 * and sends a MESSAGE REJECT), and the list of messages transmitted 1441 * this time around (in case the target stays in MESSAGE OUT phase to 1442 * request a retransmit). 1443 */ 1444 1445 out: 1446 /* Disable REQ/ACK protocol. */ 1447 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1448 } 1449 1450 /* aic_dataout_pio: perform a data transfer using the FIFO datapath in the 1451 * aic6360 1452 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1453 * and ACK deasserted (i.e. waiting for a data byte) 1454 * This new revision has been optimized (I tried) to make the common case fast, 1455 * and the rarer cases (as a result) somewhat more comlex 1456 */ 1457 int 1458 aic_dataout_pio(struct aic_softc *sc, u_char *p, int n) 1459 { 1460 bus_space_tag_t iot = sc->sc_iot; 1461 bus_space_handle_t ioh = sc->sc_ioh; 1462 u_char dmastat = 0; 1463 int out = 0; 1464 #define DOUTAMOUNT 128 /* Full FIFO */ 1465 1466 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1467 bus_space_read_1(iot, ioh, SSTAT2))); 1468 1469 /* Clear host FIFO and counter. */ 1470 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO | WRITE); 1471 /* Enable FIFOs. */ 1472 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1473 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1474 1475 /* Turn off ENREQINIT for now. */ 1476 bus_space_write_1(iot, ioh, SIMODE1, 1477 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1478 1479 /* I have tried to make the main loop as tight as possible. This 1480 * means that some of the code following the loop is a bit more 1481 * complex than otherwise. 1482 */ 1483 while (n > 0) { 1484 for (;;) { 1485 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1486 if ((dmastat & (DFIFOEMP | INTSTAT)) != 0) 1487 break; 1488 } 1489 1490 if ((dmastat & INTSTAT) != 0) 1491 goto phasechange; 1492 1493 if (n >= DOUTAMOUNT) { 1494 n -= DOUTAMOUNT; 1495 out += DOUTAMOUNT; 1496 1497 #if AIC_USE_DWORDS 1498 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1499 (u_int32_t *) p, DOUTAMOUNT >> 2); 1500 #else 1501 bus_space_write_multi_2(iot, ioh, DMADATA, 1502 (u_int16_t *) p, DOUTAMOUNT >> 1); 1503 #endif 1504 1505 p += DOUTAMOUNT; 1506 } else { 1507 int xfer; 1508 1509 xfer = n; 1510 AIC_MISC(("%d> ", xfer)); 1511 1512 n -= xfer; 1513 out += xfer; 1514 1515 #if AIC_USE_DWORDS 1516 if (xfer >= 12) { 1517 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1518 (u_int32_t *) p, xfer >> 2); 1519 p += xfer & ~3; 1520 xfer &= 3; 1521 } 1522 #else 1523 if (xfer >= 8) { 1524 bus_space_write_multi_2(iot, ioh, DMADATA, 1525 (u_int16_t *) p, xfer >> 1); 1526 p += xfer & ~1; 1527 xfer &= 1; 1528 } 1529 #endif 1530 1531 if (xfer > 0) { 1532 bus_space_write_1(iot, ioh, DMACNTRL0, 1533 ENDMA | B8MODE | WRITE); 1534 bus_space_write_multi_1(iot, ioh, DMADATA, 1535 p, xfer); 1536 p += xfer; 1537 bus_space_write_1(iot, ioh, DMACNTRL0, 1538 ENDMA | DWORDPIO | WRITE); 1539 } 1540 } 1541 } 1542 1543 if (out == 0) { 1544 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1545 for (;;) { 1546 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1547 != 0) 1548 break; 1549 } 1550 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1551 AIC_MISC(("extra data ")); 1552 } else { 1553 /* See the bytes off chip */ 1554 for (;;) { 1555 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1556 if ((dmastat & INTSTAT) != 0) 1557 goto phasechange; 1558 if ((dmastat & DFIFOEMP) != 0 && 1559 (bus_space_read_1(iot, ioh, SSTAT2) & SEMPTY) != 0) 1560 break; 1561 } 1562 } 1563 1564 phasechange: 1565 if ((dmastat & INTSTAT) != 0) { 1566 /* Some sort of phase change. */ 1567 int amount; 1568 1569 /* Stop transfers, do some accounting */ 1570 amount = bus_space_read_1(iot, ioh, FIFOSTAT) 1571 + (bus_space_read_1(iot, ioh, SSTAT2) & 15); 1572 if (amount > 0) { 1573 out -= amount; 1574 bus_space_write_1(iot, ioh, DMACNTRL0, 1575 RSTFIFO | WRITE); 1576 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH); 1577 AIC_MISC(("+%d ", amount)); 1578 } 1579 } 1580 1581 /* Turn on ENREQINIT again. */ 1582 bus_space_write_1(iot, ioh, SIMODE1, 1583 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1584 1585 /* Stop the FIFO data path. */ 1586 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1587 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1588 1589 return out; 1590 } 1591 1592 /* aic_datain_pio: perform data transfers using the FIFO datapath in the 1593 * aic6360 1594 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1595 * and ACK deasserted (i.e. at least one byte is ready). 1596 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1597 * transferred. This, is OK for fast targets, but not so smart for slow 1598 * targets which don't disconnect or for huge transfers. 1599 */ 1600 int 1601 aic_datain_pio(struct aic_softc *sc, u_char *p, int n) 1602 { 1603 bus_space_tag_t iot = sc->sc_iot; 1604 bus_space_handle_t ioh = sc->sc_ioh; 1605 u_char dmastat; 1606 int in = 0; 1607 #define DINAMOUNT 128 /* Full FIFO */ 1608 1609 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1610 bus_space_read_1(iot, ioh, SSTAT2))); 1611 1612 /* Clear host FIFO and counter. */ 1613 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1614 /* Enable FIFOs. */ 1615 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO); 1616 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1617 1618 /* Turn off ENREQINIT for now. */ 1619 bus_space_write_1(iot, ioh, SIMODE1, 1620 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1621 1622 /* We leave this loop if one or more of the following is true: 1623 * a) phase != PH_DATAIN && FIFOs are empty 1624 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 1625 */ 1626 while (n > 0) { 1627 /* Wait for fifo half full or phase mismatch */ 1628 for (;;) { 1629 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1630 if ((dmastat & (DFIFOFULL | INTSTAT)) != 0) 1631 break; 1632 } 1633 1634 if ((dmastat & DFIFOFULL) != 0) { 1635 n -= DINAMOUNT; 1636 in += DINAMOUNT; 1637 1638 #if AIC_USE_DWORDS 1639 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1640 (u_int32_t *) p, DINAMOUNT >> 2); 1641 #else 1642 bus_space_read_multi_2(iot, ioh, DMADATA, 1643 (u_int16_t *) p, DINAMOUNT >> 1); 1644 #endif 1645 1646 p += DINAMOUNT; 1647 } else { 1648 int xfer; 1649 1650 xfer = min(bus_space_read_1(iot, ioh, FIFOSTAT), n); 1651 AIC_MISC((">%d ", xfer)); 1652 1653 n -= xfer; 1654 in += xfer; 1655 1656 #if AIC_USE_DWORDS 1657 if (xfer >= 12) { 1658 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1659 (u_int32_t *) p, xfer >> 2); 1660 p += xfer & ~3; 1661 xfer &= 3; 1662 } 1663 #else 1664 if (xfer >= 8) { 1665 bus_space_read_multi_2(iot, ioh, DMADATA, 1666 (u_int16_t *) p, xfer >> 1); 1667 p += xfer & ~1; 1668 xfer &= 1; 1669 } 1670 #endif 1671 1672 if (xfer > 0) { 1673 bus_space_write_1(iot, ioh, DMACNTRL0, 1674 ENDMA | B8MODE); 1675 bus_space_read_multi_1(iot, ioh, DMADATA, 1676 p, xfer); 1677 p += xfer; 1678 bus_space_write_1(iot, ioh, DMACNTRL0, 1679 ENDMA | DWORDPIO); 1680 } 1681 } 1682 1683 if ((dmastat & INTSTAT) != 0) 1684 goto phasechange; 1685 } 1686 1687 /* Some SCSI-devices are rude enough to transfer more data than what 1688 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1689 * requested 512. Test for progress, i.e. real transfers. If no real 1690 * transfers have been performed (n is probably already zero) and the 1691 * FIFO is not empty, waste some bytes.... 1692 */ 1693 if (in == 0) { 1694 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1695 for (;;) { 1696 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1697 != 0) 1698 break; 1699 } 1700 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1701 AIC_MISC(("extra data ")); 1702 } 1703 1704 phasechange: 1705 /* Turn on ENREQINIT again. */ 1706 bus_space_write_1(iot, ioh, SIMODE1, 1707 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1708 1709 /* Stop the FIFO data path. */ 1710 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1711 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1712 1713 return in; 1714 } 1715 1716 /* 1717 * This is the workhorse routine of the driver. 1718 * Deficiencies (for now): 1719 * 1) always uses programmed I/O 1720 */ 1721 int 1722 aicintr(void *arg) 1723 { 1724 struct aic_softc *sc = arg; 1725 bus_space_tag_t iot = sc->sc_iot; 1726 bus_space_handle_t ioh = sc->sc_ioh; 1727 u_char sstat0, sstat1; 1728 struct aic_acb *acb; 1729 struct scsipi_periph *periph; 1730 struct aic_tinfo *ti; 1731 int n; 1732 1733 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1734 return (0); 1735 1736 /* 1737 * Clear INTEN. We enable it again before returning. This makes the 1738 * interrupt esssentially level-triggered. 1739 */ 1740 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1741 1742 AIC_TRACE(("aicintr ")); 1743 1744 loop: 1745 /* 1746 * First check for abnormal conditions, such as reset. 1747 */ 1748 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1749 AIC_MISC(("sstat1:0x%02x ", sstat1)); 1750 1751 if ((sstat1 & SCSIRSTI) != 0) { 1752 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1753 goto reset; 1754 } 1755 1756 /* 1757 * Check for less serious errors. 1758 */ 1759 if ((sstat1 & SCSIPERR) != 0) { 1760 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1761 bus_space_write_1(iot, ioh, CLRSINT1, CLRSCSIPERR); 1762 if (sc->sc_prevphase == PH_MSGIN) { 1763 sc->sc_flags |= AIC_DROP_MSGIN; 1764 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1765 } else 1766 aic_sched_msgout(sc, SEND_INIT_DET_ERR); 1767 } 1768 1769 /* 1770 * If we're not already busy doing something test for the following 1771 * conditions: 1772 * 1) We have been reselected by something 1773 * 2) We have selected something successfully 1774 * 3) Our selection process has timed out 1775 * 4) This is really a bus free interrupt just to get a new command 1776 * going? 1777 * 5) Spurious interrupt? 1778 */ 1779 switch (sc->sc_state) { 1780 case AIC_IDLE: 1781 case AIC_SELECTING: 1782 sstat0 = bus_space_read_1(iot, ioh, SSTAT0); 1783 AIC_MISC(("sstat0:0x%02x ", sstat0)); 1784 1785 if ((sstat0 & TARGET) != 0) { 1786 /* 1787 * We don't currently support target mode. 1788 */ 1789 printf("%s: target mode selected; going to BUS FREE\n", 1790 sc->sc_dev.dv_xname); 1791 bus_space_write_1(iot, ioh, SCSISIG, 0); 1792 1793 goto sched; 1794 } else if ((sstat0 & SELDI) != 0) { 1795 AIC_MISC(("reselected ")); 1796 1797 /* 1798 * If we're trying to select a target ourselves, 1799 * push our command back into the ready list. 1800 */ 1801 if (sc->sc_state == AIC_SELECTING) { 1802 AIC_MISC(("backoff selector ")); 1803 AIC_ASSERT(sc->sc_nexus != NULL); 1804 acb = sc->sc_nexus; 1805 sc->sc_nexus = NULL; 1806 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1807 } 1808 1809 /* Save reselection ID. */ 1810 sc->sc_selid = bus_space_read_1(iot, ioh, SELID); 1811 1812 sc->sc_state = AIC_RESELECTED; 1813 } else if ((sstat0 & SELDO) != 0) { 1814 AIC_MISC(("selected ")); 1815 1816 /* We have selected a target. Things to do: 1817 * a) Determine what message(s) to send. 1818 * b) Verify that we're still selecting the target. 1819 * c) Mark device as busy. 1820 */ 1821 if (sc->sc_state != AIC_SELECTING) { 1822 printf("%s: selection out while idle; " 1823 "resetting\n", sc->sc_dev.dv_xname); 1824 AIC_BREAK(); 1825 goto reset; 1826 } 1827 AIC_ASSERT(sc->sc_nexus != NULL); 1828 acb = sc->sc_nexus; 1829 periph = acb->xs->xs_periph; 1830 ti = &sc->sc_tinfo[periph->periph_target]; 1831 1832 sc->sc_msgpriq = SEND_IDENTIFY; 1833 if (acb->flags & ACB_RESET) 1834 sc->sc_msgpriq |= SEND_DEV_RESET; 1835 else if (acb->flags & ACB_ABORT) 1836 sc->sc_msgpriq |= SEND_ABORT; 1837 else { 1838 #if AIC_USE_SYNCHRONOUS 1839 if ((ti->flags & DO_SYNC) != 0) 1840 sc->sc_msgpriq |= SEND_SDTR; 1841 #endif 1842 #if AIC_USE_WIDE 1843 if ((ti->flags & DO_WIDE) != 0) 1844 sc->sc_msgpriq |= SEND_WDTR; 1845 #endif 1846 } 1847 1848 acb->flags |= ACB_NEXUS; 1849 ti->lubusy |= (1 << periph->periph_lun); 1850 1851 /* Do an implicit RESTORE POINTERS. */ 1852 sc->sc_dp = acb->data_addr; 1853 sc->sc_dleft = acb->data_length; 1854 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1855 sc->sc_cleft = acb->scsipi_cmd_length; 1856 1857 /* On our first connection, schedule a timeout. */ 1858 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1859 callout_reset(&acb->xs->xs_callout, 1860 (acb->timeout * hz) / 1000, 1861 aic_timeout, acb); 1862 1863 sc->sc_state = AIC_CONNECTED; 1864 } else if ((sstat1 & SELTO) != 0) { 1865 AIC_MISC(("selection timeout ")); 1866 1867 if (sc->sc_state != AIC_SELECTING) { 1868 printf("%s: selection timeout while idle; " 1869 "resetting\n", sc->sc_dev.dv_xname); 1870 AIC_BREAK(); 1871 goto reset; 1872 } 1873 AIC_ASSERT(sc->sc_nexus != NULL); 1874 acb = sc->sc_nexus; 1875 1876 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1877 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 1878 bus_space_write_1(iot, ioh, CLRSINT1, CLRSELTIMO); 1879 delay(250); 1880 1881 acb->xs->error = XS_SELTIMEOUT; 1882 goto finish; 1883 } else { 1884 if (sc->sc_state != AIC_IDLE) { 1885 printf("%s: BUS FREE while not idle; " 1886 "state=%d\n", 1887 sc->sc_dev.dv_xname, sc->sc_state); 1888 AIC_BREAK(); 1889 goto out; 1890 } 1891 1892 goto sched; 1893 } 1894 1895 /* 1896 * Turn off selection stuff, and prepare to catch bus free 1897 * interrupts, parity errors, and phase changes. 1898 */ 1899 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRSTCNT | CLRCH); 1900 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1901 bus_space_write_1(iot, ioh, SCSISEQ, ENAUTOATNP); 1902 bus_space_write_1(iot, ioh, CLRSINT0, CLRSELDI | CLRSELDO); 1903 bus_space_write_1(iot, ioh, CLRSINT1, 1904 CLRBUSFREE | CLRPHASECHG); 1905 bus_space_write_1(iot, ioh, SIMODE0, 0); 1906 bus_space_write_1(iot, ioh, SIMODE1, 1907 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | 1908 ENPHASECHG); 1909 1910 sc->sc_flags = 0; 1911 sc->sc_prevphase = PH_INVALID; 1912 goto dophase; 1913 } 1914 1915 if ((sstat1 & BUSFREE) != 0) { 1916 /* We've gone to BUS FREE phase. */ 1917 bus_space_write_1(iot, ioh, CLRSINT1, 1918 CLRBUSFREE | CLRPHASECHG); 1919 1920 switch (sc->sc_state) { 1921 case AIC_RESELECTED: 1922 goto sched; 1923 1924 case AIC_CONNECTED: 1925 AIC_ASSERT(sc->sc_nexus != NULL); 1926 acb = sc->sc_nexus; 1927 1928 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1929 if (sc->sc_prevphase == PH_MSGOUT) { 1930 /* 1931 * If the target went to BUS FREE phase during 1932 * or immediately after sending a SDTR or WDTR 1933 * message, disable negotiation. 1934 */ 1935 periph = acb->xs->xs_periph; 1936 ti = &sc->sc_tinfo[periph->periph_target]; 1937 switch (sc->sc_lastmsg) { 1938 #if AIC_USE_SYNCHRONOUS 1939 case SEND_SDTR: 1940 ti->flags &= ~DO_SYNC; 1941 ti->period = ti->offset = 0; 1942 break; 1943 #endif 1944 #if AIC_USE_WIDE 1945 case SEND_WDTR: 1946 ti->flags &= ~DO_WIDE; 1947 ti->width = 0; 1948 break; 1949 #endif 1950 } 1951 } 1952 #endif 1953 1954 if ((sc->sc_flags & AIC_ABORTING) == 0) { 1955 /* 1956 * Section 5.1.1 of the SCSI 2 spec suggests 1957 * issuing a REQUEST SENSE following an 1958 * unexpected disconnect. Some devices go into 1959 * a contingent allegiance condition when 1960 * disconnecting, and this is necessary to 1961 * clean up their state. 1962 */ 1963 printf("%s: unexpected disconnect; " 1964 "sending REQUEST SENSE\n", 1965 sc->sc_dev.dv_xname); 1966 AIC_BREAK(); 1967 aic_sense(sc, acb); 1968 goto out; 1969 } 1970 1971 acb->xs->error = XS_DRIVER_STUFFUP; 1972 goto finish; 1973 1974 case AIC_DISCONNECT: 1975 AIC_ASSERT(sc->sc_nexus != NULL); 1976 acb = sc->sc_nexus; 1977 #if 1 /* XXXX */ 1978 acb->data_addr = sc->sc_dp; 1979 acb->data_length = sc->sc_dleft; 1980 #endif 1981 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1982 sc->sc_nexus = NULL; 1983 goto sched; 1984 1985 case AIC_CMDCOMPLETE: 1986 AIC_ASSERT(sc->sc_nexus != NULL); 1987 acb = sc->sc_nexus; 1988 goto finish; 1989 } 1990 } 1991 1992 bus_space_write_1(iot, ioh, CLRSINT1, CLRPHASECHG); 1993 1994 dophase: 1995 if ((sstat1 & REQINIT) == 0) { 1996 /* Wait for REQINIT. */ 1997 goto out; 1998 } 1999 2000 sc->sc_phase = bus_space_read_1(iot, ioh, SCSISIG) & PH_MASK; 2001 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase); 2002 2003 switch (sc->sc_phase) { 2004 case PH_MSGOUT: 2005 if (sc->sc_state != AIC_CONNECTED && 2006 sc->sc_state != AIC_RESELECTED) 2007 break; 2008 aic_msgout(sc); 2009 sc->sc_prevphase = PH_MSGOUT; 2010 goto loop; 2011 2012 case PH_MSGIN: 2013 if (sc->sc_state != AIC_CONNECTED && 2014 sc->sc_state != AIC_RESELECTED) 2015 break; 2016 aic_msgin(sc); 2017 sc->sc_prevphase = PH_MSGIN; 2018 goto loop; 2019 2020 case PH_CMD: 2021 if (sc->sc_state != AIC_CONNECTED) 2022 break; 2023 #if AIC_DEBUG 2024 if ((aic_debug & AIC_SHOWMISC) != 0) { 2025 AIC_ASSERT(sc->sc_nexus != NULL); 2026 acb = sc->sc_nexus; 2027 printf("cmd=0x%02x+%d ", 2028 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length-1); 2029 } 2030 #endif 2031 n = aic_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 2032 sc->sc_cp += n; 2033 sc->sc_cleft -= n; 2034 sc->sc_prevphase = PH_CMD; 2035 goto loop; 2036 2037 case PH_DATAOUT: 2038 if (sc->sc_state != AIC_CONNECTED) 2039 break; 2040 AIC_MISC(("dataout %ld ", (long)sc->sc_dleft)); 2041 n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 2042 sc->sc_dp += n; 2043 sc->sc_dleft -= n; 2044 sc->sc_prevphase = PH_DATAOUT; 2045 goto loop; 2046 2047 case PH_DATAIN: 2048 if (sc->sc_state != AIC_CONNECTED) 2049 break; 2050 AIC_MISC(("datain %ld ", (long)sc->sc_dleft)); 2051 n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 2052 sc->sc_dp += n; 2053 sc->sc_dleft -= n; 2054 sc->sc_prevphase = PH_DATAIN; 2055 goto loop; 2056 2057 case PH_STAT: 2058 if (sc->sc_state != AIC_CONNECTED) 2059 break; 2060 AIC_ASSERT(sc->sc_nexus != NULL); 2061 acb = sc->sc_nexus; 2062 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 2063 acb->target_stat = bus_space_read_1(iot, ioh, SCSIDAT); 2064 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 2065 AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2066 sc->sc_prevphase = PH_STAT; 2067 goto loop; 2068 } 2069 2070 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2071 AIC_BREAK(); 2072 reset: 2073 aic_init(sc, 1); 2074 return 1; 2075 2076 finish: 2077 callout_stop(&acb->xs->xs_callout); 2078 aic_done(sc, acb); 2079 goto out; 2080 2081 sched: 2082 sc->sc_state = AIC_IDLE; 2083 aic_sched(sc); 2084 goto out; 2085 2086 out: 2087 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 2088 return 1; 2089 } 2090 2091 void 2092 aic_abort(struct aic_softc *sc, struct aic_acb *acb) 2093 { 2094 2095 /* 2 secs for the abort */ 2096 acb->timeout = AIC_ABORT_TIMEOUT; 2097 acb->flags |= ACB_ABORT; 2098 2099 if (acb == sc->sc_nexus) { 2100 /* 2101 * If we're still selecting, the message will be scheduled 2102 * after selection is complete. 2103 */ 2104 if (sc->sc_state == AIC_CONNECTED) 2105 aic_sched_msgout(sc, SEND_ABORT); 2106 } else { 2107 aic_dequeue(sc, acb); 2108 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2109 if (sc->sc_state == AIC_IDLE) 2110 aic_sched(sc); 2111 } 2112 } 2113 2114 void 2115 aic_timeout(void *arg) 2116 { 2117 struct aic_acb *acb = arg; 2118 struct scsipi_xfer *xs = acb->xs; 2119 struct scsipi_periph *periph = xs->xs_periph; 2120 struct aic_softc *sc = 2121 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2122 int s; 2123 2124 scsipi_printaddr(periph); 2125 printf("timed out"); 2126 2127 s = splbio(); 2128 2129 if (acb->flags & ACB_ABORT) { 2130 /* abort timed out */ 2131 printf(" AGAIN\n"); 2132 /* XXX Must reset! */ 2133 } else { 2134 /* abort the operation that has timed out */ 2135 printf("\n"); 2136 acb->xs->error = XS_TIMEOUT; 2137 aic_abort(sc, acb); 2138 } 2139 2140 splx(s); 2141 } 2142 2143 #ifdef AIC_DEBUG 2144 /* 2145 * The following functions are mostly used for debugging purposes, either 2146 * directly called from the driver or from the kernel debugger. 2147 */ 2148 2149 void 2150 aic_show_scsi_cmd(struct aic_acb *acb) 2151 { 2152 u_char *b = (u_char *)&acb->scsipi_cmd; 2153 struct scsipi_periph *periph = acb->xs->xs_periph; 2154 int i; 2155 2156 scsipi_printaddr(periph); 2157 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2158 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2159 if (i) 2160 printf(","); 2161 printf("%x", b[i]); 2162 } 2163 printf("\n"); 2164 } else 2165 printf("RESET\n"); 2166 } 2167 2168 void 2169 aic_print_acb(struct aic_acb *acb) 2170 { 2171 2172 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2173 printf(" dp=%p dleft=%d target_stat=%x\n", 2174 acb->data_addr, acb->data_length, acb->target_stat); 2175 aic_show_scsi_cmd(acb); 2176 } 2177 2178 void 2179 aic_print_active_acb(void) 2180 { 2181 extern struct cfdriver aic_cd; 2182 struct aic_acb *acb; 2183 struct aic_softc *sc = aic_cd.cd_devs[0]; 2184 2185 printf("ready list:\n"); 2186 for (acb = sc->ready_list.tqh_first; acb != NULL; 2187 acb = acb->chain.tqe_next) 2188 aic_print_acb(acb); 2189 printf("nexus:\n"); 2190 if (sc->sc_nexus != NULL) 2191 aic_print_acb(sc->sc_nexus); 2192 printf("nexus list:\n"); 2193 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2194 acb = acb->chain.tqe_next) 2195 aic_print_acb(acb); 2196 } 2197 2198 void 2199 aic_dump6360(struct aic_softc *sc) 2200 { 2201 bus_space_tag_t iot = sc->sc_iot; 2202 bus_space_handle_t ioh = sc->sc_ioh; 2203 2204 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIG=%x\n", 2205 bus_space_read_1(iot, ioh, SCSISEQ), 2206 bus_space_read_1(iot, ioh, SXFRCTL0), 2207 bus_space_read_1(iot, ioh, SXFRCTL1), 2208 bus_space_read_1(iot, ioh, SCSISIG)); 2209 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2210 bus_space_read_1(iot, ioh, SSTAT0), 2211 bus_space_read_1(iot, ioh, SSTAT1), 2212 bus_space_read_1(iot, ioh, SSTAT2), 2213 bus_space_read_1(iot, ioh, SSTAT3), 2214 bus_space_read_1(iot, ioh, SSTAT4)); 2215 printf(" SIMODE0=%x SIMODE1=%x DMACNTRL0=%x DMACNTRL1=%x " 2216 "DMASTAT=%x\n", 2217 bus_space_read_1(iot, ioh, SIMODE0), 2218 bus_space_read_1(iot, ioh, SIMODE1), 2219 bus_space_read_1(iot, ioh, DMACNTRL0), 2220 bus_space_read_1(iot, ioh, DMACNTRL1), 2221 bus_space_read_1(iot, ioh, DMASTAT)); 2222 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2223 bus_space_read_1(iot, ioh, FIFOSTAT), 2224 bus_space_read_1(iot, ioh, SCSIBUS)); 2225 } 2226 2227 void 2228 aic_dump_driver(struct aic_softc *sc) 2229 { 2230 struct aic_tinfo *ti; 2231 int i; 2232 2233 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2234 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2235 "currmsg=%x\n", 2236 sc->sc_state, sc->sc_imess[0], 2237 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2238 for (i = 0; i < 7; i++) { 2239 ti = &sc->sc_tinfo[i]; 2240 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2241 i, ti->cmds, ti->dconns, ti->touts); 2242 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2243 } 2244 } 2245 #endif 2246
Indexes created Sat Oct 25 16:10:12 GMT 2025